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Note:
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T est Conditions: VDD = 5V ± 5%, T A = -40qC to +85qC, unless otherwise specified. All timing characteristics
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Symbol
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2 Whenthedecoderis enabled,a handlingdelayof six anda halfRCLK clockcycleswill alwaysexist betweenRPDAT A/RNDAT A
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4 All inputs exceptpin 19, 20 andpin 26.
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Notes :
1
The pulse templateproposedby G.703 standardsis shownin Figure 4 andspecifiedin T able4 The proposedG.703 standards
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of precedingpulses.
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3 The all 1s patternmust bea pureall 1s signal, withoutframingor othercontrolbits.
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NormalizedAmplitudes
Figure 3. DSX-3 Isolated Pulse T emplatefor
ANSI T1.404 Standards
Parameter
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