XRT73L04BIV

XRT73L04B 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT OCTOBER 2003 REV. 1.0.1 GENERAL DESCRIPTION The XRT73L04B, 4-Channel, DS3/E3/STS-1 Line Interface Unit is a low power CMOS version of the XRT73L04A and consists of four independent line transmitters and receivers integrated on a single chip designed for DS3, E3 or SONET STS-1 applications. FEATURES • Incorporates an improved Timing Recovery circuit and is pin and functional compatible to XRT73L04A • Meets E3/DS3/STS-1 Jitter Tolerance Requirements • Contains a 4-Wire Microprocessor Serial Interface Each channel of the XRT73L04B can be configured to support the E3 (34.368 Mbps), DS3 (44.736 Mbps) or the SONET STS-1 (51.84 Mbps) rates. Each channel can be configured to operate in a mode/data rate that is independent of the other channels. • Full Loop-Back Capability In the transmit direction, each channel encodes input data to either B3ZS (DS3/STS-1) or HDB3 (E3) format and converts the data into the appropriate pulse shapes for transmission over coaxial cable via a 1:1 transformer. • Single +3.3V Power Supply In the receive direction, the XRT73L04B performs equalization on incoming signals, performs Clock Recovery, decodes data from either B3ZS or HDB3 format, converts the receive data into TTL/CMOS format, checks for LOS or LOL conditions and detects and declares the occurrence of Line Code Violations. • Transmit and Receive Power Down Modes • Full Redundancy Support • Uses Minimum External components • Low Power CMOS design • 5V tolerant I/O • -40°C to +85°C Operating Temperature Range • Available in a Thermally Enhanced 144 pin LQFP package APPLICATIONS • Digital Cross Connect Systems • CSU/DSU Equipment • Routers • Fiber Optic Terminals • Multiplexers • ATM Switches FIGURE 1. XRT73L04B BLOCK DIAGRAM E3_(n) RTIP_(n) RRing_(n) STS-1/DS3_(n) Host/(HW) AGC/ Equalizer RLOL_(n) EXClk_(n) RxClkINV Clock Recovery Slicer Peak Detector REQEN_(n) RxOFF Data Recovery LOS Detector LOSTHR Invert RxClk_(n) HDB3/ B3ZS Decoder RPOS_(n) RNEG_(n)/ (LCV_(n)) SDI SDO SClk CS/(SR/DR) Serial Processor Interface RLOS_(n) LLB_(n) Loop MUX RLB_(n) REGR TAOS_(n) TTIP_(n) Pulse Shaping HDB3/ B3ZS Encoder MRing_(n) DMO_(n) Device Monitor TNData_(n) Duty Cycle Adjust TRing_(n) MTIP_(n) TPData_(n) Transmit Logic TxClk_(n) TxLEV_(n) Tx Control TxOFF Channel 0 Channel 1 Channel 2 Channel 3 Notes: 1. (n) = 0, 1, 2 , or 3 for respective Channels 2. Serial Processor Interface input pins are shared by the four Channels in HOST Mode and redefined in Hardware Mode. Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com XRT73L04B 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 TYPICAL APPLICATIONS FIGURE 2. MULTICHANNEL ATM APPLICATION RPOS RNEG RxLineClk ATM Switch/ SAR RRPOS RRNEG RRClk XRT74L74 RPOS RNEG RxClk XRT71D04 RPOS RNEG RxClk RTIP RRing XRT73L04B MClk TPOS TNEG TxClk TPOS TNEG TxLineClk 4 Channel E3/DS3 ATM UNI 4 Channel E3/DS3 J/A TTIP TRing 4 Channel E3/DS3 LIU FIGURE 3. MULTISERVICE - FRAME RELAY APPLICATION RPOS RNEG RxLineClk Frame Relay RRPOS RRNEG RRClk RPOS RNEG RxClk XRT71D04 XRT72L58 RPOS RNEG RxClk RTIP RRing XRT73L04B MClk TPOS TNEG TxLineClk 8 Channel E3/DS3 Framer TPOS TNEG TxClk 2 x 4 Channel E3/DS3 J/A TTIP TRing 2 x 4 Channel E3/DS3 LIU RECEIVE INTERFACE CHARACTERISTICS: • Integrated Adaptive Receive Equalization (optional) and Timing Recovery TRANSMIT INTERFACE CHARACTERISTICS: • Accepts either Single-Rail or Dual-Rail data from Terminal Equipment and generates a bipolar signal from the line • Integrated Pulse Shaping Circuit • Declares and Clears the LOS defect per ITU-T G.775 requirements (E3 and DS3 applications) • Built-in B3ZS/HDB3 Encoder (which can be disabled) • Meets Jitter Tolerance Requirements as specified in ITU-T G.823_1993 (E3 Applications) • Contains Transmit Clock Duty Cycle Correction Circuit on-chip • Meets Jitter Tolerance Requirements as specified in Bellcore GR-499-CORE (DS3 Applications) • Generates pulses that comply with the ITU-T G.703 pulse template (E3 applications) • Declares Loss of Signal (LOS) and Loss of Lock (LOL) Alarms • Generates pulses that comply with the DSX-3 pulse template as specified in Bellcore GR-499-CORE and ANSI T1.102_1993 • Built-in B3ZS/HDB3 Decoder (which can be disabled) • Recovered Data can be muted while the LOS Condition is declared • Generates pulses that comply with the STSX-1 pulse template as specified in Bellcore GR-253CORE • Outputs either Single-Rail or Dual-Rail data to the Terminal Equipment • Transmitter can be turned off in order to support redundancy designs • Receiver can be powered down in order to conserve power in redundancy designs 2 XRT73L04B 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 E3_2 E3_3 STS1/DS3_2 LLB_2 RLB_2 RxAVDD_2 RRing_2 RTIP_2 RxAGND_2 REQEN_2 STS1/DS3_3 LLB_3 RLB_3 RxAVDD_3 RRing_3 RTIP_3 RxAGND_3 REQEN_3 REQEN_1 RxAGND_1 RTIP_1 RRing_1 RxAVDD_1 RLB_1 LLB_1 STS1/DS3_1 REQEN_0 RxAGND_0 RTIP_0 RRing_0 RxAVDD_0 RLB_0 LLB_0 LOSTHR ICT STS1/DS3_0 FIGURE 4. PIN OUT OF THE XRT73L04B IN THE 144 PIN TQFP PACKAGE 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 XRT73L04B SDO/E3_0 SDI/E3_1 SClk/(RxOFF) CS/(SR/DR) RLOL_1 RLOS_1 EXClk_0 RLOL_0 RLOS_0 AGND_1 RxDGND_0 RPOS_0 RNEG_0/LCV_0 RxClk_0 RxDVDD_0 EXClk_1 RxDGND_1 RPOS_1 RNEG_1/LCV_1 RxClk_1 Host/(HW) RxDVDD_1 AGND_0 TxAGND_0 DMO_0 TxAVDD_0 TAOS_0 TAOS_1 TxLEV_0 TxLEV_1 TxClk_0 TPData_0 TNData_0 NC NC NC MRing_2 MTIP_2 TTIP_2 TxAVDD_2 TRing_2 TxAGND_2 TxClk_3 TPData_3 TNData_3 TxAVDD_3 DMO_3 TTIP_3 TxAVDD_3 TRing_3 TxAGND_3 MTIP_3 MRing_3 TxAGND_3 TxAGND_1 MRing_1 MTIP_1 TxAGND_1 TRing_1 TxAVDD_1 TTIP_1 DMO_1 TxAVDD_1 TNData_1 TPData_1 TxClk_1 TxAGND_0 TRing_0 TxAVDD_0 TTIP_0 MTIP_0 MRing_0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 AGND_2 REGR/(RxClkINV) LOSMUTEN AGND_3 RLOL_3 RLOS_3 EXClk_2 RLOL_2 RLOS_2 RxDGND_2 RPOS_2 RNEG_2/LCV_2 RxClk_2 RxDVDD_2 EXClk_3 RxDGND_3 RPOS_3 RNEG3/LCV_3 RxClk_3 RxDVDD_3 EXDGNDA EXDVDDA TxOFF TxAGND_2 DMO_2 TxAVDD_2 TAOS_2 TAOS_3 TxLEV_2 TxLEV_3 TxClk_2 TPData_2 TNData_2 NC NC NC ORDERING INFORMATION PART # PACKAGE OPERATING TEMPERATURE RANGE XRT73L04BIV 144 Pin LQFP 20 X 20 X 1.4 mm -40oC to +85oC 3 XRT73L04B 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 TABLE OF CONTENTS GENERAL DESCRIPTION ......................................................................................................... 1 FEATURES .................................................................................................................................................... APPLICATIONS ......................................................................................................................................... Figure 1.XRT73L04B Block Diagram ................................................................................................................ TYPICAL APPLICATIONS ................................................................................................................................. Figure 2.MultiChannel ATM Application ............................................................................................................ Figure 3.MultiService - Frame Relay Application .............................................................................................. TRANSMIT INTERFACE CHARACTERISTICS: ..................................................................................................... RECEIVE INTERFACE CHARACTERISTICS: ....................................................................................................... Figure 4.Pin out of the XRT73L04B in the 144 Pin TQFP package .................................................................. 1 1 1 2 2 2 2 2 3 ORDERING INFORMATION ....................................................................................................... 3 TABLE OF CONTENTS ....................................................................................................... I PIN DESCRIPTIONS (BY FUNCTION) ......................................................................................... 4 TRANSMIT INTERFACE ................................................................................................................................... 4 RECEIVE INTERFACE ..................................................................................................................................... 6 CLOCK INTERFACE ........................................................................................................................................ 7 OPERATING MODE SELECT ........................................................................................................................... 8 CONTROL AND ALARM INTERFACE ................................................................................................................. 9 MICROPROCESSOR INTERFACE .................................................................................................................... 11 POWER AND GROUND PINS ......................................................................................................................... 13 NO CONNECTION PINS ................................................................................................................................ 14 ELECTRICAL CHARACTERISTICS ........................................................................................... 15 ABSOLUTE MAXIMUM RATINGS .................................................................................................................... 15 DC Electrical Characteristics .......................................................................................................... 15 AC Electrical Characteristics (See Figure 5) ........................................................................................................ 16 Terminal Side Timing Parameters (See Figure 6 and Figure 7) -- {(n) = 0, 1, 2 or 3 } ......................................... 16 Figure 5.Transmit Pulse Amplitude Test Circuit for E3, DS3 and STS-1 Rates (typical channel) .................. 17 Figure 6.Timing Diagram of the Transmit Terminal Input Interface ................................................................. 17 Figure 7.Timing Diagram of the Receive Terminal Output Interface ............................................................... 17 Line Side Parameters E3 Application ................................................................................................................... Transmit Characteristics (see Figure 5) ............................................................................................................... Line Side Parameters Sonet STS-1 Application ................................................................................................... Transmit Characteristics (See Figure 5) ............................................................................................................... Line Side Parameters DS3 Application ................................................................................................................ Transmit Characteristics (see Figure 5) ............................................................................................................... 18 18 19 19 20 20 Figure 8.ITU-T G.703 Transmit Output Pulse Template for E3 Applications .................................................. Figure 9.Bellcore GR-499-CORE Transmit Output Pulse Template for DS3 Applications ............................. Figure 10.Bellcore GR-253-CORE Transmit Output Pulse Template for SONET STS-1 Applications ........... Figure 11.Microprocessor Serial Interface Data Structure .............................................................................. 21 21 22 22 Microprocessor Serial Interface Timing (See Figure 12) ...................................................................................... 23 Figure 12.Timing Diagram for the Microprocessor Serial Interface ................................................................. 23 SYSTEM DESCRIPTION .................................................................................................. 24 THE TRANSMIT SECTION - CHANNELS 0, 1, 2, AND 3 .................................................................................... 24 THE RECEIVE SECTION - CHANNELS 0, 1, 2 AND 3 ....................................................................................... 24 THE MICROPROCESSOR SERIAL INTERFACE ................................................................................................. 24 Table 1:Role of Microprocessor Serial Interface pins when the XRT73L04B is operating in the Hardware Mode 24 Figure 13.Functional Block Diagram of the XRT73L04B ................................................................................ 25 I XRT73L04B 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 1.0 SELECTING THE DATA RATE ............................................................................................................... 25 1.1 CONFIGURING CHANNEL(N) ............................................................................................................ 25 Table 2:Hexadecimal Addresses and Bit Formats of XRT73L04B Command Registers ............................... 26 Table 3:Selecting the Data Rate for Channel(n) via the E3_(n) and STS-1/DS3_(n) input pins (Hardware Mode) 27 COMMAND REGISTER, CR4-(N) ........................................................................................................... 27 Table 4:Selecting the Data Rate for Channel(n) via the STS-1/DS3_(n) and the E3_(n) bit-fields within the Appropriate Command Register (HOST Mode) ..................................................................................... 27 2.0 THE TRANSMIT SECTION ...................................................................................................................... 28 2.1 THE TRANSMIT LOGIC BLOCK ......................................................................................................... 28 Accepting Dual-Rail Data from the Terminal Equipment ................................................................... 28 Figure 14. The typical interface for the Transmission of Data in a Dual-Rail Format from the Transmitting Terminal Equipment to the Transmit Section of a channel .................................................................... 28 Figure 15.The XRT73L04B Samples the data on the TPData and TNData input pins ................................... 28 Accepting Single-Rail Data from the Terminal Equipment ................................................................ 29 COMMAND REGISTER CR3-(N) ............................................................................................................ 29 Figure 16.The Behavior of the TPData and TxClk Input Sgnals, while the Transmit Logic Block is Accepting Single-Rail Data from the Terminal Equipment ..................................................................................... 29 2.2 THE TRANSMIT CLOCK DUTY CYCLE ADJUST CIRCUITRY ................................................................. 29 2.3 THE HDB3/B3ZS ENCODER BLOCK ............................................................................................... 29 B3ZS Encoding .................................................................................................................................. 29 Figure 17.An Example of B3ZS Encoding ...................................................................................................... 30 HDB3 Encoding ................................................................................................................................. 30 Figure 18.An Example of HDB3 Encoding ..................................................................................................... 30 Disabling the HDB3/B3ZS Encoder ................................................................................................... 30 COMMAND REGISTER CR3-(N) ............................................................................................................ 31 2.4 THE TRANSMIT PULSE SHAPING CIRCUITRY .................................................................................... Figure 19.The Bellcore GR-499-CORE Transmit Output Pulse Template for DS3 Applications .................... Figure 20.The Bellcore GR-253-CORE Transmit Output Pulse Template for SONET STS-1 Applications ... Enabling the Transmit Line Build-Out Circuit ..................................................................................... 31 31 32 32 COMMAND REGISTER, CR1-(N) ........................................................................................................... 32 Disabling the Transmit Line Build-Out Circuit .................................................................................... 32 COMMAND REGISTER, CR1-(N) ........................................................................................................... 33 Design Guideline for Setting the Transmit Line Build-Out Circuit ...................................................... The Transmit Line Build-Out Circuit and E3 Applications .................................................................. 2.5 INTERFACING THE TRANSMIT SECTIONS OF THE XRT73L04B TO THE LINE ...................................... Figure 21.Recommended Schematic for Interfacing the Transmit Section of the XRT73L04B to the Line .... 33 33 33 33 TRANSFORMER RECOMMENDATIONS .................................................................................................... 34 3.0 THE RECEIVE SECTION ......................................................................................................................... 35 3.1 INTERFACING THE RECEIVE SECTIONS OF THE XRT73L04B TO THE LINE ........................................ 35 Figure 22.Recommended Schematic for Interfacing the Receive Section of the XRT73L04B to the Line (Transformer-Coupling) .............................................................................................................................. 35 3.2 THE RECEIVE EQUALIZER BLOCK ................................................................................................... 36 Figure 23.The Typical Application for the System Installer ............................................................................ 36 Guidelines for Setting the Receive Equalizer ................................................................................... 36 II XRT73L04B 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 COMMAND REGISTER CR-2(N) ............................................................................................................ 37 3.3 CLOCK RECOVERY PLL .................................................................................................................. The Training Mode ............................................................................................................................. The Data/Clock Recovery Mode ........................................................................................................ 3.4 THE HDB3/B3ZS DECODER .......................................................................................................... B3ZS Decoding (DS3/STS-1 Applications) ........................................................................................ Figure 24.An Example of B3ZS Decoding ...................................................................................................... HDB3 Decoding (E3 Applications) ..................................................................................................... Figure 25.An Example of HDB3 Decoding ...................................................................................................... Configuring the HDB3/B3ZS Decoder ................................................................................................ 38 38 38 38 38 38 38 39 39 COMMAND REGISTER CR3-(N) ............................................................................................................ 39 3.5 LOS DECLARATION/CLEARANCE ..................................................................................................... 39 The LOS Declaration/Clearance Criteria for E3 Applications ............................................................. 39 Figure 26.The Signal Levels that the XRT73L04B declares and clears LOS ................................................. 40 Figure 27.The Behavior of the LOS Output Indicator in response to the Loss of Signal and the Restoration of Signal ................................................................................................................................................ 41 The LOS Declaration/Clearance Criteria for DS3 and STS-1 Applications ........................................ 41 Table 5:The ALOS (Analog LOS) Declare and Clear Thresholds for a given setting of LOSTHR and REQEN (DS3 and STS-1 Applications) ........................................................................................................... 41 COMMAND REGISTER CR0-(N) ............................................................................................................ 42 COMMAND REGISTER CR2-(N) ............................................................................................................ 42 COMMAND REGISTER CR0-(N) ............................................................................................................ 42 COMMAND REGISTER CR2-(N) ............................................................................................................ 42 Muting the Recovered Data while the LOS is being Declared ........................................................... 42 COMMAND REGISTER CR3-(N) ............................................................................................................ 43 3.6 ROUTING THE RECOVERED TIMING AND DATA INFORMATION TO THE RECEIVING TERMINAL EQUIPMENT . 43 Routing Dual-Rail Format Data to the Receiving Terminal Equipment .............................................. 43 Figure 28.The typical interface for the Transmission of Data in a Dual-Rail Format, from the Receive Section of the XRT73L04B to the Receiving Terminal Equipment .................................................................... 43 Figure 29.How the XRT73L04B outputs data on the RPOS and RNEG output pins ...................................... 44 Figure 30.The Behavior of the RPOS, RNEG, and RxClk signals when RxClk is inverted ............................. 44 COMMAND REGISTER CR3-(N) ............................................................................................................ 45 Routing Single-Rail Format (Binary Data Stream) data to the Receive Terminal Equipment ............ 45 COMMAND REGISTER CR3-(N) ............................................................................................................ 45 Figure 31.The typical interface for the Transmission of Data in a Single-Rail Format from the Receive Section of the XRT73L04B to the Receiving Terminal Equipment ................................................................ 45 Figure 32.The behavior of the RPOS and RxClk output signals while the XRT73L04B is transmitting Single-Rail data to the Receiving Terminal Equipment ....................................................................................... 46 3.7 SHUTTING OFF THE RECEIVE SECTION ........................................................................................... 46 COMMAND REGISTER CR3-(N) ............................................................................................................ 46 4.0 DIAGNOSTIC FEATURES OF THE XRT73L04B .................................................................................... 47 4.1 THE ANALOG LOCAL LOOP-BACK MODE ......................................................................................... 47 Figure 33. A channel operating in the Analog Local Loop-Back Mode ........................................................... 47 4.2 THE DIGITAL LOCAL LOOP-BACK MODE. ......................................................................................... 48 III XRT73L04B 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 COMMAND REGISTER CR4-(N) ............................................................................................................ 48 Figure 34.The Digital Local Loop-Back path within a given channel .............................................................. 48 COMMAND REGISTER CR4-(N) ............................................................................................................ 48 4.3 THE REMOTE LOOP-BACK MODE ................................................................................................... 49 Figure 35.The Remote Loop-Back path, within a given channel .................................................................... 49 COMMAND REGISTER CR4-(n) ............................................................................................................ 49 4.4 TXOFF FEATURES ......................................................................................................................... 50 COMMAND REGISTER CR1-(N) ............................................................................................................ 50 Table 6:The Relationship Between the TxOFF Input Pin, the TxOFF Bit Field and the State of the Transmitter 50 4.5 THE TRANSMIT DRIVE MONITOR FEATURES .................................................................................... 50 Figure 36.The XRT73L04B employing the Transmit Drive Monitor Features ................................................. 51 4.6 THE TAOS (TRANSMIT ALL ONES) FEATURE ................................................................................. 51 5.0 THE MICROPROCESSOR SERIAL INTERFACE ................................................................................... 51 5.1 DESCRIPTION OF THE COMMAND REGISTERS .................................................................................. 51 COMMAND REGISTER CR1-(N) ............................................................................................................ 51 Table 7:Hexadecimal Addresses and Bit Formats of XRT73L04B Command Registers ............................... 52 5.2 DESCRIPTION OF BIT-FIELDS FOR EACH COMMAND REGISTER ......................................................... 53 Command Register - CR0-(n) ............................................................................................................ 53 COMMAND REGISTER CR0-(N) ............................................................................................................. 53 COMMAND REGISTER CR1-(N) ............................................................................................................ 54 Command Register CR2-(n) .............................................................................................................. 54 COMMAND REGISTER CR2-(N) ............................................................................................................ 54 COMMAND REGISTER CR3-(N) ............................................................................................................ 55 COMMAND REGISTER CR4-(N) ............................................................................................................ 56 Table 8:Contents of LLB_(n) and RLB_(n) and the Corresponding Loop-Back Mode for Channel(n) ........... 5.3 OPERATING THE MICROPROCESSOR SERIAL INTERFACE. ................................................................. Figure 37.Microprocessor Serial Interface Data Structure ............................................................................. Figure 38.Timing Diagram for the Microprocessor Serial Interface ................................................................ 56 56 57 58 ORDERING INFORMATION ..................................................................................................... 59 PACKAGE DIMENSIONS ........................................................................................................ 59 REVISION HISTORY ..................................................................................................................................... 60 IV XRT73L04B 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 PIN DESCRIPTIONS (BY FUNCTION) TRANSMIT INTERFACE PIN # NAME TYPE DESCRIPTION 34 25 3 12 TTIP_0 TTIP_1 TTIP_2 TTIP_3 O 32 23 5 14 TRing_0 TRing_1 TRing_2 TRing_3 O 42 30 139 7 TxClk_0 TxClk_1 TxClk_2 TxClk_3 I 41 29 140 8 TPData_0 TPData_1 TPData_2 TPData_3 I Transmit Positive Data Input - Channel (n): The XRT73L04B samples this pin on the falling edge of TxClk_(n). If the device samples a "1", then it generates and transmits a positive polarity pulse to the line. The data should be applied to this input pin if the Transmit Section is configured to accept Single-Rail data from the Terminal Equipment. NOTE: If the XRT73L04B is operating in the HOST Mode, then the XRT73L04B can be configured to sample the TPData_(n) pin on either the rising or falling edge of TxClk_(n). 40 28 141 9 TNData_0 TNData_1 TNData_2 TNData_3 I Transmit Negative Data Input - Channel (n): Transmit TTIP Output - Channel (n): The XRT73L04B uses this pin along with TRing_(n) to transmit a bipolar line signal via a 1:1 transformer. Transmit Ring Output - Channel (n): The XRT73L04B uses this pin along with TTIP_(n) to transmit a bipolar line signal via a 1:1 transformer. Transmit Clock Input for TPData and TNData - Channel (n): This input pin must be driven at 34.368 MHz (for E3 applications), 44.736 MHz (for DS3 applications), or 51.84 MHz (for SONET STS-1 applications). The XRT73L04B uses this signal to sample the TPData_(n) and TNData_(n) input pins. By default, the XRT73L04B is configured to sample these two pins on the falling edge of this signal. NOTE: If the XRT73L04B is operating in the HOST Mode, then the device can be configured to sample the TPData_(n) and TNData_(n) input pins on either the rising or falling edge of TxClk_(n). The XRT73L04B samples this pin on the falling edge of TxClk_(n). If the device samples a "1", then it generates and transmits a negative polarity pulse to the line. In Single-Rail Mode, this pin must be tied to GND to enable the HDB3/ B3ZS Encoder and Decoder, (internally pulled-down). In Dual-Rail Mode this input is the N-Rail Data input. NOTE: If the XRT73L04B is operating in the HOST Mode, then the XRT73L04B can be configured to sample the TNData_(n) pin on either the rising or falling edge of TxClk_(n). 4 XRT73L04B 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 TRANSMIT INTERFACE PIN # NAME TYPE DESCRIPTION 44 43 137 138 TxLEV_0 TxLEV_1 TxLEV_2 TxLEV_3 I Transmit Line Build-Out Enable/Disable Select - Channel (n): This input pin permits the Transmit Line Build-Out circuit, within Channel (n), to be enabled or disabled. In E3 mode, this pin has no effect on the transmit pulse shape. Setting this pin to "High" disables the Line Build-Out circuit. In this mode, Channel (n) outputs partially-shaped pulses onto the line via the TTIP_(n) and TRing_(n) output pins. Setting this pin to "Low" enables the Line Build-Out circuit within Channel (n). In this mode, Channel (n) outputs shaped pulses onto the line via the TTIP_(n) and TRing_(n) output pins. To comply with the Isolated DSX-3/STSX-1 Pulse Template Requirements per Bellcore GR-499-CORE or Bellcore GR-253-CORE: 1. Set this input pin to "1" if the cable length between the Cross-Connect and the transmit output of Channel (n) is greater than 225 feet. 2. Set this input pin to "0" if the cable length between the Cross-Connect and the transmit output of Channel (n) is less than 225 feet. This pin is active only if the following two conditions are true: a. The XRT73L04B is configured to operate in either the DS3 or SONET STS-1 Modes. b. The XRT73L04B is configured to operate in the Hardware Mode. NOTE: This pin to should be tied to GND if the XRT73L04B is going to be operating in the HOST Mode, (internally pulled-down). 131 TxOFF I Transmitter OFF Input: Setting this input pin "High" turns off all of the Transmitter Sections. In this mode the TTIP and TRing outputs are tri-stated. NOTES: 1. This input pin controls the TTIP and TRing outputs even when the XRT73L04B is operating in the HOST Mode. 2. For HOST Mode Operation, this pin is tied to GND if the Transmitter is intended to be turned off via the Microprocessor Serial Interface. 5 XRT73L04B 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 RECEIVE INTERFACE PIN # NAME TYPE DESCRIPTION 59 53 121 127 RxClk_0 RxClk_1 RxClk_2 RxClk_3 O Receive Clock Output - Channel (n): This output pin is the Recovered Clock signal from the incoming line signal for Channel (n). The Receive Section of Channel (n) outputs data via the RPOS_(n) and RNEG_(n) output pins on the rising edge of this clock signal. Configure the Receive Section of Channel (n) to update the data on the RPOS_(n) and RNEG_(n) output pins on the falling edge of RxClk_(n) by doing one of the following: a. Operating in the Hardware Mode Pull the RxClkINV pin to "High". b. Operating in the HOST Mode Write a "1" into the RxClkINV bit-field within the Command Register. 60 54 120 126 RNEG_0/LCV_0 RNEG_1/LCV_1 RNEG_2/LCV_2 RNEG_3/LCV_3 O Receive Negative Data Output - Channel (n): The function of this pin is dependent on whether the 73L04A is in the Hardware or HOST Mode (HOST/HW) and the condition of CS/(SR/DR). a. Operating in the Hardware Mode Receive Negative Data: Setting the CS/(SR/DR) pin ”Low”, (Dual-Rail operation) this output pin pulses "High" whenever Channel (n) has received a Negative Polarity pulse in the incoming line signal at the RTIP_(n) and RRing_(n) inputs. Line Code Violation: When CS/(SR/DR) is set “High”, (Single-Rail operation), the B3ZS/HDB3 Encoder/Decoder is activated and the Line Code Violation signal is output on this pin. b. Operating in the HOST Mode Receive Negative Data: Writing a “0” to the (SR/DR)_(n) bit in the command register configures channel(n) in the Dual-Rail Mode and activates RNEG_(n). Writing a “1” to (SR/DR)_(n) bit of the Command Register configures the Single-Rail Mode and activates LCV_(n). If the B3ZS/HDB3 Decoder is enabled then the zero suppression patterns in the incoming line signal (such as: "00V", "000V", "B0V", "B00V") is not reflected at this output. 61 55 119 125 RPOS_0 RPOS_1 RPOS_2 RPOS_3 O 79 87 102 94 RRing_0 RRing_1 RRing_2 RRing_3 I Receive Positive Data Output - Channel (n): The function of this pin is dependent on the setting of the CS/(SR/DR) pin. Receive Positive Data If CS/(SR/DR) is set “Low” (Dual-Rail Mode), this output pin pulses "High" whenever Channel (n) has received a Positive Polarity pulse in the incoming line signal at the RTIP_(n)/RRing_(n) inputs. Data Output If CS/(SR/DR) is set “High” (Single-Rail Mode), data is output on this pin. If the B3ZS/HDB3 Decoder is enabled then the zero suppression patterns in the incoming line signal (such as: "00V", "000V", "B0V", "B00V") is not reflected at this output. Receive Ring Input - Channel (n): This input pin along with RTIP_(n) is used to receive the bipolar line signal from the Remote DS3/E3/STS-1 Terminal. 6 XRT73L04B 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 RECEIVE INTERFACE PIN # NAME TYPE DESCRIPTION 80 88 101 93 RTIP_0 RTIP_1 RTIP_2 RTIP_3 I 82 90 99 91 REQEN_0 REQEN_1 REQEN_2 REQEN_3 I Receive Equalization Enable Input - Channel (n): Setting this input pin "High" enables the Internal Receive Equalizer within Channel (n). Setting this pin "Low" disables the Internal Receive Equalizer. The guidelines for enabling and disabling the Receive Equalizer are described in Section 3.2. NOTE: This pin is ignored and should be tied to GND if the XRT73L04B is going to be operating in the HOST Mode, (internally pulled-down). 110 RxClkINV I Invert RxClk_(n) Output - Select: Receive TIP Input - Channel (n): This input pin along with RRing_(n) is used to receive the bipolar line signal from the Remote DS3/E3/STS-1 Terminal. The function of this pin depends upon the mode of operation. Hardware Mode - Invert RxClk Output Select: Setting this input pin "High" configures the Receive Section of all Channels to invert their RxClk_(n) clock output signals. Setting this pin "Low" configures Channel(n) to output the recovered data via the RPOS_(n) and RNEG_(n) output pins on the rising edge of RxClk_(n). Setting this input pin "High" configures Channel (n) to output the recovered data via the RPOS_(n) and RNEG_(n) output pins on the falling edge of RxClk_(n). NOTE: This pin is internally pulled “High”. CLOCK INTERFACE PIN # NAME TYPE DESCRIPTION 66 57 115 123 EXClk_0 EXClk_1 EXClk_2 EXClk_3 I External Reference Clock Input - Channel (n): Apply a 34.368 MHz clock signal for E3 applications, a 44.736 MHz clock signal for DS3 applications or a 51.84 MHz clock signal for SONET STS-1 applications. The Channel (n) Clock Recovery PLL uses this signal as a Reference Signal for Declaring and Clearing the Receive Loss of Lock Alarm. The Clock recovery PLL also generates the exact clock for the LIU. It is permissible to use the same clock that drives the TxClk_(n) input pin. It is permissible to operate the four Channels at different data rates. 7 XRT73L04B 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 OPERATING MODE SELECT PIN # NAME TYPE 69 SR/DR/CS I DESCRIPTION Microprocessor Serial Interface - Chip Select Input/EncoderDecoder Disable Input: The function of this pin depends upon whether the XRT73L04B is operating in the HOST Mode or in the Hardware Mode. NOTE: This pin is internally pulled "High". Hardware Mode - Receive Output Single-Rail/Dual-Rail Select: In Hardware Mode, setting this pin “High” configures each of the four channels to operate in the Single-Rail Mode. When each of the four channels are configured to operate in the Single-Rail Mode, then the Receive Section of each channel will output data via the RPOS_(n) output pin. NOTE: Tie the TNData_(n) input to GND to enable HDB3/B3ZS Encoding and Decoding. Setting this pin “Low” configures each of the four channels to operate in the Dual-Rail Mode. When each of the four channels are configured to operate in the Dual-Rail Mode, then the Receive Section of each channel will output data via both the RPOS_(n) and RNEG_(n) output pins. NOTE: This input pin functions as the CS input pin, if the XRT73L04B device has been configured to operate in the HOST Mode. 72 E3_0/SDO I/O 71 E3_1/SDI I E3_Mode Select - Channel 0: This pin has a dual function. In HOST mode, this pin functions as SDO. E3_Mode Select - Channel 1 This pin has a dual function. In HOST mode,this pin functions as SDI. E3_Mode Select - Channel 2 108 107 E3_2 E3_3 I I E3_Mode Select - Channel 3 73 83 106 98 STS1/DS3_0 STS1/DS3_1 STS1/DS3_2 STS1/DS3_3 I STS-1/DS3 Select Input - Channel (n): “High” for STS-1 and “Low” for DS3 Operation. The XRT73L04B ignores this pin if the E3_(n) pin is set to "1". This input pin is ignored if the XRT73L04B is operating in the HOST Mode. NOTE: This pin should be tied to GND if the XRT73L04B is going to be operating in the HOST Mode, (internally pulled-down). Hardware Mode Operation - E3 Mode Select - Channel (n): This input pin is used to configure Channel (n) of the XRT73L04B to operate in the E3 or STS-1/DS3 Modes. Setting this input pin to "High" configures Channel (n) to operate in the E3 Mode. Setting it "Low" configures Channel (n) to operate in either the DS3 or STS-1 Modes, depending upon the state of the STS-1/DS3_(n) input pin. NOTE: This pin is internally pulled “Low” when XRT73L04B is in the Hardware Mode. 8 XRT73L04B 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 OPERATING MODE SELECT PIN # NAME TYPE DESCRIPTION 52 HOST/(HW) I HOST-Hardware Mode Select: This input pin is used to enable or disable the Microprocessor Serial Interface (e.g., consisting of the SDI, SDO, SClk, and CS pins). Setting this input pin "High" enables the Microprocessor Serial Interface (e.g. configures the XRT73L04B to operate in the HOST Mode). In this mode, configure the XRT73L04B via the Microprocessor Serial Interface. When the XRT73L04B is operating in the HOST Mode, then it ignores the states of many of the discrete input pins. Setting this input pin "Low" disables the Microprocessor Serial Interface (e.g., configures the XRT73L04B to operate in the Hardware Mode). In this mode, many of the external input control pins are functional. (Internally Pulled-up) CONTROL AND ALARM INTERFACE PIN # NAME TYPE DESCRIPTION 36 20 1 17 MRing_0 MRing_1 MRing_2 MRing_3 I 35 21 2 16 MTIP_0 MTIP_1 MTIP_2 MTIP_3 I 48 26 133 11 DMO_0 DMO_1 DMO_2 DMO_3 O Drive Monitor Output - Channel (n): If no transmitted AMI signal is present on MTIP_(n) and MRing_(n) input pins for 128±32 TxClk periods, then DMO_(n) toggles and remains "High" until the next AMI signal is detected. 46 45 135 136 TAOS_0 TAOS_1 TAOS_2 TAOS_3 I Transmit All Ones Select - Channel (n): A "High" on this pin causes the Transmit Section, within Channel (n), to generate and transmit a continuous AMI all “1’s" pattern onto the line. The frequency of this "1’s" pattern is determined by TxClk_(n). This input pin is ignored if the XRT73L04B is operating in the HOST Mode. NOTE: This pin should be tied to GND if the XRT73L04B is going to be operating in the HOST Mode, (internally pulled-down). 64 67 117 114 RLOS_0 RLOS_1 RLOS_2 RLOS_3 O Receive Loss of Signal Output Indicator - Channel (n): 65 68 116 113 RLOL_0 RLOL_1 RLOL_2 RLOL_3 O Monitor Ring Input - Channel (n): The bipolar line output signal from TRing_(n) can be connected to this pin via a 270-ohm resistor in order to check for line driver failure. This pin is internally pulled "High". Monitor Tip Input - Channel (n): The bipolar line output signal from TTIP_(n) can be connected to this pin via a 270-ohm resistor in order to check for line driver failure. This pin is internally pulled "High". This output pin toggles "High" if Channel (n) has detected a Loss of Signal Condition in the incoming line signal. The criteria that the XRT73L04B uses to declare an LOS Condition depends upon whether the device is operating in the E3 or STS-1/DS3 Mode. Receive Loss of Lock Output Indicator - Channel (n): This output pin toggles "High" if Channel (n) has detected a Loss of Lock Condition. Channel (n) declares an LOL (Loss of Lock) condition if the recovered clock frequency deviates from the Reference Clock frequency (available at the EXClk_(n) input pin) by more than 0.5%. 9 XRT73L04B 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 CONTROL AND ALARM INTERFACE PIN # NAME TYPE DESCRIPTION 60 54 120 126 RNEG_0/(LCV_0) RNEG_1/(LCV_1) RNEG_2/(LCV_2) RNEG_3/(LCV_3) O Line Code Violation - Channel (n): The function of this pin is dependent on whether the XRT73L04B is in the Hardware or HOST Mode (HOST/HW) and if CS/(SR/DR) is set “High”. Hardware Mode Line Code Violation: When CS/(SR/DR) is set “High”, (Single-Rail operation), the B3ZS/HDB3 Encoder/Decoder is activated and the Line Code Violation signal is output on this pin. HOST Mode Receive Negative Data: Writing a “1” to (SR/DR)_(n) bit of the Command Register configures the Single-Rail Mode and activates LCV_(n). If the B3ZS/HDB3 Decoder is enabled then the zero suppression patterns in the incoming line signal (such as: "00V", "000V", "B0V", "B00V") is not reflected at this output. 74 ICT I In-Circuit Test Input: Setting this pin "Low" causes all digital and analog outputs to go into a high-impedance state to allow for in-circuit testing. This pin should be set to "High" for normal operation. This pin is internally pulled "High". 75 LOSTHR I Loss of Signal Threshold Control: Forcing the LOSTHR pin to GND or VDD provides two settings. This pin must be set to a “High” or “Low” level upon power up and should not be changed during operation. This pin is only applicable during DS3 or STS-1 operations. 76 84 105 97 LLB_0 LLB_1 LLB_2 LLB_3 I 77 85 104 96 RLB_0 RLB_1 RLB_2 RLB_3 I Local Loop-back - Channel (n): This input pin along with RLB_(n) dictates which Loop-Back mode Channel (n) is operating in. A "High" on this pin with RLB_(n) set to "Low" configures Channel (n) to operate in the Analog Local Loop-Back Mode. A "High" on this pin with RLB_(n) also being set to "High" configures Channel (n) to operate in the Digital Local Loop-Back Mode. NOTE: This pin is ignored and should be tied to GND if the XRT73L04B is going to be operating in the HOST Mode. Remote Loop-Back - Channel (n): This input pin in conjunction with LLB_(n) dictates which Loop-Back mode Channel (n) is operating in. A "High" on this pin with LLB_(n) being set to "Low" configures Channel (n) to operate in the Remote Loop-Back Mode. A "High" on this pin with LLB_(n) also being set to "High" configures Channel (n) to operate in the Digital Local Loop-Back Mode. NOTE: This pin is ignored and should be tied to GND if the XRT73L04B is going to be operating in the HOST Mode. 10 XRT73L04B 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 CONTROL AND ALARM INTERFACE PIN # NAME TYPE DESCRIPTION 111 LOSMUTEN I MUTE-upon-LOS Enable Input (Hardware Mode): This input pin is use to configure the XRT73L04B, while it is operating in the Hardware Mode, to MUTE the recovered data via the RPOS_(n), RNEG_(n) output pins whenever one of the Channels declares an LOS conditions. Setting this input pin “High" configures all Channels to automatically pull the RPOS_(n) and RNEG_(n) output pins “Low” whenever it is declaring an LOS condition, thereby MUTing the data being output to the Terminal Equipment. Setting this input pin "Low" configures all Channels to NOT automatically MUTE the recovered data whenever an LOS condition is declared. NOTES: 1. This pin is ignored and should be tied to GND if the XRT73L04B is going to be operating in the HOST Mode. 2. This pin is internally pulled "Low". MICROPROCESSOR INTERFACE PIN # NAME TYPE 69 CS/ SR/DR I DESCRIPTION Microprocessor Serial Interface - Chip Select Input/EncoderDecoder Disable Input: The function of this pin depends upon whether the XRT73L04B is operating in the HOST Mode or in the Hardware Mode. HOST Mode Operation - Chip Select Input: The Local Microprocessor must assert this pin to "0" in order to enable communication with the XRT73L04B via the Microprocessor Serial Interface. NOTE: This pin is internally pulled "High". 70 SClk/(RxOFF) I Microprocessor Serial Interface Clock Signal/Receiver Shut OFF Input: The function of this pin depends upon: HOST Mode - Microprocessor Serial Interface Clock Signal: This signal is used to sample the data on the SDI pin on the rising edge of this signal. During Read operations the Microprocessor Serial Interface updates the SDO output on the falling edge of this signal. Hardware Mode - Receiver Shut OFF input: Setting this input pin "High" shuts off all of the Receiver Sections. Setting this input pin "Low" enables all of the Receive Sections for full operation. 71 SDI/E3_1 I Serial Data Input for the Microprocessor Serial Interface This pin has a dual function. HOST Mode: To read or write data into the Command Registers over the Microprocessor Serial Interface, apply the Read/Write bit, the Address Values of the Command Registers and Data Value to be written during Write Operations to this pin. This input is sampled on the rising edge of the SClk pin. 11 XRT73L04B 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 MICROPROCESSOR INTERFACE PIN # NAME TYPE DESCRIPTION 72 SDO/E3_0 O Serial Data Output from the Microprocessor Serial Interface The function of this pin depends upon the mode of operation. HOST Mode Operation: This pin serially outputs the contents of the specified Command Register during Read Operations. The data on this pin is updated on the falling edge of the SClk input signal. This pin is tri-stated upon completion of data transfer. 110 REGR/ RxClkINV I Register Reset Input (Invert RxClk_(n) Output - Select): The function of this pin depends upon the mode of operation.In Hardware mode, this pin functions as RxClkINV. HOST Mode - Register Reset Input: Setting this input pin "Low" causes the XRT73L04B to reset the contents of the Command Registers to their default settings and to its default operating configuration. NOTE: This pin is internally pulled “High”. 12 XRT73L04B 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 POWER AND GROUND PINS PIN # NAME TYPE DESCRIPTION 4 TxAVDD_2 **** Transmitter Analog Supply, 3.3V + 5% - Channel(n) 6 TxAGND_2 **** Transmitter Analog Ground - Channel(n) 10 TxAVDD_3 **** Transmitter Analog Supply, 3.3V + 5% - Channel(n) 13 TxAVDD_3 **** Transmitter Analog Supply, 3.3V + 5% - Channel(n) 15 TxAGND_3 **** Transmitter Analog Ground - Channel(n) 18 TxAGND_3 **** Transmitter Analog Ground - Channel(n) 19 TxAGND_1 **** Transmitter Analog Ground - Channel(n) 22 TxAGND_1 **** Transmitter Analog Ground - Channel(n) 24 TxAVDD_1 **** Transmitter Analog Supply, 3.3V + 5% - Channel(n) 27 TxAVDD_1 **** Transmitter Analog Supply, 3.3V + 5% - Channel(n) 31 TxAGND_0 **** Transmitter Analog Ground - Channel(n) 33 TxAVDD_0 **** Transmitter Analog Supply, 3.3V + 5% - Channel(n) 47 TxAVDD_0 **** Transmitter Analog Supply, 3.3V + 5% - Channel(n) 49 TxAGND_0 **** Transmitter Analog Ground - Channel (n) 50 AGND_0 **** Analog Ground Pin - Channel (n) 51 RxDVDD_1 **** Receiver Digital Supply 3.3V + 5% Channel (n) 56 RxDGND_1 **** Receiver Digital Ground - Channel(n) 58 RxDVDD_0 **** Receiver Digital Supply 3.3V + 5% Channel (n) 62 RxDGND_0 **** Receiver Digital Ground - Channel(n) 63 AGND_1 **** Analog Ground Pin - Channel(n) 78 RxAVDD_0 **** Receiver Analog Supply 3.3V + 5% - Channel (n) 81 RxAGND_0 **** Receiver Analog Ground - Channel (n) 86 RxAVDD_1 **** Receiver Analog Supply 3.3V + 5% - Channel (n) 89 RxAGND_1 **** Receiver Analog Ground - Channel (n) 92 RxAGND_3 **** Receiver Analog Ground - Channel (n) 95 RxAVDD_3 **** Receiver Analog Supply 3.3V + 5% - Channel (n) 100 RxAGND_2 **** Receiver Analog Ground - Channel (n) 103 RxAVDD_2 **** Receiver Analog Supply 3.3V + 5% - Channel (n) 109 AGND_2 **** Analog Ground Pin - Channel (n) 112 AGND_3 **** Analog Ground Pin - Channel (n) 118 RxDGND_2 **** Receiver Digital Ground - Channel(n) 122 RxDVDD_2 **** Receiver Digital Supply 3.3V + 5% - Channel (n) 13 XRT73L04B 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 POWER AND GROUND PINS PIN # NAME TYPE DESCRIPTION 124 RxDGND_3 **** Receiver Digital Ground - Channel(n) 128 RxDVDD_3 **** Receiver Digital Supply 3.3V + 5% - Channel (n) 129 EXDGNDA **** External Clock Digital Ground 130 EXDVDDA **** External Clock Digital Supply 132 TxAGND_2 **** Transmitter Analog Ground - Channel (n) 134 TxAVDD_2 **** Transmitter Analog Supply 3.3V + 5% - Channel(n) NO CONNECTION PINS PIN # NAME TYPE DESCRIPTION 37 NC No connection 38 NC No connection 39 NC No connection 142 NC No connection 143 NC No connection 144 NC No connection 14 XRT73L04B 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Storage Temperature - 65°C to + 150°C Operating Temperature - 40°C to + 85°C Supply Voltage Range -0.5V to +3.465V Theta-JA 24° C/W Theta-JC 5.5° C/W NOTE: The XRT73L04B is assembled in a thermally enhanced package with an integral Copper Heat Slug. The Heat Slug is solder plated and is exposed on the bottom of the package and is electrically connected to the internal Ground connections of the device. This Heat Slug can be soldered to the mounting board if desired, but must be electrically isolated from any VDD connections. ELECTRICAL CHARACTERISTICS (TA = 25°C, VDD = 3.3V + 5%, UNLESS OTHERWISE SPECIFIED) SYMBOL PARAMETER MIN. TYP. MAX. UNITS DC Electrical Characteristics DVDD Digital DC Supply Voltage 3.135 3.3 3.465 V AVDD Analog DC Supply Voltage 3.135 3.3 3.465 V ICC Supply Current (Measured while Transmitting and Receiving all "1’s") 500 mA VIL Input Low Voltage * 0.8 V VIH Input High Voltage * 5.0 V VOL Output Low Voltage, IOUT = -4.0mA * 0.4 V VOH Output High Voltage, IOUT = 4.0mA * IL 2.0 2.8 Input Leakage Current * V ±10 NOTE: * Not applicable to pins with pull-up or pull-down resistors. 15 µA XRT73L04B 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 ELECTRICAL CHARACTERISTICS (CONTINUED) (TA = 25°C, VDD = 3.3V + 5%, UNLESS OTHERWISE SPECIFIED) AC ELECTRICAL CHARACTERISTICS (SEE FIGURE 5) TERMINAL SIDE TIMING PARAMETERS (SEE FIGURE 6 AND FIGURE 7) -- {(n) = 0, 1, 2 OR 3 } SYMBOL PARAMETER MIN. TYP. MAX. UNITS TxClk_(n) Clock Duty Cycle (STS-1/DS3) 30 50 70 % TxClk_(n) Clock Duty Cycle (E3) 30 50 70 % TxClk_(n) Frequency (SONET STS-1) 51.84 MHz TxClk_(n) Frequency (DS3) 44.736 MHz TxClk_(n) Frequency (E3) 34.368 MHz tRTX TxClk_(n) Clock Rise Time (10% to 90%) 3 5 ns tFTX TxClk_(n) Clock Fall Time (90% to 10%) 3 5 ns tTSU TPData_(n)/TNData_(n) to TxClk_(n) Falling Set up time 3 1.5 ns tTHO TPData_(n)/TNData_(n) to TxClk_(n) Falling Hold time 3 1.5 ns tLCVO RxClk_(n) to rising edge of LCV_(n) output delay 2.5 ns tTDY TTIP_(n)/TRing_(n) to TxClk_(n) Rising Propagation Delay time 8 ns RxClk_(n) Clock Duty Cycle 50 % RxClk_(n) Frequency (SONET STS-1) 51.84 MHz RxClk_(n) Frequency (DS3) 44.736 MHz RxClk_(n) Frequency (E3) 34.368 MHz 2.5 ns tCO RxClk_(n) to RPOS_(n)/RNEG_(n) Delay Time 0 tRRX RxClk_(n) Clock Rise Time (10% to 90%) 1.5 ns tFRX RxClk_(n) Clock Fall Time (10% to 90%) 1.5 ns CI Input Capacitance 10 pF CL Load Capacitance 10 pF NOTES: 1. All XRT73L04B digital inputs are designed to be TTL 5V compliant. 2. All XRT73L04B digital outputs are also TTL 5V compliant. However, these outputs will not drive to 5V nor will they accept external 5V pull-ups. 16 XRT73L04B 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 FIGURE 5. TRANSMIT PULSE AMPLITUDE TEST CIRCUIT FOR E3, DS3 AND STS-1 RATES (TYPICAL CHANNEL) TTIP_(n) Channel (n) Channel (n) TxPOS_(n) TxNEG_(n) TxLineClk_(n) R1 31.6Ω TPData_(n) TNData_(n) TxClk_(n) R3 75Ω 1:1 R2 31.6Ω TRing_(n) Only One Channel Shown FIGURE 6. TIMING DIAGRAM OF THE TRANSMIT TERMINAL INPUT INTERFACE tRTX tFTX TClk tTSU tTHO TPDATA or TNDATA TTIP or TRING tTDY FIGURE 7. TIMING DIAGRAM OF THE RECEIVE TERMINAL OUTPUT INTERFACE tRRX tFRX RClk tLCVO LCV tCO RPOS or RNEG 17 XRT73L04B 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 ELECTRICAL CHARACTERISTICS (CONTINUED), (TA = 25°C, VDD = 3.3V + 5%, UNLESS OTHERWISE SPECIFIED) LINE SIDE PARAMETERS E3 APPLICATION TRANSMIT CHARACTERISTICS (SEE FIGURE 5) SYMBOL PARAMETER MIN. TYP. MAX UNITS Transmit Output Pulse Amplitude (Measured at Secondary Output of Transformer) 0.90 1.00 1.10 Vpk Transmit Output Pulse Amplitude Ratio 0.95 1.00 1.05 Transmit Output Pulse Width 12.5 14.55 16.5 Transmit Output Pulse Width Ratio 0.95 1.00 1.05 0.02 0.05 Transmit Output Jitter with jitter-free input @ TxClk_(n) ns UIpp Receive Line Characteristics Receive Sensitivity (Length of cable) Interference Margin 1200 1400 feet -20 -15 dB Signal Level to Declare Loss of Signal -35 dB Signal Level to Clear Loss of Signal -15 Occurrence of LOS to LOS Declaration Time 10 255 UI Termination of LOS to LOS Clearance Time 10 255 UI Intrinsic Jitter (all “1’s” pattern) dB 0.02 UI Jitter Tolerance @ Jitter Frequency = 100Hz 64 UI Jitter Tolerance @ Jitter Frequency = 1kHz 30 UI Jitter Tolerance @ Jitter Frequency = 10kHz 4 UI Jitter Tolerance @ Jitter Frequency = 800kHz 0.15 18 0.20 UI XRT73L04B 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 ELECTRICAL CHARACTERISTICS (CONTINUED), (TA = 25°C, VDD = 3.3V + 5%, UNLESS OTHERWISE SPECIFIED) LINE SIDE PARAMETERS SONET STS-1 APPLICATION TRANSMIT CHARACTERISTICS (SEE FIGURE 5) SYMBOL PARAMETER MIN. TYP. MAX UNITS Transmit Output Pulse Amplitude (Measured with TxLEV=0) 0.65 0.75 0.90 Vpk Transmit Output Pulse Amplitude (Measured with TxLEV=1) 0.90 1.00 1.10 Vpk Transmit Output Pulse Width 8.6 9.65 10.6 ns Transmit Output Pulse Amplitude Ratio 0.90 1.00 1.10 0.02 0.05 Transmit Output Jitter with jitter-free input @ TxClk_(n) UI Receive Line Characteristics Receive Sensitivity (Length of cable) 900 1100 Signal Level to Declare or Clear Loss of Signal (See Table 5 ) feet mV Intrinsic Jitter (all “1’s” pattern) 0.02 UI Jitter Tolerance @ Jitter Frequency = 100Hz 64 UI Jitter Tolerance @ Jitter Frequency = 1kHz 64 UI Jitter Tolerance @ Jitter Frequency = 10kHz 5 UI Jitter Tolerance @ Jitter Frequency = 400kHz 0.15 19 0.35 UI XRT73L04B 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 ELECTRICAL CHARACTERISTICS (CONTINUED), (TA = 25°C, VDD = 3.3V + 5%, UNLESS OTHERWISE SPECIFIED) LINE SIDE PARAMETERS DS3 APPLICATION TRANSMIT CHARACTERISTICS (SEE FIGURE 5) SYMBOL PARAMETER MIN. TYP. MAX UNITS Transmit Output Pulse Amplitude (Measured at 0 feet, TxLEV=0) 0.65 0.75 0.85 Vpk Transmit Output Pulse Amplitude (Measured at 0 feet, TxLEV=1) 0.90 1.00 1.10 Vpk Transmit Output Pulse Width 10.10 11.18 12.28 ns Transmit Output Pulse Amplitude Ratio 0.90 1.00 1.10 0.02 0.05 Transmit Output Jitter with jitter-free input @ TxClk_(n) UI Receive Line Characteristics Receive Sensitivity (Length of cable) 900 1100 Signal Level to Declare or Clear Loss of Signal (See Table 5 ) feet mV Intrinsic Jitter (all “1’s” pattern) 0.02 UI Jitter Tolerance @ Jitter Frequency = 100Hz 64 UI Jitter Tolerance @ Jitter Frequency = 1kHz 64 UI Jitter Tolerance @ Jitter Frequency = 10kHz 5 UI Jitter Tolerance @ Jitter Frequency = 300kHz (Cat II) 20 0.35 0.45 UI XRT73L04B 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 Figure 8, Figure 9 and Figure 10 present the Pulse Template requirements for the E3, DS3 and STS-1 Rates. FIGURE 8. ITU-T G.703 TRANSMIT OUTPUT PULSE TEMPLATE FOR E3 APPLICATIONS 17 ns (14.55 + 2.45) 8.65 ns V = 100% Nominal Pulse 50% 14.55ns 12.1ns (14.55 - 2.45) 10% 0% 10% 20% FIGURE 9. BELLCORE GR-499-CORE TRANSMIT OUTPUT PULSE TEMPLATE FOR DS3 APPLICATIONS DS3 Pulse Template 1.2 1 0.6 Lower Curve Upper Curve 0.4 0.2 0 21 2 3 4 1. 1. 1. 1 1 9 0. 1. 7 8 0. 0. 5 6 0. 4 0. Time, in UI 0. 2 3 0. 0. 0 1 2 1 -0 . 0. 3 -0 . 5 4 -0 . -0 . -0 . 7 6 -0 . -0 . -0 . 9 8 -0 . -0.2 -1 Normalized Amplitude 0.8 XRT73L04B 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 FIGURE 10. BELLCORE GR-253-CORE TRANSMIT OUTPUT PULSE TEMPLATE FOR SONET STS-1 APPLICATIONS STS-1 Pulse Template 1.2 1 Normalized Amplitude 0.8 0.6 Lower Curve Upper Curve 0.4 0.2 0 1. 4 1. 3 1. 2 1 1. 1 0. 9 0. 8 0. 7 0. 6 0. 4 0. 5 0. 3 0. 2 0 0. 1 -0 .1 -0 .2 -0 .3 -0 .4 -0 .5 -0 .6 -0 .7 -0 .8 -0 .9 -1 -0.2 Time, in UI FIGURE 11. MICROPROCESSOR SERIAL INTERFACE DATA STRUCTURE CS SClk 1 SDI R/W 2 A0 3 A1 4 A2 5 A3 6 A4 7 0 8 A6 9 10 11 12 13 14 15 16 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 0 0 0 High Z High Z SDO NOTES: 1. A5 is always "0". 2. R/W = "1" for "Read" Operations 3. R/W = "0" for "Write" Operations 4. A shaded pulse, denotes a “don’t care” value. 22 XRT73L04B 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 ELECTRICAL CHARACTERISTICS (CONTINUED), (TA = 25°C, VDD = 3.3V + 5%, UNLESS OTHERWISE SPECIFIED) MICROPROCESSOR SERIAL INTERFACE TIMING (SEE FIGURE 12) SYMBOL PARAMETER MIN. TYP. MAX UNITS t21 CS Low to Rising Edge of SClk Setup Time 5 ns t22 CS High to Rising Edge of SClk Hold Time 5 ns t23 SDI to Rising Edge of SClk Setup Time 5 ns t24 SDI to Rising Edge of SClk Hold Time 5 ns t25 SClk "Low" Time 65 80 ns t26 SClk "High" Time 65 80 ns t27 SClk Period 160 ns t28 CS Low to Rising Edge of SClk Hold Time 5 ns t29 CS "Inactive" Time 160 ns t30 Falling Edge of SClk to SDO Valid Time 80 ns t31 Falling Edge of SClk to SDO Invalid Time 65 ns t32 Rising edge of CS to High Z t33 Rise/Fall time of SDO Output 100 ns 20 NOTE: The load is 10pF FIGURE 12. TIMING DIAGRAM FOR THE MICROPROCESSOR SERIAL INTERFACE t29 t21 CS t27 t22 t25 SCLK t26 t24 t23 SDI t28 A0 R/W A1 CS SCLK t31 t30 SDO SDI Hi-Z D0 t33 t32 D2 D1 Hi-Z 23 D7 ns XRT73L04B 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 SYSTEM DESCRIPTION a. Operating in the Hardware Mode A functional block diagram of the XRT73L04B E3/ DS3/STS-1 Transceiver IC is presented in Figure 13. The XRT73L04B contains four separate channels with three distinct sections: When the XRT73L04B is operating in the Hardware Mode, then the following is true: 1. The Microprocessor Serial Interface block is disabled. 2. The XRT73L04B is configured via input pin settings. The XRT73L04B can be configured to operate in the Hardware Mode by tying the HOST/(HW) input pin to GND. • The Transmit Section - Channels 0, 1, 2, and 3 • The Receive Section - Channels 0, 1, 2, and 3 • The Microprocessor Serial Interface Section THE TRANSMIT SECTION - CHANNELS 0, 1, 2, AND 3 The Transmit Section, within each Channel, accepts TTL/CMOS level signals from the Terminal Equipment in either a Single-Rail or Dual-Rail format. The Transmit Section then takes this data and does the following: Each of the pins associated with the Microprocessor Serial Interface takes on their alternative role as defined inTable 1. TABLE 1: ROLE OF MICROPROCESSOR SERIAL INTERFACE PINS WHEN THE XRT73L04B IS OPERATING IN THE HARDWARE MODE • Encode this data into the B3ZS format if the DS3 or SONET STS-1 Modes has been selected or into the HDB3 format if the E3 Mode has been selected. • Convert the CMOS level B3ZS or HDB3 encoded data into pulses with shapes that are compliant with the various industry standard pulse template requirements. • Drive these pulses onto the line via the TTIP_(n) and TRing_(n) output pins across a 1:1 Transformer. NOTE: The Transmit Section drives a "1" (or a Mark) onto the line by driving either a positive or negative polarity pulse across the 1:1 Transformer within a given bit period. The Transmit Section drives a "0" (or a Space) onto the line by driving no pulse onto the line. FUNCTION, WHILE IN PIN # PIN NAME 69 CS/(SR/DR) (SR/DR) 70 SClk/(RxOFF) RxOFF 71 SDI/(E3_1) E3_1 72 SDO/(E3_0) E3_0 110 REGR/(RxClkINV) RxClkINV HARDWARE MODE When the XRT73L04B is operating in the Hardware Mode, all of the remaining input pins become active. b. Operating in the HOST Mode The XRT73L04B can be configured to operate in the HOST Mode by tying the HOST/(HW) input pin to VDD. THE RECEIVE SECTION - CHANNELS 0, 1, 2 AND 3 The Receive Section, within each Channel, receives a bipolar signal from the line via the RTIP and RRing signals through a 1:1 Transformer or 0.01µF Capacitor. When the XRT73L04B is operating in the HOST Mode, then the following is true. 1. The Microprocessor Serial Interface block is enabled. Writing the appropriate data into the onchip Command Registers makes many configuration selections. 2. All of the following input pins are disabled and should be connected to ground: • Pins 43, 44, 137 & 138 - TxLEV_(n) The recovered clock and data outputs to the Local Terminal Equipment in the form of CMOS level signals via the RPOS_(n), RNEG_(n) and RxClk_(n) output pins. THE MICROPROCESSOR SERIAL INTERFACE The XRT73L04B can be configured to operate in either the Hardware Mode or the HOST Mode. • Pins 45, 46, 135 & 136 TAOS_(n) • Pin 82, 90, 91 & 99 - REQEN_(n) The XRT73L04B contains four identical channels. The Microprocessor Interface Inputs are common to all channels. The descriptions that follow refer to Channel(n) where (n) represents channel 0, 1, 2 or 3. • Pin 77, 85, 96 & 104 - RLB_(n) • Pin 76, 84, 97 & 105 - LLB_(n) • Pin 107 & 108 - E3_(n) • Pin 73, 83, 98 &106 - STS-1/DS3_(n) 24 XRT73L04B 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 In HOST Mode Operation, the TxOFF input pins can be used to turn on or turn off the Transmit Output Drivers within all Channels concurrently. The intent behind this feature is to permit a system designed for redundancy to quickly switch out a defective line card and switch-in the back-up line card. FIGURE 13. FUNCTIONAL BLOCK DIAGRAM OF THE XRT73L04B E3_(n) RTIP_(n) RRing_(n) STS-1/DS3_(n) Host/(HW) AGC/ Equalizer RLOL_(n) EXClk_(n) RxClkINV Clock Recovery Slicer Peak Detector REQEN_(n) RxOFF Data Recovery LOS Detector LOSTHR Invert RxClk_(n) HDB3/ B3ZS Decoder RPOS_(n) RNEG_(n)/ (LCV_(n)) SDI SDO SClk CS/(SR/DR) Serial Processor Interface RLOS_(n) LLB_(n) Loop MUX RLB_(n) REGR TAOS_(n) TTIP_(n) Pulse Shaping HDB3/ B3ZS Encoder MRing_(n) Device Monitor TNData_(n) Duty Cycle Adjust TRing_(n) MTIP_(n) TPData_(n) Transmit Logic TxClk_(n) TxLEV_(n) Tx Control TxOFF Channel 0 DMO_(n) Channel 1 Channel 2 Channel 3 Notes: 1. (n) = 0, 1, 2 , or 3 for respective Channels 2. Serial Processor Interface input pins are shared by the four Channels in HOST Mode and redefined in Hardware Mode. 1.1 CONFIGURING CHANNEL(n) For the following disscussion the reader should refer toTable 2 to determine the appropriate Address for each command register of each channel in the XRT73L04B. The command register description refers to CR(x)-(n), where (x) = 0 to 7 and (n) refers to a particular channel of the XRT73L04B. 1.0 SELECTING THE DATA RATE Each channel within the XRT73L04B can be configured to support the E3 (34.368 Mbps), DS3 (44.736 Mbps) or the SONET STS-1 (51.84 Mbps) rates. Further, each channel can be configured to operate in a mode/data rate that is independent of the other channels. Two methods are available to select the data rate for each channel of the XRT73L04B. 25 XRT73L04B 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 TABLE 2: HEXADECIMAL ADDRESSES AND BIT FORMATS OF XRT73L04B COMMAND REGISTERS REGISTER BIT-FORMAT ADDRESS COMMAND REGISTER TYPE D4 D3 D2 D1 D0 CHANNEL 0 0x00 CR0-0 RO RLOL_0 RLOS_0 ALOS_0 DLOS_0 DMO_0 0x01 CR1-0 R/W TxOFF_0 TAOS_0 TxClkINV_0 TxLEV_0 Reserved 0x02 CR2-0 R/W Reserved Reserved ALOSDIS_0 DLOSDIS_0 REQEN_0 0x03 CR3-0 R/W (SR/DR)_0 LOSMUT_0 RxOFF RxClk_0INV Reserved 0x04 CR4-0 R/W Reserved STS-1/DS3_0 E3_0 LLB_0 RLB_0 0x05 CR5-0 R/W Reserved Reserved Reserved Reserved Reserved 0x06 CR6-0 R/W Reserved Reserved Reserved Reserved Reserved 0x07 CR7-0 R/W Reserved Reserved Reserved Reserved Reserved CHANNEL 1 0x08 CR0-1 RO RLOL_1 RLOS_1 ALOS_1 DLOS_1 DMO_1 0x09 CR1-1 R/W TxOFF_1 TAOS_1 TxClkINV_1 TxLEV_1 Reserved 0x0A CR2-1 R/W Reserved Reserved ALOSDIS_1 DLOSDIS_1 REQEN_1 0x0B CR3-1 R/W (SR/DR)_1 LOSMUT_1 RxOFF RxClk_1INV Reserved 0x0C CR4-1 R/W Reserved STS-1/DS3_1 E3_1 LLB_1 RLB_1 0x0D CR5-1 R/W Reserved Reserved Reserved Reserved Reserved 0x0E CR6-1 R/W Reserved Reserved Reserved Reserved Reserved 0x0F CR7-1 R/W Reserved Reserved Reserved Reserved Reserved CHANNEL 2 0x10 CR0-2 RO RLOL_2 RLOS_2 ALOS_2 DLOS_2 DMO_2 0x11 CR1-2 R/W TxOFF_2 TAOS_2 TxClkINV_2 TxLEV_2 Reserved 0x12 CR2-2 R/W Reserved Reserved ALOSDIS_2 DLOSDIS_2 REQEN_2 0x13 CR3-2 R/W (SR/DR)_2 LOSMUT_2 RxOFF RxClk_2INV Reserved 0x14 CR4-2 R/W Reserved STS-1/DS3_2 E3_2 LLB_2 RLB_2 0x15 CR5-2 R/W Reserved Reserved Reserved Reserved Reserved 0x16 CR6-2 R/W Reserved Reserved Reserved Reserved Reserved 0x17 CR7-2 R/W Reserved Reserved Reserved Reserved Reserved 26 XRT73L04B 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 TABLE 2: HEXADECIMAL ADDRESSES AND BIT FORMATS OF XRT73L04B COMMAND REGISTERS REGISTER BIT-FORMAT ADDRESS COMMAND REGISTER TYPE D4 D3 D2 D1 D0 CHANNEL3 0x18 CR0-3 RO RLOL_3 RLOS_3 ALOS_3 DLOS_3 DMO_3 0x19 CR1-3 R/W TxOFF_3 TAOS_3 TxClkINV_3 TxLEV_3 Reserved 0x1A CR2-3 R/W Reserved Reserved ALOSDIS_3 DLOSDIS_3 REQEN_3 0x1B CR3-3 R/W (SR/DR)_3 LOSMUT_3 RxOFF RxClk_3INV Reserved 0x1C CR4-3 R/W Reserved STS-1/DS3_3 E3_3 LLB_3 RLB_3 0x1D CR5-3 R/W Reserved Reserved Reserved Reserved Reserved 0x1E CR6-3 R/W Reserved Reserved Reserved Reserved Reserved 0x1F CR7-3 R/W Reserved Reserved Reserved Reserved Reserved The default value for each of the bit-fields within these registers is "0". Address: The register addresses are presented in the Hexadecimal format. a. Operating in the Hardware Mode. In order to configure individual Channels into the appropriate mode, set the E3_(n), and the STS-1/ DS3_(n) input pins (where n = 0, 1, 2, or 3) to the appropriate logic states, as presented below inTable 3. Type: The Command Registers are either Read-Only (RO) type of registers or Read/Write (R/W) type of registers. TABLE 3: SELECTING THE DATA RATE FOR CHANNEL(n) VIA THE E3_(n) AND STS-1/DS3_(n) INPUT PINS (HARDWARE MODE) STATE OF E3_(n) PIN STATE OF STS-1/DS3_(n) PIN MODE OF B3ZS/HDB3 ENCODER/ DECODER BLOCKS E3 (34.368 Mbps) 1 X (Don’t Care) HDB3 DS3 (44.736 Mbps) 0 0 B3ZS STS-1 (51.84 Mbps) 0 1 B3ZS DATA RATE Table 4 relates the values of these two bit-fields to the selected data rates. b. Operating in the HOST Mode. To configure a Channel into the appropriate mode, write the appropriate values into the STS-1/DS3_(n) and E3_(n) bit-fields within the Command Register CR4-(n), as illustrated below (refer to Table 2 for the correct address for each channel). TABLE 4: SELECTING THE DATA RATE FOR CHANNEL(n) VIA THE STS-1/DS3_(n) AND THE E3_(n) BIT-FIELDS WITHIN THE APPROPRIATE COMMAND REGISTER (HOST MODE) COMMAND REGISTER, CR4-(n) D4 D3 D2 X STS-1/(DS3)_(n)) E3_(n) x x x D1 D0 LLB_(n) RLB_(n) x x 27 SELECTED DATA RATE STS-1/DS3_(n) (D3) E3_(n) (D2) E3 X (Don’t Care) 1 DS3 0 0 STS-1 1 0 XRT73L04B 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 2.0 THE TRANSMIT SECTION Figure 13 indicates that the Transmit Section within each Channel of the XRT73L04B consists of the following blocks: 2.1 THE TRANSMIT LOGIC BLOCK The purpose of the Transmit Logic Block is to accept either Dual-Rail or Single-Rail (e.g., a binary data stream) TTL/CMOS level data and timing information from the Terminal Equipment. • Transmit Logic Block 2.1.1 Accepting Dual-Rail Data from the Terminal Equipment Whenever the XRT73L04B accepts Dual-Rail data from the Terminal Equipment, it does so via the following input signals: • TxClk_(n) Duty Cycle Adjust Block • HDB3/(B3ZS) Encoder • Pulse Shaping Block The purpose of the Transmit Section is to take TTL/ CMOS level data from the terminal equipment and encode it into a format such that it can: • TPData_(n) • TNData_(n) 1. Be efficiently transmitted over coaxial cable at E3, DS3, or STS-1 data rates. 2. Be reliably received by the Remote Terminal Equipment at the other end of the E3, DS3, or STS-1 data link. 3. Comply with the applicable pulse template requirements. • TxClk_(n) Figure 14 illustrates the typical interface for the transmission of data in a Dual-Rail Format between the Terminal Equipment and the Transmit Section of the XRT73L04B. FIGURE 14. THE TYPICAL INTERFACE FOR THE TRANSMISSION OF DATA IN A DUAL-RAIL FORMAT FROM THE TRANSMITTING TERMINAL EQUIPMENT TO THE TRANSMIT SECTION OF A CHANNEL Terminal Equipment (E3/DS3 or STS-1 Framer) TxPOS TPData TxNEG TNData TxLineClk TxClk Transmit Logic Block Exar E3/DS3/STS-1 LIU The manner that the LIU handles Dual-Rail data is described below and illustrated in Figure 15. The Transmit Section (of a Channel) typically samples the data on the TPData_(n) and TNData_(n) input pins on the falling edge of TxClk_(n). FIGURE 15. THE XRT73L04B SAMPLES THE DATA ON THE TPDATA AND TNDATA INPUT PINS Data 1 1 TPData TNData TxClk 28 0 XRT73L04B 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 TxClk_(n) is the clock signal that is of the selected data rate frequency, E3 = 34.368 MHz, DS3 = 44.736 MHz and STS-1 = 51.84 MHz. If the Transmit Section samples a "1" on the TPData_(n) input pin, then the Transmit Section of the device generates a positive polarity pulse via the TTIP_(n) and TRing_(n) output pins across a 1:1 transformer. If the Transmit Section samples a "1" on the TNData_(n) input pin, then the Transmit Section of the device generates a negative polarity pulse via the TTIP_(n) and TRing_(n) output pins across a 1:1 transformer. COMMAND REGISTER CR3-(n) D4 D3 D2 D1 D0 (SR/DR)_(n) LOSMUT_(n) RxOFF RxClk_(n)INV Reserved 1 x x x x The Transmit Section (of each channel) samples this input pin on the falling edge of the TxClk_(n) clock signal and encodes this data into the appropriate bipolar line signal across the TTIP_(n) and TRing_(n) output pins. 2.1.2 Accepting Single-Rail Data from the Terminal Equipment To transmit data in a Single-Rail data from the Terminal Equipment, configure the XRT73L04B in the HOST Mode. To Configure Channel(n) to accept Single-Rail Data from the Terminal Equipment: NOTES: 1. In this mode, the Transmit Logic Block ignores the TNData_(n) input pin. 2. If the Transmit Section of a given channel is configured to accept Single-Rail data from the Terminal Equipment, the B3ZS/HDB3 Encoder must be enabled. Write a "1" into the (SR/DR)_(n) bit-field, within Command Register CR3-(n) shown below. (Please refer toTable 2 for the Address of the individual (n) channel. Figure 16 Illustrates the behavior of the TPData_(n) and TxClk_(n) signals when the Transmit Logic Block has been configured to accept Single-Rail data from the Terminal Equipment. FIGURE 16. THE BEHAVIOR OF THE TPDATA AND TXCLK INPUT SGNALS, WHILE THE TRANSMIT LOGIC BLOCK IS ACCEPTING SINGLE-RAIL DATA FROM THE TERMINAL EQUIPMENT Data 1 1 0 TPData TxClk 2.2 THE TRANSMIT CLOCK DUTY CYCLE ADJUST CIR- The Transmit Clock Duty Cycle Adjust Circuitry accepts clock pulses via the TxClk_(n) input pin at duty cycles ranging from 30% to 70% and converts them to a 50% duty cycle. CUITRY The on-chip Pulse-Shaping circuitry within the Transmit Section of each Channel in the XRT73L04B generates pulses of the appropriate shapes and width to meet the applicable pulse template requirements. The widths of these output pulses are defined by the width of the half-period pulses within the TxClk_(n) signal. 2.3 THE HDB3/B3ZS ENCODER BLOCK The purpose of the HDB3/B3ZS Encoder Block is to aid in the Clock Recovery process at the Remote Terminal Equipment by ensuring an upper limit on the number of consecutive zeros that can exist within the line signal. However, if the widths of the pulses within the TxClk_(n) clock signal are allowed to vary significantly, this could jeopardize the chip’s ability to generate Transmit Output pulses of the appropriate width and thereby not meet the Pulse Template requirement specification. Consequently, the chip’s ability to generate compliant pulses could depend upon the duty cycle of the clock signal applied to the TxClk_(n) input pin. 2.3.1 B3ZS Encoding If the XRT73L04B has been configured to operate in the DS3 or SONET STS-1 Modes, then the HDB3/ B3ZS Encoder blocks operate in the B3ZS Mode. When the Encoder is operating in this mode, it parses through and searches the Transmit Binary Data Stream from the Transmit Logic Block for the occur- 29 XRT73L04B 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 rence of three (3) consecutive zeros (e.g., "000"). If the B3ZS Encoder finds an occurrence of three consecutive zeros, then it substitutes these three "0’s", with either a "00V" or a "B0V" pattern. "V" represents a Bipolar Violation (e.g., a bipolar pulse that violates the Alternating Polarity requirements of the AMI line code). The B3ZS Encoder decides whether to substitute with either the “00V" or the "B0V" pattern in order to insure that an odd number of bipolar pulses exist between any two consecutive violation pulses. Where: "B" represents a Bipolar pulse that is compliant with the Alternating Polarity requirements of the AMI (Alternate Mark Inversion) line code; and Figure 17 illustrates the B3ZS Encoder at work with two separate strings of three (or more) consecutive zeros FIGURE 17. AN EXAMPLE OF B3ZS ENCODING TClk TPOS SR data 1 0 1 1 0 0 0 0 0 1 1 1 1 0 1 1 0 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1 0 0 Encoded PDATA 1 0 0 1 0 0 1 0 0 0 1 0 1 0 0 1 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 Encoded NDATA 0 0 1 0 0 0 0 0 0 1 0 1 0 0 1 0 0 1 0 0 0 1 0 1 0 1 0 0 1 0 0 0 0 0 0 0 V Line signal B 2.3.2 HDB3 Encoding If the XRT73L04B is configured to operate in the E3 Mode, then the HDB3/B3ZS Encoder blocks operate in the HDB3 Mode. When the Encoder is operating in this mode, it parses through and searches the Transmit Data Stream from the Transmit Logic Block for the occurrence of four (4) consecutive zeros (e.g., "0000"). If the HDB3 Encoder finds an occurrence of four consecutive zeros, then it substitutes these four 0 V "0’s", with either a "000V" or a "B00V" pattern. The HDB3 Encoder decides whether to substitute with either the "000V" or the "B00V" pattern in order to insure that an odd number of bipolar pulses exist between any two consecutive violation pulses. Figure 18 illustrates the HDB3 Encoder at work with two separate strings of four (or more) consecutive zeros. FIGURE 18. AN EXAMPLE OF HDB3 ENCODING TClk TPOS SR data 1 0 1 1 0 0 0 0 0 1 1 1 1 0 1 1 0 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1 0 0 Encoded PDATA 1 0 0 1 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 Encoded NDATA 0 0 1 0 0 0 0 0 0 1 0 1 0 0 1 0 0 1 0 0 0 1 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 V Line signal B 0 0 V 2.3.3 Disabling the HDB3/B3ZS Encoder The XRT73L04B HDB3/B3ZS Encoder can be disabled by two methods. The HBD3/B3ZS Encoder blocks within all channels are disabled by setting the CS/(SR/DR) input pin to "1". a. Operating in the Hardware Mode. NOTE: By executing this step the HDB3/B3ZS Encoder and Decoder blocks in all channels of the XRT73L04B are globally disabled. 30 XRT73L04B 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 a. Operating in the HOST Mode. Disable the HDB3/B3ZS Encoder block within Channel(n) by setting the (SR/DR)_(n) bit-field within Command Register (CR3-(n)) to "1" as illustrated below. When the XRT73L04B is operating in the HOST Mode, then the HDB3/B3ZS Encoders within each channel can be individually enabled or disabled. COMMAND REGISTER CR3-(n) D4 D3 D2 D1 D0 (SR/DR)_(n) LOSMUT_(n) RxOFF RxClk_(n)INV Reserved 1 X X X X NOTE: This method can only be used if the XRT73L04B is operating in the HOST Mode. uration of each channel to transmit an output pulse which is compliant to either of the following pulse template requirements when measured at the Digital Cross Connect System. Each of these Bellcore specifications state that the cable length between the Transmit Output and the Digital Cross Connect system can range anywhere from 0 to 450 feet. If either of these methods are used to disable the HDB3/B3ZS Encoder, then the LIU transmits the data as received via the TPData_(n) and TNData_(n) input pins. 2.4 THE TRANSMIT PULSE SHAPING CIRCUITRY The Transmit Pulse Shaper Circuitry consists of a Transmit Line Build-Out circuit which can be enabled or disabled by setting the TxLEV_(n) input pin or TxLEV_(n) bit-field to “High”or "Low". The purpose of the Transmit Line Build-Out circuit is to permit config- The Isolated DSX-3 Pulse Template Requirement per Bellcore GR-499-CORE is illustrated in Figure 19 and the Isolated STSX-1 Pulse Template Requirement per Bellcore GR-253-CORE is illustrated in Figure 20. FIGURE 19. THE BELLCORE GR-499-CORE TRANSMIT OUTPUT PULSE TEMPLATE FOR DS3 APPLICATIONS D S3 Pu lse T em p late 1.2 1 0.6 Lower Curve Upper Curve 0.4 0.2 0 Tim e , in UI 31 2 3 4 1. 1. 1 1. 1. 9 0. 1 7 8 0. 0. 5 6 0. 0. 3 4 0. 2 0. 0. 0 1 0. .1 -0 .3 .2 -0 -0 .5 .4 -0 .6 -0 -0 .7 .8 -0 -0 -1 .9 -0.2 -0 Norm a lize d Am plitude 0.8 XRT73L04B 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 . FIGURE 20. THE BELLCORE GR-253-CORE TRANSMIT OUTPUT PULSE TEMPLATE FOR SONET STS-1 APPLICATIONS ST S-1 Pulse T emplate 1.2 1 Norm a lize d Am plitude 0.8 0.6 Lower Curve Upper Curve 0.4 0.2 0 2 3 4 1. 1. 1. 1 9 0. 1 8 0. 1. 6 7 0. 5 0. 0. 3 4 0. 0. 2 0. 0 -0 . 1 1 -0 . 0. 3 2 -0 . 5 4 6 -0 . -0 . -0 . 7 -0 . -0 . 9 8 -0 . -1 -0.2 Time, in UI 2.4.1 Enabling the Transmit Line Build-Out Circuit If the Transmit Line Build-Out Circuit is enabled, then the Transmit Section of the Channel outputs shaped pulses onto the line via the TTIP_(n) and TRing_(n) output pins. Enable the Transmit Line Build-Out circuit for each channel by doing the following: a. Operating in the Hardware Mode Set the TxLEV_(n) input pin to “Low". b. Operating in the HOST Mode Set the TxLEV_(n) bit-field to "0", as illustrated below. COMMAND REGISTER, CR1-(n) D4 D3 D2 D1 D0 TxOFF_(n) TAOS_(n) TxClkINV_(n) TxLEV_(n) Reserved 0 X X 0 X 2.4.2 Disabling the Transmit Line Build-Out Circuit If the Transmit Line Build-Out circuit is disabled, then the XRT73L04B outputs partially shaped pulses onto the line via the TTIP_(n) and TRing_(n) output pins. Disable the Transmit Line Build-Out circuit by doing the following: a. Operating in the Hardware Mode Set the TxLEV_(n) input pin to “High". b. Operating in the HOST Mode Set the TxLEV_(n) bit-field to "1" as illustrated below. 32 XRT73L04B 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 COMMAND REGISTER, CR1-(n) D4 D3 D2 D1 D0 TxOFF_(n) TAOS_(n) TxClkINV_(n) TxLEV_(n) Reserved 0 X X 1 X output pins. The cable loss that these pulses experience over long cable lengths (e.g., greater than 225 feet) cause these pulses to be properly shaped and comply with the appropriate pulse template requirement. 2.4.3 Design Guideline for Setting the Transmit Line Build-Out Circuit The TxLEV_(n) input pins or bit-fields should be set based upon the overall cable length between the Transmitting Terminal and the Digital Cross Connect system where the pulse template measurements are made. 2.4.4 The Transmit Line Build-Out Circuit and E3 Applications The ITU-T G.703 Pulse Template Requirements for E3 states that the E3 transmit output pulse should be measured at the Secondary Side of the Transmit Output Transformer for Pulse Template compliance. In other words, there is no Digital Cross Connect System pulse template requirement for E3. Consequently, the Transmit Line Build-Out circuit within a given Channel is disabled whenever that channel has been configured to operate in the E3 Mode. If the cable length between the Transmitting Terminal and the DSX-3 or STSX-1 is less than 225 feet, enable the Transmit Line Build-Out circuit by setting the TxLEV_(n) input pin or bit-field to "0". NOTE: In this case, the configured channel outputs shaped (e.g., not square-wave) pulses onto the line via its TTIP_(n) and TRing_(n) output pins. The shape of this output pulse is such that it complies with the pulse template requirements even when subjected to cable loss ranging from 0 to 225 feet. 2.5 INTERFACING THE TRANSMIT SECTIONS OF THE XRT73L04B TO THE LINE The E3, DS3 and SONET STS-1 specification documents all state that line signals transmitted over coaxial cable are to be terminated with 75 Ohm resistor. Interface the Transmit Section of the XRT73L04B in the manner illustrated in Figure 21. If the cable length between the Transmitting Terminal and the DSX-3 or STSX-1 is greater than 225 feet, disable the Transmit Line Build-Out circuit by setting the TxLEV_(n) input pin or bit-field to "1". NOTE: In this case, the configured channel outputs partially shaped pulses onto the line via the TTIP_(n) and TRing_(n) FIGURE 21. RECOMMENDED SCHEMATIC FOR INTERFACING THE TRANSMIT SECTION OF THE XRT73L04B TO THE LINE TTIP_(n) Channel (n) TxPOS_(n) TxNEG_(n) TxLineClk_(n) R1 31.6Ω J1 BNC TPData_(n) TNData_(n) TxClk_(n) 1:1 R2 31.6Ω TRing_(n) Only One Channel Shown 33 XRT73L04B 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 TRANSFORMER RECOMMENDATIONS PARAMETER VALUE Turns Ratio 1:1 Primary Inductance 40µH Isolation Voltage 1500Vrms Leakage Inductance 0.6µH PART NUMBER VENDOR INSULATION PACKAGE TYPE PE-68629 Pulse 3000V Large Thru-Hole PE-65966 Pulse 1500V Small Thru-Hole PE-65967 Pulse 1500V Small SMT T3001 Pulse 1500V Small SMT TG01-0406NS Halo 1500V Small SMT TTI 7601-SM Trans-Power 1500V Small SMT TRANSFORMER VENDOR INFORMATION Pulse Halo Electronics Corporate Office Corporate Office 12220 World Trade Drive P.O. Box 5826 San Diego, CA 92128 Redwood City, CA 94063 Tel: (858)-674-8100 Tel: (650)568-5800 FAX: (858)-674-8262 FAX: (650)568-6165 Europe Email: info@haloelectronics.com 1 & 2 Huxley Road Website: http://www.haloelectronics.com The Surrey Research Park Guildford, Surrey GU2 5RE Transpower Technologies, Inc. United Kingdom Corporate Office Tel: 44-1483-401700 Park Center West Building FAX: 44-1483-401701 9805 Double R Blvd, Suite # 100 Asia Reno, NV 89511 150 Kampong Ampat (800)500-5930 or (775)852-0140 #07-01/02 Email: info@trans-power.com KA Centre Website: http://www.trans-power.com Singapore 368324 Tel: 65-287-8998 FAX: 65-280-0080 Website: http://www.pulseeng.com 34 XRT73L04B 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 3.0 THE RECEIVE SECTION Figure 13 indicates the Receive Section consists of the following blocks: line and encode it back into the TTL/CMOS format where it can be received and processed by the Terminal Equipment. • AGC/Equalizer 3.1 INTERFACING THE RECEIVE SECTIONS OF THE XRT73L04B TO THE LINE The design of the Receive Circuitry should be transformer-coupled to the Receive Section to the line. The specification documents for E3, DS3, and STS-1 all specify 75 Ohm termination loads when transmitting over coaxial cable. The recommended method to interface the Receive Section to the line in a manner is shown in Figure 22. • Peak Detector • Slicer • Clock Recovery PLL • Data Recovery • HDB3/B3ZS Decoder The purpose of the Receive Section is to take an incoming attenuated/distorted bipolar signal from the FIGURE 22. RECOMMENDED SCHEMATIC FOR INTERFACING THE RECEIVE SECTION OF THE XRT73L04B TO THE LINE (TRANSFORMER-COUPLING) RTIP_(n) Channel (n) RxPOS_(n) RxNEG_(n) RxClk_(n) R1 37.4Ω RPOS_(n) RNEG_(n) RxClk_(n) R2 37.4Ω RRing_(n) Only One Channel Shown 35 T1 C1 0.01uf 1:1 J1 BNC XRT73L04B 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 Equalizer attempts to restore the shape of the line signal so that the transmitted data and clock can be recovered reliably. 3.2 THE RECEIVE EQUALIZER BLOCK The purpose of this block is to equalize the incoming distorted signal due to cable loss. The Receive . FIGURE 23. THE TYPICAL APPLICATION FOR THE SYSTEM INSTALLER Digital Cross-Connect System Transmitting Terminal 0 to 450 feet of Cable Pulses that are compliant to the Isolated DSX-3 or STSX-1 Pulse Template Requirement DSX-3 or STSX-1 0 to 450 feet of Cable Receiving Terminal 3.2.1 izer Guidelines for Setting the Receive Equal- Equalizer by setting either the REQEN_(n) input pin “high” or the REQEN_(n) bit-field to “1”. The remainder of this section provides an explanation why we recommend enabling the Receive Equalizer for these applications. This data sheet presents guidelines for setting the Receive Equalizer, for the following conditions. 1. If the overall cable length, from the local Receiving Terminal to the Remote Transmitting Terminal is NOT known. 2. If the overall cable length, from the Local Receiving Terminal to the remote Transmitting Terminal is known. 3.2.1.1 If the Overall Cable Length is NOT Known 3.2.1.1.1 The Use of the Receive Equalizer in a Typical DS3 or STS-1 Application Most System Manufacturers of equipment supporting DS3 and STS-1 lines, interface their equipment to either a DSX-3 or STSX-1 Cross-Connect. While installing their equipment the Transmit Line Build-Out circuit is set to the proper setting that makes the transmit output pulse compliant with the Isolated DSX-3 or STSX-1 Pulse Template requirements. For the XRT73L04B, this is achieved by setting the TXLEV_(n) input pin or bit-field to the appropriate level. This section presents recommendations on what state to set the Receive Equalizer when the overall cable-length, from the local Receiving Terminal to the remote Transmitting Terminal is NOT known. For DS3, STS-1 and E3 applications, enable the Receive 36 XRT73L04B 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 When the System Manufacturer is interfacing the Receive Section of the XRT73L04B to the Cross-Connect, they should be aware of the following facts: In E3 System installation, it is recommended that the Receive Equalizer of the XRT73L04B be enabled by pulling the REQEN_(n) input pins “High” or by setting the REQEN_(n) bit-fields to “1”. 1. All DS3 or STS-1 line signals that are present at either the DSX-3 or the STSX-1 Cross Connect are required to meet the Isolated Pulse Template Requirements per Bellcore GR-499-CORE for DS3 applications, or Bellcore GR-253-CORE for STS-1 applications. NOTE: The results of extensive testing indicates that when the Receive Equalizer is enabled, the XRT73L04B is capable of receiving an E3 line signal with anywhere from 0 to 12dB of cable loss over the Industrial Temperature range. • Design Considerations for E3 Applications or if the Overall Cable Length is known 2. Bellcore documents state that the amplitude of these pulses at the DSX-3 or STSX-1 location can range in amplitude from 360mVpk to 850mVpk. If during System Installation the overall cable length is known, then in order to optimize the performance of the XRT73L04B in terms of receive intrinsic jitter, etc., enable or disable the Receive Equalizer based upon the following recommendations: Bellcore documents stipulate that the Receiving Terminal must be able to receive the pulse template compliant line signal over a cable length of 0 to 450 feet from the DSX-3 or the STSX-1 Cross-Connect location. The Receive Equalizer should be turned ON if the Receive Section of a given channel is going to receive a line signal with an overall cable length of 300 feet or greater. Conversely, turn OFF the Receive Equalizer if the Receive Section of a given channel is going to receive a line signal over a cable length of less than 300 feet. These facts are reflected in Figure 23. Design Considerations for DS3 and STS-1 Applications When installing equipment into environments depicted in Figure 23, the system installation personnel may be able to determine the cable length between the local terminal equipment and the DSX-3/STSX-1 Cross-Connect Patch-Panel. The cable length between the local terminal equipment and the DSX-3/ STSX-1 Cross-Connect Patch Panel ranges between 0 and 450 feet. NOTES: 1. If the Receive Equalizer block is turned ON when it is receiving a line signal over short cable length, the received line signal may be over-equalized which could degrade performance by increasing the amount of jitter that exists in the recovered data and clock signals or by creating bit-errors 2. The Receive Equalizer has been designed to counter the frequency-dependent cable loss that a line signal experiences as it travels from the transmitting terminal to the receiving terminal. However, the Receive Equalizer was not designed to counter flat loss where all of the Fourier frequency components within the line signal are subject to the same amount of attenuation. Flat loss is handled by the AGC block. It is extremely unlikely that the system installation personnel will know the cable length between the DSX-3/STSX-1 Cross-Connect Patch-Panel and the remote terminal equipment. Therefore, we recommend that the Receive Equalizer be enabled by setting the REQEN_(n) input pin or bit-field to “1”. The only time that the Receive Equalizer should be disabled is when there is an off-chip equilizer in the Receive path between the DSX-3/STSX-1 CrossConnect and the RTIP_(n)/RRING_(n) input pins, or in applications where the Receiver is directly monitoring the transmit output signal directly. 3.2.1.2 tions Disable the Receive Equalizer block by doing either of the following. a. Operating in the Hardware Mode Setting the REQEN_(n) input pin “Low". b. Operating in the HOST Mode Design Considerations for E3 Applica- Writing a "0" to the REQEN_(n) bit-field within Command Register CR2, as illustrated below. COMMAND REGISTER CR-2(n) D4 D3 D2 D1 D0 Reserved Reserved ALOSDIS_(n) DLOSDIS_(n) REQEN_(n) X X X X 0 37 XRT73L04B 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 3.3 CLOCK RECOVERY PLL The purpose of the Clock Recovery PLL is to track the incoming Dual-Rail data stream and to derive and generate a recovered clock signal. 3.4 THE HDB3/B3ZS DECODER The Remote Transmitting Terminal typically encodes the line signal into some sort of Zero Suppression Line Code (e.g., HDB3 for E3, and B3ZS for DS3 and STS-1). The purpose of this encoding activity was to aid in the Clock Recovery process of this data within the Near-End Receiving Terminal. However, once the data has made it across the E3, DS3 or STS-1 Transport Medium and has been recovered by the Clock Recovery PLL, it is now necessary to restore the original content of the data. Hence, the purpose of the HDB3/B3ZS Decoding block is to restore the data transmitted over the E3, DS3 or STS-1 line to its original content prior to Zero Suppression Coding. It is important to note that the Clock Recovery PLL requires a line rate clock signal at the EXClk_(n) input pin. The Clock Recovery PLL operates in one of two modes: • The Training Mode. • The Data/Clock Recovery Mode 3.3.1 The Training Mode If a given channel is not receiving a line signal via the RTIP and RRing input pins, or if the frequency difference between the line signal and that applied via the EXClk_(n) input pin exceeds 0.5%, then the channel operates in the Training Mode. When the channel is operating in the Training Mode, it does the following: 3.4.1 B3ZS Decoding (DS3/STS-1 Applications) If the XRT73L04B is configured to operate in the DS3 or STS-1 Modes, then the HDB3/B3ZS Decoding Blocks performs B3ZS Decoding. When the Decoders are operating in this mode, each of the Decoders parses through its respective incoming Dual-Rail data and checks for the occurrence of either a “00V" or a "B0V" pattern. If the B3ZS Decoder detects this particular pattern, then it substitutes these bits with a "000" pattern. a. Declare a Loss of Lock indication by toggling its respective RLOL_(n) output pin “High". b. Output a clock signal via the RxClk_(n) output pins which is derived from the signal applied to the EXClk_(n) input pin. NOTE: If the B3ZS Decoder detects any bipolar violations that is not in accordance with the B3ZS Line Code format, or if the B3ZS Decoder detects a string of 3 (or more) consecutive "0’s” in the incoming line signal, then the B3ZS Decoder flags this event as a Line Code Violation by pulsing the LCV output pin “High". 3.3.2 The Data/Clock Recovery Mode If the frequency difference between the line signal and that applied via the EXClk_(n) input pin is less than 0.5%, then the channel operates in the Data/ Clock Recovery mode. In this mode, the Clock Recovery PLL locks onto the line signal via the RTIP and RRing input pins. Figure 24 illustrates the B3ZS Decoder at work with two separate Zero Suppression patterns in the incoming Dual-Rail Data Stream. FIGURE 24. AN EXAMPLE OF B3ZS DECODING 0 0 V Line Signal B 0 V RCLK RPOS RNEG Data 0 1 0 1 1 0 0 0 1 0 1 1 1 1 0 1 1 0 1 1 0 0 1 1 1 3.4.2 HDB3 Decoding (E3 Applications) If the XRT73L04B is configured to operate in the E3 Mode, then each of the HDB3/B3ZS Decoding Blocks performs HDB3 Decoding. When the Decoders are 0 0 0 1 operating in this mode, they each parse through the incoming Dual-Rail data and check for the occurrence of either a "000V" or a "B00V" pattern. If the HDB3 38 XRT73L04B 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 Decoder detects this particular pattern, then it substitutes these bits with a “0000" pattern. Figure 25 illustrates the HDB3 Decoder at work with two separate Zero Suppression patterns, in the incoming Dual-Rail Data Stream. FIGURE 25. AN EXAMPLE OF HDB3 DECODING 0 0 0 V Line Signal B 0 0 V RCLK RPOS RNEG Data 0 1 0 1 1 0 0 0 0 0 1 1 1 1 0 1 1 0 1 1 0 0 1 1 0 0 0 0 1 NOTE: If the HDB3 Decoder detects any bipolar violation (e.g., "V") pulses that is not in accordance with the HDB3 Line Code format, or if the HDB3 Decoder detects a string of 4 (or more) "0’s" in the incoming line signal, then the HDB3 Decoder flags this event as a Line Code Violation by pulsing the LCV output pin “High". 3.4.3 The XRT73L04B can enable or disable the HDB3/ B3ZS Decoder blocks by either of the following means. a. Operating in the HOST Mode Enable the HDB3/B3ZS Decoder block of Channel(n) by writing a "0" into the (SR/DR)_(n) bit-field within Command Register CR3-(n), as illustrated below. Configuring the HDB3/B3ZS Decoder COMMAND REGISTER CR3-(n) D4 D3 D2 D1 D0 (SR/DR)_(n) LOSMUT_(n) RxOFF RxClk_(n)INV Reserved 0 X X X X declares a Loss of Signal (LOS) condition. The channel declares the LOS condition by toggling its respective RLOS_(n) output pin “High" and by setting its corresponding RLOS_(n) bit field within Command Register 0 (or Command Register 8) to "1". b. Operating in the Hardware Mode To globally enable all HDB3/B3ZS Decoder blocks, pull the CS/(SR/DR)_(n) input pin "Low". To globally disable all HDB3/B3ZS Decoder blocks and configure the device to transmit and receive in an AMI format by pulling the CS/(SR/DR)_(n) input pin "High". Conversely, if the channel determines that the incoming line signal has been restored (e.g., there is sufficient amplitude and pulses in the incoming line signal), then it clears the LOS condition by toggling its respective RLOS_(n) output pin “Low" and setting its corresponding RLOS_(n) bit-field to "0". 3.5 LOS DECLARATION/CLEARANCE Each channel contains circuitry that monitors the following two parameters associated with the incoming line signals. 1. The amplitude of the incoming line signal via the RTIP and RRing inputs. 2. The number of pulses detected in the incoming line signal within a certain amount of time. If a given channel determines that the incoming line signal is missing either due to insufficient amplitude or a lack of pulses in the incoming line signal, then it In general, the LOS Declaration/Clearance scheme that is employed in the XRT73L04B is based upon ITU-T Recommendation G.775 for both E3 and DS3 applications. 3.5.1 The LOS Declaration/Clearance Criteria for E3 Applications 39 XRT73L04B 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 When the XRT73L04B is operating in the E3 Mode, a given channel declares an LOS Condition if its receive line signal amplitude drops to -35dB or below. Further, the channel clears the LOS Condition if its receive line signal amplitude rises back to -15dB or above. Figure 26 illustrates the signal levels at which each channel of the XRT73L04B declares and clears LOS. FIGURE 26. THE SIGNAL LEVELS THAT THE XRT73L04B DECLARES AND CLEARS LOS 0 dB Maximum Cable Loss for E3 LOS Signal Must be Cleared -12 dB -15dB LOS Signal may be Cleared or Declared -35dB LOS Signal Must be Declared Timing Requirements associated with Declaring and Clearing the LOS Indicator bit-periods) after the actual time the LOS condition occurred. Further, the channel clears the LOS indicator within 10 to 255 UI after restoration of the incoming line signal. Figure 27 illustrates the LOS Declaration and Clearance behavior in response to the Loss of Signal event and then the restoration of the signal. The XRT73L04B was designed to meet the ITU-T G.775 specification timing requirements for declaring and clearing the LOS indicator. In particular, a channel declares an LOS between 10 and 255 UI (or E3 40 XRT73L04B 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 FIGURE 27. THE BEHAVIOR OF THE LOS OUTPUT INDICATOR IN RESPONSE TO THE LOSS OF SIGNAL AND THE RESSIGNAL TORATION OF Actual Occurrence of LOS Condition Line Signal is Restored RTIP/ RRing 255 UI 10 UI Time Range for LOS Declaration 10 UI 255 UI RLOS Output Pin 0 UI 0 UI G.775 Compliance Time Range for LOS Clearance 3.5.2 The LOS Declaration/Clearance Criteria for DS3 and STS-1 Applications When the XRT73L04B is operating in the DS3 or STS-1 Mode, then each channel declares and clears LOS based upon the following two criteria. G.775 Compliance 1. The Analog LOS (ALOS) Declaration/Clearance Criteria A channel declares an Analog LOS (ALOS_(n)) Condition if the amplitude of the incoming line signal drops below a specific amplitude as defined by the voltage at the LOSTHR input pin, and whether the Receive Equalizer is enabled or not. • Analog LOS (ALOS) Declaration/Clearance Criteria Table 5 presents the various voltage levels at the LOSTHR input pin, the state of the Receive Equalizer and the corresponding ALOS (Analog LOS) threshold amplitudes. • Digital LOS (DLOS) Declaration/Clearance Criteria In the DS3 Mode, the LOS output (RLOS) is simply the logical "OR" of the ALOS and DLOS states. TABLE 5: THE ALOS (ANALOG LOS) DECLARE AND CLEAR THRESHOLDS FOR A GIVEN SETTING OF LOSTHR AND REQEN (DS3 AND STS-1 APPLICATIONS) APPLICATION REQEN SETTING LOSTHR SETTING SIGNAL LEVEL TO DECLARE ALOS SGNAL LEVEL TO CLEAR ALOS DS3 1 1 90mV 0 1