XRT73LC00A
E3/DS3/STS-1 LINE INTERFACE UNIT
MAY 2011
REV. 1.0.2
GENERAL DESCRIPTION
FEATURES
The XRT73LC00A DS3/E3/STS-1 Line Interface Unit
is a low power CMOS version of the XRT73L00A and
consists of a line transmitter and receiver integrated
on a single chip and is designed for DS3, E3 or
SONET STS-1 applications.
Incorporates an improved Timing Recovery circuit
XRT73LC00A can be configured to support the E3
(34.368 Mbps), DS3 (44.736 Mbps) or the SONET
STS-1 (51.84 Mbps) rates.
In the transmit direction, the XRT73LC00A encodes
input data to either B3ZS (for DS3/STS-1
applications) or HDB3 (for E3 applications) format
and converts the data into the appropriate pulse
shapes for transmission over coaxial cable via a 1:1
transformer.
In the receive direction the XRT73LC00A performs
equalization on incoming signals, performs Clock
Recovery, decodes data from either B3ZS or HDB3
format, converts the receive data into TTL/CMOS
format, checks for LOS or LOL conditions and detects
and declares the occurrence of line code violations.
The XRT73LC00A also contains a 4-Wire
Microprocessor Serial Interface for accessing the onchip Command registers.
and is pin and functional compatible to XRT73L00A
Meets
E3/DS3/STS-1
Requirements
Jitter
Tolerance
Full Loop-Back Capability
Transmit and Receive Power Down Modes
Full Redundancy Support
Contains a 4-Wire Microprocessor Serial Interface
Uses Minimum External components
Low Power CMOS Design
Single +3.3V Power Supply
5 V Tolerant pins
-40°C to +85°C Operating Temperature Range
Available in a 44 pin TQFP package
APPLICATIONS
Interfaces to E3, DS3 or SONET STS-1 Networks
CSU/DSU Equipment
PCM Test Equipment
Fiber Optic Terminals
Multiplexers
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
XRT73LC00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
FIGURE 1. BLOCK DIAGRAM OF THE XRT73LC00A
E3
RTIP
RRING
STS-1/DS3
Host/(HW )
AGC/
Equalizer
RLOL EXCLK
Invert
LCV/(RCLK2)
Data
Recovery
LOS Detector
LOSTHR
RCLKINV
RCLK1
Clock
Recovery
Slicer
Peak
Detector
REQDIS
ICT
HDB3/
B3ZS
Decoder
SClk
CS
RNEG
DR/SR
SDI
SDO/(LCV)
RPOS
Serial
Processor
Interface
RLOS
LLB
Loop MUX
RLB
ENDECDIS
REGRESET
TAOS
TTIP
Pulse
Shaping
HDB3/
B3ZS
Encoder
TRING
M TIP
M RING
Device
Monitor
TPDATA
Transm it
Logic
TNDATA
Duty Cycle Adjust
TClk
TXLEV
Tx
Control
TXOFF
DM O
ORDERING INFORMATION
PART NUMBER
PACKAGE TYPE
OPERATING TEMPERATURE RANGE
XRT73LC00AIV
44 Pin TQFP (10mm x 10mm)
-40°C to +85°C
2
XRT73LC00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
MRING
TxAVDD
TTIP
TRING
TxAGND
TNDATA
TPDATA
TCLK
TXOFF
44
43
42
41
40
39
38
37
36
35
ICT
MTIP
FIGURE 2. PIN OUT OF THE XRT73LC00A IN THE 44 PIN TQFP
34
TxLEV
1
33
RPOS
TAOS
2
32
RNEG
TxAVDD
3
31
RCLK1
DMO
4
30
LCV/(RCLK2)
TxAGND
5
29
RxDVDD
AGND
6
28
RxDGND
RxAGND
7
27
EXCLK
RTIP
8
26
DVDD
RRING
9
25
DGND
RxAVDD
10
24
RLOS
REGRESET/
RCLK2INV
11
23
RLOL
LLB
RLB
STS1/DS3
18
19
20
21
22
CS/(DR/SR)
LOSTHR
17
SCLK/(ENDECDIS)
16
SDO/(LCV)
15
SDI/(LOSMUTEN)
14
HOST/HW
13
E3
12
REQDIS
XRT73LC00A
(Top View)
3
XRT73LC00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
TABLE OF CONTENTS
FEATURES ..................................................................................................................................................1
APPLICATIONS ...........................................................................................................................................1
FIGURE 1. BLOCK DIAGRAM OF THE XRT73LC00A .......................................................................................................................... 2
ORDERING INFORMATION...............................................................................................2
FIGURE 2. PIN OUT OF THE XRT73LC00A IN THE 44 PIN TQFP ...................................................................................................... 3
PIN DESCRIPTION.............................................................................................................4
ELECTRICAL CHARACTERISTICS ................................................................................12
ABSOLUTE MAXIMUM RATINGS .........................................................................................................12
DC ELECTRICAL CHARACTERISTICS ..............................................................................................................12
AC ELECTRICAL CHARACTERISTICS ..............................................................................................................13
FIGURE 3. TIMING DIAGRAM OF THE TRANSMIT TERMINAL INPUT INTERFACE .................................................................................... 14
FIGURE 4. TIMING DIAGRAM OF THE RECEIVE TERMINAL OUTPUT INTERFACE .................................................................................. 14
FIGURE 5. TRANSMIT PULSE AMPLITUDE TEST CIRCUIT FOR DS3, E3 AND STS-1 RATES ................................................................ 14
AC ELECTRICAL CHARACTERISTICS (CONT’D) LINE SIDE PARAMETERS .............................................17
FIGURE 6. ITU-T G.703 TRANSMIT OUTPUT PULSE TEMPLATE FOR E3 APPLICATIONS..................................................................... 18
FIGURE 7. BELLCORE GR-499-CORE TRANSMIT OUTPUT PULSE TEMPLATE FOR DS3 APPLICATIONS ............................................. 18
FIGURE 8. BELLCORE GR-253-CORE TRANSMIT OUTPUT PULSE TEMPLATE FOR SONET STS-1 APPLICATIONS ............................ 19
FIGURE 9. MICROPROCESSOR SERIAL INTERFACE DATA STRUCTURE .............................................................................................. 19
AC ELECTRICAL CHARACTERISTICS (CONT.) .....................................................................................20
FIGURE 10. TIMING DIAGRAM FOR THE MICROPROCESSOR SERIAL INTERFACE ................................................................................ 20
SYSTEM DESCRIPTION ..................................................................................................21
THE TRANSMIT SECTION...............................................................................................................................21
THE RECEIVE SECTION.................................................................................................................................21
THE MICROPROCESSOR SERIAL INTERFACE ..................................................................................................21
TABLE 1: ROLE OF MICROPROCESSOR SERIAL INTERFACE PINS WHEN THE XRT73LC00A IS OPERATING IN THE HARDWARE MODE .. 22
1.0 SELECTING THE DATA RATE ............................................................................................................23
TABLE 2: SELECTING THE DATA RATE FOR THE XRT73LC00A VIA THE E3 AND STS-1/DS3 INPUT PINS (HARDWARE MODE) ........... 23
COMMAND REGISTER CR4 (ADDRESS = 0X04) .............................................................................................23
TABLE 3: SELECTING THE DATA RATE FOR THE XRT73LC00A VIA THE STS-1/DS3 AND THE E3 BIT-FIELDS WITHIN COMMAND REGISTER
CR4 (HOST MODE) ....................................................................................................................................................... 24
2.0 THE TRANSMIT SECTION ..................................................................................................................24
2.1 THE TRANSMIT LOGIC BLOCK .................................................................................................................... 24
FIGURE 11. THE TYPICAL INTERFACE FOR THE TRANSMISSION OF DATA IN A DUAL-RAIL FORMAT FROM THE TRANSMITTING TERMINAL
EQUIPMENT TO THE TRANSMIT SECTION OF THE XRT73LC00A ....................................................................................... 25
FIGURE 12. HOW THE XRT73LC00A SAMPLES THE DATA ON THE TPDATA AND TNDATA INPUT PINS .......................................... 25
2.1.1 ACCEPTING SINGLE-RAIL DATA FROM THE TERMINAL EQUIPMENT ............................................................... 25
COMMAND REGISTER CR1 (ADDRESS = 0X01) .............................................................................................26
FIGURE 13. THE BEHAVIOR OF THE TPDATA AND TCLK INPUT SIGNALS WHILE THE TRANSMIT LOGIC BLOCK IS ACCEPTING SINGLE-RAIL
DATA FROM THE TERMINAL EQUIPMENT .......................................................................................................................... 26
2.2 THE TRANSMIT CLOCK DUTY CYCLE ADJUST CIRCUITRY .................................................................... 26
2.3 THE HDB3/B3ZS ENCODER BLOCK ............................................................................................................ 26
2.3.1 B3ZS ENCODING ....................................................................................................................................................... 26
FIGURE 14. AN EXAMPLE OF B3ZS ENCODING ............................................................................................................................... 27
2.3.2 HDB3 ENCODING....................................................................................................................................................... 27
FIGURE 15. AN EXAMPLE OF HDB3 ENCODING .............................................................................................................................. 27
2.3.3 ENABLING/DISABLING THE HDB3/B3ZS ENCODER ............................................................................................. 27
COMMAND REGISTER CR2 (ADDRESS = 0X02) .............................................................................................28
2.4 THE TRANSMIT PULSE SHAPER CIRCUITRY ............................................................................................ 28
2.4.1 ENABLING THE TRANSMIT LINE BUILD-OUT CIRCUIT ......................................................................................... 28
COMMAND REGISTER CR1 (ADDRESS = 0X01) .............................................................................................28
2.4.2 DISABLING THE TRANSMIT LINE BUILD-OUT CIRCUIT ........................................................................................ 29
COMMAND REGISTER CR1 (ADDRESS = 0X01) .............................................................................................29
2.4.3 DESIGN GUIDELINE FOR SETTING THE TRANSMIT LINE BUILD-OUT CIRCUIT ................................................ 29
2.4.4 THE TRANSMIT LINE BUILD-OUT CIRCUIT AND E3 APPLICATIONS................................................................... 29
2.5 INTERFACING THE TRANSMIT SECTION OF THE XRT73LC00A TO THE LINE ...................................... 29
FIGURE 16. RECOMMENDED SCHEMATIC FOR INTERFACING THE TRANSMIT SECTION OF THE XRT73LC00A TO THE LINE ................. 30
TRANSFORMER RECOMMENDATIONS ................................................................................................... 30
3.0 THE RECEIVE SECTION .....................................................................................................................32
I
XRT73LC00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
3.1 INTERFACING THE RECEIVE SECTION OF THE XRT73LC00A TO THE LINE ......................................... 32
FIGURE 17. RECOMMENDED SCHEMATIC FOR INTERFACING THE RECEIVE SECTION OF THE XRT73LC00A TO THE LINE (TRANSFORMERCOUPLING)..................................................................................................................................................................... 32
FIGURE 18. RECOMMENDED SCHEMATIC FOR INTERFACING THE RECEIVE SECTION OF THE XRT73LC00A TO THE LINE (CAPACITIVE-COUPLING)............................................................................................................................................................................ 33
3.2 THE RECEIVE EQUALIZER BLOCK ............................................................................................................. 33
3.2.1 GUIDELINES FOR SETTING THE RECEIVE EQUALIZER ....................................................................................... 33
FIGURE 19. THE TYPICAL APPLICATION FOR THE SYSTEM INSTALLER ............................................................................................. 34
COMMAND REGISTER CR2 (ADDRESS = 0X02)............................................................................................. 35
3.3 PEAK DETECTOR AND SLICER ................................................................................................................... 35
3.4 CLOCK RECOVERY PLL ............................................................................................................................... 35
3.5 THE HDB3/B3ZS DECODER ......................................................................................................................... 36
3.5.1 B3ZS DECODING DS3/STS-1 APPLICATIONS ........................................................................................................ 36
FIGURE 20. AN EXAMPLE OF B3ZS DECODING ............................................................................................................................... 36
3.5.2 HDB3 DECODING E3 APPLICATIONS...................................................................................................................... 36
FIGURE 21. AN EXAMPLE OF HDB3 DECODING .............................................................................................................................. 37
3.5.3 ENABLING/DISABLING THE HDB3/B3ZS DECODER ............................................................................................. 37
COMMAND REGISTER CR2 (ADDRESS = 0X02)............................................................................................. 37
3.6 LOS DECLARATION/CLEARANCE .............................................................................................................. 37
3.6.1 THE LOS DECLARATION/CLEARANCE CRITERIA FOR E3 APPLICATIONS....................................................... 38
FIGURE 22. THE SIGNAL LEVELS THAT THE XRT73LC00A DECLARES AND CLEARS LOS (E3 MODE ONLY)..................................... 38
FIGURE 23. THE BEHAVIOR OF THE LOS OUTPUT INDICATOR IN RESPONSE TO THE LOSS OF SIGNAL AND THE RESTORATION OF SIGNAL
39
3.6.2 THE LOS DECLARATION/CLEARANCE CRITERIA FOR DS3 AND STS-1 APPLICATIONS ................................ 39
TABLE 4: THE ALOS (ANALOG LOS) DECLARE AND CLEAR THRESHOLDS FOR A GIVEN SETTING OF LOSTHR AND REQEN FOR DS3 AND
STS-1 APPLICATIONS ..................................................................................................................................................... 39
COMMAND REGISTER CR0 (ADDRESS = 0X00)............................................................................................. 40
COMMAND REGISTER CR2 (ADDRESS = 0X02)............................................................................................. 40
COMMAND REGISTER CR0 (ADDRESS = 0X00)............................................................................................. 40
COMMAND REGISTER CR2 (ADDRESS = 0X02)............................................................................................. 41
3.6.3 MUTING THE RECOVERED DATA WHILE THE LOS IS BEING DECLARED......................................................... 41
COMMAND REGISTER CR3 (ADDRESS = 0X03)............................................................................................. 41
3.7 ROUTING THE RECOVERED TIMING AND DATA INFORMATION TO THE RECEIVING TERMINAL EQUIPMENT .............................................................................................................................................................. 41
FIGURE 24. THE TYPICAL INTERFACE FOR THE TRANSMISSION OF DATA IN A DUAL-RAIL FORMAT FROM THE RECEIVE SECTION OF THE
XRT73LC00A TO THE RECEIVING TERMINAL EQUIPMENT ................................................................................................ 42
FIGURE 25. HOW THE XRT73LC00A OUTPUTS DATA ON THE RPOS AND RNEG OUTPUT PINS .................................................... 42
FIGURE 26. THE BEHAVIOR OF THE RPOS, RNEG AND RCLK1 SIGNALS WHEN RCLK1 IS INVERTED ............................................ 43
COMMAND REGISTER CR3 (ADDRESS = 0X03)............................................................................................. 43
3.7.1 ROUTING SINGLE-RAIL FORMAT DATA (BINARY DATA STREAM) TO THE RECEIVE TERMINAL EQUIPMENT 43
COMMAND REGISTER CR3 (ADDRESS = 0X03)............................................................................................. 43
FIGURE 27. THE TYPICAL INTERFACE FOR THE TRANSMISSION OF DATA IN A SINGLE-RAIL FORMAT FROM THE RECEIVE SECTION OF THE
XRT73LC00A TO THE RECEIVING TERMINAL EQUIPMENT ................................................................................................ 44
FIGURE 28. THE BEHAVIOR OF THE RPOS AND RCLK1 OUTPUT SIGNALS WHILE THE XRT73LC00A IS TRANSMITTING SINGLE-RAIL DATA
TO THE RECEIVING TERMINAL EQUIPMENT ....................................................................................................................... 44
4.0 DIAGNOSTIC FEATURES OF THE XRT73LC00A ............................................................................. 44
4.1 THE ANALOG LOCAL LOOP-BACK MODE ................................................................................................. 44
FIGURE 29. THE ANALOG LOCAL LOOP-BACK IN THE XRT73LC00A ............................................................................................... 45
COMMAND REGISTER CR4 (ADDRESS = 0X04)............................................................................................. 45
4.2 THE DIGITAL LOCAL LOOP-BACK MODE .................................................................................................. 45
FIGURE 30. THE DIGITAL LOCAL LOOP-BACK PATH IN THE XRT73LC00A ....................................................................................... 46
COMMAND REGISTER CR4 (ADDRESS = 0X04)............................................................................................. 46
4.3 THE REMOTE LOOP-BACK MODE .............................................................................................................. 46
FIGURE 31. THE REMOTE LOOP-BACK PATH IN THE XRT73LC00A................................................................................................. 47
COMMAND REGISTER CR4 (ADDRESS = 0X04)............................................................................................. 47
4.4 TXOFF FEATURES ........................................................................................................................................ 47
COMMAND REGISTER CR1 (ADDRESS = 0X01)............................................................................................. 48
4.5 THE TRANSMIT DRIVE MONITOR FEATURES ........................................................................................... 48
FIGURE 32. THE XRT73LC00A EMPLOYING THE TRANSMIT DRIVE MONITOR FEATURES ................................................................. 48
FIGURE 33. TWO LIU’S, EACH MONITORING THE TRANSMIT OUTPUT SIGNAL OF THE OTHER LIU IC ............................................... 49
4.6 THE TAOS (TRANSMIT ALL ONES) FEATURE ........................................................................................... 49
COMMAND REGISTER CR1 (ADDRESS = 0X01)............................................................................................. 50
II
XRT73LC00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
5.0 THE MICROPROCESSOR SERIAL INTERFACE ...............................................................................51
5.1 DESCRIPTION OF THE COMMAND REGISTERS ........................................................................................ 51
TABLE 5: ADDRESSES AND BIT FORMATS OF XRT73LC00A COMMAND REGISTERS......................................................................... 51
DESCRIPTION OF BIT-FIELDS FOR EACH COMMAND REGISTER .......................................................................51
5.1.1
5.1.2
5.1.3
5.1.4
5.1.5
TABLE 6:
COMMAND REGISTER - CR0 .................................................................................................................................... 51
COMMAND REGISTER - CR1 .................................................................................................................................... 52
COMMAND REGISTER - CR2 .................................................................................................................................... 54
COMMAND REGISTER - CR3 .................................................................................................................................... 54
COMMAND REGISTER - CR4 .................................................................................................................................... 55
LOOP-BACK MODES ........................................................................................................................................................ 55
5.2 OPERATING THE MICROPROCESSOR SERIAL INTERFACE. .................................................................. 55
FIGURE 34. MICROPROCESSOR SERIAL INTERFACE DATA STRUCTURE ............................................................................................ 56
ORDERING INFORMATION.............................................................................................58
PACKAGE DIMENSIONS.................................................................................................58
REVISION HISTORY.......................................................................................................................................59
III
XRT73LC00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
PIN DESCRIPTION
PIN DESCRIPTION
PIN #
SYMBOL
TYPE
DESCRIPTION
1
TXLEV
I
Transmit Line Build-Out Enable/Disable Select:
This input pin is used to enable or disable the Transmit Line Build-Out circuit in
the XRT73LC00A.
Setting this pin to “High” disables the Line Build-Out circuit. In this mode, the
XRT73LC00A outputs partially shaped pulses onto the line via the TTIP and
TRING output pins.
Setting this pin to “Low” enables the Line Build-Out circuit. In this mode, the
XRT73LC00A outputs partially-shaped pulses onto the line via the TTIP and
TRING output pins.
To comply with the isolated DSX-3/STSX-1 Pulse Template Requirements per
Bellcore GR-499-Core or Bellcore GR-253-Core:
1. Set this input pin to a "1" if the cable length between the Cross-Connect and
the transmit output of the XRT73LC00A is greater than 225 feet.
2. Set this input pin to a "0" if the cable length between the Cross-Connect and
the transmit output of the XRT73LC00A is less than 225 feet.
This pin is active only if both of the following are true:
(a) The XRT73LC00A is configured to operate in either the DS3 or SONET
STS-1 modes and
(b) The XRT73LC00A is configured to operate in the Hardware Mode.
NOTE: This pin should be tied to GND if the XRT73LC00A is to be operated in
the HOST mode.
2
TAOS
I
Transmit All Ones Select:
A “High” on this pin causes a continuous AMI all “1’s” pattern to be transmitted
onto the line. The frequency of this “1’s” pattern is determined by TCLK.
NOTES:
1.
This input pin is ignored if the XRT73LC00A is operating in the HOST
Mode.
2.
Tie this pin to GND if the XRT73LC00A is going to be operating in the
HOST Mode.
3
TxAVDD
****
4
DMO
O
5
TxAGND
****
Transmit Analog Ground
6
AGND
****
Analog Ground (Substrate)
7
RxAGND
****
Receive Analog Ground
8
RTIP
I
Receive TIP Input:
This input pin along with RRING is used to receive the line signal from the
Remote DS3/E3/STS-1 Terminal.
9
RRING
I
Receive RING Input:
This input pin along with RTIP is used to receive the line signal from the Remote
DS3/E3/STS-1 Terminal.
10
RxAVDD
****
Transmit Analog Power Supply
Drive Monitor Output:
If no bipolar line signal is detected on the TTIP/TRING output pins via the MTIP
and MRING input pins for 128±32 TCLK periods, then the DMO output pin toggles and remains “High” until the next bipolar pulse is detected.
Receive Analog Power Supply
4
XRT73LC00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
PIN DESCRIPTION
PIN #
11
SYMBOL
TYPE
DESCRIPTION
REGRESET/
I
Register Reset Input pin (Invert RCLK2 Output - Select):
The function of this pin depends upon whether the XRT73LC00A is operating in
the HOST Mode or in the Hardware Mode.
HOST Mode - Register Reset Input pin:
Setting this input pin “Low” causes the XRT73LC00A to reset the contents of the
Command Registers to their default settings and operating configuration. This
pin is internally pulled “High”.
Hardware Mode - Invert RCLK2 Output Select:
Setting this input pin “Low” configures the Receive Section of the XRT73LC00A
to output the recovered data via the RPOS and RNEG output pins on the rising
edge of the RCLK2 output signal.
Setting this input pin “High” configures the Receive Section to output the recovered data on the falling edge of the RCLK2 output signal.
I
Receive Equalization Disable Input:
Setting this input pin “High” disables the Internal Receive Equalizer in the
XRT73LC00A. Setting this pin “Low” enables the Internal Receive Equalizer.
The guidelines for enabling and disabling the Receive Equalizer are described in
Section 3.2.
(RCLK2INV)
12
REQDIS
NOTES:
13
LOSTHR
I
1.
This input pin is ignored if the XRT73LC00A is operating in the HOST
Mode.
2.
Tie this pin to GND if the XRT73LC00A is going to be operating in the
HOST Mode.
Loss of Signal Threshold Control:
This input pin is used to select the LOS (Loss of Signal) Declaration and Clearance thresholds for the Analog LOS Detector circuit. Two settings are provided
by forcing this signal to either GND or VDD.
NOTE: This pin is only applicable during DS3 or STS-1 operations.
14
LLB
I
Local Loop-Back Select:
This input pin along with RLB dictates which Loop-Back mode the XRT73LC00A
is operating in.
A “High” on this pin with RLB being set to “Low” configures the XRT73LC00A to
operate in the Analog Local Loop-Back Mode.
A “High” on this pin with RLB also being set to “High” configures the
XRT73LC00A to operate in the Digital Local Loop-Back Mode.
NOTES:
1.
This input pin is ignored if the XRT73LC00A is operating in the HOST
Mode.
2.
Tie this pin to GND if the XRT73LC00A is going to be operating in the
HOST Mode.
5
XRT73LC00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
PIN DESCRIPTION
PIN #
SYMBOL
TYPE
DESCRIPTION
15
RLB
I
Remote Loop-Back Select:
This input pin along with LLB dictates which Loop-Back mode the XRT73LC00A
is operating in.
A “High” on this pin with LLB being set to “Low” configures the XRT73LC00A to
operate in the Remote Loop-Back Mode.
A “High” on this pin with LLB also being set to “High” configures the
XRT73LC00A to operate in the Digital Local Loop-Back Mode.
NOTES:
16
STS-1/DS3
I
1.
This input pin is ignored if the XRT73LC00A is operating in the HOST
Mode.
2.
Tie this pin to GND if the XRT73LC00A is going to be operating in the
HOST Mode.
STS-1/DS3 Select Input:
A “High” on this pin configures the Clock Recovery Phase Locked Loop to set its
VCO Center frequency to around 51.84 MHz for SONET STS-1 operations. A
“Low” on this pin configures the Clock Recovery Phase Locked Loop to set its
VCO Center frequency to around 44.736 MHz for DS3 operations.
NOTES:
17
E3
I
1.
The XRT73LC00A ignores this pin if the E3 pin (pin 17) is set to “1”.
2.
This input pin is ignored if the XRT73LC00A is operating in the HOST
Mode.
3.
Tie this pin to GND if the XRT73LC00A is going to be operating in the
HOST Mode.
E3 Select Input:
A “High” on this pin configures the XRT73LC00A to operate in the E3 Mode.
A “Low” on this pin configures the XRT73LC00A to check the state of the STS-1/
DS3 input pin.
NOTES:
18
HOST/HW
I
1.
This input pin is ignored if the XRT73LC00A is operating in the HOST
Mode.
2.
Tie this pin to GND if the XRT73LC00A is going to be operating in the
HOST Mode.
HOST/HW Mode Select:
This input pin is used to enable or disable the Microprocessor Serial Interface
(e.g., consisting of the SDI, SDO, SCLK, CS and REGRESET pins).
Setting this input pin “High” enables the Microprocessor Serial Interface (e.g.
configures the XRT73LC00A to operate in the HOST Mode). In this mode, the
XRT73LC00A is configured by writing data into the on-chip Command Registers
via the Microprocessor Serial Interface. When the XRT73LC00A is operating in
the HOST Mode, it ignores the states of many of the discrete input pins.
Setting this input pin “Low” disables the Microprocessor Serial Interface (e.g.,
configures the XRT73LC00A to operate in the Hardware Mode). In this mode,
many of the external input control pins are functional.
6
XRT73LC00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
PIN DESCRIPTION
PIN #
SYMBOL
TYPE
DESCRIPTION
19
SDI/
(LOSMUTEN)
I
Serial Data Input for the Microprocessor Serial Interface (HOST Mode) or
MUTE-upon-LOS Enable Input (Hardware Mode):
The function of this input pin depends upon whether the XRT73LC00A is operating in the HOST or the Hardware Mode.
Serial Data Input for the Microprocessor Serial Interface (HOST Mode):
This pin is used to read or write data into the Command Registers of the Microprocessor Serial Interface. The Read/Write bit, the Address Values of the Command Registers and Data Value to be written during Write Operations are
applied to this pin.
This input is sampled on the rising edge of the SCLK pin (pin 21).
MUTE-upon-LOS Enable Input (Hardware Mode):
In the Hardware Mode this input pin is used to configure the XRT73LC00A to
Mute the recovered data via the RPOS and RNEG output pins whenever it
declares an LOS condition.
Setting this input pin “High” configures the XRT73LC00A to automatically pull
the RPOS and RNEG output pins to GND whenever it is declaring an LOS condition, thereby Muting the data being output to the Terminal Equipment.
Setting this input pin “Low” configures the XRT73LC00A to NOT automatically
Mute the recovered data whenever an LOS condition is declared.
20
SDO/(LCV)
O
Serial Data Output from the Controller Port/(Line Code Violation Output (LCV)
Indicator.):
The function of this input pin depends upon whether the XRT73LC00A is operating in the HOST or the Hardware Mode.
HOST Mode - Microprocessor Serial Interface - Serial Data Output.
This pin serially outputs the contents of the specified Command Register during
Read Operations. The data on this pin is updated on the falling edge of the
SCLK input signal. This pin is tri-stated upon completion of data transfer.
Hardware Mode - Line Code Violation Output Indicator.
This pin pulses “High” for one bit period any time the Receive Section of the
XRT73LC00A detects a Line Code Violation in the incoming E3, DS3 or STS-1
Data Stream.
21
SCLK/
(ENDECDIS)
I
Microprocessor Serial Interface Clock Signal/Encoder Disable:
HOST Mode - Microprocessor Serial Interface Clock Signal
This signal is used to sample the data on the SDI pin on the rising edge of this
signal. During Read operations, the Microprocessor Serial Interface updates the
SDO output on the falling edge of this signal.
Hardware Mode - B3ZS/HDB3 Encoder/Decoder Disable
Setting this input pin “High” disables both the B3ZS/HDB3 Encoder and
Decoder. This setting configures the Transmit Section of the XRT73LC00A to
transmit data to the remote terminal equipment via the AMI Line Code. This setting also configures the Receive Section to receive a line signal via the AMI Line
Code.
Setting this input pin “Low” enables both the B3ZS/HDB3 Encoder and Decoder.
This setting configures the Transmit Section of the XRT73LC00A to transmit
data in the B3ZS format for DS3/STS-1 applications or the HDB3 format for E3
applications. This setting configures the Receive Section to receive a line signal
that has been encoded into the B3ZS or HDB3 line code.
7
XRT73LC00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
PIN DESCRIPTION
PIN #
SYMBOL
TYPE
DESCRIPTION
22
CS/(DR/SR)
I
Microprocessor Serial Interface - Chip Select/Encoder and Decoder Disable
The function of this input pin depends upon whether the XRT73LC00A is operating in the HOST or the Hardware Mode.
HOST Mode - Chip Select Input:
The Local Microprocessor must assert this pin (e.g., set it to “0”) in order to
enable communication with the XRT73LC00A via the Microprocessor Serial
Interface.
Hardware Mode - Dual-Rail/Single-Rail Select Input:
Setting this input pin “High” configures the XRT73LC00A to operate in the DualRail Mode. When the XRT73LC00A is operating in this mode, then the Receive
Section of the LIU IC outputs the Recovered Data via both RPOS and RNEG
output pins.
Setting this input pin “Low” configures the XRT73LC00AXRT73LC00A to operate in the Single-Rail Mode. When the XRT73LC00A is operating in this mode,
the Receive Section of the LIU IC outputs the Recovered Data via the RPOS
output pin in a binary data stream. No data will output via the RNEG output pin.
23
RLOL
O
Receive Loss of Lock Output Indicator
This output pin toggles “High” if the XRT73LC00A has detected a Loss of Lock
Condition. The XRT73LC00A declares an LOL (Loss of Lock) Condition if the
recovered clock frequency deviates from the Reference Clock frequency (available at the EXCLK input pin) by more than 0.5%.
NOTE: The RCLK1/2 output pins are sourced by the signal applied at the EXCLK
input pin anytime the XRT73LC00A declares an LOL condition.
24
RLOS
O
25
DGND
****
Digital Ground
26
DVDD
****
Digital Power Supply
27
EXCLK
I
Receive Loss of Signal Output Indicator
This output pin toggles “High” if the XRT73LC00A has detected a Loss of Signal
Condition in the incoming line signal.
The criteria the XRT73LC00A uses to declare an LOS Condition depends upon
whether the device is operating in the E3 or DS3/STS-1 Mode.
External Reference Clock Input:
Apply a line-rate clock signal to this input pin. This signal is a 34.368MHz clock
signal for E3 applications, a 44.736 MHz clock signal for DS3 applications or a
51.84 MHz clock signal for SONET STS-1 applications.
NOTE: This input pin functions as the source of the RxCLK output clock signal
any time the XRT73LC00A declares an LOL condition.
28
RxDGND
****
Receiver Digital Ground
29
RxDVDD
****
Receiver Digital Power Supply
8
XRT73LC00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
PIN DESCRIPTION
PIN #
SYMBOL
TYPE
DESCRIPTION
30
LCV/(RCLK2)
O
Line Code Violation Indicator/Receive Clock Output pin 2:
The function of this pin depends upon whether the XRT73LC00A is operating in
the HOST Mode, the Hardware Mode or User selection.
HOST Mode - Line Code Violation Indicator Output:
If the XRT73LC00A is configured to operate in the HOST Mode, then this pin
functions as the LCV output pin by default. However, by using the on-chip Command Registers, this pin can be configured to function as the second Receive
Clock signal output pin RCLK2.
Hardware Mode - Receive Clock Output pin 2:
This output pin is the Recovered Clock signal from the incoming line signal. The
receive section of the XRT73LC00A outputs data via the RPOS and RNEG output pins on the rising edge of this clock signal.
NOTE:
31
RCLK1
O
If the XRT73LC00A is operating in the HOST Mode and this pin is
configured to function as the additional Receive Clock signal output pin,
then the XRT73LC00A can be configured to update the data on the
RPOS and RNEG output pins on the falling edge of this clock signal.
Receive Clock Output pin 1:
This output pin is the Recovered Clock signal from the incoming line signal. The
receive section of the XRT73LC00A outputs data via the RPOS and RNEG output pins on the rising edge of this clock signal.
NOTE: If the XRT73LC00A is operating in the HOST Mode, the device can be
configured to update the data on the RPOS and RNEG output pins on
the falling edge of this clock signal.
32
RNEG
O
Receive Negative Pulse Output:
This output pin pulses “High” whenever the XRT73LC00A has received a Negative Polarity pulse in the incoming line signal at the RTIP/RRING inputs.
NOTES:
33
RPOS
O
1.
If the B3ZS/HDB3 Decoder is enabled, the zero suppression patterns in
the incoming line signal (such as: "00V", "000V", "B0V", "B00V") are not
reflected at this output.
2.
This output pin is inactive if the XRT73LC00A has been configured to
operate in the Single-Rail Mode.
Receive Positive Pulse Output:
This output pin pulses “High” whenever the XRT73LC00A has received a Positive Polarity pulse in the incoming line signal at the RTIP/RRING inputs.
NOTE: If the B3ZS/HDB3 Decoder is enabled, the zero suppression patterns in
the incoming line signal (such as: "00V", "000V", "B0V", "B00V") are not
reflected at this output.
34
ICT
I
In-Circuit Test Input:
Setting this input pin “Low” causes all digital and analog outputs to go into a
high-impedance state in order to permit in-circuit testing. Set this pin “High” for
normal operation.
NOTE: This pin is internally pulled “High”.
9
XRT73LC00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
PIN DESCRIPTION
PIN #
SYMBOL
TYPE
DESCRIPTION
35
TXOFF
I
Transmitter OFF Input:
Setting this input pin “High” configures the XRT73LC00A to turn off the Transmitter in the device. When the Transmitter is shut-off, the TTIP and TRING output
pins will be tri-stated in the XRT73LC00A.
NOTES:
1.
This input pin is NOT ignored if the XRT73LC00A is operating in the
HOST Mode.
2.
Tie this pin to GND if the XRT73LC00A is going to be operating in the
HOST Mode.
36
TCLK
I
Transmit Clock Input for TPDATA and TNDATA:
This input pin must be driven at 34.368 MHz for E3 applications, 44.736MHz for
DS3 applications, or 51.84MHz for SONET STS-1 applications. The
XRT73LC00A uses this signal to sample the TPDATA and TNDATA input pins.
The XRT73LC00A is configured to sample these two pins on the falling edge of
this signal.
If the XRT73LC00A is operating in the HOST Mode, then the device can be configured to sample the TPDATA and TNDATA input pins on the rising edge of
TCLK.
37
TPDATA
I
Transmit Positive Data Input:
The XRT73LC00A samples this pin on the falling edge of TCLK. If the device
samples a “1” at this input pin, then it generates and transmits a positive polarity
pulse to the line.
NOTES:
38
TNDATA
I
1.
The data should be applied to this input pin if the Transmit Section is
configured to accept Single-Rail data from the Terminal Equipment.
2.
If the XRT73LC00A is operating in the HOST Mode, then the
XRT73LC00A can be configured to sample the TPDATA pin on either
the rising or falling edge of TCLK.
Transmit Negative Data Input:
The XRT73LC00A samples this pin on the falling edge of TCLK. If the device
samples a “1” at this input pin, then it generates and transmits a negative polarity
pulse to the line.
NOTES:
1.
This input pin is ignored and should be tied to GND if the Transmit
Section is configured to accept Single-Rail data from the Terminal
Equipment.
2.
If the XRT73LC00A is operating in the HOST Mode, then the
XRT73LC00A can be configured to sample the TNDATA pin on either
the rising or falling edge of TCLK.
39
TxAGND
-
Transmit Analog Ground
40
TRING
O
Transmit TRING Output:
The XRT73LC00A uses this pin along with TTIP to transmit a bipolar line signal
via a 1:1 transformer.
NOTE: This output pin along with TTIP is tri-stated anytime the TxOFF input pin
or bit-field is set “high”.
10
XRT73LC00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
PIN DESCRIPTION
PIN #
SYMBOL
TYPE
DESCRIPTION
41
TTIP
O
Transmit TIP Output:
The XRT73LC00A uses this pin along with TRING to transmit a bipolar line signal via a 1:1 transformer.
NOTE: This output pin along with TRING is tri-stated anytime the TxOFF input
pin or bit-field is set “high”.
42
TxAVDD
-
Transmit Analog Power Supply
43
MRING
I
Monitor Ring Input:
This input pin along with the MTIP pin function as the input pins for the Transmit
Drive Monitor. These two input pins are used to determine whether or not a
bipolar line signal is being output via the TTIP and TRING output pins. The
Transmit Drive Monitor circuit will toggle the DMO output pin “high” denoting a
Transmit Line Fault condition if no bipolar pulses are detected via the TTIP/
TRING output pins for 128 bit-periods.
Connect this input pin to the TRING output pin via a 270 ohm resistor.
NOTE: Tie this input pin to GND if you do not intend to use the Transmit Drive
Monitor.
44
MTIP
I
Monitor Tip Input:
This input pin along with the MRING pin function as the input pins for the Transmit Drive Monitor. These two input pins are to be used to determine whether or
not a bipolar line signal is being output via the TTIP and TRING output pins. The
Transmit Drive Monitor circuit will toggle the DMO output pin “high” denoting a
Transmit Line Fault condition if no bipolar pulses are detected via the TTIP/
TRING output pins for 128 bit periods.
Connect this input pin to the TTIP output pin via a 270 ohm resistor.
NOTE: Tie this input pin to GND if you do not intend to use the Transmit Drive
Monitor.
11
XRT73LC00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
POWER SUPPLY
-0.5 TO +3.465V
STORAGE TEMPERATURE
-65°C TO 150°C
INPUT VOLTAGE AT ANY PIN
-0.5V TO 5.0V
POWER DISSIPATION TQFP PACKAGE
1.2W
INPUT CURRENT AT ANY PIN
+100MA
ESD RATING (MIL-STD-883, M-3015)
1500V
DC ELECTRICAL CHARACTERISTICS
(Ta = 25°C, Vdd = 3.3V + 5%, unless otherwise specified)
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNITS
VDDD
DC Supply Voltage
3.135
3.3
3.465
V
VDDA
DC Supply Voltage
3.135
3.3
3.465
V
ICC
Supply Current (Measured while Transmitting and Receiving all “1’s”)
125
mA
VIL
Input Low Voltage
0.8
V
VIH
Input High Voltage
5.0
V
VOL
Output Low Voltage, IOUT = -4.0mA
0.4
V
VOH
Output High Voltage, IOUT = 4.0mA
IL
2.0
2.8
Input Leakage Current*
V
±10
* Not applicable to pins with pull-up/pull-down resistors.
12
A
XRT73LC00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
AC ELECTRICAL CHARACTERISTICS
(Ta = 25°C, Vdd = 3.3V + 5%, unless otherwise specified)
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNITS
TCLK Clock Duty Cycle (DS3/STS-1)
30
50
70
%
TCLK Clock Duty Cycle (E3)
30
50
70
%
Terminal Side Timing Parameters (See Figure 3 & Figure 4)
TCLK Frequency (SONET STS-1)
51.84
MHz
TCLK Frequency (DS3)
44.736
MHz
TCLK Frequency (E3)
34.368
MHz
tRTX
TCLK Clock Rise Time (10% to 90%)
4
ns
tFTX
TCLK Clock Fall Time (90% to 10%)
4
ns
tTSU
TPDATA/TNDATA to TCLK Falling Set up time
3
ns
tTHO
TPDATA/TNDATA to TCLK Falling Hold time
3
ns
tLCVO
RCLK to rising edge of LCV output delay
tTDY
TTIP/TRING to TCLK Rising Propagation Delay time
0.6
RCLK Clock Duty Cycle
45
2.5
50
ns
14
ns
55
%
RCLK Frequency (SONET STS-1)
51.84
MHz
RCLK Frequency (DS3)
44.736
MHz
RCLK Frequency (E3)
34.368
MHz
tCO
RCLK to RPOS/RNEG Delay Time
tRRX
RCLK Clock Rise Time (10% to 90%)
tFRX
RCLK Clock Fall Time (10% to 90%)
4
ns
2
4
ns
1.5
3
ns
Ci
Input Capacitance
10
pF
CL
Load Capacitance
10
pF
13
XRT73LC00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
FIGURE 3. TIMING DIAGRAM OF THE TRANSMIT TERMINAL INPUT INTERFACE
tRTX
tFTX
TClk
tTSU
tTHO
TPDATA or
TNDATA
TTIP or
TRING
tTDY
FIGURE 4. TIMING DIAGRAM OF THE RECEIVE TERMINAL OUTPUT INTERFACE
tRRX
tFRX
RClk
tLCVO
LCV
tCO
RPOS or
RNEG
FIGURE 5. TRANSMIT PULSE AMPLITUDE TEST CIRCUIT FOR DS3, E3 AND STS-1 RATES
TTIP
R1
31.6
T1
R3
75
1:1
R2
31.6
TRING
14
XRT73LC00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
AC ELECTRICAL CHARACTERISTICS (CONT’D) Line Side Parameters
(Ta = 25°C, Vdd = 3.3V + 5%, unless otherwise specified)
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNITS
Transmit Output Pulse Amplitude (Measured at Secondary Output of Transformer)
0.9
1.0
1.1
Vpk
Transmit Output Pulse Amplitude Ratio
0.95
1.00
1.05
Transmit Output Pulse Width
12.5
14.55
16.5
Transmit Output Pulse Width Ratio
0.95
1.00
1.05
0.02
0.05
E3 Application Parameters
Transmit Line Characteristics (See Figure 5)
Transmit Output Jitter with jitter-free input clock at TCLK
ns
UIpp
Receive Line Characteristics
Receive Sensitivity (Length of cable)
Interference Margin
1200
1400
feet
-20
-17
dB
Signal Level to Declare Loss of Signal
-35
dB
Signal Level to Clear Loss of Signal
-15
Occurrence of LOS to LOS Declaration Time
10
100
255
UI
Termination of LOS to LOS Clearance Time
10
100
255
UI
Intrinsic Jitter (all "1’s" Pattern)
dB
0.01
UI
Jitter Tolerance @ Jitter Frequency = 100Hz
64
UI
Jitter Tolerance @ Jitter Frequency = 1KHz
30
UI
Jitter Tolerance @ Jitter Frequency = 10KHz
4
UI
Jitter Tolerance @ Jitter Frequency = 800KHz
0.15
15
0.20
UI
XRT73LC00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
AC ELECTRICAL CHARACTERISTICS (CONT’D) Line Side Parameters
(Ta = 25°C, Vdd = 3.3V + 5%, unless otherwise specified)
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNITS
Transmit Output Pulse Amplitude (Measured with TXLEV = 0)
0.65
0.75
0.90
Vpk
Transmit Output Pulse Amplitude (Measured with TXLEV = 1)
0.93
0.98
1.08
Vpk
Transmit Output Pulse Width
8.6
9.65
10.6
ns
Transmit Output Pulse Amplitude Ratio
0.9
1.0
1.1
0.02
0.05
SONET STS-1 Application Parameters
Transmit Line Characteristics (See Figure 5)
Transmit Output Jitter with jitter-free clock input at TCLK
UIpp
Receive Line Characteristics
Receive Sensitivity (Length of cable)
900
1100
Signal Level to Declare or Clear Loss of Signal (see Table 4)
feet
mV
Intrinsic Jitter (all "1’s" Pattern)
0.03
UI
Jitter Tolerance @ Jitter Frequency = 100Hz
64
UI
Jitter Tolerance @ Jitter Frequency = 1KHz
64
UI
Jitter Tolerance @ Jitter Frequency = 10KHz
5
UI
Jitter Tolerance @ Jitter Frequency = 400KHz
0.15
16
0.35
UI
XRT73LC00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
AC ELECTRICAL CHARACTERISTICS (CONT’D) LINE SIDE PARAMETERS
(Ta = 25°C, Vdd = 3.3V + 5%, unless otherwise specified)
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNITS
Transmit Output Pulse Amplitude (Measured at 0 feet, TXLEV = 0)
0.65
0.75
0.85
Vpk
Transmit Output Pulse Amplitude (Measured at 0 feet, TXLEV = 1)
0.9
1.0
1.1
Vpk
10.10
11.18
12.28
ns
0.9
1.0
1.1
0.02
0.05
DS3 Application Parameters
Transmit Line Characteristics (See Figure 5)
Transmit Output Pulse Width
Transmit Output Pulse Amplitude Ratio
Transmit Output Jitter with jitter-free input clock at TCLK
UIpp
Receive Line Characteristics
Receive Sensitivity (Length of Cable)
900
1100
Signal Level to Declare or Clear Loss of Signal (see Table 4)
feet
mV
Intrinsic Jitter (All One’s Pattern)
0.01
UI
Jitter Tolerance @ Jitter Frequency = 100Hz
64
UI
Jitter Tolerance @ Jitter Frequency = 1KHz
64
UI
Jitter Tolerance @ Jitter Frequency = 10KHz
5
UI
Jitter Tolerance @ Jitter Frequency = 300KHz -- (Cat II)
17
0.35
0.45
UI
XRT73LC00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
Figure 6, Figure 7 and Figure 8 present the Pulse Template requirements for the E3, DS3 and STS-1 Rates.
FIGURE 6. ITU-T G.703 TRANSMIT OUTPUT PULSE TEMPLATE FOR E3 APPLICATIONS
17 ns
(14.55 + 2.45)
8.65 ns
V = 100%
N om inal P ulse
50%
14.55ns
12.1ns
(14.55 - 2.45)
10%
0%
10%
20%
FIGURE 7. BELLCORE GR-499-CORE TRANSMIT OUTPUT PULSE TEMPLATE FOR DS3 APPLICATIONS
DS3 Pulse Template
1.2
1
0.6
Lower Curve
Upper Curve
0.4
0.2
0
Time, in UI
18
1.
3
1.
4
1.
2
1
1.
1
0.
9
0.
8
0.
7
0.
6
0.
5
0.
4
0.
3
0.
2
0
1
-0
.
0.
1
3
2
-0
.
4
-0
.
-0
.
6
5
7
-0
.
-0
.
8
-0
.
-0
.
9
-0
.
-0.2
-1
Normalized Amplitude
0.8
XRT73LC00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
FIGURE 8. BELLCORE GR-253-CORE TRANSMIT OUTPUT PULSE TEMPLATE FOR SONET STS-1 APPLICATIONS
STS-1 Pulse Template
1.2
1
Normalized Amplitude
0.8
0.6
Lower Curve
Upper Curve
0.4
0.2
0
1.
4
1.
3
1.
2
1
1.
1
0.
9
0.
8
0.
7
0.
6
0.
5
0.
4
0.
3
0.
2
0
0.
1
-0
.9
-0
.8
-0
.7
-0
.6
-0
.5
-0
.4
-0
.3
-0
.2
-0
.1
-1
-0.2
Time, in UI
FIGURE 9. MICROPROCESSOR SERIAL INTERFACE DATA STRUCTURE
CS
SClk
1
SDI
R/W
2
A0
3
A1
4
A2
5
A3
6
0
7
0
8
A6
9
10
11
12
13
14
15
16
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
0
0
0
High Z
SDO
High Z
NOTES:
1.
A4 and A5 are always "0".
2.
R/W = "1" for "Read" Operations
3.
R/W = "0" for "Write" Operations
A shaded pulse, denotes a “don’t care” value.
19
XRT73LC00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
AC ELECTRICAL CHARACTERISTICS (CONT.)
(Ta = 25°C, Vdd = 3.3V + 5%, unless otherwise specified)
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNITS
Microprocessor Serial Interface Timing (see Figure 10)
t21
CS Low to Rising Edge of SCLK Setup Time
5
ns
t22
SCLK Falling Edge to CS Low Assertion Time
20
ns
t23
SDI to Rising Edge of SCLK Setup Time
50
ns
t24
SDI to Rising Edge of SCLK Hold Time
50
ns
t25
SCLK “Low” Time
240
ns
t26
SCLK “High” Time
240
ns
t27
SCLK Period
500
ns
t28
CS Low to Rising Edge of SCLK Hold Time
5
ns
t29
CS Inactive Time
250
ns
t30
Falling Edge of SCLK to SDO Valid Time
200
ns
t31
Falling Edge of SCLK to SDO Invalid Time
100
ns
t32
Falling Edge of SCLK or Rising Edge of CS to High Z
t33
Rise/Fall time of SDO Output
100
ns
40
FIGURE 10. TIMING DIAGRAM FOR THE MICROPROCESSOR SERIAL INTERFACE
t29
t21
CS
t27
t22
t25
SCLK
t23
SDI
t28
t26
t24
A0
R/W
A1
CS
SCLK
t31
t30
SDO
SDI
Hi-Z
D0
t33
t32
D2
D1
Hi-Z
20
D7
ns
XRT73LC00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
SYSTEM DESCRIPTION
A functional block diagram of the XRT73LC00A E3/DS3/STS-1 Transceiver IC (see Figure 1) shows that the
device contains three distinct sections:
The Transmit Section
The Receive Section
The Microprocessor Serial Interface
THE TRANSMIT SECTION
The Transmit Section accepts TTL/CMOS level signals from the Terminal Equipment in either a Single-Rail or
Dual-Rail format. The Transmit Section then takes this data and does the following:
Encodes the data into the B3ZS format if the DS3 or SONET STS-1 Modes have been selected or into the
HDB3 format if the E3 Mode has been selected.
Converts the CMOS level B3ZS or HDB3 encoded data into pulses with shapes that are compliant with the
various industry standard pulse template requirements.
Drives these pulses onto the line via the TTIP and TRING output pins across a 1:1 Transformer.
NOTE: The Transmit Section drives a "1" (or a Mark) on the line by driving either a positive or negative polarity pulse across
the 1:1 Transformer within a given bit period. The Transmit Section drives a "0" (or a Space) onto the line by driving
no pulse onto the line.
THE RECEIVE SECTION
The Receive Section receives a bipolar signal from the line either via a 1:1 Transformer or a 0.01mF Capacitor.
As the Receive Section receives this line signal it does the following:
Adjusts the signal level through an AGC circuit.
Optionally equalizes this signal for cable loss.
Attempts to quantify a bit-interval within the line signal as either a “1”, “-1” or a “0” by slicing this data. This
sliced data is used by the Clock Recovery PLL to recover the timing element within the line signal.
The sliced data is routed to the HDB3/B3ZS Decoder, during which the original data content as transmitted
by the Remote Terminal Equipment is restored to its original content.
Outputs the recovered clock and data to the Local Terminal Equipment in the form of CMOS level signals via
the RPOS, RNEG, RCLK1 and RCLK2 output pins.
THE MICROPROCESSOR SERIAL INTERFACE
The XRT73LC00A can be configured to operate in either the Hardware Mode or the HOST Mode.
The Hardware Mode
Connect the HOST/HW input pin (pin 18) to GND to configure the XRT73LC00A to operate in the Hardware
Mode.
When the XRT73LC00A is operating in the Hardware Mode, the following is true:
1. The Microprocessor Serial Interface block is
disabled.
2. The XRT73LC00A is configured via input pin settings.
Each of the pins associated with the Microprocessor Serial Interface takes on their alternative role as defined
in Table 1.
21
XRT73LC00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
3. All of the remaining input pins become active.
TABLE 1: ROLE OF MICROPROCESSOR SERIAL INTERFACE PINS WHEN THE XRT73LC00A IS OPERATING IN THE
HARDWARE MODE
PIN #
PIN NAME
FUNCTION WHILE IN THE HARDWARE MODE
11
REGRESET/(RCLK2INV)
RCLK2INV
19
SDI/(LOSMUTEN)
LOSMUTEN
20
SDO/(LCV)
LCV
21
SCLK/(ENDECDIS)
ENDECDIS
22
CS/(DR/SR)
DR/SR
30
LCV/(RCLK2)
RCLK2
22
XRT73LC00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
The HOST Mode
To configure the XRT73LC00A to operate in the HOST Mode, connect the HOST/HW input pin (pin 18) to VDD.
When the XRT73LC00A is operating in the HOST Mode, the following is true:
1. The Microprocessor Serial Interface block is enabled. Many configuration selections are made by writing
the appropriate data into the on-chip Command Registers via the Microprocessor Serial Interface.
2. All of the following input pins are disabled:
n Pin 1 - TXLEV
n Pin 2 - TAOS
n Pin 12 - REQDIS
n Pin 14 - LLB
n Pin 15 - RLB
n Pin 16 - STS-1/DS3
n Pin 17 - E3
n Pin 35 - TXOFF
Tie each of these pins to GND if the XRT73LC00A IC is to be operated in the HOST Mode.
Please see Section 5.0 for a detailed description on operating the Microprocessor Serial Interface or the onchip Command Registers.
1.0 SELECTING THE DATA RATE
The XRT73LC00A can be configured to support the E3 (34.368 Mbps), DS3 (44.736 Mbps) or the SONET
STS-1 (51.84 Mbps) rates. Selection of the data rate is dependent on whether the XRT73LC00A is operating
in the Hardware or HOST Mode.
TABLE 2: SELECTING THE DATA RATE FOR THE XRT73LC00A VIA THE E3 AND STS-1/DS3 INPUT PINS (HARDWARE
MODE)
DATA RATE
STATE OF E3 PIN
(PIN 17)
STATE OF STS-1/DS3 PIN
(PIN 16)
MODE OF B3ZS/HDB3 ENCODER/
DECODER BLOCKS
E3 (34.368 Mbps)
VDD
X (Don’t Care)
HDB3
DS3 (44.736 Mbps)
0
0
B3ZS
STS-1 (51.84 Mbps)
0
VDD
B3ZS
A. When operating in the Hardware Mode.
To configure the XRT73LC00A for the desired data rate, the E3 and the STS-1/DS3 pins must be set to the
appropriate logic states shown in Table 2.
B. When operating in the HOST Mode.
To configure the XRT73LC00A for the desired data rate, appropriate values need to be written into the STS-1/
DS3 and E3 bit-fields in Command Register CR4.
COMMAND REGISTER CR4 (ADDRESS = 0X04)
D4
D3
D2
D1
D0
X
STS-1/DS3
E3
LLB
RLB
X
X
X
X
X
Table 3 relates the values of these two bit-fields with respect to the selected data rates.
23
XRT73LC00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
TABLE 3: SELECTING THE DATA RATE FOR THE
XRT73LC00A VIA THE STS-1/DS3 AND THE E3 BITFIELDS WITHIN COMMAND REGISTER CR4 (HOST
MODE)
SELECTED DATA RATE
STS-1/DS3
E3
E3
Don't Care
1
DS3
0
0
STS-1
1
0
The results of making these selections are:
1. The VCO Center Frequency of the Clock Recovery Phase-Locked-Loop is configured to match the
selected data rate.
2. The B3ZS/HDB3 Encoder and Decoder blocks are configured to support B3ZS Encoding/Decoding if the
DS3 or STS-1 data rates were selected or,
3. The B3ZS/HDB3 Encoder and Decoder blocks are configured to support HDB3 Encoding/Decoding if the
E3 data rate was selected.
4. The on-chip Pulse-Shaping circuitry is configured to generate Transmit Output pulses of the correct shape
and width to meet the applicable pulse template requirement.
5. The LOS Declaration/Clearance Criteria is established.
2.0 THE TRANSMIT SECTION
Figure 1 indicates that the Transmit Section of the XRT73LC00A consists of the following blocks:
Transmit Logic Block
Duty Cycle Adjust Block
HDB3/B3ZS Encoder
Pulse Shaping Block
The purpose of the Transmit Section in the XRT73LC00A is to take TTL/CMOS level data from the terminal
equipment and encode it into a format that can:
1. be efficiently transmitted over coaxial cable at E3, DS3 or STS-1 data rates.
2. be reliably received by the Remote Terminal at the other end of the E3, DS3 or STS-1 data link.
3. comply with the applicable pulse template requirements.
2.1
The Transmit Logic Block
The purpose of the Transmit Logic Block is to accept either Dual-Rail or Single-Rail (a binary data stream) TTL/
CMOS level data and timing information from the Terminal Equipment.
Accepting Dual-Rail Data from the Terminal Equipment
The XRT73LC00A accepts Dual-Rail data from the Terminal Equipment via the following input signals:
TPDATA
TNDATA
TCLK
24
XRT73LC00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
Figure 11 illustrates the typical interface for the transmission of data in a Dual-Rail Format between the
Terminal Equipment and the Transmit Section of the XRT73LC00A.
FIGURE 11. THE TYPICAL INTERFACE FOR THE TRANSMISSION OF DATA IN A DUAL-RAIL FORMAT FROM THE TRANSMITTING TERMINAL EQUIPMENT TO THE TRANSMIT SECTION OF THE XRT73LC00A
Terminal
Terminal
Equipment
Equipment
(E3/DS3
or STS-1
(E3/DS3
or STS-1
Framer)
Framer)
TxPOS
TPDATA
TxNEG
TNDATA
TxLineClk
TCLK
Transmit
Transmit
Logic
Logic
Block
Block
Exar E3/DS3/STS-1 LIU
FIGURE 12. HOW THE XRT73LC00A SAMPLES THE DATA ON THE TPDATA AND TNDATA INPUT PINS
Data
1
1
0
0
TPDATA
TNDATA
TCLK
The manner that the LIU handles Dual-Rail data is described below and illustrated in Figure 12. The
XRT73LC00A typically samples the data on the TPDATA and TNDATA input pins on the falling edge of TCLK.
TCLK is typically a clock signal that is of the selected data rate frequency. For the E3 data rate, TCLK is
34.368 MHz. For the DS3 data rate, TCLK is 44.736 MHz and for the SONET STS-1 rate, TCLK is 51.84 MHz.
In general, if the XRT73LC00A samples a “1” on the TPDATA input pin, the Transmit Section of the device
ultimately generates a positive polarity pulse via the TTIP and TRING output pins across a 1:1 transformer. If
the XRT73LC00A samples a “1” on the TNDATA input pin, the Transmit Section of the device ultimately
generates a negative polarity pulse via the TTIP and TRING output pins across a 1:1 transformer.
2.1.1
Accepting Single-Rail Data from the Terminal Equipment
Do the following if data is to be transmited from the Terminal Equipment to the XRT73LC00A in Single-Rail
format (a binary data stream) without having to convert it into a Dual-Rail format.
A. Configure the XRT73LC00A to operate in the HOST Mode or,
25
XRT73LC00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
B. access the Microprocessor Serial Interface and write a “1” into the TXBIN (TRANSMIT BINary) bit-field in
Command Register 1.
COMMAND REGISTER CR1 (ADDRESS = 0X01)
D4
D3
D2
D1
D0
TXOFF
TAOS
TXCLKINV
TXLEV
TXBIN
X
X
X
X
1
After taking these steps, the Transmit Logic Block accepts Single-Rail data via the TPDATA input pin. The
XRT73LC00A samples this input pin on the falling edge of the TCLK clock signal and encodes it into the
appropriate bipolar line signal across the TTIP and TRING output pins.
NOTES:
1.
In this mode the Transmit Logic Block ignores the TNDATA input pin.
2.
If the Transmit Section of the XRT73LC00A is configured to accept Single-Rail data from the Terminal Equipment,
the B3ZS/HDB3 Encoder must be enabled.
Figure 13 illustrates the behavior of the TPDATA and TCLK signals when the Transmit Logic Block has been
configured to accept Single-Rail data from the Terminal Equipment.
FIGURE 13. THE BEHAVIOR OF THE TPDATA AND TCLK INPUT SIGNALS WHILE THE TRANSMIT LOGIC BLOCK IS
ACCEPTING SINGLE-RAIL DATA FROM THE TERMINAL EQUIPMENT
Data
1
1
0
0
TPDATA
TCLK
2.2
The Transmit Clock Duty Cycle Adjust Circuitry
The on-chip Pulse-Shaping circuitry in the Transmit Section of the XRT73LC00A has the responsibility for
generating pulses of the shape and width to comply with the applicable pulse template requirement. The
widths of these output pulses are defined by the width of the half-period pulses in the TCLK signal.
Allowing the widths of the pulses in the TCLK clock signal to vary significantly could jeopardize the chip’s ability
to generate Transmit Output pulses of the appropriate width, thereby failing the applicable Pulse Template
Requirement Specification. The chips ability to generate compliant pulses could depend upon the duty cycle of
the clock signal applied to the TCLK input pin.
In order to combat this phenomenon, the Transmit Clock Duty Cycle Adjust circuit was designed into the
XRT73LC00A. The Transmit Clock Duty Cycle Adjust Circuitry is a PLL that was designed to accept clock
pulses via the TCLK input pin at duty cycles ranging from 30% to 70% and to regenerate these signals with a
50% duty cycle.
The XRT73LC00A Transmit Clock Duty Cycle Adjust circuit alleviates the need to supply a signal with a 50%
duty cycle to the TCLK input pin.
2.3
The HDB3/B3ZS Encoder Block
The purpose of the HDB3/B3ZS Encoder Block is to aid in the Clock Recovery process at the Remote Terminal
Equipment by ensuring an upper limit on the number of consecutive zeros that can exist in the line signal.
2.3.1
B3ZS Encoding
If the XRT73LC00A is configured to operate in the DS3 or SONET STS-1 Modes, then the HDB3/B3ZS
Encoder block operates in the B3ZS Mode. When the Encoder is operating in this mode, it parses through and
26
XRT73LC00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
searches the Transmit Binary Data Stream from the Transmit Logic Block for the occurrence of three (3)
consecutive zeros (“000”). If the B3ZS Encoder finds an occurrence of three consecutive zeros, it substitutes
these three “0’s” with either a "00V" or a "B0V" pattern.
“B” represents a Bipolar pulse that is compliant with the Alternating Polarity requirements of the AMI (Alternate
Mark Inversion) line code and “V” represents a bipolar Violation (e.g., a bipolar pulse that violates the
Alternating Polarity requirements of the AMI line code).
The B3ZS Encoder decides whether to substitute with either a "00V" or a "B0V" pattern to insure that an odd
number of bipolar pulses exist between any two consecutive violation pulses.
Figure 14 illustrates the B3ZS Encoder at work with two separate strings of three (or more) consecutive zeros.
FIGURE 14. AN EXAMPLE OF B3ZS ENCODING
TClk
TPOS
SR data
1
0
1
1
0
0
0
0
0
1
1
1
1
0
1
1
0
1
1
0
0
1
1
0
0
0
0
1
1
0
0
1
0
0
Encoded
PDATA
1
0
0
1
0
0
1
0
0
0
1
0
1
0
0
1
0
0
1
0
0
0
1
0
0
0
0
1
0
0
0
1
0
0
Encoded
NDATA
0
0
1
0
0
0
0
0
0
1
0
1
0
0
1
0
0
1
0
0
0
1
0
1
0
1
0
0
1
0
0
0
0
0
0
0
V
Line signal
B
2.3.2
V
0
HDB3 Encoding
If the XRT73LC00A is configured to operate in the E3 Mode, then the HDB3/B3ZS Encoder block operates in
the HDB3 Mode. When the Encoder is operating in this mode, it parses through and searches the Transmit
Data Stream from the Transmit Logic Block for the occurrence of four (4) consecutive zeros (“0000”). If the
HDB3 Encoder finds an occurrence of four consecutive zeros, then it substitutes these four “0’s” with either a
“000V” or a “B00V” pattern to insure that an odd number of bipolar pulses exist between any two consecutive
violation pulses.
Figure 15 illustrates the HDB3 Encoder at work with two separate strings of four (or more) consecutive zeros.
FIGURE 15. AN EXAMPLE OF HDB3 ENCODING
TClk
TPOS
SR data
1
0
1
1
0
0
0
0
0
1
1
1
1
0
1
1
0
1
1
0
0
1
1
0
0
0
0
1
1
0
0
1
0
0
Encoded
PDATA
1
0
0
1
0
0
0
1
0
0
1
0
1
0
0
1
0
0
1
0
0
0
1
0
0
0
0
1
0
0
0
1
0
0
Encoded
NDATA
0
0
1
0
0
0
0
0
0
1
0
1
0
0
1
0
0
1
0
0
0
1
0
1
0
0
1
0
1
0
0
0
0
0
0
0
0
V
Line signal
B
2.3.3
0
0
V
Enabling/Disabling the HDB3/B3ZS Encoder
The XRT73LC00A allows two methods to enable or disable the HDB3/B3ZS Encoder.
If the XRT73LC00A is operating in the Hardware Mode.
To enable the HDB3/B3ZS Encoder, set the ENDECDIS input pin (pin 21) to “0”. To disable the HDB3/B3ZS
Encoder, set the ENDECDIS input pin (pin 21) to “1”.
27
XRT73LC00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
If the XRT73LC00A is operating in the HOST Mode.
To enable the HDB3/B3ZS Encoder, set the ENDECDIS bit-field in Command Register (CR2) to “0”.
COMMAND REGISTER CR2 (ADDRESS = 0X02)
D4
D3
D2
D1
D0
Reserved ENDECDIS ALOSDIS DLOSDIS REQDIS
X
0
X
X
X
To disable the HDB3/B3ZS Encoder, set the ENDECDIS bit-field in Command Register (CR2) to “1”.
If either of these two methods is employed to disable the HDB3/B3ZS Encoder, the LIU transmits the data onto
the line as it is received via the TPDATA and TNDATA input pins.
2.4
The Transmit Pulse Shaper Circuitry
The Transmit Pulse Shaper Circuitry consists of a Transmit Line Build-Out circuit which can be enabled or
disabled by setting the TXLEV input pin or bit-field to “High” or “Low”. The purpose of the Transmit Line BuildOut circuit is to permit configuring of the XRT73LC00A to transmit an output pulse which is compliant to either
of the following Bellcore pulse template requirements when measured at the Digital Cross Connect System.
Each of these Bellcore specifications further state that the cable length between the Transmit Output and the
Digital Cross Connect system can range anywhere from 0 to 450 feet.
The Isolated DSX-3 Pulse Template Requirement per Bellcore GR-499-CORE is illustrated in Figure 7.
The Isolated STSX-1 Pulse Template Requirement per Bellcore GR-253-CORE is illustrated in Figure 8.
2.4.1
Enabling the Transmit Line Build-Out Circuit
If the Transmit Line Build-Out Circuit is enabled, the XRT73LC00A outputs shaped pulses onto the line via the
TTIP and TRING output pins.
Do the following to enable the Transmit Line Build-Out circuit in the XRT73LC00A:
If the XRT73LC00A is operating in the Hardware Mode, set theTXLEV input pin (pin 1) to “Low”
If the XRT73LC00A is operating in the HOST Mode, set the TXLEV bit-field to “0” as illustrated below.
COMMAND REGISTER CR1 (ADDRESS = 0X01)
D4
D3
D2
D1
D0
TXOFF
TAOS
TXCLKINV
TXLEV
TXBIN
0
X
X
0
X
28
XRT73LC00A
E3/DS3/STS-1 LINE INTERFACE UNIT
2.4.2
REV. 1.0.2
Disabling the Transmit Line Build-Out Circuit
If the Transmit Line Build-Out circuit is disabled, then the XRT73LC00A outputs partially-shaped pulses onto
the line via the TTIP and TRING output pins.
Disable the Transmit Line Build-Out circuit in the XRT73LC00A by doing the following:
If the XRT73LC00A is operating in the Hardware Mode, set the TXLEV input pin (pin 1) to “High”
If the XRT73LC00A is operating in the HOST Mode, set the TXLEV bit-field to “1” as illustrated below.
COMMAND REGISTER CR1 (ADDRESS = 0X01)
D4
D3
D2
D1
D0
TXOFF
TAOS
TXCLKINV
TXLEV
TXBIN
0
X
X
1
X
2.4.3
Design Guideline for Setting the Transmit Line Build-Out Circuit
The setting ofTXLEV input pin or bit-field should be based upon the overall cable length between the
Transmitting Terminal and the Digital Cross Connect system where the pulse template measurements are
made.
If the cable length between the Transmitting Terminal and the DSX-3 or STSX-1 is less than 225 feet, it is
advisable to enable the Transmit Line Build-Out circuit by setting the TXLEV input pin or bit-field to "0".
NOTE: In this case the XRT73LC00A outputs shaped (e.g., not square-wave) pulses onto the line via the TTIP and TRING
output pins. The shape of this output pulse is such that it complies with the pulse template requirements even
when subjected to cable loss ranging from 0 to 225 feet.
If the cable length between the Transmitting
Terminal and the DSX-3 or STSX-1 is greater than 225 feet, it is advisable to disable the Transmit Line BuildOut circuit by setting the TXLEV input pin or bit-field to "1".
NOTE: In this case the XRT73LC00A outputs partially-shaped pulses onto the line via the TTIP and TRING output pins.
The cable loss that these pulses experience over long cable lengths (e.g., greater than 225 feet) causes these
pulses to be properly shaped and comply with the appropriate pulse template requirement.
2.4.4
The Transmit Line Build-Out Circuit and E3 Applications
The ITU-T G.703 Pulse Template Requirements for E3 states that the E3 transmit output pulse should be
measured at the Secondary Side of the Transmit Output Transformer for Pulse Template compliance. There is
no Digital Cross Connect System pulse template requirement for E3 and the Transmit Line Build-Out circuit in
the XRT73LC00A is disabled whenever it is operating in the E3 Mode.
2.5
Interfacing the Transmit Section of the XRT73LC00A to the Line
The E3, DS3 and SONET STS-1 specification documents all state that line signals transmitted over coaxial
cable are to be terminated with 75 Ohms. Therefore, interface the Transmit Section of the XRT73LC00A, as
illustrated in Figure 16 which shows two 31.6 Ohm resistors in series with the primary side of the transformer.
These two 31.6Ohm resistors closely match the 75Ohm load termination resistor thereby minimizing Transmit
Return Loss.
29
XRT73LC00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
FIGURE 16. RECOMMENDED SCHEMATIC FOR INTERFACING THE TRANSMIT SECTION OF THE XRT73LC00A TO THE
LINE
TTIP
R1
31.6
T1
BNC
1:1
R2
31.6
TRING
TRANSFORMER RECOMMENDATIONS
PARAMETER
VALUE
Turns Ratio
1:1
Primary Inductance
40H
Isolation Voltage
1500Vrms
Leakage Inductance
0.6H
PART NUMBER
VENDOR
INSULATION
PACKAGE TYPE
PE-68629
Pulse
3000V
Large Thru-Hole
PE-65966
Pulse
1500V
Small Thru-Hole
PE-65967
Pulse
1500V
Small SMT
T3001
Pulse
1500V
Small SMT
TG01-0406NS
Halo
1500V
Small SMT
TTI 7601-SM
Trans-Power
1500V
Small SMT
TRANSFORMER VENDOR INFORMATION
Pulse
Corporate Office
12220 World Trade Drive
San Diego, CA 92128
Tel: (858)-674-8100
FAX: (858)-674-8262
Europe
1 & 2 Huxley Road
30
XRT73LC00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
The Surrey Research Park
Guildford, Surrey GU2 5RE
United Kingdom
Tel: 44-1483-401700
FAX: 44-1483-401701
Asia
150 Kampong Ampat
#07-01/02
KA Centre
Singapore 368324
Tel: 65-287-8998
FAX: 65-280-0080
Website: http://www.pulseeng.com
Halo Electronics
Corporate Office
P.O. Box 5826
Redwood City, CA 94063
Tel: (650)568-5800
FAX: (650)568-6165
Email: info@haloelectronics.com
Website: http://www.haloelectronics.com
Transpower Technologies, Inc.
Corporate Office
Park Center West Building
9805 Double R Blvd, Suite # 100
Reno, NV 89511
(800)500-5930 or (775)852-0140
Email: info@trans-power.com
Website: http://www.trans-power.com
31
XRT73LC00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
3.0 THE RECEIVE SECTION
Figure 1 indicates that the XRT73LC00A Receive Section consists of the following blocks:
AGC/Equalizer
Peak Detector
Slicer
Clock Recovery PLL
Data Recovery
HDB3/B3ZS Decoder
The purpose of the XRT73LC00A Receive Section is to take an incoming attenuated/distorted bipolar signal
from the line and encode it back into the TTL/CMOS format where it can be received and processed by digital
circuitry in the Terminal Equipment.
3.1
Interfacing the Receive Section of the XRT73LC00A to the Line
By design, the Receive Section of the XRT73LC00A can be transformer-coupled or capacitive-coupled to the
line. The specification documents for E3, DS3 and STS-1 all specify 75Ohm termination loads when
transmitting over coaxial cable. It is recommended to interface the Receive Section of the XRT73LC00A to the
line as shown in Figure 17 or Figure 18.
FIGURE 17. RECOMMENDED SCHEMATIC FOR INTERFACING THE RECEIVE SECTION OF THE XRT73LC00A TO THE
LINE (TRANSFORMER-COUPLING)
RTIP
RxPOS
RxNEG
RxLineClk
RxLOS
RxLOL
RPOS
RNEG
RCLK1
R1
37.4
RLOS
RLOL
R2
37.4
RRING
32
T2
C1
0.01uf
1:1
BNC
XRT73LC00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
FIGURE 18. RECOMMENDED SCHEMATIC FOR INTERFACING THE RECEIVE SECTION OF THE XRT73LC00A TO THE
LINE (CAPACITIVE-COUPLING)
C1
0.01uF
Receive Line Signal
RTIP
R1
75
C2
0.01uF
RRING
3.2
The Receive Equalizer Block
After the XRT73LC00A has received the incoming line signal via the RTIP and RRING input pins, the first block
that this signal passes through is the AGC (Automatic Gain Control) circuit followed by the Receive Equalizer.
As the line signal is transmitted from a given transmitting terminal, the pulse shapes at that location are
basically square. These pulses consist of a combination of “Low” and “High” frequency Fourier components.
As this line signal travels from the transmitting terminal via the coaxial cable to the receiving terminal, it is
subjected to frequency-dependent loss. The higher-frequency components of the signal is subjected to a
greater amount of attenuation than the lower-frequency components. If this line signal travels over reasonably
long cable lengths (e.g., greater than 450 feet), then the shape of the pulses which were originally square is
distorted and inter-symbol interference increases.
The purpose of the Receive Equalizer is to equalize the distortion of the incoming signal due to cable loss. The
Receive Equalizer accomplishes this by subjecting the received line signal to frequency-dependent
amplification which attempts to counter the frequency dependent loss that the line signal has experienced and
to restore the shape of the line signal so that the transmitted data and clock can be recovered reliably.
3.2.1
Guidelines for Setting the Receive Equalizer
This data sheet presents guidelines for setting the Receive Equalizer, for the following conditions.
1. If the overall cable length from the local Receiving Terminal to the remote Transmitting Terminal is NOT
known.
2. If the overall cable length from the local Receiving Terminal to the remote Transmitting Terminal is known.
3.2.1.1
If the Overall Cable Length is NOT Known
This section presents recommendations on what state to set the Receive Equalizer when the overall cablelength from the local Receiving Terminal to the remote Transmitting Terminal is NOT known. For DS3, STS-1
and E3 applications, enable the Receive Equalizer by setting either the REQDIS input pin “low” or the REQDIS
bit-field to “0”. The remainder of this section provides an explanation why we recommend enabling the
Receive Equalizer for these applications.
3.2.1.1.1
The Use of the Receive Equalizer in a Typical DS3 or STS-1 Application
Most System Manufacturers of equipment supporting DS3 and STS-1 lines interface their equipment to either
a DSX-3 or STSX-1 Cross-Connect. While installing their equipment the Transmit Line Build-Out circuit is set
to the proper setting that makes the transmit output pulse compliant with the Isolated DSX-3 or STSX-1 Pulse
33
XRT73LC00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
Template requirements. For the XRT73LC00A this is achieved by setting the TXLEV input pin or bit-field to
the appropriate level.
When the System Manufacturer is interfacing the Receive Section of the XRT73LC00A to the Cross-Connect,
they should keep aware of the following facts:
1. All DS3 or STS-1 line signals that are present at either the DSX-3 or the STSX-1 Cross-Connect are
required to meet the Isolated Pulse Template Requirements per Bellcore GR-499-CORE for DS3 applications or Bellcore GR-253-CORE for STS-1 applications.
2. Bellcore documents state that the amplitude of these pulses at the DSX-3 or STSX-1 can range in amplitude from 360mVpk to 850mVpk.
3. Bellcore documents stipulate that the Receiving Terminal must be able to receive this pulse-template compliant line signal over a cable length of 0 to 450 feet from the DSX-3 or the STSX-1 Cross Connect.
These facts are reflected in Figure 19.
FIGURE 19. THE TYPICAL APPLICATION FOR THE SYSTEM INSTALLER
Transmitting
Terminal
Digital CrossConnect System
0 to 450 feet of
Cable
DSX-3
or
STSX-1
Pulses that are
compliant to the
Isolated DSX-3 or
STSX-1 Pulse
Template
Requirement
0 to 450 feet of
Cable
Receiving
Terminal
Design Considerations for DS3 and STS-1 Applications
When installing equipment into environments as depicted in Figure 18, the system installation personnel may
be able to determine the cable length between the local terminal equipment and the DSX-3/STSX-1 CrossConnect Patch-Panel. The cable length between the local terminal equipment and the DSX-3/STSX-1 CrossConnect Patch Panel ranges between 0 and 450 feet.
It is extremely unlikely that the system installation personnel will know the cable length between the DSX-3/
STSX-1 Cross-Connect Patch-Panel and the remote terminal equipment. We recommend that the Receive
Equalizer be enabled by setting the REQDIS input pin or bit-field to "0".
34
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REV. 1.0.2
The only time the Receive Equalizer should be disabled is when there is an off-chip equalizer in the Receive
path between the DSX-3/STSX-1 Cross-Connect and the RTIP/RRING input pins or, in applications where the
Receiver is monitoring the transmit output signal directly.
3.2.1.1.2
Design Considerations for E3 Applications
In E3 system installation, it is recommended that the Receive Equalizer of the XRT73LC00A be enabled by
pulling the REQDIS input pin to GND or by setting the REQDIS bit-field to “0”.
NOTE: The results of extensive testing indicates that when the Receive Equalizer is enabled, the XRT73LC00A is capable
of receiving an E3 line signal with anywhere from 0 to 12dB of cable loss over the Industrial Temperature range.
Design Considerations if the Overall Cable Length is known
If during system installation the overall cable length is known, then in order to optimize the performance of the
XRT73LC00A in terms of receive intrinsic jitter, etc., the Receive Equalizer should be enabled or disabled
based upon the following recommendations:
The Receive Equalizer should be turned ON if the Receive Section is going to receive a line signal with an
overall cable length of 300 feet or greater. The Receive Equalizer should be turned OFF if the Receive Section
is going to receive a line signal over a cable length of less than 300 feet.
NOTES:
1.
If the Receive Equalizer block is turned ON in a given Receive Section that is receiving a line signal over short
cable length, there is the risk of over-equalizing the received line signal which could degrade performance by
increasing the amount of jitter that exists in the recovered data and clock signals or by creating bit-errors.
2.
The Receive Equalizer has been designed to counter the frequency-dependent cable loss that a line signal
experiences as it travels from the Transmitting Terminal to the Receiving Terminal. However, Receive Equalizer
was not designed to counter flat loss where all of the Fourier frequency components in the line signal are subject
to the same amount of attenuation. Flat loss is handled by the AGC block.
The Receive Equalizer block can be disabled setting the REQDIS input pin “High” when operating in the
Hardware Mode or writing a "1" to the REQDIS bit-field in Command Register CR2 when operating the
XRT73LC00A in the HOST Mode.
COMMAND REGISTER CR2 (ADDRESS = 0X02)
D4
D3
D2
D1
D0
Reserved ENDECDIS ALOSDIS DLOSDIS REQDIS
X
3.3
X
X
X
1
Peak Detector and Slicer
After the incoming line signal has passed through the Receive Equalizer, it is routed to the Slicer block. The
purpose of the Slicer is to quantify a given bit-period or symbol within the incoming line signal as either a “1” or
a “0”.
3.4
Clock Recovery PLL
The output of the Slicer, which is now Dual-Rail digital pulses, is routed to the Clock Recovery PLL. The
purpose of the Clock Recovery PLL is to track the incoming Dual-Rail data stream and to derive and generate
a recovered clock signal.
It is important to note that the Clock Recovery PLL requires a line rate clock signal at the EXCLK input pin.
The Clock Recovery PLL operates in one of two modes:
The Training Mode.
The Data/Clock Recovery Mode
1. The Training Mode
If the XRT73LC00A is not receiving a line signal via the RTIP and RRING input pins or if the frequency
difference between the line signal and that applied via the EXCLK input pin exceeds 0.5%, then the
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E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
XRT73LC00A LIU IC is operating in the Training Mode. When the LIU is operating in the Training Mode it does
the following:
A. declares a Loss of Lock indication by toggling the RLOL output pin “High” and
B. outputs a clock signal via the RCLK1 and RCLK2 output pins which is derived from the signal applied to
the EXCLK input pin.
2. The Data/Clock Recovery Mode
If the frequency difference between the line signal and that applied via the EXCLK input pin is less than 0.5%,
the XRT73LC00A LIU IC is operating in the Data/Clock Recovery Mode. In this mode, the Clock Recovery PLL
is locked onto the line signal via the RTIP and RRING input pins.
3.5
The HDB3/B3ZS Decoder
The Remote Transmitting Terminal typically encodes the line signal into some sort of Zero Suppression Line
Code (e.g., HDB3 for E3 and B3ZS for DS3 and STS-1). The purpose of this encoding activity was to aid in the
Clock Recovery process of this data in the Near-End Receiving Terminal. Once the data has made it across
the E3, DS3 or STS-1 Transport Medium and has been recovered by the Clock Recovery PLL, it is now
necessary to restore the original content of the data. The purpose of the HDB3/B3ZS Decoding block is to
restore the data transmitted over the E3, DS3 or STS-1 line to its original content prior to Zero Suppression
encoding.
3.5.1
B3ZS Decoding DS3/STS-1 Applications
If the XRT73LC00A is configured to operate in the DS3 or STS-1 Modes, then the HDB3/B3ZS Decoding Block
performs B3ZS Decoding. When the Decoder is operating in this mode it parses through the incoming DualRail data and checks for the occurrence of either a “00V” or a “B0V” pattern. If the B3ZS Decoder detects this
particular pattern it substitutes these bits with a “000” pattern.
NOTE: If the B3ZS Decoder detects any bipolar violations that is not in accordance with the”B3ZS Line Code” format, or if
the B3ZS Decoder detects a string of 3 (or more) consecutive “0’s” in the incoming line signal, then the B3ZS
Decoder flags this event as a Line Code Violation by pulsing the LCV output pin “High”.
Figure 20 illustrates the B3ZS Decoder at work with two separate Zero Suppression patterns in the incoming
Dual-Rail Data Stream.
FIGURE 20. AN EXAMPLE OF B3ZS DECODING
0 0 V
Line Signal
B 0 V
RCLK
RPOS
RNEG
Data
3.5.2
0 1 0 1 1 0 0 0 1 0 1 1 1 1 0 1 1 0 1 1 0 0 1 1 1 0 0 0 1
HDB3 Decoding E3 Applications
If the XRT73LC00A is configured to operate in the E3 Mode, the HDB3/B3ZS Decoding Block performs HDB3
Decoding. When the Decoder is operating in this mode it parses through the incoming Dual-Rail data and
checks for the occurrence of either a “000V” or a “B00V” pattern. If the HDB3 Decoder detects this particular
pattern, it substitutes these bits with a “0000” pattern.
Figure 21 illustrates the HDB3 Decoder at work with two separate Zero Suppression patterns in the incoming
Dual-Rail Data Stream.
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E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
FIGURE 21. AN EXAMPLE OF HDB3 DECODING
0 0 0 V
Line Signal
B 0 0 V
RCLK
RPOS
RNEG
Data
0
1 0 1 1 0 0 0 0 0 1 1 1 1 0 1 1 0 1 1 0 0 1 1 0 0 0 0 1
NOTE: If the HDB3 Decoder detects any bipolar violation (e.g., “V”) pulses that is not in accordance with the HDB3 Line
Code format, or if the HDB3 Decoder detects a string of 4 (or more) “0’s” in the incoming line signal, then the HDB3
Decoder flags this event as a Line Code Violation by pulsing the LCV output pin “High”.
3.5.3
Enabling/Disabling the HDB3/B3ZS Decoder
The HDB3/B3ZS Decoder of the XRT73LC00A can be enabled or disabled by either of the following means:
If the XRT73LC00A is operating in the Hardware Mode:
Enable the HDB3/B3ZS Encoder/Decoder by pulling the ENDECDIS input pin (pin 21) to GND. To disable the
HDB3/B3ZS Encoder/Decoder, pull the ENDECDIS input pin to VDD.
If the XRT73LC00A is operating in the HOST Mode:
Enable the XRT73LC00A HDB3/B3ZS Encoder/Decoder by writing a “0” into the ENDECDIS bit-field in
Command Register CR2. To disable the HDB3/B3ZS Encoder/Decoder, write a “1” into the ENDECDIS bitfield.
COMMAND REGISTER CR2 (ADDRESS = 0X02)
D4
D3
D2
D1
D0
Reserved ENDECDIS ALOSDIS DLOSDIS REQDIS
X
3.6
0
X
X
X
LOS Declaration/Clearance
The XRT73LC00A contains circuitry that monitors the following two parameters associated with the incoming
line signals.
1. The amplitude of the incoming line signal via the RTIP and RRING inputs; and
2. The number of pulses detected in the incoming line signal within a certain amount of time.
If the XRT73LC00A determines that the incoming line signal is missing due to insufficient amplitude or a lack of
pulses in the incoming line signal) then it declares a Loss of Signal (LOS) condition. The XRT73LC00A
declares the LOS condition by toggling the RLOS output pin “High” and by setting the RLOS bit field in
Command Register 0 to “1”.
If the XRT73LC00A determines that the incoming line signal has been restored (e.g., there is sufficient
amplitude and pulses in the incoming line signal) then it clears the LOS condition by toggling the RLOS output
pin “Low” and setting the RLOS bit-field to “0”.
The LOS Declaration/Clearance scheme that is employed in the XRT73LC00A is based upon ITU-T
Recommendation G.775 for both E3 and DS3 applications. The LOS Declaration and Clearance criteria that
the XRT73LC00A uses for each of these modes (e.g., E3 and DS3) are presented below.
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XRT73LC00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
3.6.1
The LOS Declaration/Clearance Criteria for E3 Applications
When the XRT73LC00A is operating in the E3 Mode, it declares an LOS Condition if the signal amplitude
drops to -35dB or below. The XRT73LC00A clears the LOS Condition if the signal amplitude rises back up to 15dB or above. Figure 22 illustrates the signal levels at which the XRT73LC00A asserts and clears LOS.
FIGURE 22. THE SIGNAL LEVELS THAT THE XRT73LC00A DECLARES AND CLEARS LOS (E3 MODE ONLY)
0 dB
Maximum Cable Loss for E3
LOS Signal Must be Cleared
-12 dB
-15dB
LOS Signal may be Cleared or Declared
-35dB
LOS Signal Must be Declared
Timing Requirements associated with Declaring and Clearing the LOS Indicator for E3 Applications
The XRT73LC00A was designed to meet the ITU-T G.775 specification timing requirements for declaring and
clearing the LOS indicator. The XRT73LC00A declares an LOS between 10 and 255 UI or E3 bit-periods after
the actual time the LOS condition occurred. The XRT73LC00A clears the LOS indicator within 10 to 255 UI
after restoration of the incoming line signal. Figure 23 illustrates the LOS Declaration and Clearance behavior
in response to the first loss of signal event and then afterwards to the restoration of the signal.
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XRT73LC00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
FIGURE 23. THE BEHAVIOR OF THE LOS OUTPUT INDICATOR IN RESPONSE TO THE LOSS OF SIGNAL AND THE RESTORATION OF SIGNAL
Actual Occurrence
of LOS Condition
Line Signal
is Restored
RTIP/
RRing
10 UI
255 UI
Time Range for
LOS Declaration
10 UI
255 UI
RLOS Output Pin
0 UI
0 UI
G.775
Compliance
3.6.2
Time Range for
LOS Clearance
G.775
Compliance
The LOS Declaration/Clearance Criteria for DS3 and STS-1 Applications
When the XRT73LC00A is operating in the DS3 or STS-1 Modes it declares and clears LOS based on either:
Analog LOS (ALOS) Declaration/Clearance Criteria or,
Digital LOS (DLOS) Declaration/Clearance Criteria
In the DS3 or STS-1 Modes the LOS output (RLOS) is simply the logical OR of the ALOS and DLOS states.
1. The Analog LOS (ALOS) Declaration/Clearance Criteria
The XRT73LC00A declares an Analog LOS (ALOS) Condition if the amplitude of the incoming line signal drops
below a specific amplitude as defined by the state of the LOSTHR input pin.
TABLE 4: THE ALOS (ANALOG LOS) DECLARE AND CLEAR THRESHOLDS FOR A GIVEN SETTING OF LOSTHR AND
REQEN FOR DS3 AND STS-1 APPLICATIONS
APPLICATION
REQEN SETTING
LOSTHR SETTING
SIGNAL LEVEL TO
DECLARE ALOS
SIGNAL LEVEL TO CLEAR
ALOS
DS3
1
1
90mV
0
1
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