XRT75L04
FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER
JULY 2006
GENERAL DESCRIPTION
The XRT75L04 is a four-channel fully integrated Line
Interface Unit (LIU) with Jitter Attenuator for E3/DS3/
STS-1 applications. It incorporates four independent
Receivers, Transmitters and Jitter Attenuators in a
single 176 pin LQFP package.
Each channel of the XRT75L04 can be configured to
operate in E3 (34.368 MHz), DS3 (44.736 MHz) or
STS-1 (51.84 MHz) rates that are independent of
each other. Each transmitter can be turned off and tristated for redundancy support and for conserving
power.
The XRT75L04’s differential receivers provide high
noise interference margin and are able to receive the
data over 1000 feet of cable or with up to 12 dB of
cable attenuation.
The XRT75L04 incorporates an advanced crystalless jitter attenuator per channel that can be selected
either in the transmit or receive path. The jitter
attenuator performance meets the ETSI TBR-24 and
Telcordia GR-499, GR-253 specifications.
REV. 1.0.4
• Provides low jitter clock outputs for either DS3,E3
or STS-1 rates.
TRANSMITTER:
• Compliant with Telcordia GR-499, GR-253 and
ANSI T1.102 Specification for transmit pulse
• Tri-state Transmit output capability for redundancy
applications
• Transmitters can be turned on or off.
JITTER ATTENUATOR:
• On chip advanced crystal-less Jitter Attenuator.
• Jitter Attenuators can be selected in Receive or
Transmit paths.
• Compliant with jitter transfer template outlined in
ITU G.751, G.752, G.755, GR-253 and GR-499CORE,1995 standards.
• Meets ETSI TBR 24 Jitter Transfer Requirements.
• 16 or 32 bits selectable FIFO size.
• Meets the Wander specifications described in
T1.105.03b.
The XRT75L04 provides both Serial Microprocessor
Interface as well as Hardware mode for programming
and control.
• Jitter Attenuators can be disabled.
The XRT75L04 supports local, remote and digital
loop-backs. The XRT75L04 also contains an onboard Pseudo Random Binary Sequence (PRBS)
generator and detector with the ability to insert and
detect single bit error.
• Serial Microprocessor Interface for control and
FEATURES
RECEIVER:
• On chip Clock and Data Recovery circuit for high
input jitter tolerance.
• Meets the jitter tolerance requirements as specified
in ITU-T G.823_1993 for E3 and Telcordia GR-499CORE for DS3 applications.
• Detects and Clears LOS as per G.775.
• Receiver Monitor mode handles up to 20 dB flat
loss with 6 dB cable attenuation.
• On chip B3ZS/HDB3 encoder and decoder that can
either be enabled or disabled.
• On-chip
clock
synthesizer
generates
the
appropriate rate clock from a single frequency
XTAL.
CONTROL AND DIAGNOSTICS:
configuration.
• Supports
optional
internal
Transmit
Driver
Monitoring.
• PRBS error counter register to accumulate errors.
• Supports Local, Remote and Digital Loop-backs.
• Single 3.3 V ± 5% power supply.
• 5 V Tolerant I/O.
• Maximum Power Dissipation 1.5W.
• Available in 176 pin LQFP package
• - 40°C to 85°C Industrial Temperature Range.
APPLICATIONS
• E3/DS3 Access Equipment.
• STS1-SPE to DS3 Mapper.
• DSLAMs.
• Digital Cross Connect Systems.
• CSU/DSU Equipment.
• Routers.
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
XRT75L04
FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.4
FIGURE 1. BLOCK DIAGRAM OF THE XRT 75L04
SDI
SDO
INT
SClk
CS
RESET
HOST/HW
STS-1/DS3_(n)
E3_(n)
REQEN_(n)
RTIP_(n)
RRing_(n)
SR/DR
LLB_(n)
XRT75L04
XRT75L04
Serial
Processor
Interface
CLKOUT
E3Clk,DS3Clk,
STS-1Clk
RLOL_(n)
RxON
RxClkINV
Clock
Synthesizer
Peak Detector
AGC/
Equalizer
Clock & Data
Recovery
Slicer
Jitter
Attenuator
LOS
Detector
Local
LoopBack
MUX
Invert
RxClk_(n)
HDB3/
B3ZS
Decoder
RPOS_(n)
Remote
LoopBack
RNEG_(n)/
LCV_(n)
RLB_(n)
RLOS_(n)
JATx/Rx
TTIP_(n)
TRing_(n)
MTIP_(n)
MRing_(n)
Line
Driver
Device
Monitor
Tx
Pulse
Shaping
Jitter
Attenuator
Timing
Control
MUX
HDB3/
B3ZS
Encoder
TPData_(n)
TNData_(n)
TxClk_(n)
TAOS_(n)
Tx
Control
DMO_(n)
TxLEV_(n)
Channel 0
Channel 1..2
Channel 3
TxON_(n)
Notes: 1. (n) = 0, 1, 2 or 3 for respective Channels
2. Serial Processor Interface input pins are shared by the four Channels in "Host" Mode and redefined in the "Hardware" Mode.
TRANSMIT INTERFACE CHARACTERISTICS
• Accepts either Single-Rail or Dual-Rail data from Terminal Equipment and generates a bipolar signal to the
line
• Integrated Pulse Shaping Circuit.
• Built-in B3ZS/HDB3 Encoder (which can be disabled).
• Accepts Transmit Clock with duty cycle of 30%-70%.
• Generates pulses that comply with the ITU-T G.703 pulse template for E3 applications.
• Generates pulses that comply with the DSX-3 pulse template, as specified in Telcordia GR-499-CORE and
ANSI T1.102_1993.
• Generates pulses that comply with the STSX-1 pulse template, as specified in Telcordia GR-253-CORE.
• Transmitters can be turned off to support redundancy designs.
RECEIVE INTERFACE CHARACTERISTICS
• Integrated Adaptive Receive Equalization for optimal Clock and Data Recovery.
• Declares and Clears the LOS defect per ITU-T G.775 requirements for E3 and DS3 applications.
• Meets Jitter Tolerance Requirements, as specified in ITU-T G.823_1993 for E3 Applications.
• Declares Loss of Signal (LOS) and Loss of Lock (LOL) Alarms.
• Built-in B3ZS/HDB3 Decoder (which can be disabled).
• Recovered Data can be muted while the LOS Condition is declared.
2
XRT75L04
FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.4
• Outputs either Single-Rail or Dual-Rail data to the Terminal Equipment.
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
TEST
ICT
REQEN_2
E3_2
STS1/DS3_2
LLB_2
RLB_2
RxAVDD_2
RRING_2
RTIP_2
RxAGND_2
REQEN_3
E3_3
STS1/DS3_3
LLB_3
RLB_3
RxAVDD_3
RRING_3
RTIP_3
RxAGND_3
RefAGND
RxA
RxB
RefAVDD_1
RxAGND_1
RTIP_1
RRING_1
RxAVDD_1
RLB_1
LLB_1
STS1/DS3_1
E3_1
REQEN_1
RxAGND_0
RTIP_0
RRING_0
RxAVDD_0
RLB_0
LLB_0
STS1/DS3_0
E3_0
REQEN_0
AGND
AGND
FIGURE 2. PIN OUT OF THE XRT75L04
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
XRT75L04
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
SCLK/TxCLKINV
SDI/RxON
CS/RxCLKINV
SDO/RxMON
INT/LOSMUT
RLOS_0
RLOL_0
DGND_0
RPOS_0
RNEG/LCV_0
RxCLK_0
DVDD_0
RLOS_1
RLOL_1
DGND_1
RPOS_1
RNEG/LCV_1
RxCLK_1
DVDD_1
E3CLK
CLKVDD
DS3CLK
CLKGND
STS1CLK/12M
JaDVDD_1
CLKOUT_1
JaDGND_1
JaDGND_0
CLKOUT_0
JaDVDD_0
JaAVDD_0
CLKOUTEN_0
JaAGND_0
JaAGND_1
CLKOUTEN_1
JaAVDD_1
TxON_0
TAOS_0
TxLEV_0
TxON_1
TAOS_1
TxLEV_1
TxCLK_0
TPOS_0
TNEG_2
TxAVDD_2
DMO_2
TTIP_2
TxVDD_2
TRING_2
TxGND_2
MTIP_2
MRING_2
TxAGND_2
TxCLK_3
TPOS_3
TNEG_3
TxAVDD_3
DMO_3
TTIP_3
TxVDD_3
TRING_3
TxGND_3
MTIP_3
MRING_3
TxAGND_3
TxAGND_1
MRING_1
MTIP_1
TxGND_1
TRING_1
TxVDD_1
TTIP_1
DMO_1
TxAVDD_1
TNEG_1
TPOS_1
TxCLK_1
TxAGND_0
MRING_0
MTIP_0
TxGND_0
TRING_0
TxVDD_0
TTIP_0
DMO_0
TxAVDD_0
TNEG_0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
RESET
HOST/HW
NC
SR/DR
NC
RLOS_2
RLOL_2
DGND_2
RPOS_2
RNEG/LCV_2
RxCLK_2
DVDD_2
RLOS_3
RLOL_3
DGND_3
RPOS_3
RNEG/LCV_3
RxCLK_3
DVDD_3
TxMON
JA0
JA1
JATx/Rx
SFM_EN
JaDVDD_3
CLKOUT_3
JaDGND_3
JaDGND_2
CLKOUT_2
JaDVDD_2
JaAVDD_2
CLKOUTEN_2
JaAGND_2
JaAGND_3
CLKOUTEN_3
JaAVDD_3
TxON_2
TAOS_2
TxLEV_2
TxON_3
TAOS_3
TxLEV_3
TxCLK_2
TPOS_2
ORDERING INFORMATION
PART NUMBER
PACKAGE
OPERATING TEMPERATURE RANGE
XRT75L04IV
176 Pin LQFP
-40°C to +85°C
3
XRT75L04
FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.4
TABLE OF CONTENTS
GENERAL DESCRIPTION .................................................................................................1
FEATURES .....................................................................................................................................................1
APPLICATIONS ................................................................................................................................................1
FIGURE 1. BLOCK DIAGRAM OF THE XRT 75L04 .............................................................................................................................. 2
TRANSMIT INTERFACE CHARACTERISTICS ........................................................................................................2
RECEIVE INTERFACE CHARACTERISTICS ..........................................................................................................2
FIGURE 2. PIN OUT OF THE XRT75L04............................................................................................................................................ 3
ORDERING INFORMATION.....................................................................................................................3
TABLE OF CONTENTS ............................................................................................................ I
PIN DESCRIPTIONS (BY FUNCTION) .............................................................................4
TRANSMIT INTERFACE.....................................................................................................................................4
RECEIVE INTERFACE.......................................................................................................................................7
CLOCK INTERFACE .........................................................................................................................................9
CONTROL AND ALARM INTERFACE .................................................................................................................10
OPERATING MODE SELECT ..........................................................................................................................12
SERIAL MICROPROCESSOR INTERFACE .........................................................................................................12
JITTER ATTENUATOR INTERFACE ...................................................................................................................13
ANALOG POWER AND GROUND .....................................................................................................................14
DIGITAL POWER AND GROUND ......................................................................................................................16
1.0 ELECTRICAL CHARACTERISTICS ....................................................................................................17
TABLE 1: ABSOLUTE MAXIMUM RATINGS ......................................................................................................................................... 17
TABLE 2: DC ELECTRICAL CHARACTERISTICS: ................................................................................................................................ 17
2.0 TIMING CHARACTERISTICS ..............................................................................................................18
FIGURE 3.
FIGURE 4.
FIGURE 5.
FIGURE 6.
TYPICAL INTERFACE BETWEEN TERMINAL EQUIPMENT AND THE XRT75L04 (DUAL-RAIL DATA)........................................... 18
TRANSMITTER TERMINAL INPUT TIMING .......................................................................................................................... 18
RECEIVER DATA OUTPUT AND CODE VIOLATION TIMING ................................................................................................... 19
TRANSMIT INTERFACE CIRCUIT FOR E3, DS3 AND STS-1 RATES .................................................................................... 19
3.0 LINE SIDE CHARACTERISTICS: ........................................................................................................20
3.1 E3 LINE SIDE PARAMETERS: ...................................................................................................................... 20
FIGURE 7. PULSE MASK FOR E3 (34.368 MBITS/S) INTERFACE AS PER ITU-T G.703......................................................................... 20
TABLE 3: E3 TRANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS........................................................ 20
FIGURE 8. BELLCORE GR-253 CORE TRANSMIT OUTPUT PULSE TEMPLATE FOR SONET STS-1 APPLICATIONS............................. 21
TABLE 4: STS-1 PULSE MASK EQUATIONS ..................................................................................................................................... 21
TABLE 5: STS-1 TRANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS (GR-253) .............................. 22
FIGURE 9. TRANSMIT OUPUT PULSE TEMPLATE FOR DS3 AS PER BELLCORE GR-499 ..................................................................... 22
TABLE 6: DS3 PULSE MASK EQUATIONS ........................................................................................................................................ 23
TABLE 7: DS3 TRANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS (GR-499) ................................. 23
FIGURE 10. MICROPROCESSOR SERIAL INTERFACE STRUCTURE...................................................................................................... 24
FIGURE 11. TIMING DIAGRAM FOR THE MICROPROCESSOR SERIAL INTERFACE ................................................................................ 24
TABLE 8: MICROPROCESSOR SERIAL INTERFACE TIMINGS ( TA = 250C, VDD=3.3V± 5% AND LOAD = 10PF) .................................. 25
4.0 THE TRANSMITTER SECTION: ..........................................................................................................26
FIGURE 12. SINGLE-RAIL OR NRZ DATA FORMAT (ENCODER AND DECODER ARE ENABLED)............................................................ 26
FIGURE 13. DUAL-RAIL DATA FORMAT (ENCODER AND DECODER ARE DISABLED) ............................................................................. 26
4.1 TRANSMIT CLOCK: ....................................................................................................................................... 26
4.2 B3ZS/HDB3 ENCODER: ................................................................................................................................. 26
4.2.1 B3ZS ENCODING: ...................................................................................................................................................... 26
FIGURE 14. B3ZS ENCODING FORMAT ........................................................................................................................................... 27
4.2.2 HDB3 ENCODING:...................................................................................................................................................... 27
FIGURE 15. HDB3 ENCODING FORMAT .......................................................................................................................................... 27
4.3 TRANSMIT PULSE SHAPER: ........................................................................................................................ 27
4.3.1 GUIDELINES FOR USING TRANSMIT BUILD OUT CIRCUIT: ................................................................................. 28
4.3.2 INTERFACING TO THE LINE: .................................................................................................................................... 28
4.4 TRANSMIT DRIVE MONITOR: ....................................................................................................................... 28
FIGURE 16. TRANSMIT DRIVER MONITOR SET-UP. ........................................................................................................................... 28
4.5 TRANSMITTER SECTION ON/OFF: .............................................................................................................. 30
5.0 THE RECEIVER SECTION: .................................................................................................................30
5.1 AGC/EQUALIZER: .......................................................................................................................................... 30
5.1.1 INTERFERENCE TOLERANCE: ................................................................................................................................ 31
I
XRT75L04
REV. 1.0.4
FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
FIGURE 17. INTERFERENCE MARGIN TEST SET UP FOR DS3/STS-1................................................................................................ 31
FIGURE 18. INTERFERENCE MARGIN TEST SET UP FOR E3. ............................................................................................................ 32
TABLE 9: INTERFERENCE MARGIN TEST RESULTS ........................................................................................................................... 32
5.2 CLOCK AND DATA RECOVERY: .................................................................................................................. 32
5.3 B3ZS/HDB3 DECODER: ................................................................................................................................ 32
5.4 LOS (LOSS OF SIGNAL) DETECTOR: ......................................................................................................... 33
5.4.1 DS3/STS-1 LOS CONDITION: .................................................................................................................................... 33
TABLE 10: THE ALOS (ANALOG LOS) DECLARATION AND CLEARANCE THRESHOLDS FOR A GIVEN SETTING OF REQEN (DS3 AND STS1 APPLICATIONS) ............................................................................................................................................................ 33
DISABLING ALOS/DLOS DETECTION: .......................................................................................................... 33
5.4.2 E3 LOS CONDITION:.................................................................................................................................................. 33
FIGURE 19. LOSS OF SIGNAL DEFINITION FOR E3 AS PER ITU-T G.775.......................................................................................... 34
FIGURE 20. LOSS OF SIGNAL DEFINITION FOR E3 AS PER ITU-T G.775. ......................................................................................... 34
5.4.3 MUTING THE RECOVERED DATA WITH LOS CONDITION:................................................................................... 35
6.0 JITTER: ................................................................................................................................................ 36
6.1 JITTER TOLERANCE - RECEIVER: .............................................................................................................. 36
FIGURE 21. JITTER TOLERANCE MEASUREMENTS ........................................................................................................................... 36
6.1.1 DS3/STS-1 JITTER TOLERANCE REQUIREMENTS:............................................................................................... 36
FIGURE 22. INPUT JITTER TOLERANCE FOR DS3/STS-1................................................................................................................ 37
6.1.2 E3 JITTER TOLERANCE REQUIREMENTS:............................................................................................................. 37
FIGURE 23. INPUT JITTER TOLERANCE FOR E3 .............................................................................................................................. 37
TABLE 11: JITTER AMPLITUDE VERSUS MODULATION FREQUENCY (JITTER TOLERANCE) .................................................................. 38
6.2 JITTER TRANSFER - RECEIVER/TRANSMITTER: ...................................................................................... 38
TABLE 12: JITTER TRANSFER SPECIFICATION/REFERENCES ............................................................................................................ 38
6.3 JITTER GENERATION: .................................................................................................................................. 38
6.4 JITTER ATTENUATOR: ................................................................................................................................. 38
TABLE 13: JITTER TRANSFER PASS MASKS .................................................................................................................................... 39
FIGURE 24. JITTER TRANSFER REQUIREMENTS AND JITTER ATTENUATOR PERFORMANCE ................................................................ 39
7.0 SERIAL HOST INTERFACE: ............................................................................................................... 40
TABLE 14:
TABLE 15:
TABLE 16:
TABLE 17:
TABLE 18:
TABLE 19:
TABLE 20:
TABLE 21:
FUNCTIONS OF SHARED PINS ......................................................................................................................................... 40
REGISTER MAP AND BIT NAMES .................................................................................................................................... 40
REGISTER MAP DESCRIPTION - GLOBAL ......................................................................................................................... 41
REGISTER MAP AND BIT NAMES - CHANNEL 0 REGISTERS .............................................................................................. 42
REGISTER MAP AND BIT NAMES - CHANNEL 1 REGISTERS .............................................................................................. 42
REGISTER MAP AND BIT NAMES - CHANNEL 2 REGISTERS .............................................................................................. 43
REGISTER MAP AND BIT NAMES - CHANNEL 3 REGISTERS .............................................................................................. 43
REGISTER MAP DESCRIPTION ........................................................................................................................................ 44
8.0 DIAGNOSTIC FEATURES: ................................................................................................................. 49
8.1 PRBS GENERATOR AND DETECTOR: ........................................................................................................ 49
FIGURE 25. PRBS MODE ............................................................................................................................................................. 49
8.2 LOOPBACKS: ................................................................................................................................................ 49
8.2.1 ANALOG LOOPBACK:............................................................................................................................................... 49
FIGURE 26. ANALOG LOOPBACK ..................................................................................................................................................... 50
8.2.2 DIGITAL LOOPBACK:................................................................................................................................................ 50
FIGURE 27. DIGITAL LOOPBACK...................................................................................................................................................... 50
8.2.3 REMOTE LOOPBACK:............................................................................................................................................... 51
FIGURE 28. REMOTE LOOPBACK .................................................................................................................................................... 51
8.3 TRANSMIT ALL ONES (TAOS): .................................................................................................................... 51
FIGURE 29. TRANSMIT ALL ONES (TAOS)...................................................................................................................................... 51
APPENDIX B .................................................................................................................... 52
TABLE 22: TRANSFORMER RECOMMENDATIONS .................................................................................................................. 52
TABLE 23: TRANSFORMER DETAILS ................................................................................................................................................ 52
ORDERING INFORMATION .................................................................................................................. 54
PACKAGE DIMENSIONS - 176 PIN PACKAGE .................................................................................................. 54
REVISIONS................................................................................................................................................... 55
II
XRT75L04
FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.4
PIN DESCRIPTIONS (BY FUNCTION)
TRANSMIT INTERFACE
PIN #
SIGNAL NAME
TYPE
52
49
169
172
TxON_0
TxON_1
TxON_2
TxON_3
I
DESCRIPTION
Transmitter ON Input - Channel 0:
Transmitter ON Input - Channel 1:
Transmitter ON Input - Channel 2:
Transmitter ON Input - Channel 3:
These pins are active only when the corresponding TxON bit is set.
Table below shows the status of the transmitter based on theTxON bit and
TxON pin settings.
Host/HW
Bit
Pin
Transmitter Status
1
0
0
OFF
1
0
1
OFF
1
1
0
OFF
1
1
1
ON
0
x
0
OFF
0
x
1
ON
NOTES:
46
34
175
11
TxCLK_0
TxCLK_1
TxCLK_2
TxCLK_3
I
1.
These pins will be active and can control the TTIP and TRING outputs
only when the TxON_n bits in the channel register are set .
2.
When Transmitters are turned off the TTIP and TRING outputs are Tristated.
3.
These pins are internally pulled up.
Transmit Clock Input for TPOS and TNEG - Channel 0:
Transmit Clock Input for TPOS and TNEG - Channel 1:
Transmit Clock Input for TPOS and TNEG - Channel 2:
Transmit Clock Input for TPOS and TNEG - Channel 3:
The frequency accuracy of this input clock must be of nominal bit rate ± 20 ppm.
The duty cycle can be 30%-70%.
By default, input data is sampled on the falling edge of TxCLK when input data
is changing on the rising edge of TxCLK..
44
32
1
13
TNEG_0
TNEG_1
TNEG_2
TNEG_3
I
Transmit Negative Data Input - Channel 0:
Transmit Negative Data Input - Channel 1:
Transmit Negative Data Input - Channel 2:
Transmit Negative Data Input - Channel 3:
In Dual-rail mode, these pins are sampled on the falling or rising edge of
TxCLK_n .
NOTES:
1.
These input pins are ignored and must be grounded if the Transmitter
Section is configured to accept Single-Rail data from the Terminal
Equipment.
4
XRT75L04
REV. 1.0.4
FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
TRANSMIT INTERFACE
PIN #
SIGNAL NAME
TYPE
45
33
176
12
TPOS_0
TPOS_1
TPOS_2
TPOS_3
I
DESCRIPTION
Transmit Positive Data Input - Channel 0:
Transmit Positive Data Input - Channel 1:
Transmit Positive Data Input - Channel 2:
Transmit Positive Data Input - Channel 3:
By default sampled on the falling edge of TxCLK
41
29
4
16
TTIP_0
TTIP_1
TTIP_2
TTIP_3
O
Transmit TTIP Output - Channel 0:
Transmit TTIP Output - Channel 1:
Transmit TTIP Output - Channel 2:
Transmit TTIP Output - Channel 3:
These pins along with TRING transmit bipolar signals to the line using a 1:1
transformer.
39
27
6
18
TRING_0
TRING_1
TRING_2
TRING_3
O
Transmit Ring Output - Channel 0:
Transmit Ring Output - Channel 1:
Transmit Ring Output - Channel 2:
Transmit Ring Output - Channel 3:
These pins along with TTIP transmit bipolar signals to the line using a 1:1 transformer.
50
47
171
174
TxLEV_0
TxLEV_1
TxLEV_2
TxLEV_3
I
Transmit Line Build-Out Enable/Disable Select - Channel 0:
Transmit Line Build-Out Enable/Disable Select - Channel 1:
Transmit Line Build-Out Enable/Disable Select - Channel 2:
Transmit Line Build-Out Enable/Disable Select - Channel 3:
These input pins are used to select the Transmit Line Build-Out circuit of Channel n.
Setting these pins to "High" disables the Line Build-Out circuit of Channel n. In
this mode, Channel n outputs partially-shaped pulses onto the line via the
TTIP_n and TRing_n output pins.
Setting these pins to "Low" enables the Line Build-Out circuit of Channel n. In
this mode, Channel n outputs shaped pulses onto the line via the TTIP_n and
TRing_n output pins.
To comply with the Isolated DSX-3/STSX-1 Pulse Template Requirements per
Bellcore GR-499-CORE or Bellcore GR-253-CORE:
1. Set these pins to "1" if the cable length between the Cross-Connect and the
transmit output of Channel is greater than 225 feet.
2. Set these pins to "0" if the cable length between the Cross-Connect and the
transmit output of Channel is less than 225 feet.
These pins are active only if the following two conditions are true:
a. The XRT75L04 is configured to operate in either the DS3 or SONET STS-1
Modes.
b. The XRT75L04 is configured to operate in the Hardware Mode.
NOTES:
1.
These pins are internally pulled down.
2.
If the XRT75L04 is configured in HOST mode, these pins should be
tied to GND.
5
XRT75L04
FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.4
TRANSMIT INTERFACE
PIN #
SIGNAL NAME
TYPE
DESCRIPTION
88
TxClkINV/
SClk
I
Hardware Mode: Transmit Clock Invert
Host Mode: Serial Clock Input:
Function of this pin depends on whether the XRT75L04 is configured to operate
in Hardware mode or Host mode.
In Hardware mode, setting this input pin “High” configures all three Transmitters
to sample the TPOS_n and TNEG_n data on the rising edge of the TxCLK_n .
NOTES:
1.
If the XRT75L04 is configured in HOST mode, this pin functions as
SClk input pin (please refer to the pin description for Microprocessor
interface).
152
TxMON
I
Transmitter Monitor:
When this pin is pulled “High”, MTIP and MRING are connected internally to
TTIP and TRING and allows self monitoring of the transmitter.
51
48
170
173
TAOS_0
TAOS_1
TAOS_2
TAOS_3
I
Transmit All Ones Select - Channel 0:
Transmit All Ones Select - Channel 1:
Transmit All Ones Select - Channel 2:
Transmit All Ones Select - Channel 3:
A “High" on this pin causes the Transmitter Section of Channel_n to generate
and transmit a continuous AMI all “1’s” pattern onto the line. The frequency of
this “1’s” pattern is determined by TxClk_n.
NOTES:
1.
This input pin is ignored if the XRT75L04 is operating in the HOST
Mode and should be tied to GND.
2.
Analog Loopback and Remote Loopback have priority over request.
3.
This pin is internally pulled down.
6
XRT75L04
REV. 1.0.4
FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
RECEIVE INTERFACE
PIN #
SIGNAL NAME
TYPE
DESCRIPTION
78
71
143
150
RxCLK_0
RXCLK_1
RxCLK_2
RxCLK_3
O
Receive Clock Output - Channel 0:
Receive Clock Output - Channel 1:
Receive Clock Output - Channel 2:
Receive Clock Output - Channel 3:
By default, RPOS and RNEG data sampled on the rising edge RxCLK..
Set the RxCLKINV bit to sample RPOS/RNEG data on the falling edge of
RxCLK
80
73
141
148
RPOS_0
RPOS_1
RPOS_2
RPOS_3
O
Receive Positive Data Output - Channel 0:
Receive Positive Data Output - Channel 1:
Receive Positive Data Output - Channel 2:
Receive Positive Data Output - Channel 3:
NOTE: If the B3ZS/HDB3 Decoder is enabled in Single-rail mode, then the zero
suppression patterns in the incoming line signal (such as: "00V",
"000V", "B0V", "B00V") is removed and replaced with ‘0’.
79
72
142
149
RNEG_0/LCV_0
RNEG_1/LCV_1
RNEG_2/LCV_2
RNEG_3/LCV_3
O
Receive Negative Data Output/Line Code Violation Indicator Channel 0:
Receive Negative Data Output/Line Code Violation Indicator Channel 1:
Receive Negative Data Output/Line Code Violation Indicator Channel 2:
Receive Negative Data Output/Line Code Violation Indicator Channel 3:
In Dual Rail mode, a negative pulse is output through RNEG.
Line Code Violation Indicator - Channel n:
If configured in Single Rail mode then Line Code Violation will be output.
97
106
124
115
RRING_0
RRING_1
RRING_2
RRING_3
I
Receive Ring Input - Channel 0:
Receive Ring Input - Channel 1:
Receive Ring Input - Channel 2:
Receive Ring Input - Channel 3:
These pins along with RTIP receive the bipolar line signal from the remote
DS3/E3/STS-1 Terminal.
98
107
123
114
RTIP_0
RTIP_1
RTIP_2
RTIP_3
I
Receive TIP Input - Channel 0:
Receive TIP Input - Channel 1:
Receive TIP Input - Channel 2:
Receive TIP Input - Channel 3:
These pins along with RRING receive the bipolar line signal from the Remote
DS3/E3/STS-1 Terminal.
7
XRT75L04
FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.4
RECEIVE INTERFACE
PIN #
SIGNAL NAME
TYPE
91
100
130
121
REQEN_0
REQEN_1
REQEN_2
REQEN_3
I
DESCRIPTION
Receive Equalizer On/Off - Channel 0:
Receive Equalizer On/Off- Channel 1:
Receive Equalizer On/Off - Channel 2:
Receive Equalier On/Off- Channel 3:
Tie these pins “High” to enable the receive equalizer.
NOTES:
87
RxON/
SDI
I
1.
This input pin is ignored and should be connected to GND if the
XRT75L04 is operating in the HOST Mode
2.
This pin is internally pulled down.
Hardware Mode: Receiver Turn ON Input
Host Mode: Serial Data Input:
Function of this pin depends on whether the XRT75L04 is configured to operate
in Hardware mode or Host mode.
In Hardware mode, setting this input pin “High” turns on and enables the
Receivers of all three channels.
NOTES:
86
RxClkINV/
CS
I
1.
If the XRT75L04 is configured in HOST mode, this pin functions as
SDI input pin (please refer to the pin description for Microprocessor
Interface)
2.
This pin is internally pulled down.
Hardware Mode: RxClk INVERT
Host Mode: Chip Select:
Function of this pin depends on whether the XRT75L04 is configured to operate
in Hardware mode or Host mode.
In Hardware mode, setting this input pin “High” configures the Receiver Section of all channels to invert the RxClk_n output signals and outputs the recovered data via RPOS_n and RNEG_n on the falling edge of RxClk_n.
NOTE: If the XRT75L04 is configured in HOST mode, this pin functions as CS
input pin (please refer to the pin description for Microprocessor
Interface).
85
RxMON/
SDO
I
Hardware Mode: Receive Monitoring Mode
Host Mode: Serial Data Output:
In Hardware mode, when this pin is tied “High” all 4 channels configure into
monitoring channels. In the monitoring mode, the Receiver is capable of monitoring the signals with 20 dB flat loss plus 6 dB cable attenuation. This allows
monitoring very weak signal before declaring LOS.
In HOST Mode each channel can be independently configured to be a monitoring channel by setting the bits in the channel control registers.
NOTE: If the XRT75L04 is configured in HOST mode, this pin functions as SDO
pin (please refer to the pin description for the Microprocessor Interface).
8
XRT75L04
REV. 1.0.4
FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
CLOCK INTERFACE
PIN #
SIGNAL NAME
TYPE
69
E3CLK
I
DESCRIPTION
E3 Clock Input (34.368 MHz ± 20 ppm):
If any of the channels is configured in E3 mode, a reference clock 34.368 MHz
is applied on this pin.
NOTE: In single frequency mode, this reference clock is not required.
67
DS3CLK
I
DS3 Clock Input (44.736 MHz ± 20 ppm):
If any of the channels is configured in DS3 mode, a reference clock 44.736
MHz. is applied on this pin.
NOTE: In single frequency mode, this reference clock is not required.
65
STS-1CLK/ 12M
I
STS-1 Clock Input (51.84 MHz ± 20 ppm):
If any of the channels is configured in STS-1 mode, a reference clock 51.84
MHz is applied on this pin..
In Single Frequency Mode, a reference clock of 12.288 MHz ± 20 ppm is connected to this pin and the internal clock synthesizer generates the appropriate
clock frequencies based on the configuration of the channels in E3, DS3 or
STS-1.
156
SFM_EN
I
Single Frequency Mode Enable:
Tie this pin “High” to enable the Single Frequency Mode. A reference clock of
12.288 MHz ± 20 ppm is applied. This offers the flexibility of using a low cost
reference clock and configures the board for either E3 or DS3 or STS-1 without
the need to change any components on the board.
In the Single Frequency Mode (SFM) an output clock is provided for each channel if the CLK_EN bit is set thus eliminating the need for a separate clock
source for the framer.
Tie this pin “Low” if single frequency mode is not selected. In this case, the
appropriate reference clocks must be provided.
NOTE:
57
54
164
167
CLKOUTEN_0
CLKOUTEN_1
CLKOUTEN_2
CLKOUTEN_3
O
This pin is internally pulled down
Clock output enable for channel 0
Clock output enable for channel 1
Clock output enable for channel 2
Clock output enable for channel 3
Pull this pin “High” to output low jitter clock on the CLKOUT_n pins.
NOTES:
60
63
161
158
CLKOUT_0
CLKOUT_1
CLKOUT_2
CLKOUT_3
O
1.
This clock output is only available in SFM mode.
2.
The maximum drive capability for the clockouts is 16 mA.
Clock output for channel 0
Clock output for channel 1
Clock output for channel 2
Clock output for channel 3
If CLKOUTEN_n pin is “High”, low jitter clock is output for each channel. Frequency of these clocks is based on the mode (E3,DS3 or STS-1) the channels
are configured.
This eliminates the need for a separate clock source for the framer.
NOTES:
1.
This clock output is only available in SFM mode.
2.
The maximum drive capability for the clockouts is 16 mA.
9
XRT75L04
FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.4
CONTROL AND ALARM INTERFACE
PIN #
SIGNAL NAME
TYPE
36
24
9
21
MRING_0
MRING_1
MRING_2
MRING_3
I
DESCRIPTION
Monitor Ring Input - Channel 0:
Monitor Ring Input - Channel 1:
Monitor Ring Input - Channel 2:
Monitor Ring Input - Channel 3:
The bipolar line output signal from TRING_n is connected to this pin via a 270 Ω
resistor to check for line driver failure.
NOTE: This pin is internally pulled "Low".
37
25
8
20
MTIP_0
MTIP_1
MTIP_2
MTIP_3
I
Monitor Tip Input - Channel 0:
Monitor Tip Input - Channel 1:
Monitor Tip Input - Channel 2:
Monitor Tip Input - Channel 3:
The bipolar line output signal from TTIP_n is connected to this pin via a 270ohm resistor to check for line driver failure.
NOTE: This pin is internally pulled "Low".
42
30
3
15
DMO_0
DMO_1
DMO_2
DMO_3
O
Drive Monitor Output - Channel 0:
Drive Monitor Output - Channel 1:
Drive Monitor Output - Channel 2:
Drive Monitor Output - Channel 3:
If MTIP_n and MRING_n has no transition pulse for 128 ± 32 TxCLK_n cycles,
DMO_n goes “High” to indicate the driver failure. DMO_n output stays “High”
until the next AMI signal is detected.
83
76
138
145
RLOS_0
RLOS_1
RLOS_2
RLOS_3
O
Receive Loss of Signal Output Indicator - Channel 0:
Receive Loss of Signal Output Indicator - Channel 1:
Receive Loss of Signal Output Indicator - Channel 2:
Receive Loss of Signal Output Indicator - Channel 3:
This output pin toggles "High" if the receiver has detected a Loss of Signal Condition.
The criteria for declaring /clearing an LOS Condition depends upon whether it is
operating in the E3 or STS-1/DS3 Mode.
82
75
139
146
RLOL_0
RLOL_1
RLOL_2
RLOL_3
O
Receive Loss of Lock Output Indicator - Channel 0:
Receive Loss of Lock Output Indicator - Channel 1:
Receive Loss of Lock Output Indicator - Channel 2:
Receive Loss of Lock Output Indicator - Channel 3:
This output pin toggles "High" if a Loss of Lock Condition is detected. LOL
(Loss of Lock) condition occurs if the recovered clock frequency deviates from
the Reference Clock frequency (available at either E3CLK or DS3CLK or STS1CLK input pins) by more than 0.5%.
111
RXA
****
External Resistor of 3 K Ω ± 1%.
Should be connected between RxA and RxB for internal bias.
110
RXB
****
External Resistor of 3K Ω ±1%.
Should be connected between RxA and RxB for internal bias.
10
XRT75L04
FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.4
CONTROL AND ALARM INTERFACE
131
ICT
I
In-Circuit Test Input:
Setting this pin "Low" causes all digital and analog outputs to go into a highimpedance state to allow for in-circuit testing. For normal operation, tie this pin
"High".
NOTE: This pin is internally pulled “High".
132
TEST
****
Factory Test Pin
NOTE: This pin must be connected to GND for normal operation.
84
LOSMUT/
INT
I/O
Hardware Mode: MUTE-upon-LOS Enable Input
Host Mode: Interrupt Ouput:
In Hardware Mode, setting pin “High” configures all three channels to Mute the
recovered data on the RPOS_n and RNEG_n whenever one of the channels
declares an LOS condition. RPOS_n and RNEG_n outputs are pulled “Low”.
Muting of the output data can be configured/controlled on a per channel basis
in Host Mode.
NOTE:
94
103
127
118
LLB_0
LLB_1
LLB_2
LLB_3
I
If the XRT75L04 is configured in HOST mode, this pin functions as INT
pin (please refer to the pin description for the Microprocessor Interface).
Local Loop-back - Channel 0:
Local Loop-back - Channel 1:
Local Loop-back - Channel 2:
Local Loop-back - Channel 3:
This input pin along with RLB_n configures different Loop-Back modes.
A "High" on this pin with RLB_n set to "Low" configures Channel_n to operate
in the Analog Local Loop-back Mode.
A "High" on this pin with RLB_n set to "High" configures Channel_n to operate
in the Digital Local Loop-back Mode.
NOTE:
95
104
126
117
RLB_0
RLB_1
RLB_2
RLB_3
I
This input pin is ignored and should be connected to GND if the
XRT75L04 is operating in the HOST Mode.
Remote Loop-back - Channel 0:
Remote Loop-back - Channel 1:
Remote Loop-back - Channel 2:
Remote Loop-back - Channel 3:
This input pin along with LLB_n configures different Loop-Back modes.
A "High" on this pin with LLB_n set to “Low" configures Channel_n to operate in
the Remote Loop-back Mode.
A "High" on this pin with LLB_n set to "High" configures Channel_n to operate
in the Digital Local Loop-back Mode.
NOTE:
RLB_n
LLB_n
Loopback Mode
0
0
Normal Operation
0
1
Analog Local
1
0
Remote
1
1
Digital
This input pin is ignored and should be connected to GND if the
XRT75L04 is operating in the HOST Mode.
11
XRT75L04
FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.4
OPERATING MODE SELECT
PIN #
SIGNAL NAME
TYPE
DESCRIPTION
134
HOST/(HW)
I
HOST/Hardware Mode Select:
Tie this pin “High” to configure in HOST mode. Tie this “Low” to configure in
Hardware mode.
When configured in HOST mode, the states of many of the discrete input pins
are controlled by internal register bits.
NOTE: This pin is internally pulled up.
92
101
129
120
E3_0
E3_1
E3_2
E3_3
I
E3 Mode Select Input
A "High" on this pin configures Channel_n to operate in E3 mode.
A "Low" on this pin configures Channel_n to operate in either STS-1 or DS3
mode depending on the settings on pins 93,102,128 and 119 pins.
NOTES:
93
102
128
119
STS-1/DS3_0
STS-1/DS3_1
STS-1/DS3_2
STS-1/DS3_3
I
1.
This pin is internally pulled down
2.
This pin is ignored and should be tied to GND if configured to operate
in HOST mode.
STS-1/DS3 Select Input
A “High” on these pins configures the Channel_n to operate in STS-1 mode.
A “Low” on these pins configures the Channel_n to operate in DS3 mode.
These pins are ignored if the E3_n pins are set to “High”.
NOTES:
136
SR/DR
I
1.
This pin is internally pulled down
2.
This pin is ignored and should be tied to GND if configured to operate
in HOST mode.
Single-Rail/Dual-Rail Select:
Setting this “High” configures both the Transmitter and Receiver to operate in
Single-rail mode and also enables the B3ZS/HDB3 Encoder and Decoder. In
Single-rail mode, TNEG_n pin should be grounded.
Setting this “Low” configures both the Transmitter and Receiver to operate in
Dual-rail mode and disables the B3ZS/HDB3 Encoder and Decoder.
NOTE: This pin is internally pulled down.
SERIAL MICROPROCESSOR INTERFACE
86
CS
RxCLKINV
I
Microprocessor Serial Interface - Chip Select
Toggle this pin “Low” to enable the communication with the Microprocessor
Serial Interface.( see figures 10 & 11)
NOTE: If configured in Hardware Mode, this pin functions as RxClkINV.
88
SClk
TxCLKINV
I
Serial Interface Clock Input
The data on the SDI pin is sampled on the rising edge of this signal. Additionally, during Read operations the Microprocessor Serial Interface updates the
SDO output on the falling edge of this signal.
NOTE: If configured in Hardware Mode, this pin functions as TxClkINV.
12
XRT75L04
FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.4
SERIAL MICROPROCESSOR INTERFACE
87
SDI
RxON
I
Serial Data Input:
Data is serially input through this pin.
The input data is sampled on the rising edge of the SClk pin (pin 88).
NOTES:
85
SDO
RxMON
I/O
1.
This pin is internally pulled down
2.
If configured in Hardware Mode, this pin functions as RxON.
Serial Data Output:
This pin serially outputs the contents of the specified Command Register during
Read Operations. The data is updated on the falling edge of the SClk and this
pin is tri-stated upon completion of data transfer.
NOTE: If configured in Hardware Mode, this pin functions as RxMON.
84
INT
LOSMUT
I/O
INTERRUPT Output:
This pin functions as Interrupt Output for Serial Interface. A transition to “Low”
indicates that an interrupt has been generated by the Serial Interface. The interrupt function can be disabled by setting the interrupt enable bit to “0” in the
Channel Control Register.
NOTES:
133
RESET
I
1.
In Hardware mode, this pin functions as LOSMUT.
2.
This pin will remain asserted “Low” until the interrupt is serviced.
Register Reset:
Setting this input pin "Low" causes the XRT75L04 to reset the contents of the
Command Registers to their default settings and default operating configuration
NOTE: This pin is internally pulled up.
JITTER ATTENUATOR INTERFACE
PIN #
SIGNAL NAME
TYPE
154
JA1
I
DESCRIPTION
Jitter Attenuator Select 1:
In Hardware Mode, this pin along with the pin JA0 configures the Jitter Attenuator as shown in the table.
JA0
JA1
Mode
0
0
16 bit FIFO
0
1
1
0
1
1
NOTE: This pin is internally pulled down.
13
32 bit FIFO
Disable Jitter
Attenuator
Disable Jitter
Attenuator
XRT75L04
FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.4
JITTER ATTENUATOR INTERFACE
155
JATx/Rx
I
Jitter Attenuator Path Select
In Hardware Mode, tie this pin “High” to select the Jitter Attenuator in the Transmit Path . Connect this pin “Low” to select the Jitter Attenuator in the Receive
Path. This applies to all4 channels.
NOTE: This pin is internally pulled down.
153
JA0
I
Jitter Attenuator Select 0:
In Hardware Mode, this pin along with pin 154 configures the Jitter Attenuator
as shown in the above table for JA1 pin 154.
NOTE: This pin is internally pulled down.
ANALOG POWER AND GROUND
PIN #
SIGNAL NAME
TYPE
DESCRIPTION
43
TxAVDD_0
****
Transmitter Analog 3.3 V ± 5% VDD - Channel 0
31
TxAVDD_1
****
Transmitter Analog 3.3 V ± 5% VDD - Channel 1
2
TxAVDD_2
****
Transmitter Analog 3.3 V ± 5% VDD - Channel 2
14
TxAVDD_3
****
Transmitter Analog 3.3 V ± 5% VDD - Channel 3
35
TxAGND_0
****
Transmitter Analog GND - Channel 0
23
TxAGND_1
****
Transmitter Analog GND - Channel 1
10
TxAGND_2
****
Transmitter Analog GND - Channel 2
22
TxAGND_3
****
Transmitter Analog GND - Channel 3
96
RxAVDD_0
****
Receiver Analog 3.3 V ± 5% VDD - Channel 0
105
RxAVDD_1
****
Receiver Analog 3.3 V ± 5% VDD - Channel 1
125
RxAVDD_2
****
Receiver Analog 3.3 V ± 5% VDD - Channel 2
116
RxAVDD_3
****
Receiver Analog 3.3 V ± 5% VDD - Channel 3
99
RxAGND_0
****
Receiver Analog GND - Channel_0
108
RxAGND_1
****
Receive Analog GND - Channel 1
122
RxAGND_2
****
Receive Analog GND - Channel 2
113
RxAGND_3
****
Receive Analog GND - Channel 3
58
JaAVDD_0
****
Analog 3.3 V ± 5% VDD - Channel 0
53
JaAVDD_1
****
Analog 3.3 V ± 5% VDD - Channel 1
163
JaAVDD_2
****
Analog 3.3 V ± 5% VDD - Channel 2
168
JaAVDD_3
****
Analog 3.3 V ± 5% VDD - Channel 3
56
JaAGND_0
****
Analog GND - Channel 0
55
JaAGND_1
****
Analog GND - Channel 1
165
JaAGND_2
****
Analog GND - Channel 2
14
XRT75L04
REV. 1.0.4
FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
ANALOG POWER AND GROUND
PIN #
SIGNAL NAME
TYPE
DESCRIPTION
166
JaAGND_3
****
Analog GND - Channel 3
89
AGND
****
Analog GND
90
AGND
****
Analog GND
109
REFAVDD
****
Analog 3.3 V ± 5% VDD - Reference
112
REFAGND
****
Reference GND
15
XRT75L04
FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
DIGITAL POWER AND GROUND
PIN #
SIGNAL NAME
TYPE
DESCRIPTION
40
TxVDD_0
****
Transmitter 3.3 V ± 5% VDD Channel 0
28
TxVDD_1
****
Transmitter 3.3 V ± 5% VDD Channel 1
5
TxVDD_2
****
Transmitter 3.3 V ± 5% VDD Channel 2
17
TxVDD_3
****
Transmitter 3.3 V ± 5% VDD Channel 3
38
TxGND_0
****
Transmitter GND - Channel 0
26
TxGND_1
****
Transmitter GND - Channel 1
7
TxGND_2
****
Transmitter GND - Channel 2
19
TxGND_3
****
Transmitter GND - Channel 3
77
DVDD_0
****
Receiver 3.3 V ± 5% VDD - Channel 0
70
DVDD_1
****
Receiver 3.3 V ± 5% VDD - Channel 1
144
DVDD_2
****
Receiver 3.3 V ± 5% VDD - Channel 2
151
DVDD_3
****
Receiver 3.3 V ± 5% VDD - Channel 3
81
DGND_0
****
Receiver Digital GND - Channel 0
74
DGND_1
****
Receiver Digital GND - Channel 1
140
DGND_2
****
Receiver Digital GND - Channel 2
147
DGND_3
****
Receiver Digital GND - Channel 3
59
JaDVDD_0
****
VDD 3.3 V ± 5%
64
JaDVDD_1
****
VDD 3.3 V ± 5%
162
JaDVDD_2
****
VDD 3.3 V ± 5%
157
JaDVDD_3
****
VDD 3.3 V ± 5%
61
JaDGND_0
****
GND
62
JaDGND_1
****
Digital GND
160
JaDGND_2
****
Digital GND
159
JaDGND_3
****
Digital GND
68
CLKVDD
****
VDD 3.3 V± 5%
66
CLKGND
****
Digital GND
16
REV. 1.0.4
XRT75L04
REV. 1.0.4
FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
1.0 ELECTRICAL CHARACTERISTICS
TABLE 1: ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
MIN
MAX
UNITS
COMMENTS
VDD
Supply Voltage
-0.5
5.0
V
Note 1
VIN
Input Voltage at any Pin
-0.5
5+0.5
V
Note 1
IIN
Input current at any pin
100
mA
Note 1
STEMP
Storage Temperature
-65
150
0
C
Note 1
ATEMP
Ambient Operating Temperature
-40
85
0C
linear airflow 0 ft./min
ThetaJA
Thermal Resistance
linear air flow 0ft/min
ThetaJC
MLEVL
Exposure to Moisture
ESD
ESD Rating
26.6
0
C/W
7.2
0
C/W
5
2000
level
EIA/JEDEC
JESD22-A112-A
V
Note 2
NOTES:
1.
Exposure to or operating near the Min or Max values for extended period may cause permanent failure and impair
reliability of the device.
2.
ESD testing method is per MIL-STD-883D,M-3015.7
TABLE 2: DC ELECTRICAL CHARACTERISTICS:
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNITS
DVDD
Digital Supply Voltage
3.135
3.3
3.465
V
AVDD
Analog Supply Voltage
3.135
3.3
3.465
V
ICC
Supply current (Measured while transmitting and receiving all
1’s)
450
520
mA
PDD
Power Dissipation
1.3
1.5
W
VIL
Input Low Voltage
0.8
V
VIH
Input High Voltage
5.0
V
VOL
Output Low Voltage, IOUT = - 4mA
0.4
V
VOH
Output High Voltage, IOUT = 4 mA
2.0
2.4
V
IL
Input Leakage Current1
±10
µA
CI
Input Capacitance
10
pF
CL
Load Capacitance
10
pF
NOTES:
1.
Not applicable for pins with pull-up or pull-down resistors.
2.
The Digital inputs and outputs are TTL 5V compliant.
17
XRT75L04
FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.4
2.0 TIMING CHARACTERISTICS
FIGURE 3. TYPICAL INTERFACE BETWEEN TERMINAL EQUIPMENT AND THE XRT75L04 (DUAL-RAIL DATA)
Terminal
Equipment
(E3/DS3 or STS-1
Framer)
TxPOS
TPData
TxNEG
TNData
TxLineClk
TxClk
Transmit
Logic
Block
Exar E3/DS3/STS-1 LIU
FIGURE 4. TRANSMITTER TERMINAL INPUT TIMING
t RTX
t FTX
TxCLK
t TSU
t THO
TPO S or
TNEG
TTIP or
TRING
t TDY
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
TxClk
Duty Cycle
E3
DS3
STS-1
30
50
34.368
44.736
51.84
70
%
MHz
MHz
MHz
tRTX
TxCLK Rise Time (10% to 90%)
4
ns
tFTX
TxCLKFall Time (10% to 90%)
4
ns
tTSU
TPOS/TNEG to TxCLK falling set up time
3
ns
tTHO
TPOS/TNEG to TxCLK falling hold time
3
ns
tTDY
TTIP/TRINGto TxCLK rising propagation delay time
18
8
ns
XRT75L04
REV. 1.0.4
FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
FIGURE 5. RECEIVER DATA OUTPUT AND CODE VIOLATION TIMING
tRRX
tFRX
RxCLK
tLCVO
LCV
tCO
RPOS or
RNEG
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
RxClk
Duty Cycle
E3
DS3
STS-1
45
50
34.368
44.736
51.84
55
%
MHz
MHz
MHz
tRRX
RxCLK rise time (10% o 90%)
2
4
ns
tFRX
RxCLKfalling time (10% to 90%)
2
4
ns
tCO
RxCLKto RPOS/RNEG delay time
4
ns
tLCVO
RxCLK to rising edge of LCV output delay
2.5
ns
FIGURE 6. TRANSMIT INTERFACE CIRCUIT FOR E3, DS3 AND STS-1 RATES
R1
TTIP(n)
31.6Ω +1%
TxPOS(n)
TxNEG(n)
TxLineClk(n)
TPOS(n)
TNEG(n)
TxCLK(n)
R3
75Ω
3 kΩ + 1%
1:1
RxB
RxA
31.6Ω + 1%
TRING(n)
R2
XRT75L04 (0nly one channel shown)
19
XRT75L04
FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.4
3.0 LINE SIDE CHARACTERISTICS:
3.1
E3 line side parameters:
The XRT75L04 line output at the transformer output meets the pulse shape specified in ITU-T G.703 for 34.368
Mbits/s operation. The pulse mask as specified in ITU-T G.703 for 34.368 Mbits/s is shown in Figure 7.
FIGURE 7. PULSE MASK FOR E3 (34.368 MBITS/S) INTERFACE AS PER ITU-T G.703
17 ns
(14.55 + 2.45)
8.65 ns
V = 100%
Nominal Pulse
50%
14.55ns
12.1ns
(14.55 - 2.45)
10%
0%
10%
20%
TABLE 3: E3 TRANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS
PARAMETER
MIN
TYP
MAX
UNITS
1.00
1.10
Vpk
TRANSMITTER LINE SIDE OUTPUT CHARACTERISTICS
Transmit Output Pulse Amplitude
(Measured at secondary of the transformer)
0.90
Transmit Output Pulse Amplitude Ratio
0.95
1.00
1.05
Transmit Output Pulse Width
12.5
14.55
16.5
ns
RECEIVER LINE SIDE INPUT CHARACTERISTICS
Receiver Sensitivity (length of cable)
1200
feet
Interference Margin
-20
-16
dB
Jitter Tolerance @ Jitter Frequency 800KHz
0.15
0.30
UIPP
Signal level to Declare Loss of Signal
-35
dB
Signal Level to Clear Loss of Signal
-15
Occurence of LOS to LOS Declaration Time
10
255
UI
Termination of LOS to LOS Clearance Time
10
255
UI
NOTE: The above values are at
TA = 250C and VDD = 3.3 V± 5%.
20
dB
XRT75L04
FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.4
FIGURE 8. BELLCORE GR-253 CORE TRANSMIT OUTPUT PULSE TEMPLATE FOR SONET STS-1 APPLICATIONS
ST S-1 Pulse T emplate
1.2
1
Norm a liz e d Am plitude
0.8
0.6
Lower Curve
Upper Curve
0.4
0.2
0
2
3
4
1.
1.
1.
1
9
0.
1
8
0.
1.
6
0.
7
5
0.
0.
4
0.
0.
2
3
0.
0
1
0.
.1
-0
.3
.4
.2
-0
-0
.6
.7
.5
-0
-0
-0
-0
.9
.8
-0
-0
-1
-0.2
Time, in UI
TABLE 4: STS-1 PULSE MASK EQUATIONS
TIME IN UNIT INTERVALS
NORMALIZED AMPLITUDE
LOWER CURVE
-0.85 < T < -0.38
-0.38
- 0.03
π
T
0.5 1 + sin --- ⎛ 1 + ----------- ⎞ – 0.03
2⎝
0.18 ⎠
< T < 0.36
0.36 < T < 1.4
- 0.03
UPPER CURVE
-0.85 < T < -0.68
0.03
-0.68 < T < 0.26
T
π
0.5 1 + sin --- ⎛ 1 + ----------- ⎞ + 0.03
⎝
2
0.34 ⎠
0.26 < T < 1.4
0.1 + 0.61 x e-2.4[T-0.26]
21
XRT75L04
FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.4
TABLE 5: STS-1 TRANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS (GR-253)
PARAMETER
MIN
TYP
MAX
UNITS
TRANSMITTER LINE SIDE OUTPUT CHARACTERISTICS
Transmit Output Pulse Amplitude
(measured with TxLEV = 0)
0.65
0.75
0.90
Vpk
Transmit Output Pulse Amplitude
(measured with TxLEV = 1)
0.90
1.00
1.10
Vpk
Transmit Output Pulse Width
8.6
9.65
10.6
ns
Transmit Output Pulse Amplitude Ratio
0.90
1.00
1.10
RECEIVER LINE SIDE INPUT CHARACTERISTICS
Receiver Sensitivity (length of cable)
900
1100
feet
Jitter Tolerance @ Jitter Frequency 400 KHz
0.15
0.79
UIpp
NOTE: The above values are at
TA = 250C and VDD = 3.3 V ± 5%.
FIGURE 9. TRANSMIT OUPUT PULSE TEMPLATE FOR DS3 AS PER BELLCORE GR-499
D S3 Pulse T em plate
1.2
1
0.6
Lower Curve
Upper Curve
0.4
0.2
0
Tim e , in UI
22
1
2
3
4
1.
1.
9
0.
1.
8
0.
1
7
0.
1.
5
6
0.
0.
3
4
0.
2
0.
0.
0
1
0.
.2
.3
.4
.5
.6
.7
.8
.1
-0
-0
-0
-0
-0
-0
-0
-0
-0
.9
-0.2
-1
Norm a lize d Am plitude
0.8
XRT75L04
REV. 1.0.4
FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
TABLE 6: DS3 PULSE MASK EQUATIONS
TIME IN UNIT INTERVALS
NORMALIZED AMPLITUDE
LOWER CURVE
-0.85 < T < -0.36
-0.36
- 0.03
π
T
0.5 1 + sin --- ⎛ 1 + ----------- ⎞ – 0.03
2⎝
0.18 ⎠
< T < 0.36
0.36 < T < 1.4
- 0.03
UPPER CURVE
-0.85 < T < -0.68
0.03
-0.68 < T < 0.36
π
T
0.5 1 + sin --- ⎛ 1 + ----------- ⎞ + 0.03
2⎝
0.34 ⎠
0.36 < T < 1.4
0.08 + 0.407 x e-1.84[T-0.36]
TABLE 7: DS3 TRANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS (GR-499)
PARAMETER
MIN
TYP
MAX
UNITS
TRANSMITTER LINE SIDE OUTPUT CHARACTERISTICS
Transmit Output Pulse Amplitude
(measured with TxLEV = 0)
0.65
0.75
0.85
Vpk
Transmit Output Pulse Amplitude
(measured with TxLEV = 1)
0.90
1.00
1.10
Vpk
Transmit Output Pulse Width
10.10
11.18
12.28
ns
Transmit Output Pulse Amplitude Ratio
0.90
1.00
1.10
RECEIVER LINE SIDE INPUT CHARACTERISTICS
Receiver Sensitivity (length of cable)
900
Jitter Tolerance @ 400 KHz (Cat II)
NOTE: The above values are at
TA = 250C and VDD = 3.3V ± 5%.
23
1100
feet
0.60
UIpp
XRT75L04
FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.4
FIGURE 10. MICROPROCESSOR SERIAL INTERFACE STRUCTURE
CS
SClk
1
SDI
R/W
2
3
A0
A1
4
A2
5
A3
6
A4
7
A5
8
0
9
10
11
12
13
14
15
16
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
High Z
High Z
SDO
FIGURE 11. TIMING DIAGRAM FOR THE MICROPROCESSOR SERIAL INTERFACE
t28
t21
CS
t26
t 24
SCLK
t 23
t 22
SDI
t27
t 25
A0
R/W
A1
CS
SCLK
t30
t29
SDO
SDI
Hi-Z
D0
t 32
t 31
D2
D1
Hi-Z
24
D7
XRT75L04
REV. 1.0.4
FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
TABLE 8: MICROPROCESSOR SERIAL INTERFACE TIMINGS ( TA = 250C, VDD=3.3V± 5% AND LOAD = 10PF)
SYMBOL
PARAMETER
MIN.
TYP.
MAX
UNITS
t21
CS Low to Rising Edge of SClk
5
ns
t22
SDI to Rising Edge of SClk
5
ns
t23
SDI to Rising Edge of SClk Hold Time
5
ns
t24
SClk "Low" Time
25
ns
t25
SClk "High" Time
25
ns
t26
SClk Period
50
ns
t27
Falling Edge of SClk to rising edge of CS
0
ns
t28
CS "Inactive" Time
50
ns
t29
Falling Edge of SClk to SDO Valid Time
20
ns
t30
Falling Edge of SClk to SDO Invalid Time
10
ns
t31
Rising edge of CS to High Z
t32
Rise/Fall time of SDO Output
10
ns
5
25
ns
XRT75L04
FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.4
4.0 THE TRANSMITTER SECTION:
The Transmitter Section, within each Channel, accepts TTL/CMOS level signals from the Terminal Equipment
in selectable data formats.
• Convert the CMOS level B3ZS or HDB3 encoded data into pulses with shapes that are compliant with the
various industry standard pulse template requirements. Figures 7, 8 and 9 illustrate the pulse template
requirements.
• Encode the un-encoded NRZ data into either B3ZS format (for DS3 or STS-1) or HDB3 format (for E3) and
convert to pulses with shapes and width that are compliant with industry standard pulse template
requirements. Figures 7, 8 and 9 illustrate the pulse template requirements.
• In Single-Rail or un-encoded Non-Return-to-Zero (NRZ) mode, data is input via TPOS_n pins while TNEG_n
pins must be grounded. The NRZ or Single-Rail mode is selected when the SR/DR input pin is “High” (in
Hardware Mode) or bit 0 of channel control register is “1” (in Host Mode). Figure 12 illustrates the Single-Rail
or NRZ format.
FIGURE 12. SINGLE-RAIL OR NRZ DATA FORMAT (ENCODER AND DECODER ARE ENABLED)
Data
1
1
0
TPOS
TxClk
• In Dual-Rail mode, data is input via TPOS_n and TNEG_n pins. TPOS_n contains positive data and
TNEG_n contains negative data. The SR/DR input pin = “Low” (in Hardware Mode) or bit 0 of channel
register = “0” (in Host Mode) enables the Dual-Rail mode. Figure 13 illustrates the Dual-Rail data format.
FIGURE 13. DUAL-RAIL DATA FORMAT (ENCODER AND DECODER ARE DISABLED)
Data
1
1
0
TPOS
TNEG
TxClk
4.1
TRANSMIT CLOCK:
The Transmit Clock applied via TxClk_n pins, for the selected data rate (for E3 = 34.368 MHz, DS3 = 44.736
MHz or STS-1 = 51.84 MHz), is duty cycle corrected by the internal PLL circuit to provide a 50% duty cycle
clock to the pulse shaping circuit. This allows a 30% to 70% duty cycle Transmit Clock to be supplied.
4.2
B3ZS/HDB3 ENCODER:
When the Single-Rail (NRZ) data format is selected, the Encoder Block encodes the data into either B3ZS
format (for either DS3 or STS-1) or HDB3 format (for E3).
4.2.1
B3ZS Encoding:
26
XRT75L04
REV. 1.0.4
FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
An example of B3ZS encoding is shown in Figure 14. If the encoder detects an occurrence of three
consecutive zeros in the data stream, it is replaced with either B0V or 00V, where ‘B’ refers to Bipolar pulse
that is compliant with the Alternating polarity requirement of the AMI (Alternate Mark Inversion) line code and
‘V’ refers to a Bipolar Violation (e.g., a bipolar pulse that violates the AMI line code). The substitution of B0V or
00V is made so that an odd number of bipolar pulses exist between any two consecutive violation (V) pulses.
This avoids the introduction of a DC component into the line signal.
FIGURE 14. B3ZS ENCODING FORMAT
T C lk
4.2.2
T PD AT A
1
0
Line
Signal
1
0
1
1
1
0
0
0
0
0
V
0
1
0
1
0
0
0
0
0
1
0
0
0
B
0
V
V
0
0
0
B
0
V
HDB3 Encoding:
An example of the HDB3 encoding is shown in Figure 15. If the HDB3 encoder detects an occurrence of four
consecutive zeros in the data stream, then the four zeros are substituted with either 000V or B00V pattern. The
substitution code is made in such a way that an odd number of bipolar (B) pulses exist between any
consecutive V pulses. This avoids the introduction of DC component into the analog signal.
FIGURE 15. HDB3 ENCODING FORMAT
TClk
TPDATA
1
0
Line
Signal
1
0
1
1
1
0
0
0
0
0
0
0
V
1
1
1
0
0
0
0
0
0
0
0
0
0
0
B
0
0
V
0
V
NOTES:
4.3
1.
When Dual-Rail data format is selected, the B3ZS/HDB3 Encoder is automatically disabled.
2.
In Dual-Rail format, the Bipolar Violations in the incoming data stream is converted to valid data pulses.
3.
Encoder and Decoder is enabled only in Single-Rail mode.
TRANSMIT PULSE SHAPER:
The Transmit Pulse Shaper converts the B3ZS encoded digital pulses into a single analog Alternate Mark
Inversion (AMI) pulse that meet the industry standard mask template requirements for STS-1 and DS3. See
Figures 8 and 9.
For E3 mode, the pulse shaper converts the HDB3 encoded pulses into a single full amplitude square shaped
pulse with very little slope. This is illustrated in Figure 7.
27
XRT75L04
FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.4
The Pulse Shaper Block also includes a Transmit Build Out Circuit, which can either be disabled or enabled by
setting the TxLEV_n input pin “High” or “Low” (in Hardware Mode) or setting the TxLEV_n bit to “1” or “0” in the
control register (in Host Mode).
For DS3/STS-1 rates, the Transmit Build Out Circuit is used to shape the transmit waveform that ensures that
transmit pulse template requirements are met at the Cross-Connect system. The distance between the
transmitter output and the Cross-Connect system can be between 0 to 450 feet.
For E3 rate, since the output pulse template is measured at the secondary of the transformer and since there is
no Cross-Connect system pulse template requirements, the Transmit Build Out Circuit is always disabled.
4.3.1
Guidelines for using Transmit Build Out Circuit:
If the distance between the transmitter and the DSX3 or STSX-1, Cross-Connect system, is less than 225 feet,
enable the Transmit Build Out Circuit by setting the TxLEV_n input pin “Low” (in Hardware Mode) or setting the
TxLEV_n control bit to “0” (in Host Mode).
If the distance between the transmitter and the DSX3 or STSX-1 is greater than 225 feet, disable the Transmit
Build Out Circuit.
4.3.2
Interfacing to the line:
The differential line driver increases the transmit waveform to appropriate level and drives into the 75Ω load as
shown in Figure 6.
4.4
Transmit Drive Monitor:
This feature is used for monitoring the transmit line for occurrence of fault conditions such as a short circuit on
the line or a defective line driver.
To activate this function, connect MTIP_n pins to the TTIP_n lines via a 270 Ω resistor and MRing_n pins to
TRing_n lines via 270 Ω resistor as shown in Figure 16.
FIGURE 16. TRANSMIT DRIVER MONITOR SET-UP.
R1
TTIP(n)
31.6Ω +1%
TxPOS(n)
TxNEG(n)
TxLineClk(n)
R3
75Ω
TPOS(n)
TNEG(n)
TxCLK(n) TRING(n)
R2
1:1
3kΩ + 1%
31.6Ω + 1%
RxB
RxA
MTIP(n)
R4 270Ω
MRING(n)
R5 270Ω
XRT75L04 (0nly one channel shown)
Case 1:
MTIP_1 connected to TTIP_1
MRING_1 connected to TRING_1
TxMON_1 (bit) = 0
As shown in the figure 18, connect MTIP_1 to TTIP_1 and MRING_1 to TRING_1 via the 270 Ω resistors.
When no transitions on the line are detected for 128 ± 32 TxClk_1 periods, the DMO_1 pin will toggle “High”.
28
XRT75L04
REV. 1.0.4
FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
The DMO_1 and the DMOIS_1 bits also will be set in the control register. When the transitions are detected,
the DMO_1 pin will toggle back to normal state. The DMO_1 bit also will be cleared. However, the DMOIS_1 bit
will remain set until read. If the DMOIE_1 bit has been set, an interrupt will be generated.
29
XRT75L04
FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.4
Case 2:
MTIP_1 connected to TTIP_1
MRING_1 connected to TRING_1
TxMON_1 (bit) = 1
This has the same effect as in Case 1. It is redundant to use the MTIP_1/MRING_1 pins in this case.
Case 3:
MTIP_1 not connected to TTIP_1
MRING_1 not connected to TRING_1
TxMON_1 (bit) = 1
When no transitions on the TTIP_1/TRING_1 are detected for 128 ± 32 TxClk_1 periods, the DMO_1 pin will
toggle “High”. The DMO_1 and the DMOIS_1 bits also will be set in the control register. When the transitions
are detected, the DMO_1 pin will toggle back to normal state. The DMO_1 bit also will be cleared. However,
the DMOIS_1 bit will remain set until read. If the DMOIE_1 bit has been set, an interrupt will be generated.
Please note that the MTIP_1/MRING_1 pins cannot be used to monitor any other adjacent channels.
Case 4:
MTIP_m not connected to TTIP_m +n where m = 0,1...3 and n = 0,1...3
MRING_m not connected to TRING_m +n where m = 0,1...3 and n = 0,1...3
TxMON_n (bit) = 0
In this case, with external connection, any of the MTIP/MRING can be connected to any of the adjacent
channel to be monitored.
Please note that if TxMON_n bit is set, then monitoring will be done for that channel n. By toggling the
TxMON_n bit from 0 to 1, the monitoring can be switched between self-monitoring to monitoring any adajcent
channels.
NOTE: The Drive Monitor Circuit is only for diagnostic purpose and does not have to be used to operate the transmitter.
4.5
Transmitter Section On/Off:
The transmitter section of each channel can either be turned on or off. To turn on the transmitter, set the input
pin TxON_n to “High” (in Hardware Mode) or write a “1” to the TxON_n control bits (in Host Mode) with
TxON_n pins tied “High”.
When the transmitter is turned off, TTIP_n and TRing_n are tri-stated.
NOTES:
1.
This feature provides support for Redundancy.
2.
If the XRT75L04 is configured in Host mode, to permit a system designed for redundancy to quickly shut-off the
defective line card and turn on the back-up line card, writing a “1” to the TxON_n control bits transfers the control
to TxON_n pins.
5.0 THE RECEIVER SECTION:
This section describes the detailed operation of the various blocks in the receiver. The receiver recovers the
TTL/CMOS level data from the incoming bipolar B3ZS or HDB3 encoded input pulses.
5.1
AGC/Equalizer:
The Adaptive Gain Control circuit amplifies the incoming analog signal and compensates for the various flat
losses and also for the loss at one-half symbol rate. The AGC has a dynamic range of 30 dB.
The Equalizer restores the integrity of the signal and compensates for the frequency dependent attenuation of
up to 900 feet of coaxial cable (1300 feet for E3). The Equalizer also boosts the high frequency content of the
30
XRT75L04
FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.4
signal to reduce Inter-Symbol Interference (ISI) so that the slicer slices the signal at 50% of peak voltage to
generate Positive and Negative data.
The Equalizer can either be “IN” or “OUT” by setting the REQEN_n pin “High” or “Low” (in Hardware Mode) or
setting the REQEN_n control bit to “1” or “0” (in Host Mode).
RECOMMENDATIONS FOR EQUALIZER SETTINGS:
The Equalizer has two gain settings to provide optimum equalization. In the case of normally shaped DS3/
STS-1 pulses (pulses that meet the template requirements) that has been driven through 0 to 900 feet of cable,
the Equalizer can be left “IN” by setting the REQEN_n pin to “High” (in Hardware Mode) or setting the
REQEN_n control bit to “1” (in Host Mode).
However, for square-shaped pulses such as E3 or for DS3/STS-1 high pulses (that does not meet the pulse
template requirements), it is recommended that the Equalizer be left “OUT” for cable length less than 300 feet
by setting the REQEN_n pin “Low” (in Hardware Mode) or by setting the REQEN_n control bit to “0” (in Host
Mode).This would help to prevent over-equalization of the signal and thus optimize the performance in terms of
better jitter transfer characteristics.
NOTE: The results of extensive testing indicates that even when the Equalizer was left “IN” (REQEN_n = “HIGH”),
regardless of the cable length, the integrity of the E3 signal was restored properly over 0 to 12 dB cable
loss at Industrial Temperature.
The Equalizer also contain an additional 20 dB gain stage to provide the line monitoring capability of the
resistively attenuated signals which may have 20dB flat loss. This capability can be turned on by writing a “1” to
the RxMON_n bits in the control register or by setting the RxMON pin (pin 69) “High”.
5.1.1
Interference Tolerance:
For E3 mode, ITU-T G.703 Recommendation specifies that the receiver be able to recover error-free clock and
data in the presence of a sinusoidal interfering tone signal. For DS3 and STS-1 modes, the same
recommendation is being used. Figure 17 shows the configuration to test the interference margin for DS3/
STS1. Figure 18 shows the set up for E3.
FIGURE 17. INTERFERENCE MARGIN TEST SET UP FOR DS3/STS-1
Attenuator
Sine Wave
Generator
N
DS3 = 22.368 MHz
STS-1 = 25.92 MHz
Cable Simulator
∑
DUT
XRT75L04
Test Equipment
Pattern Generator
2 23 -1 PRBS
S
31
XRT75L04
FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.4
FIGURE 18. INTERFERENCE MARGIN TEST SET UP FOR E3.
Attenuator 1
Noise Generator
Attenuator 2
N
Cable Simulator
∑
DUT
XRT75L04
Test Equipment
Signal Source
S
TABLE 9: INTERFERENCE MARGIN TEST RESULTS
MODE
CABLE LENGTH (ATTENUATION)
INTERFERENCE TOLERANCE
E3
0 dB
-14 dB
12 dB
-18 dB
0 feet
-17 dB
225 feet
-16 dB
450 feet
-16dB
0 feet
-16 dB
225 feet
-15 dB
450 feet
-15 dB
DS3
STS-1
5.2
Clock and Data Recovery:
The Clock and Data Recovery Circuit extracts the embedded clock, RxClk_n from the sliced digital data stream
and provides the retimed data to the B3ZS (HDB3) decoder.
The Clock Recovery PLL can be in one of the following two modes:
TRAINING MODE:
In the absence of input signals at RTIP_n and RRing_n pins, or when the frequency difference between the
recovered line clock signal and the reference clock applied on the ExClk_n input pins exceed 0.5%, a Loss of
Lock condition is declared by toggling RLOL_n output pin “High” (in Hardware Mode) or setting the RLOL_n bit
to “1” in the control registers (in Host Mode). Also, the clock output on the RxClk_n pins are the same as the
reference clock applied on ExClk_n pins.
DATA/CLOCK RECOVERY MODE:
In the presence of input line signals on the RTIP_n and RRing_n input pins and when the frequency difference
between the recovered clock signal and the reference clock signal is less than 0.5%, the clock that is output on
the RxClk_n out pins is the Recovered Clock signal.
5.3
B3ZS/HDB3 Decoder:
32
XRT75L04
FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.4
The decoder block takes the output from clock and data recovery block and decodes the B3ZS (for DS3 or
STS-1) or HDB3 (for E3) encoded line signal and detects any coding errors or excessive zeros in the data
stream.
Whenever the input signal violates the B3ZS or HDB3 coding sequence for bipolar violation or contains three
(for B3ZS) or four (for HDB3) or more consecutive zeros, an active “High” pulse is generated on the RLCV_n
output pins to indicate line code violation.
NOTE: In Single- Rail (NRZ) mode, the decoder is bypassed.
5.4
LOS (Loss of Signal) Detector:
5.4.1
DS3/STS-1 LOS Condition:
A Digital Loss of SIgnal (DLOS) condition occurs when a string of 175 ± 75 consecutive zeros occur on the line.
When the DLOS condition occurs, the DLOS_n bit is set to “1” in the status control register. DLOS condition is
cleared when the detected average pulse density is greater than 33% for 175 ± 75 pulses.
Analog Loss of Signal (ALOS) condition occurs when the amplitude of the incoming line signal is below the
threshold as shown in the Table 10.The status of the ALOS condition is reflected in the ALOS_n status control
register.
RLOS is the logical OR of the DLOS and ALOS states. When the RLOS condition occurs the RLOS_n output
pin is toggled “High” and the RLOS_n bit is set to “1” in the status control register.
TABLE 10: THE ALOS (ANALOG LOS) DECLARATION AND CLEARANCE THRESHOLDS FOR A GIVEN SETTING OF
REQEN (DS3 AND STS-1 APPLICATIONS)
APPLICATION
REQEN SETTING
SIGNAL LEVEL TO DECLARE ALOS
SIGNAL LEVEL TO CLEAR ALOS
DS3
0
70 mV
1
90 mV
0
90 mV
1
115 mV
STS-1
DISABLING ALOS/DLOS DETECTION:
For debugging purposes it is useful to disable the ALOS and/or DLOS detection. Writing a “1” to both
ALOSDIS_n and DLOSDIS_n bits disables the LOS detection on a per channel basis.
5.4.2
E3 LOS Condition:
If the level of incoming line signal drops below the threshold as described in the ITU-T G.775 standard, the
LOS condition is detected. Loss of signal level is defined to be between 15 and 35 dB below the normal level.
If the signal drops below 35 dB for 175 ± 75 consecutive pulse periods, LOS condition is declared. This is
illustrated in Figure 19.
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XRT75L04
FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.4
FIGURE 19. LOSS OF SIGNAL DEFINITION FOR E3 AS PER ITU-T G.775
0 dB
Maximum Cable Loss for E3
LOS Signal Must be Cleared
-12 dB
-15dB
LOS Signal may be Cleared or Declared
-35dB
LOS Signal Must be Declared
As defined in ITU-T G.775, an LOS condition is also declared between 10 and 255 UI (or E3 bit periods) after
the actual time the LOS condition has occurred. The LOS condition is cleared within 10 to 255 UI after
restoration of the incoming line signal. Figure 20 shows the LOS declaration and clearance conditions.
FIGURE 20. LOSS OF SIGNAL DEFINITION FOR E3 AS PER ITU-T G.775.
Actual Occurrence
of LOS Condition
Line Signal
is Restored
RTIP/
RRing
10 UI
255 UI
Time Range for
LOS Declaration
10 UI
255 UI
RLOS Output Pin
0 UI
0 UI
G.775
Compliance
Time Range for
LOS Clearance
34
G.775
Compliance
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REV. 1.0.4
5.4.3
FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
Muting the Recovered Data with LOS condition:
When the LOS condition is declared, the clock recovery circuit locks into the reference clock applied to the
ExClk_n pin and output this clock on the RxClk_n output.In Single Frequency Mode (SFM), the clock recovery
locks into the rate clock generated and output this clock on the RxClk_n pins. The data on the RPOS_n and
RNEG_n pins can be forced to zero by pulling the LOSMUT pin “High” (in Hardware Mode) or by setting the
LOSMUT_n bits in the individual channel control register to “1” (in Host Mode).
NOTE: When the LOS condition is cleared, the recovered data is output on RPOS_n and RNEG_n pins.
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FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.4
6.0 JITTER:
There are three fundamental parameters that describe circuit performance relative to jitter:
• Jitter Tolerance (Receiver)
• Jitter Transfer (Receiver/Transmitter)
• Jitter Generation
6.1
JITTER TOLERANCE - RECEIVER:
Jitter tolerance is a measure of how well a Clock and Data Recovery unit can successfully recover data in the
presence of various forms of jitter. It is characterized by the amount of jitter required to produce a specified bit
error rate. The tolerance depends on the frequency content of the jitter. Jitter Tolerance is measured as the
jitter amplitude over a jitter spectrum for which the clock and data recovery unit achieves a specified bit error
rate (BER). To measure the jitter tolerance as shown in Figure 21, jitter is introduced by the sinusoidal
modulation of the serial data bit sequence.
FIGURE 21. JITTER TOLERANCE MEASUREMENTS
Pattern
Pattern
Generator
Generator
Data
Error
Detector
DUT
XRT75L04
Clock
Modulation
Freq.
FREQ
Synthesizer
Input jitter tolerance requirements are specified in terms of compliance with jitter mask which is represented as
a combination of points.Each point corresponds to a minimum amplitude of sinusoidal jitter at a given jitter
frequency.
6.1.1
DS3/STS-1 Jitter Tolerance Requirements:
Bellcore GR-499 CORE, Issue 1, December 1995 specifies the minimum requirement of jitter tolerance for
Category I and Category II. The jitter tolerance requirement for Category II is the most stringent. Figure 22
shows the jitter tolerance curve as per GR-499 specification.
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XRT75L04
FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.4
JITTER AMPLITUDE (UIpp)
FIGURE 22. INPUT JITTER TOLERANCE FOR DS3/STS-1
64
GR-253 STS-1
41
15
GR-499 Cat II
GR-499 Cat I
10
XRT75L04
5
1.5
0.3
0.15
0.1
0.01
0.03
0.3
2
20
100
JITTER FREQUENCY (kHz)
6.1.2
E3 Jitter Tolerance Requirements:
ITU-T G.823 standard specifies that the clock and data recovery unit must be able to accommodate and
tolerate jitter up to certain specified limits. Figure 23 shows the tolerance curve.
FIGURE 23. INPUT JITTER TOLERANCE FOR E3
ITU-T G.823
JITTER AMPLITUDE (UIpp)
64
XRT75L04
10
1.5
0.3
0.1
1
10
800
JITTER FREQUENCY (kHz)
As shown in the Figures 22 and 23 above, in the jitter tolerance measurement, the dark line indicates the
minimum level of jitter that the E3/DS3/STS-1 compliant component must tolerate.
The Table 11 below shows the jitter amplitude versus the modulation frequency for various standards.
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FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.4
TABLE 11: JITTER AMPLITUDE VERSUS MODULATION FREQUENCY (JITTER TOLERANCE)
INPUT JITTER AMPLITUDE (UI P-P)
BIT RATE
(KB/S)
STANDARD
34368
MODULATION FREQUENCY
A1
A2
A3
F1(HZ)
F2(HZ)
F3(KHZ)
F4(KHZ)
F5(KHZ)
ITU-T G.823
1.5
0.15
-
100
1000
10
800
-
44736
GR-499
CORE Cat I
5
0.1
-
10
2.3k
60
300
-
44736
GR-499
CORE Cat II
10
0.3
-
10
669
22.3
300
-
51840
GR-253
CORE Cat II
15
1.5
0.15
10
30
300
2
20
6.2
JITTER TRANSFER - RECEIVER/TRANSMITTER:
Jitter Transfer function is defined as the ratio of jitter on the output relative to the jitter applied on the input
versus frequency.
There are two distinct characteristics in jitter transfer: jitter gain (jitter peaking) defined as the highest ratio
above 0dB; and jitter transfer bandwidth.The overall jitter transfer bandwidth is controlled by a low bandwidth
loop, typically using a voltage-controller crystal oscillator (VCXO).
The jitter transfer function is a ratio between the jitter output and jitter input for a component, or system often
expressed in dB. A negative dB jitter transfer indicates the element removed jitter. A positive dB jitter transfer
indicates the element added jitter.A zero dB jitter transfer indicates the element had no effect on jitter.
Table 12 shows the jitter transfer characteristics and/or jitter attenuation specifications for various data rates:
TABLE 12: JITTER TRANSFER SPECIFICATION/REFERENCES
E3
DS3
STS-1
ETSI TBR-24
GR-499 CORE section 7.3.2
Category I and Category II
GR-253 CORE section 5.6.2.1
The above specifications can be met only with a jitter attenuator that supports E3/DS3/STS-1 rates.
6.3
JITTER GENERATION:
Jitter Generation is defined as the process whereby jitter appears at the output port of the digital equipment in
the absence of applied input jitter. Jitter Generation is measured by sending jitter free data to the clock and
data recovery circuit and measuring the amount of jitter on the output clock or the re-timed data. Since this is
essentially a noise measurement, it requires a definition of bandwidth to be meaningful. The bandwidth is set
according to the data rate. In general, the jitter is measured over a band of frequencies.
6.4
Jitter Attenuator:
An advanced crystal-less jitter attenuator per channel is included in the XRT75L04. The jitter attenuator
requires no external crystal nor high-frequency reference clock.
In Host mode, by clearing or setting the JATx/Rx_n bits in the channel control registers selects the jitter
attenuator either in the Receive or Transmit path on per channel basis. In Hardware mode, JATx/Rx pin selects
globally all three channels either in Receive or Transmit path.
The FIFO size can be either 16-bit or 32-bit. In HOST mode, the bits JA0_n and JA1_n can be set to
appropriate combination to select the different FIFO sizes or to disable the Jitter Attenuator on a per channel
basis. In Hardware mode, appropriate setting of the pins JA0 and JA1 selects the different FIFO sizes or
disables the Jitter Attenuator for all three channels. Data is clocked into the FIFO with the associated clock
38
XRT75L04
REV. 1.0.4
FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
signal (TxClk or RxClk) and clocked out of the FIFO with the dejittered clock. When the FIFO is within two bits
of overflowing or underflowing, the FIFO limit status bit, FL_n is set to “1” in the Alarm status register. Reading
this bit clears the FIFO and resets the bit into default state.
NOTE: It is recommended to select the 16-bit FIFO for delay-sensitive applications as well as for removing smaller amounts
of jitter. Table 13 specifies the jitter transfer mask requirements for various data rates:
TABLE 13: JITTER TRANSFER PASS MASKS
RATE
F1
(HZ)
F2
(HZ)
F3
(HZ)
F4
(KHZ)
A1(dB)
A2(dB)
G.823
ETSI-TBR-24
100
300
3K
800K
0.5
-19.5
44736
GR-499, Cat I
GR-499, Cat II
GR-253 CORE
10
10
10
10k
56.6k
40
-
15k
300k
15k
0.1
0.1
0.1
-
51840
GR-253 CORE
10
40k
-
400k
0.1
-
(KBITS)
34368
MASK
The jitter attenuator in the XRT75L04 meets the latest jitter attenuation specifications and/or jitter transfer
characteristics as shown in the Figure 24.
JITTER AMPLITUDE
FIGURE 24. JITTER TRANSFER REQUIREMENTS AND JITTER ATTENUATOR PERFORMANCE
A1
A2
F1
F2
F3
F4
J IT T E R F R E Q U E N C Y (k H z )
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FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.4
7.0 SERIAL HOST INTERFACE:
A serial microprocessor interface is included in the XRT75L04. The interface is generic and is designed to
support the common microprocessors/microcontrollers. The XRT75L04 operates in Host mode when the
HOST/HW pin is tied “High”. The serial interface includes a serial clock (SClk), serial data input (SDI), serial
data output (SDO), chip select (CS) and interrupt output (INT). The serial interface timing is shown in Figure
11.
The active low interrupt output signal (INT pin) indicates alarm conditions like LOS, DMO and FL to the
processor.
When the XRT75L04 is configured in Host mode, the following input pins,TxLEV_n, TAOS_n, RLB_n, LLB_n,
E3_n, STS-1/DS3_n, REQEN_n, JATx/Rx, JA0 and JA1 are disabled and must be connected to ground.
The Table 14 below illustrates the functions of the shared pins in either Host mode or in Hardware mode.
TABLE 14: FUNCTIONS OF SHARED PINS
PIN NUMBER
IN HOST MODE
IN HARDWARE MODE
86
CS
RxClkINV
88
SClk
TxClkINV
87
SDI
RxON
85
SDO
RxMON
84
INT
LOSMUT
NOTE: While configured in Host mode, the TxON_n input pins will be active if the TxON_n bits in the control register are set
to “1”, and can be used to turn on and off the transmit output drivers. This permits a system designed for
redundancy to quickly switch out a defective line card and switch-in the backup line card.
TABLE 15: REGISTER MAP AND BIT NAMES
ADDRESS
(HEX)
PARAMETER
NAME
0x00
APS/Redundancy
(read/write)
0x010x1F
DATA BITS
7
6
5
4
3
2
1
0
RxON-3
RxON-2
RxON-1
RxON_0
TxON_3
TxON_2
TxON_1
TxON_0
Channel 0 - 3 Control Registers
0x20
Interrupt EnableGlobal
(read/write)
Reserved
INTEN_3 INTEN_2 INTEN_1 INTEN_0
0x21
Interrupt Status
(read only)
Reserved
INTST_3
0x220x2F
Reserved
Reserved
0x30 0x37
PRBS Count Registers
0x38
PRBS Holding Register
0x39 0x3D
Reserved
40
INTST_2
INTST_1
INTST_0
XRT75L04
FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.4
TABLE 15: REGISTER MAP AND BIT NAMES
DATA BITS
ADDRESS
(HEX)
PARAMETER
NAME
0x3E
Chip_id
(read only)
Device part number (7:0)
0x3F
Chip_version
(read only)
Chip revision number (7:0)
7
6
5
4
3
2
1
0
TABLE 16: REGISTER MAP DESCRIPTION - GLOBAL
ADDRESS
(HEX)
0x00
TYPE
R/W
REGISTER
NAME
APS/Redu
ndancy
DEFAULT
VALUE
SYMBOL
DESCRIPTION
RxON_n
Bit 4 = RxON_0,Bit 5 = RxON_1,Bit 6 = RxON_2 and
Bit 7 = RxON_3
Receiver Turn On. Writing a “1” to the bit field turns
on the Receiver and a “0” turn off the Receiver.
0
TxON_n
Bit 0 = TxON_0, Bit 1 = TxON_1, Bit 2 = TxON_2 and
Bit 3 = TxON_3
Table below shows the status of the transmitter based
on the bit and pin setting.
0
Bit
Pin
Transmitter Status
0
0
OFF
0
1
OFF
1
0
OFF
1
1
ON
0x20
R/W
Interrupt
Enable
INTEN_n
Bit 0 = INTEN_0, Bit 1 = INTEN_1, Bit 2 = INTEN_2
Bit 3 = INTEN_3.
Writing a “1” to these bits enable the interrupts for the
corresponding channels.
0
0x21
Read
Only
Interrupt
Status
INTST_n
Bit 0 = INTST_0, Bit 1 = INTST_1, Bit 2 = INTST_2
Bit 3 = INTST_3.
Respective bits are set to “1” if an interrupt service is
required. The respective source level interrupt status
registers are read to determine the cause of interrupt.
0
0x22 0x2F
Reserved
0x39 0x3D
Reserved
0x3E
Read
Only
Device
Number
0x3F
Read
Only
Version
Number
Chip_id
This read only register contains device id.
Chip_version This read only register contains chip version number
41
01110100
00000001
XRT75L04
FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.4
TABLE 17: REGISTER MAP AND BIT NAMES - CHANNEL 0 REGISTERS
DATA BITS
ADDRESS
(HEX)
PARAMETER
NAME
0x01
Interrupt Enable
(read/write)
Reserved
PRBSER PRBSERI
CNTIE_0
E_0
FLIE_0
RLOLIE_0 RLOSIE_ DMOIE_0
0
0x02
Interrupt Status
(reset on read)
Reserved
PRBSER PRBSERI
CNTIS_0
S_0
FLIS_0
RLOLIS_0 RLOSIS_ DMOIS_0
0
0x03
Alarm Status
(read only)
0x04
Transmit Control
(read/write)
Reserved
TxMON_0 INSPRBS
_0
0x05
Receive Control
(read/write)
Reserved
DLOSDIS ALOSDIS RxClkINV_ LOSMUT_ RxMON_0 REQEN_
_0
_0
0
0
0
0x06
Block Control
(read/write)
Reserved
PRBSEN_
0
0x07
Jitter Attenuator
(read/write)
0x08
Reserved
7
6
5
4
Reserved PRBSLS_0 DLOS_0
Reserved
3
ALOS_0
RLB_0
2
1
0
FL_0
RLOL_0
RLOS_0
Reserved
TAOS_0
TxClkINV TxLEV_0
_0
LLB_0
DFLCK_0 PNTRST_
0
DMO_0
E3_0
STS1/
DS3_0
SR/DR_0
JA1_0
JATx/
Rx_0
JA0_0
Reserved
TABLE 18: REGISTER MAP AND BIT NAMES - CHANNEL 1 REGISTERS
DATA BITS
ADDRESS
(HEX)
PARAMETER
NAME
0x09
Interrupt Enable
(read/write)
Reserved
PRBSER PRBSERI
CNTIE_1
E_1
FLIE_1
RLOLIE_1 RLOSIE_ DMOIE_1
1
0x0A
Interrupt Status
(reset on read)
Reserved
PRBSER PRBSERI
CNTIS_1
S_1
FLIS_1
RLOLIS_1 RLOSIS_ DMOIS_1
1
0x0B
Alarm Status
(read only)
Reserved PRBSLS_
1
0x0C
Transmit Control
(read/write)
Reserved
TxMON_1 INSPRBS Reserved
_1
0x0D
Receive Control
(read/write)
Reserved
DLOSDIS ALOSDIS RxClkINV LOSMUT_ RxMON_1 REQEN_1
_1
_1
_1
1
0x0E
Block Control
(read/write)
Reserved
PRBSEN_
1
0x0F
Jitter Attenuator
(read/write)
7
6
5
4
DLOS_1
Reserved
ALOS_1
RLB_1
3
FL_1
LLB_1
DFLCK_1 PNTRST_
1
42
2
1
0
RLOL_1
RLOS_1
DMO_1
TAOS_1
TxClkINV
_1
TxLEV_1
E3_1
STS1/
DS3_1
SR/DR_1
JA1_1
JATx/
Rx_1
JA0_1
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REV. 1.0.4
FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
TABLE 18: REGISTER MAP AND BIT NAMES - CHANNEL 1 REGISTERS
ADDRESS
(HEX)
PARAMETER
NAME
0x10
Reserved
DATA BITS
7
6
5
4
3
2
1
0
1
0
Reserved
TABLE 19: REGISTER MAP AND BIT NAMES - CHANNEL 2 REGISTERS
DATA BITS
ADDRESS
(HEX)
PARAMETER
NAME
0x11
Interrupt Enable
(read/write)
Reserved
PRBSER PRBSERI
CNTIE_2
E_2
FLIE_2
RLOLIE_2 RLOSIE_ DMOIE_2
2
0x12
Interrupt Status
(reset on read)
Reserved
PRBSER PRBSERI
CNTIS_2
S_2
FLIS_2
RLOLIS_2 RLOSIS_ DMOIS_2
2
0x13
Alarm Status
(read only)
Reserved PRBSLS_
2
0x14
Transmit Control
(read/write)
Reserved
TxMON_2 INSPRBS Reserved
_2
0x15
Receive Control
(read/write)
Reserved
DLOSDIS ALOSDIS RxClkINV LOSMUT_ RxMON_2 REQEN_2
_2
_2
_2
2
0x16
Block Control
(read/write)
Reserved
PRBSEN_
2
0x17
Jitter Attenuator
(read/write)
0x18
Reserved
7
6
5
4
DLOS_2
Reserved
3
ALOS_2
RLB_2
FL_2
LLB_2
DFLCK_2 PNTRST_
2
2
RLOL_2
RLOS_2
DMO_2
TAOS_2
TxClkINV
_2
TxLEV_2
E3_2
STS1/
DS3_2
SR/DR_2
JA1_2
JATx/
Rx_2
JA0_2
1
0
Reserved
TABLE 20: REGISTER MAP AND BIT NAMES - CHANNEL 3 REGISTERS
DATA BITS
ADDRESS
(HEX)
PARAMETER
NAME
0x19
Interrupt Enable
(read/write)
0x1A
Interrupt Status Reserved
(reset on read)
7
6
Reserved
0x1B
Alarm Status
(read only)
Reserved PRBSLS_
3
0x1C
Transmit Control
(read/write)
Reserved
5
4
3
2
PRBSER PRBSERI
CNTIE_3
E_3
FLIE_3
RLOLIE_3 RLOSIE_ DMOIE_3
3
PRBSER PRBSERI
CNTIS_3
S_3
FLIS_3
RLOLIS_3 RLOSIS_ DMOIS_3
3
DLOS_3
ALOS_3
FL_3
TxMON_3 INSPRBS Reserved
_3
43
RLOL_3
RLOS_3
DMO_3
TAOS_3
TxClkINV
_3
TxLEV_3
XRT75L04
FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.4
TABLE 20: REGISTER MAP AND BIT NAMES - CHANNEL 3 REGISTERS
DATA BITS
ADDRESS
(HEX)
PARAMETER
NAME
0x1D
Receive Control
(read/write)
Reserved
DLOSDIS ALOSDIS RxClkINV LOSMUT_ RxMON_3 REQEN_3
_3
_3
_3
3
0x1E
Block Control
(read/write)
Reserved
PRBSEN_
3
0x1F
Jitter Attenuator
(read/write)
7
6
5
4
Reserved
RLB_3
3
LLB_3
DFLCK_3 PNTRST_
3
2
1
0
E3_3
STS1/
DS3_3
SR/DR_3
JA1_3
JATx/
Rx_3
JA0_3
TABLE 21: REGISTER MAP DESCRIPTION
ADDRESS
(HEX)
0x01 (ch 0)
0x09 (ch 1)
0x11 (ch 2)
0x19 (ch 3)
TYPE
R/W
REGISTER
NAME
Interrupt
Enable
(source
level)
DEFAULT
VALUE
BIT#
SYMBOL
DESCRIPTION
D0
DMOIE_n
Set this bit to enable an interrupt when the no transmission detected on channel output.
0
D1
RLOSIE_n Writng a “1” to this bit enables an interrupt when
Recieve Los of Signal is detected.
0
D2
RLOLIE_n Writing a “1” to this bit enables an interrupt when
Receive Loss of Lock condition is detected
0
D3
FLIE_n
Writing a “1” to this bit enables the interrupt when
the FIFO Limit of the Jitter Attenuator is within 2 bits
of overflow/underflow condition.
NOTE:
0
This bit field is ignored when the Jitter
Attenuator is disabled.
D4
PRBSERIE Set this bit to enable the interrupt when the PRBS
_n
error is detected.
0
D5
PRBSERC Set this bit to enable the interrupt when the PRBS
NTIE_n
error count register saturates.
0
D7-D6
Reserved
44
XRT75L04
FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.4
TABLE 21: REGISTER MAP DESCRIPTION
ADDRESS
(HEX)
TYPE
REGISTER
NAME
0x02 (ch 0) Reset Interrupt
on
Status
0x0A (ch 1)
0x12 (ch 2) Read (source
level)
0x1A (ch 3)
DEFAULT
VALUE
BIT#
SYMBOL
DESCRIPTION
D0
DMOIS_n
This bit is set every time a DMO status change has
occurred since the last cleared interrupt. This bit is
cleared when the register bit is read.
0
D1
RLOSIS_n This bit is set every time a RLOS status change has
occurred since the last cleared interrupt. This bit is
cleared when the register bit is read.
0
D2
RLOLIS_n This bit is set every time a RLOL status change has
occurred since the last cleared interrupt. This bit is
cleared when the register bit is read.
0
D3
FLIS_n
D4
This bit is set every time a FIFO Limit status change
has occurred since the last cleared interrupt. This bit
is cleared when the register bit is read.
0
This bit is set when the PRBS error occurs.
0
PRBSERIS
_n
D5
PRBSERC This bit is set when the PRBS error count register
NTIS_n
saturates.
D7-D6
0x03 (ch 0)
0x0B (ch 1)
0x13 (ch 2)
0x1B (ch 3)
Read Alarm StaOnly tus
0
Reserved
D0
DMO_n
This bit is set when no transitions on the TTIP/
TRING have been detected for 128 ± 32 TxCLK
periods.
0
D1
RLOS_n
This bit is set every time the receiver declares an
LOS condition.
0
D2
RLOL_n
This bit is set every time when the receiver declares
a Loss of Lock condition.
0
D3
FL_n
This bit is set every time the FIFO in the Jitter Attenuator is within 2 bit of underflow/overflow condition.
0
D4
ALOS_n
This bit is set every time the receiver declares Analog LOS condition.
0
D5
DLOS_n
This bit is set every time the receiver declares Digital LOS condition.
0
PRBSLS_n This bit is set every time the PRBS detector is not in
sync.
0
D6
D7
Reserved
45
XRT75L04
FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.4
TABLE 21: REGISTER MAP DESCRIPTION
ADDRESS
(HEX)
TYPE
REGISTER
NAME
BIT#
D0
SYMBOL
DESCRIPTION
TxLEV_n Set this bit for cable length greater than 225
DEFAULT
VALUE
0
feet.
NOTE: See section 4.03 for detailed description.
D1
D2
0x04 (ch 0)
0x0C (ch 1)
0x14 (ch 2)
0x!C (ch 3)
R/W
Transmit
Control
TxClkINV_ Set this bit to sample the data on TPOS/TNEG pins
n
on the rising edge of TxClk.
TAOS_n
Set this bit to send a continuous stream of marks (All
Ones) out at the TTIP and TRing pins.
D3
D4
0
0
Reserved
INSPRBS_ Setting this bit causes the PRBS generator to insert
n
a single-bit error onto the transmit PRBS data
stream .
0
NOTE: PRBS Generator/Detector must be enabled
for this bit to have any effect.
D5
TxMON_n Setting this bit causes the driver monitor its own
transmit driver. When the transmit failure is
detected, DMO output pin goes “High” and DMOIS
bit is set.
When this bit is “0”, MTIP and MRing are connected
to other transmit channel for monitoring.
D7-D6
D0
0
Reserved
REQEN_n Set this bit to enable the Receive Equalizer.
0
NOTE: See section 5.01 for detailed description.
0x05 (Ch 0)
0x0D (Ch 1)
0x15 (Ch 2)
0x1D (ch 3)
R/W
D1
RxMON_n Set this bit to configure the Receiver in monitoring
mode. In this mode, the Receiver can monitor a signal at the RTIP/RRing pins that has be attenuated
up to 20dB flat loss.
0
D2
LOSMUT_ Setting this bit causes the RPOS/RNEG outputs to
n
“0” while the LOS condition is declared.
0
Receive
Control
NOTE: If this bit has been set, it will remain set even
after the LOS condition is cleared.
D3
RxClkINV_ Set this bit to configure the Receiver to output
n
RPOS/RNEG data on the falling edge of RxClk_0.
0
D4
ALOSDIS_ Set this bit to disable the ALOS detector.
n
0
D5
DLOSDIS_ Set this bit to disable the DLOS detector.
n
0
D7-D6
Reserved
46
XRT75L04
FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.4
TABLE 21: REGISTER MAP DESCRIPTION
ADDRESS
(HEX)
TYPE
REGISTER
NAME
DEFAULT
VALUE
BIT#
SYMBOL
DESCRIPTION
D0
SR/DR_n
Setting this bit configures the Receiver and Transmitter in Single-Rail (NRZ) mode.
0
NOTE: See section 4.0 for detailed description.
D1
STS-1/
DS3_n
Setting this bit configures the channel into STS-1
mode.
0
NOTE: This bit field is ignored if the channel is
configured to operate in E3 mode.
0x06 (Ch 0)
0x0E (Ch 1)
0x16 (Ch 2)
0x1E 9ch 3)
R/W
D2
E3_n
Setting this bit configures the channel in E3 mode.
0
D3
LLB_n
Setting this bit configures the channel in Local Loopback mode.
0
D4
RLB_n
Setting this bit configures the channel in Remote
Loopback mode.
0
Block Control
D5
RLB_n
LLB_n
Loopback Mode
0
0
Normal Operation
0
1
Analog Local
1
0
Remote
1
1
Digital
PRBSEN_ Setting this bit enables the PRBS generator/detecn
tor. PRBS generator generate and detect either 2151 (DS3 or STS-1) or 223-1 (for E3).
The pattern generated and detected are unframed
pattern.
D7-D6
Reserved
47
0
XRT75L04
FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.4
TABLE 21: REGISTER MAP DESCRIPTION
ADDRESS
(HEX)
0x07 (Ch 0)
0x0F (Ch 1)
0x17 (Ch 2)
0x1F (ch 3)
TYPE
R/W
REGISTER
NAME
DEFAULT
VALUE
BIT#
SYMBOL
DESCRIPTION
D0
JA0_n
This bit along with JA1_n bit configures the Jitter
Attenuator as shown in the table below.
JA0_n
JA1_n
Mode
0
0
16 bit FIFO
0
1
Jitter
Attenuator
D1
D2
D3
D4
1
0
1
1
32 bit FIFO
Disable Jitter
Attenuator
Disable Jitter
Attenuator
JATx/Rx_n Setting this bit selects the Jitter Attenuator in the
Transmit Path. A “0” selects in the Receive Path.
JA1_n
0
0
This bit along with the JA0_n configures the Jitter
Attenuator as shown in the table.
0
PNTRST_n Setting this bit resets the Read and Write pointers of
the jitter attenuator FIFO.
0
DFLCK_n
Set this bit to “1” to disable fast locking of the PLL.
This helps to reduce the time for the PLL to lock to
incoming frequeny when Jitter Attenuator switches
to narrow band.
D7-D5
0
Reserved
0x30 (Ch 0)
0x32 (Ch 1)
0x34 (Ch 2)
0x36 (ch 3)
RO
PRBS
COUNT
REG
PRBS COUNT REGISTER MSB
0
0x31 (Ch 0)
0x33 (Ch 1)
0x35 (Ch 2)
0x37 (ch 3)
RO
PRBS
COUNT
REG
PRBS COUNT REGISTER LSB
0
0x38
RO
PRBS
HOLDING
REG
PRBS HOLDING REGISTER
0
0x08
0x10
0x18
Reserved
48
XRT75L04
REV. 1.0.4
FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
8.0 DIAGNOSTIC FEATURES:
8.1
PRBS Generator and Detector:
The XRT75L04 contains an on-chip Pseudo Random Binary Sequence (PRBS) generator and detector for
diagnostic purpose. This feature is only available in Host mode. With the PRBSEN_n bit = “1”, the transmitter
will send out PRBS of 223-1 in E3 rate or 215-1 in STS-1/DS3 rate. At the same time, the receiver PRBS
detector is also enabled. When the correct PRBS pattern is detected by the receiver, the RNEG/LCV pin will go
“Low” to indicate PRBS synchronization has been achieved. When the PRBS detector is not in sync the
PRBSLS bit will be set to “1” and RNEG/LCV pin will go “High”.
With the PRBS mode enabled, the user can also insert a single bit error by toggling “INSPRBS” bit. This is
done by writing a “1” to INSPRBS bit. The receiver at RNEG/LCV pin will pulse “High” for one RxClk cycle for
every bit error detected. Any subsequent single bit error insertion must be done by first writing a “0” to
INSPRBS bit and followed by a “1”.
Figure 25 shows the status of RNEG/LCV pin when the XRT75L04 is configured in PRBS mode.
NOTE: In PRBS mode, the device is forced to operate in Single-Rail Mode.
FIGURE 25. PRBS MODE
RClk
SYNC LOSS
RNEG/LCV
PRBS SYNC
8.2
Single Bit Error
LOOPBACKS:
The XRT75L04 offers three loopback modes for diagnostic purposes. In Hardware mode, the loopback modes
are selected via the RLB_n and LLB_n pins. In Host mode, the RLB_n and LLB_n bits n the Channel control
registers select the loopback modes.
8.2.1
ANALOG LOOPBACK:
In this mode, the transmitter outputs (TTIP_n and TRING_n) are connected internally to the receiver inputs
(RTIP_n and RRING_n) as shown in Figure 26. Data and clock are output at RCLK_n, RPOS_n and RNEG_n
pins for the corresponding transceiver. Analog loopback exercises most of the functional blocks of the device
including the jitter attenuator which can be selected in either the transmit or receive path.
XRT75L04 can be configured in Analog Loopback either in Hardware mode via the LLB_n and RLB_n pins or
in Host mode via LLB_n and RLB_n bits in the channel control registers.
NOTES:
1.
In the Analog loopback mode, data is also output via TTIP_n and TRING_n pins.
2.
Signals on the RTIP_n and RRING_n pins are ignored during analog loopback.
49
XRT75L04
FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.4
TNDATA
RCLK
1
HDB3/B3ZS
DECODER
RPOS
RNEG
JITTER 2
ATTENUATOR
1
HDB3/B3ZS
ENCODER
TCLK
TPDATA
TIMING
CONTROL
JITTER 2
ATTENUATOR
FIGURE 26. ANALOG LOOPBACK
DATA &
CLOCK
RECOVERY
TTIP
Tx
TRING
RTIP
Rx
RRING
1
if enabled
2 if enabled and selected in either Receive or
Transmit path
8.2.2
DIGITAL LOOPBACK:
The Digital Loopback function is available either in Hardware mode or Host mode. When the Digital Loopback
is selected, the transmit clock (TxClk_n) and transmit data inputs (TPOS_n & TNEG_n) are looped back and
output onto the RxClk_n, RPOS_n and RNEG_n pins as shown in Figure 27. The data presented on TxClk,
TPOS and TNEG are not output on the TTIP and TRING pins.This provides the capability to configure the
protection card (in redundancy applications) in Digital Loopback mode without affecting the traffic on the
primary card.
NOTE: Signals on the RTIP_n and RRING_n pins are ignored during digital loopback.
TNDATA
RCLK
1
HDB3/B3ZS
DECODER
RPOS
RNEG
JITTER 2
ATTENUATOR
1
HDB3/B3ZS
ENCODER
TCLK
TPDATA
TIMING
CONTROL
JITTER 2
ATTENUATOR
FIGURE 27. DIGITAL LOOPBACK
DATA &
CLOCK
RECOVERY
1
if enabled
if enabled and selected in either Receive or
Transmit path
2
50
TTIP
Tx
TRING
RTIP
Rx
RRING
XRT75L04
FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.4
8.2.3
REMOTE LOOPBACK:
With Remote loopback activated as shown in Figure 28, the receive data on RTIP and RRING is looped back
after the jitter attenuator (if selected in receive or transmit path) to the transmit path using RxClk as transmit
timing. The receive data is also output via the RPOS and RNEG pins.
During the remote loopback mode, if the jitter attenuator is selected in the transmit path, the receive data after
the Clock and Data Recovery Block is looped back to the transmit path and passed through the jitter attenuator
using RxClk as the transmit timing.
NOTE: Input signals on TxClk, TPOS and TNEG are ignored during Remote loopback.
TNDATA
RCLK
HDB3/B3ZS
DECODER
RPOS
1
RNEG
JITTER 2
ATTENUATOR
1
HDB3/B3ZS
ENCODER
TCLK
TPDATA
TIMING
CONTROL
JITTER 2
ATTENUATOR
FIGURE 28. REMOTE LOOPBACK
DATA &
CLOCK
RECOVERY
TTIP
Tx
TRING
RTIP
Rx
RRING
1
if enabled
2
if enabled and selected in either Receive or
Transmit path
8.3
TRANSMIT ALL ONES (TAOS):
Transmit All Ones (TAOS) can be set either in Hardware mode by pulling the TAOS_n pins “High” or in Host
mode by setting the TAOS_n control bits to “1” in the Channel control registers. When the TAOS is set, the
Transmit Section generates and transmits a continuous AMI all “1’s” pattern on TTIP_n and TRING_n pins.
The frequency of this “1’s” pattern is determined by TClk_n.TAOS data path is shown in Figure 29.
TCLK
1
HDB3/B3ZS
ENCODER
TPDATA
TNDATA
JITTER 2
ATTENUATOR
FIGURE 29. TRANSMIT ALL ONES (TAOS)
TIMING
CONTROL
Tx
TTIP
Transmit All 1
TRING
1
HDB3/B3ZS
DECODER
RCLK
RPOS
RNEG
JITTER 2
ATTENUATOR
TAOS
DATA &
CLOCK
RECOVERY
1
if enabled
if enabled and selected in either Receive or
Transmit path
2
51
RTIP
Rx
RRING
XRT75L04
FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.4
APPENDIX B
TABLE 22: TRANSFORMER RECOMMENDATIONS
PARAMETER
VALUE
Turns Ratio
1:1
Primary Inductance
40 µH
Isolation Voltage
1500 Vrms
Leakage Inductance
0.6 µH
TABLE 23: TRANSFORMER DETAILS
PART NUMBER
VENDOR
INSULATION
PACKAGE TYPE
PE-68629
PULSE
3000 V
Large Thru-hole
PE-65966
PULSE
1500 V
Samll Thru-hole
PE-65967
PULSE
1500 V
SMT
T 3001
PULSE
1500 V
SMT
TG01-0406NS
HALO
1500 V
SMT
TTI 7601-SM
TransPower
1500 V
SMT
TRANSFORMER VENDOR INFORMATION
Pulse
Corporate Office
12220 World Trade Drive
San Diego, CA 92128
Tel: (858)-674-8100
FAX: (858)-674-8262
Europe
1 & 2 Huxley Road
The Surrey Research Park
Guildford, Surrey GU2 5RE
United Kingdom
Tel: 44-1483-401700
FAX: 44-1483-401701
52
XRT75L04
REV. 1.0.4
FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
Asia
150 Kampong Ampat
#07-01/02
KA Centre
Singapore 368324
Tel: 65-287-8998
Website: http://www.pulseeng.com
Halo Electronics
Corporate Office
P.O. Box 5826
Redwood City, CA 94063
Tel: (650)568-5800
FAX: (650)568-6165
Email: info@haloelectronics.com
Website: http://www.haloelectronics.com
Transpower Technologies, Inc.
Corporate Office
Park Center West Building
9805 Double R Blvd, Suite # 100
Reno, NV 89511
(800)500-5930 or (775)852-0140
Email: info@trans-power.com
Website: http://www.trans-power.com
53
XRT75L04
FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.4
ORDERING INFORMATION
PART NUMBER
PACKAGE
OPERATING TEMPERATURE RANGE
XRT75L04IV
24 x 24 x 1.4 mm 176 Pin LQFP
- 40°C to + 85°C
PACKAGE DIMENSIONS - 176 PIN PACKAGE
132
132
89
89
133
133
88
176
176
45
88
45
44
1
44
1
β
α
Note: The control dimension is in millimeters.
SYMBOL
A
A1
A2
B
C
D
D1
e
L
α
β
INCHES
MIN
MAX
0.055
0.063
0.002
0.006
0.053
0.057
0.007
0.011
0.004
0.008
1.016
1.031
0.941
0.949
0.020 BSC
0.018
0.030
0°
7°
7° typ
54
MILLIMETERS
MIN
MAX
1.40
1.60
0.05
0.15
1.35
1.45
0.17
0.27
0.09
0.20
25.80
26.20
23.90
24.10
0.50 BSC
0.45
0.75
0°
7°
7° typ
XRT75L04
FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.4
REVISIONS
REV. #
DATE
CHANGES
P1.0.0
2002
Oriiginal preliminary data sheet
P1.0.1
05/02
Cleaned up the Typo errors. Included the eval board schematics. Added some
explanation in the register map.
1.0.0
07/03
Release to production, included electrical specs.
1.0.1
11/03
Changed ICC in the electrical characteristics. Removed the evaluation board schematic.
1.0.2
01/06
Changed power dissaption and package power ratings.
1.0.3
01/18/06 Changed package designation from QFP or TQFP to LQFP.
1.0.4
07/11/06 Removed reference to Jitter Attenuator 128 bit FIFO.
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to
improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any
circuits described herein, conveys no license under any patent or other right, and makes no representation that
the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration
purposes and may vary depending upon a user’s specific application. While the information in this publication
has been carefully checked; no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the
failure or malfunction of the product can reasonably be expected to cause failure of the life support system or
to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless
EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has
been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately
protected under the circumstances.
Copyright 2006 EXAR Corporation
Datasheet July 2006.
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
55
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