XRT8000IDTR-F

XRT8000 Clock Synchronizer/Adapter for Communications September 2006 FEATURES D Cascadable D Clock Adaptation for Most Popular Telecommunication Frequencies D No External Components Needed D Wide Input Frequency Range D Lock Detect Indication Pin D Programmable Output Frequencies APPLICATIONS D Less than 0.05UI Wide Band Output Jitter D DSU’s, CSU’s and Access Equipment D Low Power Operation (5V and 3.3V) D ISDN Terminals D Maximum Lock Time of 45mS D Concentrators and Multiplexers GENERAL DESCRIPTION The XRT8000 is a dual phase-locked loop chip that generates two simultaneous, very low jitter, output clocks for synchronization applications in wide area networking systems. The outputs are phase locked to the input signal. The chip has four basic modes of operation; referred to as master (FORWARD, REVERSE) and slave (FORWARD, REVERSE) modes (See Figure 1). In the FORWARD mode it accepts up to 16th harmonic of either 1.544MHz or 2.048MHz as input reference and generates 1.2kHz and multiples of 2.4kHz, 56kHz or 64kHz. In the REVERSE mode an input clock of 56kHz or 64kHz is used to generate 1.544MHz or 2.048MHz output clocks. The SLAVE (FORWARD, REVERSE) modes generate the same output frequencies as the MASTER (FORWARD/ REVERSE MODES) except that the input frequency (FIN) is 8kHz. An optional divide by eight can be enabled at each of the outputs. The input and output frequency selection can be done through a serial microprocessor interface. The XRT8000 is available in either 18 pin SOIC package or 18 pin plastic DIP. ORDERING INFORMATION Part No. Package Operating Temperature Range XRT8000IP 18 Lead 300 Mil PDIP -40°C to +85°C XRT8000ID 18 Lead 300 Mil JEDEC SOIC -40°C to +85°C XRT8000 CLK2 n x 1.544{T1} n x 2.048{E1} 1