XRT8001IDTR-F

XRT8001 WAN Clock for T1 and E1 Systems October 2001-1 GENERAL DESCRIPTION • Generates Output Clock Frequencies Ranging The XRT8001 WAN Clock is a dual-phase-locked loop chip that generates two very low jitter output clock signals that can be used for synchronization clocks in wide area networking systems. The XRT8001 has preprogrammed multipliers and dividers that are selected via the serial port. It generates two integer multiples of 8kHz, 56kHz, and 64kHz while locked onto an incoming reference of 1.54MHz (T1), 2.048MHz (E1), 8kHz, 56kHz, or 64kHz • • • • • • • • • The XRT8001 WAN Clock can be configured to operate in one of six modes: 1. The Forward/Master Mode 2. The Reverse/Master Mode 3. The “Fractional T1/E1" Reverse/Master Mode 4. The “E1 to T1 - Forward/Master" Mode 5. The “High Speed - Reverse" Mode 6. The “Slave” Mode From 8kHz up to 16.384MHz Serial Port Control for Optimal Performance Sync Output: 8kHz or 64kHz Low Jitter Cascadable (Master / Slave Modes) No External Components Needed Pin Compatible with the XRT8000 Low Power (3.3V or 5V): 40 - 100mW - 40°C to +85°C Temperature Range 18-Lead PDIP or SOIC Packages APPLICATIONS • T1/E1 Access Equipment (DSU/CSU) • Frame Relay Access Devices (FRAD) • Basic Rate and Primary Rate ISDN Equipment • ISDN Routers • Terminals • Remote Access Servers • T1/E1 Concentrators • T1/E1 Multiplexers • T1/E1 Clock Rate Converters • Internal Timing Generators • System Synchronizers FEATURES • Dual Phased Locked Loops with Pre-Programmed Multipliers and Dividers • Pre-Programmed with Popular Frequency Conversions for Communications Systems 3.3V or 5V V CC Reference Clock 8kHz to 16.384 MHz Sync Out 8kHz or 64kHz 3 2 CLK1 FIN XRT8001 MSB Master/Slave CLK2 SYNC 8 CS LOCKDET SDO SDI 6 13 11 Clock Output 1 Clock Output 2 PLL Lock Detect SCLK µ C/µ µ P Serial I/O Figure 1. System Diagram ORDERING INFORMATION Part Number XRT8001IP XRT8001ID Package 18-Lead 300 Mil PDIP 18-Lead 300 Mil JEDEC SOIC Operating Temperature Range -40°C to +85°C -40°C to +85°C Rev. 1.01 EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com XRT8001 10 12 7 Digital Vcc Analog Vcc 15 Digital Vcc Analog Phase Locked Loop Feedback Divider M Post Divider Digital Vcc 13 Driver Q2 PLL2 M2 LDETDIS1 11 Lock Detector LDETDIS2 LOCKDET 2 FIN 3 Input Divider Analog Phase Locked Loop R 100K Post Divider Q Feedback Divider M PLL1 R 100K M2 SCLK 17 SDO MSB Q2 18 CS SDI 6 Driver P Vcc Serial Interface 16 Mode and Frequency Select Control 1 8 AGND DGND DGND 9 4 5 Figure 2. XRT8001 Block Diagram Rev. 1.01 2 CLK2 Q DGND 14 SYNC CLK1 XRT8001 SDO 1 18 SCLK SYNC 2 17 CS FIN 3 16 SDI GND 4 15 VCC GND 5 CLK1 6 13 CLK2 VCC 7 12 VCC MSB 8 11 LOCKDET GND 9 10 VCC XRT8001 14 GND Figure 3. XRT8001 PIN OUT PIN DESCRIPTION Pin # 1 Name SDO Type O 2 SYNC O Description Serial Data Output from the Microprocessor Serial Interface This pin will serially output the contents of the specified Command Register, during “Read” Operations. The data, on this pin, will be updated on the falling edge of the SCLK input signal. This pin will be tristated upon completion of data transfer. Sync Output - The XRT8001 will typically output an 8kHz clock signal via this output pin. However, when the XRT8001 is operating in the “High Speed - Reverse” Mode, then this device will simply output a 64kHz clock signal. 3 FIN I Reference Clock Input - The Reference Timing signal (from which the CLK1 and CLK2 output signals are derived) is to be input via this pin. 4 GND - Digital Ground 5 GND - Digital Ground 6 CLK1 O Clock Output 1 - The XRT8001 will drive the desired “synthesized” signal via this output pin. This output signal will have a 50+5% duty cycle. Note: This output pin is tri-stated unless the “CLK1EN” bit-field (within Command Register CR4) has been set to “1”. 7 VCC - Digital Power Supply Rev. 1.01 3 XRT8001 PIN DESCRIPTION (CONT'D) Pin # 8 Name MSB Type I Description Master/Slave Mode Select Input - Setting this input pin “HIGH” configures the XRT8001 to operate in the “MASTER” Mode. Conversely, setting this input pin “LOW” configures the XRT8001 to operate in the “SLAVE” Mode. 9 GND - Analog Ground 10 VCC - Analog Power Supply 11 LOCKDET O Lock Detect Output - This output indicates whether or not the “selected” internal PLL(s) are “in-lock” or are “out-of-lock”. By default, this output pin is “high” when both PLLs are in-lock” and will go toggle “low” if either one of the PLLs is “out-of-lock”. However, the XRT8001 also permits the user to configure this output pin to reflect the state of any one of the PLLs within the chip. (See Table 3.) 12 VCC - Digital Power Supply 13 CLK2 O Clock Output 2 - The XRT8001 will drive the desired “synthesized” signal via this output pin. This output signal will have a 50+5% duty cycle. Note: This output pin is tri-stated unless the “CLK1EN” bit-field (within Command Register CR4) has been set to “1”. 14 GND - Digital Ground 15 VCC - Digital Power Supply 16 SDI I Microprocessor Serial Interface – Serial Data Input Whenever, the user wishes to read or write data into the Command Registers, over the Microprocessor Serial Interface, the user is expected to apply the “Read/Write” bit, the Address Values (of the Command Registers) and Data Value to be written (during “Write” Operations) to this pin. This input will be sampled on the rising edge of the SCLK pin (pin 18). 17 CS I Microprocessor Serial Interface – Chip Select Input: The Local Microprocessor must assert this pin (e.g., set it to “0”) in order to enable communication with the XRT8001 via the Microprocessor Serial Interface. Note: This pin is internally pulled “high”. 18 SCLK I Microprocessor Serial Interface-Clock Signal This signal will be used to sample the data, on the SDI pin, on the rising edge of this signal. Additionally, during “Read” operations, the Microprocessor Serial Interface will update the SDO output on the falling edge of this signal. Rev. 1.01 4 XRT8001 ABSOLUTE MAXIMUM RATINGS Supply Range ................................................ 7V Voltage at any Pin ........... GND -0.3V to Vcc+0.3V Operating Temperature................. - 40°C to +85°C Storage Temperature ................... - 40°C to +85°C Package Dissipation ............................... 500mW DC ELECTRICAL CHARACTERISTICS (Except Microprocessor Serial Interface)1 Symbol Parameter VIL Input Low Level VIH Input High Level VOL Output Low Level (CLK1, CLK2) VOH Output High Level (CLK1, CLK2) VOL Output Low Level (LOCKDET, SYNC) VOH Output High Level (LOCKDET, SYNC) IIL Min. Typ. Max. Units 0.8 2.0 Condition V V 0.4 2.4 V IOL = -6.0mA V IOL = 6.0mA 0.4 V IOL = -3.0mA V IOL = 3.0mA Input Low Current (CSB, MSB) -150 mA IIH Input High Current (CSB, MSB) 10 mA IIL Input Low Current (except CSB, MSB) IIH Input High Current (except CSB, MSB) ICC Operating Current RIN Internal Pull-up Resistance (CSB, MSB) 2.4 -10 50 VIN = VCC mA 10 mA VIN = VCC 11 20 30 35 mA mA 3.3V, No Load, CLk1, CLK2 = 8 x 2.048MHz 100 150 kW 5V, No Load, CLk1, CLK2 = 8 x 2.048MHz Note: 1. 5V tolerant input considerations when operating from 3.3V: When the XRT8001 is powered at 3.3V, it can tolerate 5V-level signals via its inputs. However, the user should be aware the XRT8001 contains a “Factory-Test” Mode. This mode is enabled whenever the MSB (Master-Slave select) input pin is pulled to about 2V above VDD. Therefore, if the user is powering the XRT8001 at 3.3V but is applying a 5.25V signal to the MSB input pin, then it is possible that the XRT8001 could be configured to operate in this “Factory-Test” Mode. Since all “Factory-Test” Mode registers are reset to “0”, upon chip power, this should not be a problem for the user. However, if the user performs write operations to “non-defined” address locations within the XRT8001, then the user may observe strange operation from the XRT8001. The user must make sure that when the Microcontroller performs WRITE operations to the XRT8001, it is only performing these WRITE operations to the Address Locations defined in the XRT8001 Data Sheet. Rev. 1.01 5 XRT8001 AC ELECTRICAL CHARACTERISTICS (See Figure 4.) Symbol Parameter t1 Input Frequency t2 t3 t61 t74 Minimum Input Signal “High” to “Low” Duration Output Frequency Duty Cycle Jitter Added 8kHz – 40kHz t74 Jitter Added 10Hz – 40kHz t74 Broadband Jitter t74 Jitter Added 20Hz – 100kHz t74 Jitter Added 18kHz – 100kHz t8 Capture Time t9 t10 t112 t12 t13 t14 t21 Typ. 0.008 0.008 12 56 47.5 Clock Output Rise Time Clock Output Fall Time SYNC Output Signal Duty Cycle SYNC Ouput Signal + ½ Cycle SYNC Output Signal – ½ Cycle Delay Time between the rising edge of of SYNC and the Rising edge of CLK1 and CLK2 CSB Low to Rising Edge of SCLK Setup Time 40 Max. Units 32.7 32.7 50 0.01 0.01 0.03 0.03 0.03 0.035 16,384 52.5 0.02 0.02 – 0.05 0.05 0.07 0.01 0.07 0.03 0.007 0.03 40 40 10ns 10ns 60 t-20 t+20 kHz % UI UI UI UI UI UI UI UI UI UI ms ms ns ns % ns 50 ns CSB High to Rising Edge of SCLK Hold Time 20 ns t23 t24 t25 SDI to Rising Edge of SCLK Setup Time SDI to Rising Edge of SCLK Hold Time SCLK “Low” Time 50 50 240 ns ns ns t26 SCLK “High” Time 240 ns t27 SCLK Period 500 ns t28 CSB Low to Rising Edge of SCLK Hold Time 50 ns t29 CSB “Inactive” Time 250 t30 Falling Edge of SCLK to SDO Valid Time t31 t32 Falling Edge of SCLK to SDO Invalid Time Falling Edge of SCLK, or rising edge of CSB to High Z t33 Rise/Fall time of SDO Output FIN Duty Cycle t4 t6 = (t4 + t5) 2 VCC/2 switch point, 30pF Load 3.3V, Output = 1.544MHz (0.025 UI)3 5V, Output = 1.544MHz (0.025 UI)3 3.3V, Output = 1.544MHz (0.025 UI)3 5V, Output = 1.544MHz (0.025 UI)3 3.3V, Output = 1.544MHz (0.05 UI)3 5V, Output = 1.544MHz (0.05 UI)3 3.3V, Output = 2.048MHz (1.5 UI)3 5V, Output = 2.048MHz (1.5 UI)3 3.3V, Output = 2.048MHz (0.2 UI)3 5V, Output = 2.048MHz (0.2 UI)3 3.3V 5V 30pF load measured at 20/80% 30pF load measured at 20/80% VCC/2 switch point See Table 8 for values of “t” ns 200 ns 100 ns ns 40 ns 100 12 Notes: Conditions MHz 3.3V MHz 5V ns t22 PWMIN 1 Min. ns 3 Specifications from AT&T Publication 62411 and ITU-T Recommendations G-823 (for 1.544MHz and (2.048MHz). 4 t7 is guaranteed by characterization, not tested. t12 t11 = (t12 + t13) Rev. 1.01 6 XRT8001 t1 t2 t2 FIN t3 t4 CLK1 or CLK2 t9 t14 t5 t10 t7 t12 t13 SYNC Figure 4. Timing Diagram for Clocks t29 t21 CSB t27 t22 τ25 SCLK t23 SDI t28 t26 t24 A0 R/W A1 CSB SCLK t31 t30 D0 SDO Hi-Z t33 t32 D2 D1 D7 Hi-Z SDI Figure 5. Timing Diagram for the Microprocessor Serial Interface Rev. 1.01 7 XRT8001 1.0 Operating the Microprocessor Serial Interface Bits 2 Through 5: The Four (4) Bit Address Values (Labeled A0, A1, A2 and A3) The XRT8001 Serial Interface is a simple four-wire interface that is compatible with many of the microcontrollers available in the market. This interface consists of the following signals: The next four rising edges of the SCLK signal will clock in the 4-bit address value for this particular Read (or Write) operation. The address selects the Command Register, within the XRT8001, that the user will either be reading data from, or writing data to. The user must supply the address bits to the SDI input pin in ascending order with the LSB (least significant bit) first. CSB SCLK SDI SDO - Chip Select (Active Low) Serial Clock Serial Data Input Serial Data Output Bits 6 and 7: The next two bits, A4 and A5, must be set to “0”, as shown in Figure 19. Using the Microprocessor Serial Interface The following instructions, for using the Microprocessor Serial Interface, are best understood by referring to the diagram in Figure 19. Bit 8 - A6 The value of “A6” is a “don’t care”. Once these first eight bits have been written into the Microprocessor Serial Interface, the subsequent action depends upon whether the current operation is a “Read” or “Write” operation. In order to use the Microprocessor Serial Interface the user must first provide a clock signal to the SCLK input pin. Afterwards, the user will initiate a “Read” or “Write” operation by asserting the “activelow” Chip Select input pin (CSB). It is important to assert the CSB pin (e.g., toggle it “low”) at least 50ns prior to the very first rising edge of the clock signal. Read Operation Once the last address bit (A3) has been clocked into the SDI input, the “Read” operation will proceed through an idle period, lasting three SCLK periods. On the falling edge of SCLK Cycle #8 (see Figure 19) the serial data output signal (SDO) becomes active. At this point the user can begin reading the data contents of the addressed Command Register (at Address [A3, A2, A1, A0]) via the SDO output pin. The Microprocessor Serial Interface will output this 5-bit data word (D0 through D4) in ascending order (with the LSB first), on the falling edges of the SCLK pin. As a consequence, the data (on the SDO output pin) will be sufficiently stable for reading (by the Microprocessor), on the very next rising edge of the SCLK pin. Once the CSB input pin has been asserted, the type of operation and the target register address must now be specified by the user. The user provides this information to the Microprocessor Serial Interface by writing eight serial bits of data into the SDI input. Note: each of these bits will be “clocked” into the SDI input on the rising edge of SCLK. These eight bits are identified and described below. Bit 1 - “R/W” (Read/Write) Bit This bit will be clocked into the SDI input on the first rising edge of SCLK (after CSB has been asserted). This bit indicates whether the current operation is a “Read” or “Write” operation. A “1” in this bit specifies a “Read” operation; whereas, a “0” in this bit specifies a “Write” operation. Rev. 1.01 8 XRT8001 Write Operation onto the SDI input pin. The Microprocessor Serial Interface will latch the value on the SDI input pin, on the rising edge of SCLK. The user must apply this word (D0 through D7) serially, in ascending order with the LSB first. Once the last address bit (A3) has been clocked into the SDI input, the “Write” operation will proceed through an idle period, lasting three SCLK periods. Prior to the rising edge of SCLK Cycle # 9 (see Figure 6) the user must begin to apply the 8-bit data word, that he/she wishes to write to the Microprocessor Serial Interface, CSB SCLK SDI 1 R/W 2 A0 3 A1 4 A2 5 A3 6 0 7 0 8 A6 High Z SDO 9 10 11 12 13 14 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 0 0 0 - Denotes a “don’t care” value Figure 6. Microprocessor Serial Interface Data Structure The user can simplify the design of the circuitry connecting to the Microprocessor Serial Interface by tying both the SDO and SDI pins together, and reading data from and/or writing data to this “combined” signal. This simplification is possible because only one of these signals are active at any given time. The inactive signal will be tri-stated. Rev. 1.01 9 16 D0 Notes: A4 and A5 are always “0”. R/W = “1” for “Read” Operations R/W = “0” for “Write” Operations Simplified Interface Option 15 XRT8001 2.1 The Forward/Master Mode Figure 7, presents a simple illustration of the XRT8001 WAN Clock operating in the “Forward Master/Mode.” In the Forward/Master Mode, the XRT8001 will accept either an “N x 1.544MHz” or an “N x 2.048MHz” clock signal via the FIN input pin (where: 1 < N < 16). From this “reference signal” the XRT8001 will generate either a “K x 56kHz” or a “K x 64kHz” clock signal (where: 1 < K < 32). N x 1.544MHz or N x 2.048MHz Where 1 < N < 16 FIN CLK1 K x 56kHz or K x 64kHz Where 1 < K < 32 XRT8001 WAN Clock XRT8001 WAN Clock CLK2 K x 56kHz or K x 64kHz Where 1 < K < 32 Figure 7. Illustration of the XRT8001 WAN Clock Operating in the Forward/Master Mode Rev. 1.01 10 XRT8001 2.2 The Reverse/Master Mode In the Reverse/Master Mode, the XRT8001 will accept either a 56kHz or a 64kHz clock signal via the FIN input pin, and will generate either a 1.544MHz or a 2.048MHz clock signal via the Clock Output signals. 56kHz or 64kHz Figure 8, presents a simple illustration of the XRT8001 WAN Clock operating in the “Reverse/Master Mode.” CLK1 FIN 1.544MHz or 2.048MHz XRT8001 XRT8001 WAN WAN Clock Clock CLK2 1.544MHz or 2.048MHz Figure 8. Illustration of the XRT8001 WAN Clock Operating in the Reverse/Master Mode Rev. 1.01 11 XRT8001 2.3 The Fractional T1/E1 Reverse/Master Mode In the Fractional T1/E1 Reverse/Master Mode, the XRT8001 will accept either a “P x 56kHz” or a “P x 64kHz” clock signal via the FIN input pin (where: 1 < P < 32). From this “reference signal” the XRT8001 will generate either a 1.544MHz or a 2.048MHz clock signal. P x 56kHz or P x 64kHz Where: 1 < P < 32 Figure 9, presents a simple illustration of the XRT8001 WAN Clock operating in the “Fractional T1/E1 Reverse/Master" Mode. FIN CLK1 1.544MHz or 2.048MHz CLK2 1.544MHz or 2.048MHz XRT8001 XRT8001 WAN WANClock Clock Figure 9. Illustration of the XRT8001 WAN Clock Operating in the “Fractional T1/E1 Reverse/Master” Mode Rev. 1.01 12 XRT8001 2.4 The “E1 to T1 Forward/Master” Mode Figure 10, presents a simple illustration of the XRT8001 WAN Clock operating in the “E1 to T1 Forward/Master” Mode. In the “E1 to T1 Forward/Master” Mode, the XRT8001 will accept a “Q x 2.048MHz” clock signal via the “Reference Clock Input" (FIN), and will output a “1.544MHz” clock signal via the CLK1 and/or CLK2 output pins. Note: The value of “Q” can range between 1 and 16. Q x 2.048MHz Where: 1 < Q < 16 CLK1 FIN 1.544MHz XRT8001 XRT8001 WAN Clock CLK2 1.544MHz Figure 10. Illustration of the XRT8001 WAN Clock Operating in the “E1 to T1 Forward/Master” Mode Rev. 1.01 13 XRT8001 2.5 The “High Speed – Reverse” Mode Figure 11, presents a simple illustration of the XRT8001 WAN Clock operating in the “High Speed Reverse” Mode. In the “High Speed - Reverse” Mode, the XRT8001 will accept a 64kHz clock signal via the “Reference Clock Input" (FIN), and will output a “M x 2.048MHz” clock signal (where M can be equal to 1, 2, 4 or 8) via the CLK1 and/or CLK2 output pins. Note: The XRT8001 will accept and sythesze these clock frequencies independent of whether it has been configured to operate in the "Master" or "Slave" Modes. 64kHz FIN CLK1 M x 2.048MHz M = 1, 2, 4 or 8 XRT8001 WAN Clock M x 2.048MHz CLK2 M = 1, 2, 4 or 8 Figure 11. Illustration of the XRT8001 WAN Clock Operating in the “High Speed – Reverse” Mode Rev. 1.01 14 XRT8001 2.6 The “Forward/Slave” Mode In the “Forward/Slave” Mode, the XRT8001 will accept an 8kHz clock signal via the Reference Clock Input (FIN), and will output a “L x 64kHz or L x 56kHz” clock signal (where L can range from 1 to 32) via the CLK1 and CLK2 output pins. 8kHz Figure 12 presents a simple illustration of the XRT8001 WAN Clock operating in the “Forward/ Slave” Mode. CLK1 FIN L x 56kHz or L x 64kHz Where 1 < L < 32 XRT8001 WAN Clock CLK2 L x 56kHz or L x 64kHz Where 1 < L < 32 Figure 12. Illustration of the XRT8001 WAN Clock Operating in the “Forward/Slave” Mode Rev. 1.01 15 XRT8001 3.0 Description of the Command Registers 3.1 Address Map of the "On-Chip" Command Registers Address 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 3.2 Command Register CR0 CR1 CR2 CR3 CR4 CR5 CR6 CR7 Type D4 D3 Register Bit-Format D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W IOC4 M4 SEL14 SEL24 SYNCEN Reserved Reserved Reserved IOC3 M3 SEL13 SEL23 CLK1EN Reserved Reserved Reserved IOC2 M2 SEL12 SEL22 CLK2EN Reserved Reserved Reserved IOC1 M1 SEL11 SEL21 LDETDIS2 Reserved Reserved Reserved PL1EN PL2EN SEL10 SEL20 LDETDIS1 Reserved Reserved Reserved Command Register Description 3.2.1 Command Register CR0 (Address = 0x00) D4 – D1 (Configuration Mode Select Bits) These four-bit fields permit the user to select which mode the XRT8001 will operate in. Specifically, these four bit-fields make the following configuration selections: 2. What kind of input signals are to be applied to the Reference Clock Input (FIN). 3. What kind of signals will be output via the CLK1 and CLK2 output pins. 1. Whether the XRT8001 will be operating in the “Forward/Master”, “Reverse/Master”, “Fractional T1/E1 Reverse/Master”, "E1 to T1 - Forward/Master" and “High Speed - Reverse” odes. Table 2A relates the value of these four bit-fields to the four Master Modes and Table 2B relates to the three Slave Modes of the XRT8001. Rev. 1.01 16 XRT8001 D[4:1] Mode 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Forward/Master Forward/Master Forward/Master Reverse/Master Forward/Master Forward/Master Forward/Master Reverse/Master E1 to T1 – Forward/Master Fract. T1/E1 Reverse/Master Fract. T1/E1 Reverse/Master Fract. T1/E1 Reverse/Master Fract. T1/E1 Reverse/Master High Speed - Reverse Reserved Reserved Input Frequency (at the FIN input) N x 1.544MHz N x 1.544MHz N x 1.544MHz 56kHz N x 2.048MHz N x 2.048MHz N x 2.048MHz 64kHz Q x 2.048MHz P x 56kHz P x 56kHz P x 64kHz P x 64kHz 64 kHz Reserved Reserved CLK1 Output Signal K x 56kHz K x 56kHz K x 64kHz 1.544MHz K x 56kHz K x 56kHz K x 64kHz 1.544MHz 1.544MHz 1.544MHz 1.544MHz 2.048MHz 2.048MHz M x 2.048MHz Reserved Reserved CLK2 Output Signal K x 56kHz K x 64kHz K x 64kHz 2.048MHz K x 56kHz K x 64kHz K x 64kHz 2.048MHz 1.544MHz 2.048MHz 1.544MHz 1.544MHz 2.048MHz M x 2.048MHz Reserved Reserved Table 1. Relationship between the value of “D4 – D1 (within Command Register CR0) and the Operating Modes of the XRT8001 WAN Clock - Master Modes D[4:1] Mode 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Forward/Slave Forward/Slave Forward/Slave Reverse/Slave Forward/Slave Forward/Slave Forward/Slave Reverse/Slave Reverse/Slave Reverse/Slave Reverse/Slave Reverse/Slave Reverse/Slave High Speed – Reverse Reserved Reserved Input Frequency (at the FIN input) 8kHz 8kHz 8kHz 8kHz 8kHz 8kHz 8kHz 8kHz 8kHz 8kHz 8kHz 8kHz 8kHz 64kHz Reserved Reserved CLK1 Output Signal K x 56kHz K x 56kHz K x 64kHz 1.544MHz K x 56kHz K x 56kHz K x 64kHz 1.544MHz K x 56KHz 1.544MHz 1.544MHz 2.048MHz 2.048MHz M x 2.048MHz Reserved Reserved CLK2 Output Signal K x 56kHz K x 64kHz K x 64kHz 2.048MHz K x 56kHz K x 64kHz K x 64kHz 2.048MHz K x 64KHz 2.048MHz 1.554MHz 1.544MHz 2.048MHz M x 2.048MHz Reserved Reserved Table 2. Relationship between the value of “D4 – D1" (within Command Register CR0) and the Operating Modes of the XRT8001 WAN Clock – Slave Modes Rev. 1.01 17 XRT8001 3.2.3 Command Register CR2 (Address = 0x02) D0 – PL1EN (PLL # 1 Enable Select) This bit-field permits the user to enable or disable PLL # 1, within the XRT8001 WAN Clock. Setting this bitfield to “1” enables PLL # 1 for Frequency Synthesis. Conversely, setting this bit-field to “0” disables PLL # 1 for Frequency Synthesis. D4 – D0 (SEL1[4:0]) These bit-fields are used to support configuration implementation for both the “Forward/Master”, “Fractional T1/E1 Reverse/Master” and “High Speed – Reverse” Modes. 3.2.2 Command Register CR1 (Address = 0x01) In the Forward/Master Mode D4 – D1: (M4 – M1) In the “Forward/Master” Mode, the XRT8001 WAN Clock will output either a “K x 56kHz” or a “K x 64kHz” clock signal via the CLK1 output pin. These five (5) bitfields within Command Register CR2 are used to define the value of “K” for the CLK1 Output. As a consequence, the XRT8001 can be configured to generate a maximum frequency of “32 x 56kHz” or “32 x 64kHz” via the CLK1 output pin. These bit-fields are used to support configuration implementation for both the “Forward/Master” and “E1 to T1 - Forward/Master” Modes. In both the “Forward/ Master” and “E1 to T1 - Forward/Master” Modes, the XRT8001 WAN Clock will be receiving either a “N x 1.544MHz” or a “N x 2.048MHz” clock signal. The M4 through M1 bit-fields, within this register, permit the user to specify the value of “N”. As a consequence, the XRT8001 can be configured to accept a maximum frequency of “16 x 1.544MHz” or “16 x 2.048MHz”. In the “Fractional T1/E1 Reverse/Master” Mode In the “Fractional T1/E1 Reverse/Master” Mode, the XRT8001 WAN Clock will be receiving either a “P x 56kHz” or a “P x 64kHz” clock signal via the “FIN” input pin. The XRT8001 WAN Clock will, in response, generate either a 1.544MHz or a 2.048MHz clock signal via the CLK1 and/or CLK2 output pins. These five (5) bitfields are used to define the value of “P”. As a consequence, the XRT8001 can be configured to accept a maximum frequency of “32 x 56kHz” or “32 x 64kHz”. D0 – PL2EN (PLL # 2 Enable Select) This bit-field permits the user to enable or disable PLL # 2, within the XRT8001 WAN Clock. Setting this bitfield to “1” enables PLL # 2 for Frequency Synthesis. Conversely, setting this bit-field to “0” disables PLL # 2 for Frequency Synthesis. Rev. 1.01 18 XRT8001 In the “High Speed – Reverse” Mode 3.2.5 Command Register CR4 (Address = 0x04) In the “High Speed – Reverse” Mode, the XRT8001 WAN Clock will be receiving a 64kHz clock signal via the “FIN” input pin. The XRT8001 WAN Clock will, in response, generate an “M x 2.048MHz” clock via the CLK1 and CLK2 output pins. These five (5) bit-fields within Command Register CR2 are used to define the value “M” for the CLK1 output. D4 – SYNCEN (SYNC Output Driver Enable Select) This “read/write” bit-field permits the user to enable or disable the Driver associated with the SYNC output pin. Setting this bit-field to “1” enables this Driver. Setting this bit-field to “0” disables this Driver. D3 – CLK1EN (CLK1 Output Driver Enable Select) Note: The only acceptable values for “M” are 1, 2, 4, or 8. This “read/write” bit-field permits the user to enable or disable the Driver associated with the CLK1 output pin. Setting this bit-field to “1” enables this Driver. Setting this bit-field to “0” disables this Driver. 3.2.4 Command Register CR3 (Address = 0x03) D4 – D0 (SEL2[4:0]) D2 – CLK2EN (CLK2 Output Driver Enable Select) These bit-fields are used to support configuration implementation for the “Forward/Master” and the “High Speed – Reverse” Modes of operation. This “read/write” bit-field permits the user to enable or disable the Driver associated with the CLK2 output pin. Setting this bit-field to “1” enables this Driver. Setting this bit-field to “0” disables this Driver. In the “Forward/Master” Mode In the “Forward/Master” Mode, the XRT8001 WAN Clock will output either a “K x 56kHz” or a “K x 64kHz” clock signal via the CLK2 output pin. These five (5) bitfields within Command Register CR3 are used to define the value of “K” for the CLK2 Output. As a consequence, the XRT8001 can be configured to generate a maximum frequency of “32 x 56kHz” or “32 x 64kHz” via the CLK2 output pin. D1, D0 – LDETDIS[2:1] – Lock Detector Output Control The combination of these two bit-fields permit the user to specify the signal that will be output via the LOCKDET output pin. The user’s options are shown in Table 3. In the “High Speed – Reverse” Mode In the “High Speed – Reverse” Mode, the XRT8001 WAN Clock will be receiving a 64kHz clock signal via the “FIN” input pin. The XRT8001 WAN Clock will, in response, generate an “M x 2.048MHz” clock via the CLK1 and CLK2 output pins. These five (5) bit-fields within Command Register CR3 are used to define the value “M” for the CLK2 output. Note: The only acceptable values for “M” are 1, 2, 4, or 8. Rev. 1.01 19 XRT8001 LDETDIS[2:1] 00 Signal output via the LOCKDET Signal The LOCK Condition of PLL1 AND PLL2 With this selection, the LOCKDET output pin will be “high” if either one of the following conditions are true. a. 01 10 11 If both PLL1 and PLL2 are in the “LOCK” condition, (applies if both PLL1 and PLL2 are enabled) or b. If the only enabled PLL is in the “LOCK” condition (applies only if one of the PLLs are enabled). The LOCK Condition of PLL2 Only With this selection, only the “LOCK” state of PLL2 will be reflected in the LOCKDET output pin. LOCKDET = “high” if PLL2 is in “LOCK”. LOCKDET = “low” if PLL2 is out of “LOCK”. The LOCK Condition of PLL1 Only With this selection, only the “LOCK” state of PLL1 will be reflected in the LOCKDET output pin. LOCKDET = “high” if PLL1 is in “LOCK”. LOCKDET = “low” if PLL1 is out of “LOCK”. LOCKDET will be unconditionally pulled to “LOW” Table 3. Relationship Between the Values of the LDETDIS[2:1] Bit-Fields and the Meaning of the LOCKDET Output Signal 4.1 The “Forward/Master” Mode. 4.0 Instructions for Configuring the XRT8001 WAN Clock As mentioned earlier, the XRT8001 WAN Clock can be configured to operate in the following modes: When the XRT8001 WAN Clock has been configured to operate in the “Forward/Master” Mode, then it will accept an “N x 1.544MHz” or an “N x 2.048MHz” clock signal via the “Reference Clock” input at FIN (pin 3); where “N” can range anywhere between 1 and 16. In response to this clock signal, the XRT8001 WAN Clock will output either a “K x 56kHz” or a “K x 64kHz” clock signal, via the Clock Output pins (CLK1 and/or CLK2). • The “Forward/Master” Mode • The “Reverse/Master” Mode • The “Fractional T1/E1 Reverse/Master” Mode • The “E1 to T1 – Forward/Master” Mode • The “High Speed – Reverse” Mode A simple illustration of the XRT8001 WAN Clock, operating in the “Forward/Master” Mode is shown in figure 13. • The “Forward/Slave” Mode A detailed description of the operation and the configuration steps for each of these configurations follows. Rev. 1.01 20 XRT8001 N x 1.544MHz or N x 2.048MHz Where 1 < N < 16 FIN CLK1 K x 56kHz or K x 64kHz Where 1 < K < 32 XRT8001 WAN Clock CLK2 K x 56kHz or K x 64kHz Where 1 < K < 32 Figure 13. Illustration of the XRT8001 WAN Clock Device Operating in the “Forward/Master” Mode Step 1 – Configure the XRT8001 to operate in the “MASTER” Mode, by pulling the MSB pin (pin 8) to VDD. 5.0 Configuring the XRT8001 WAN Clock into the “Forward/Master” Mode The user can configure the XRT8001 WAN Clock to operate in the “Forward/Master” Mode, by executing the following steps: Input Frequency N x 1.544MHz N x 1.544MHz N x 1.544MHz N x 2.048MHz N x 2.048MHz N x 2.048MHz Step 2 – Review Table 4, and determine which combination of “Input Frequency” and “Output Frequencies” (via PLL1 and PLL2) correlate with the desired configuration. PLL1 Output Frequency K x 56kHz K x 56kHz K x 64kHz K x 56kHz K x 56kHz K x 64kHz PLL2 Output Frequency K x 56kHz K x 64kHz K x 64kHz K x 56kHz K x 64kHz K x 64kHz Value to Write to D4-D1 in CR0 0000 0001 0010 0100 0101 0110 Table 4. Listing of “Input Frequency and “Output Frequency” Cases for “Forward/Master” Mode Operation Rev. 1.01 21 XRT8001 Step 3 – Upon reviewing Table 4, write the listed value (under the “Value to Write to D4 – D1 in CR0” Register Column) into the D4 through D1 bit-fields within Command Register CR0, as illustrated below. In order to specify the value for “K”, one needs to write the value of “K - 1” (in binary format) into Command Register CR2, as illustrated below. Command Register, CR2 (Address = 0x02) D4 SEL14 Command Register CR0 (Address = 0x00) D4 D3 D2 D1 IOC4 IOC3 IOC2 IOC1 Value to Write to D4 – D1 in CR0 D0 PL1EN X For example, if one wishes to configure the XRT8001 to output a clock signal of either “56kHz” or “64kHz” (e.g., where “K” = 1) via the CLK1 output pin, then he/ she should write the value “0”, into Command Register CR2. Note: If the user wishes to output a clock signal via the CLK1 output signal, then he/she should also write a “1” into the “PL1EN” bit-field within Command Register CR0. This step configures the XRT8001 to operate in the “Forward/Master” Mode. Step 6 – Specify the value of “K” (e.g., as in the “K x 56kHz” or “K x 64kHz” clock signal which is to be output via the CLK2 output signal). Step 4 – Next, you need to specify the value for “N” (e.g., as in the “N x 1.544MHz” or “N x 2.048MHz” clock signal which is to be applied to the “FIN” input pin.) In order to specify the value for “K”, one needs to write the value of “K - 1” (binary format) into Command Register CR3, as illustrated below. In order to specify the value for “N”, one needs to write the value of “N - 1” (in binary format) into the “D4 through D1” bits within Command Register CR1, as illustrated below. Command Register, CR3 (Address = 0x03) D4 SEL24 Command Register, CR1 (Address = 0x01) D4 D3 D2 D1 M4 M3 M2 M1 Value of “N - 1” (in Binary Format) D3 D2 D1 D0 SEL13 SEL12 SEL11 SEL10 Value of “K - 1” (in Binary Format). D3 D2 D1 D0 SEL23 SEL22 SEL21 SEL20 Value of “K - 1” (in Binary Format). For example, if one wishes to configure the XRT8001 to output a clock signal of either “1.792MHz” or “2.048MHz” (e.g., where “K” = 32) via the CLK2 output pin, then he/she should write the value “31” (or “1 1 1 1 1” in binary format) into Command Register CR3. D0 PL2EN X For example, if the user wishes to configure the XRT8001 to accept a 1.544MHz clock signal, via the “FIN” input pin (e.g., N = 1), then the user should write in the value “0”, into Command Register CR1. Step 7 – Enable any of the following output signals as appropriate: “SYNC”, “CLK1”, “CLK2” and “LOCKDET”. This is accomplished by writing a “1” into the corresponding bit-fields, within Command Register CR4, as illustrated below. Note: If the user wishes to output a clock signal via the CLK2 output signal, then he/she should also write a “1” into the “PL2EN” bit-field within Command Register CR1. Command Register CR4, (Address = 0x04) Step 5 – Specify the value of “K” (e.g., as in the “K x 56kHz” or “K x 64kHz” clock signal which is to be output via the CLK1 output signal). D4 D3 D2 D1 D0 SYNCEN CLK1EN CLK2EN LDETDIS2 LDETDIS1 1 1 1 0 0 Note: For information on the “LDETDIS1” and “LDETDIS2” bit-fields, please see Table 3. Rev. 1.01 22 XRT8001 6.0 The “Reverse/Master” Mode A simple illustration of the XRT8001 WAN Clock, operating in the “Reverse/Master” Mode is presented in Figure 14. When the XRT8001 WAN Clock has been configured to operate in the “Reverse/Master” Mode, then it will accept either a “56kHz” or a “64kHz” clock signal via the “Reference Clock” input at FIN (pin 3). In response to this clock signal, the XRT8001 WAN Clock will output either a “1.544MHz” or a “2.048MHz” clock signal, via the Clock Output pins (CLK1 and/or CLK2). 56kHz or 64kHz CLK1 FIN 1.544MHz or 2.048MHz XRT8001 XRT8001 WAN WAN Clock Clock CLK2 1.544MHz or 2.048MHz Figure 14. Illustration of the XRT8001 WAN Clock Operating in the “Reverse/Master” Mode 6.1 Configuring the XRT8001 WAN Clock Device into the “Reverse/Master” Mode Step 2 – Review Table 5, and determine which combination of “Input Frequency” and “Output Frequencies” (via PLL1 and PLL2) correlate with the desired configuration. The user can configure the XRT8001 WAN Clock to operate in the “Reverse/Master” Mode, by executing the following steps: Step 1 – Configure the XRT8001 to operate in the “MASTER” Mode by pulling the “MSB” pin (pin 8) to VDD. Rev. 1.01 23 XRT8001 Input Frequency 56kHz 64kHz PLL1 Output Frequency 1.544MHz 1.544MHz PLL2 Output Frequency 2.048MHz 2.048MHz Value to Write to D4 – D1 in CR0 0011 0111 Table 5. Listing of “Input Frequency” and “Output Frequency” Cases for “Reverse/Master” Mode Operation Step 5 – Enable any of the following output signals as appropriate: SYNC”, CLK1, CLK2 and LOCKDET. This is accomplished by writing a “1” into the corresponding bit-fields, within Command Register CR4, as illustrated below: Step 3 – Upon reviewing Table 5, write the listed value (under the “Value to Write to D4 – D1 in CR0” register) into the D4 through D1 bit-fields within Command Register CR0, as illustrated below: Command Register CR0 (Address = 0x00) D4 D3 D2 D1 IOC4 IOC3 IOC2 IOC1 Value to Write to D4 – D1 in CR0 D0 PL1EN X Command Register CR4, (Address = 0x04) Note: If the user wishes to output a clock signal via the CLK1 output signal, then he/she should also write a “1” into the “PL1EN” bit-field within Command Register CR0. D4 D3 D2 D1 D0 SYNCEN CLK1EN CLK2EN LDETDIS2 LDETDIS1 1 1 1 0 0 Note: For information on the “LDETDIS1” and “LDETDIS2” bit-fields, please see Table 3. 6.2 The “Fractional T1/E1 Reverse/Master” Mode This step configures the XRT8001 to operate in the “Reverse/Master” Mode. When the XRT8001 WAN Clock has been configured to operate in the “Fractional T1/E1 Reverse/Master" Mode, then it will accept either a “P x 56kHz” or a “P x 64kHz” clock signal via the “FIN” input pin (pin 3). In response, the XRT8001 will output either a 1.544MHz or a 2.048MHz clock signal via the CLK1 and/or CLK2 outputs. Step 4 – Write a “1” into the “PL2EN” bit-field within Command Register CR1 (if you wish to output a clock signal via the “CLK2” output pin), as illustrated below: Command Register, CR1 (Address = 0x01) D4 M4 D3 D2 M3 M2 Don’t Care D1 M1 A simple illustration of the XRT8001 WAN Clock, operating in the “Fractional T1/E1 Reverse/Master” Mode is presented in Figure 15. D0 PL2EN 1 Notes: 1. The value of the “D4 through D1” bit-fields within Command Register, CR1 are “Don’t Care”. 2. The contents of Command Registers CR2 and CR3 are “Don’t Care”. Rev. 1.01 24 XRT8001 P x 56kHz or P x 64kHz Where: 1 < P < 32 FIN CLK1 1.544MHz or 2.048MHz CLK2 1.544MHz or 2.048MHz XRT8001 XRT8001 WAN WANClock Clock Figure 15. Illustration of the XRT8001 WAN Clock Operating in the “Fractional T1/E1 Reverse/Master” Mode 6.3 Configuring the XRT8001 WAN Clock into the “Fractional T1/E1 Reverse/Master” Mode Step 1 – Configure the XRT8001 to operate in the “MASTER” Mode, by pulling the “MSB” input pin (pin 8) to VDD. The user can configure the XRT8001 WAN Clock to operate in the “Fractional T1/E1 Reverse/Master” Mode by executing the following steps. Input Frequency P x 56kHz P x 56kHz P x 64kHz P x 64kHz PLL1 Output Frequency 1.544MHz 1.544MHz 2.048MHz 2.048MHz Step 2 – Review Table 6, and determine which combination of “Input Frequency” and “Output Frequencies” (via PLL1 and PLL2) correlate with the desired configuration. PLL2 Output Frequency 2.048MHz 1.544MHz 1.544MHz 2.048MHz Value to Write to D4 – D1 in CR0 1001 1010 1011 1100 Table 6. Listing of “Input Frequency” and “Output Frequency” Cases for “Fractional T1/E1 Reverse/ Master” Mode Operation Rev. 1.01 25 XRT8001 Step 5 – Write the binary expression “11111” into Command Register CR3. Step 3 – Upon reviewing Table 6, write the listed value (under the “Value to Write to D4 – D1 in CR0” register) into the D4 through D1 bit-fields within Command Register CR0, as illustrated below: This step is necessary in order to insure proper operation of the XRT8001. This step is also illustrated below: Command Register CR0 (Address = 0x00) D4 D3 D2 D1 IOC4 IOC3 IOC2 IOC1 Value to Write to D4 – D1 in CR0 D0 PL1EN X Command Register, CR3 (Address = 0x03) D4 SEL24 1 Notes: 1. If the user wishes to output a clock signal via the CLK1 output signal, then he/she should also write a “1” into the “PL1EN” bit-field within Command Register CR0. 2. The contents of bit-fields D4 through D1 (within Command Register CR1) are “Don’t Care” 3. If the user wishes to output a clock signal via the CLK2 output signal, then he/she should also write a “1” into the “PL2EN” bit-field within Command Register CR1. D2 SEL22 1 D1 SEL21 1 D0 SEL20 1 Step 6 – Enable any of the following output signals as appropriate: “SYNC”, “CLK1”, “CLK2” and “LOCKDET”. This is accomplished by writing a “1” into the corresponding bit-fields, within Command Register CR4, as illustrated below: Command Register CR4, (Address = 0x04) This step configures the XRT8001 to operate in the “Fractional T1/E1 Reverse/Master” Mode. Step 4 – Specify the value of “P” (e.g., as in the “P x 56kHz” or “P x 64kHz” clock signal which is to be input via the FIN Reference Clock input). D4 D3 D2 D1 D0 SYNCEN CLK1EN CLK2EN LDETDIS2 LDETDIS1 1 1 1 0 0 6.4 The “E1 to T1 –Forward/Master” Mode When the XRT8001 WAN Clock has been configured to operate in the “E1 to T1 – Forward/Master” Mode, then it will accept a “Q x 2.048MHz” clock signal via the “Reference Clock” input at FIN (pin 3), where “Q” can range anywhere between 1 - 16. In response to this clock signal, the XRT8001 WAN Clock will output a 1.544MHz clock signal via the Clock Output pins (CLK1 and/or CLK2). In order to specify the value for “P”, one needs to write in the value of “P - 1” (binary format) into Command Register CR2, as illustrated below: Command Register, CR2 (Address = 0x02) D4 SEL14 D3 SEL23 1 D3 D2 D1 D0 SEL13 SEL12 SEL11 SEL10 Value of “P - 1” (in Binary Format). A simple illustration of the XRT8001 WAN Clock, operating in the “E1 to T1 - Forward/Master” Mode is presented in Figure 16. In other words, if one intends to input either a “56kHz” or “64kHz” clock signal via the “FIN” input pin (e.g., where P = 1), then he/she should write a “0” into Command Register CR2. Rev. 1.01 26 XRT8001 Q x 2.048MHz Where: 1 < Q < 16 FIN CLK1 1.544MHz CLK2 1.544MHz XRT8001 XRT8001 WAN Clock Figure 16. Illustration of the XRT8001 WAN Clock Operating in the “E1 to T1 – Forward/Master” Mode 6.5 Configuring the XRT8001 WAN Clock into the “E1 to T1 – Forward/Master” Mode This step configures the XRT8001 WAN Clock to operate in the “E1 to T1 – Forward/Master” Mode. The user can configure the XRT8001 WAN Clock to operate in the “E1 to T1 – Forward/Master” Mode by executing the following steps: Note: If the user wishes to output a clock signal via the CLK1 output signal, then he/she should also write a “1” into the “PL1EN” bit-field within Command Register, CR0. Step 1 – Configure the XRT8001 to operate in the “MASTER” Mode, by pulling the “MSB” input pin (pin 8) to VDD. Step 3 – Next, you need to specify the value for “Q” *(e.g., as in the “Q x 2.048MHz” clock signal which will be applied to the “FIN” input pin). Step 2 – Write the binary value “1000” into Command Register CR0, as illustrated below: The user accomplishes this writing the binary expression for “Q - 1” into Command Register, CR1, as illustrated below. Command Register, CR1 (Address = 0x01) Command Register CR0 (Address = 0x00) D4 IOC4 1 D3 IOC3 0 D2 IOC2 0 D1 IOC1 0 D4 D3 D2 D1 M4 M3 M2 M1 Value of “Q - 1” (in Binary Format) D0 PL1EN X Rev. 1.01 27 D0 PL2EN X XRT8001 Step 6 – Enable any of the following output signals as appropriate: “SYNC”, “CLK1”, “CLK2” and “LOCKDET”. For example, if the user wishes to input a clock signal of 2.048MHz, to the “FIN” input pin (e.g., where Q = 1), then he/she should write a “0” into Command Register CR1. This is accomplished by writing a “1” into the corresponding bit-fields, within Command Register CR4, as illustrated below. Note: If the user wishes to output a clock signal via the CLK2 output signal, then he/she should also write a “1” into the “PL2EN” bit-field within Command Register CR1. Command Register CR4, (Address = 0x04) D4 D3 D2 D1 D0 Step 4 – Write the binary expression “11111” into Command Register CR2, as illustrated below. This step is necessary in order to insure proper operation of the XRT8001. SYNCEN CLK1EN CLK2EN LDETDIS2 LDETDIS1 1 1 1 0 0 6.6 The “High Speed – Reverse” Mode Command Register, CR2 (Address = 0x02) D4 D3 D2 D1 D0 SEL14 SEL13 SEL12 SEL11 SEL10 1 1 1 1 1 When the XRT8001 WAN Clock has been configured to operate in the “High Speed – Reverse” Modes, its operation is independent of whether it has been configured in the "Master" or "Slave" Mode. Step 5 – Write the binary expression “11111” into Command Register CR3, as illustrated below. When the XRT8001 WAN Clock has been configured to operate in the “High Speed – Reverse” Modes, then it will accept a “64kHz” clock signal via the “Reference Clock” input at FIN (pin 3). In response, to this clock signal, the XRT8001 WAN Clock will output an “M x 2.048MHz” clock signal via the Clock Output pins (CLK1 and/or CLK2); where M can only have the values 1, 2,4 or 8. This step is necessary in order to insure proper operation of the XRT8001. This step is also illustrated below. Command Register, CR3 (Address = 0x03) D4 D3 D2 D1 D0 SEL24 SEL23 SEL22 SEL21 SEL20 1 1 1 1 1 A simple illustration of the XRT8001 WAN Clock, operating in the “High Speed – Reverse” Mode is presented in Figure 17. Rev. 1.01 28 XRT8001 64kHz CLK1 FIN M x 2.048MHz M = 1, 2, 4 or 8 XRT8001 WAN Clock M x 2.048MHz CLK2 M = 1, 2, 4 or 8 Figure 17. Illustration of the XRT8001 WAN Clock Operating in the “High Speed – Reverse” Mode 6.7 Configuring the XRT8001 WAN Clock into the “High Speed – Reverse” Mode. The user can configure the XRT8001 WAN Clock to operate in the “High Speed – Reverse” Mode, by executing the following steps. Step 3 – Write the binary expression “0000” into bitfields “D4 through D1” within Command Register, CR1, as illustrated below. Step 1 – Configure the XRT8001 to operate in the “SLAVE” Mode, by pulling the “MSB” input pin (pin 8) to GND. Command Register, CR1 (Address = 0x01) D4 D3 D2 D1 D0 M4 M3 M2 M1 PL2EN 0 0 0 0 1 Step 2 - Write the value "1101" into bts D4-D1 within command register CR0 Note: If the user wishes to output a clock signal via the CLK2 output signal, then he/she should also write a “1” into the “PL2EN” bit-field within Command Register CR1. Command Register CR0 (Address = 0x00) D4 D3 D2 D1 D0 IOC4 IOC3 IOC2 IOC1 PL1EN 1 0 1 X 1 Step 4 – Specify the value for “M” (e.g., as in the “M x 2.048MHz” clock signal) which is to be output via the “CLK1” output pin. Note: If the user wishes to output a clock signal via the CLK1 output signal, then he/she should also write a “1” into the “PL1EN” bit-field within Command Register CR0. This is accomplished by reviewing Table 7, and determining the 5 bit binary value which corresponds with the desired value of “M”. Afterwards, the user should write this value into Command Register CR2. This step configures the XRT8001 to operate in the “High Speed – Reverse” Mode. Rev. 1.01 29 XRT8001 Value of “M” 1 2 4 8 Command Register, CR3 (Address = 0x03) Value to be Written into Command Register CR2 D4 SEL24 0000X 0001X 001XX X1XX or 1XXX D3 D2 D1 SEL23 SEL22 SEL21 Value from Table 8 D0 SEL20 Step 6 – Enable any of the following output signals as appropriate: “SYNC”, “CLK1”, “CLK2” and “LOCKDET”. Table 7. Relationship Between the Value of “M” and the Value to Be Written into Command Register CR2 (in Order to Configure the “CLK1” Output Frequency) This is accomplished by writing a “1” into the corresponding bit-fields, within Command Register CR4, as illustrated below: Note: The expression “X” indicates a “Don’t Care” value for that particular bit-field. Command Register CR4, (Address = 0x04) Command Register, CR2 (Address = 0x02) D4 SEL14 D3 D2 D1 SEL13 SEL12 SEL11 Value from Table 7 D0 SEL10 D4 D3 D2 D1 D0 SYNCEN CLK1EN CLK2EN LDETDIS2 LDETDIS1 1 1 1 0 0 6.8 The "Forward/Slave" Mode Step 5 – Specify the value for “M” (e.g., as in the “M x 2.048MHz” clock signal) which is to be the output on the “CLK2” output pin. When the XRT8001 WAN Clock has been configured to operate in the “Forward/Slave” Mode, then it will accept an 8kHz clock signal via the “Reference Clock” input at FIN (pin 3). In response to this clock signal, the XRT8001 WAN Clock will output either a “L x 56kHz” or “L x 64kHz” clock signal via the “Clock Output pins” (CLK1 and CLK2); where L can range in value from 1 to 32. This is accomplished by reviewing Table 8, and determining the 5-bit binary value which corresponds with the desired value of “M”. Afterwards, the user should write this value into Command Register, CR3. Value of “M” Value to be Written into Command Register CR3 1 2 4 8 0000X 0001X 001XX X1XXX or 1XXXX A simple illustration of the XRT8001 WAN Clock operating in the "Forward/Slave" Mode” is presented in Figure 18. Table 8. Relationship Between the Value of “M” and the Value to Be Written into Command Register CR3 (in Order to Configure the “CLK2” Output Frequency) Note: The expression “X” indicates a “Don’t Care” value for that particular bit-field. Rev. 1.01 30 XRT8001 8kHz FIN CLK1 L x 56kHz to L x 64kHz 1 < L < 32 CLK2 L x 56kHz to L x 64kHz 1 < L < 32 XRT8001 WAN Clock Figure 18. Illustration of the XRT8001 WAN Clock operating in the “Forward/Slave" Mode 6.9 Configuring the XRT8001 WAN Clock into the “Forward/Slave” Mode. Step 4- Define the value for L, for the CLK2 output by writing the appropriate value into the CR3 register. This is achieved by writing the value “L – 1” into this register. The user can configure the XRT8001 WAN Clock to operate in the “Forward/Slave Mode” by executing the following steps: Step 1 – Configure the XRT8001 to operate in the “SLAVE” Mode by pulling the MSB input pin (pin 8) to GND. Note: If the user intends to output data via CLK2, then he/ she must ensure that the PL2EN bit-field within Command Register CR1 is set to “1”. Step 2 – Refer to Table 2B and write the value that corresponds to the desired "Forward/Slave" Mode into Bits D[4:1] within Command Register CR0. Step 5 – Set the CLK1EN and CLK2EN bit-fields, within Command Register CR4 to 1 in order to enable the output drivers for CLK1 and CLK2, as illustrated below. Step 3 – Define the values for L, for the CLK1 output by writing the appropriate value into the CR2 register. This is achieved by writing the value “L – 1” into this register. Command Register CR4 D3 D2 D4 Notes: 1. For example, if the user writes “00000” into this register, then the XRT8001 device will output a 64kHz signal via the CLK1 output pin. 2. If the user intends to output data via CLK1, then he/she must ensure that the PL1EN bit-field within Command Register CR0 is set to “1”. Rev. 1.01 31 D1 D0 SYNCEN CLK1EN CLK2EN X X x 1 1 0 0 XRT8001 8 kHz 3 FIN CLK1 CLK2 6 1.544 MHz or 2.048 MHz 13 1.544 MHz or 2.048 MHz Figure 19. XRT8001 Reverse/Slave Mode 6.10 Phase relationship between the “FIN” input and the “CLK1 and CLK2” outputs The Phase relationship depends upon whether the XRT8001 is operating in the “Slave” or “Master” Mode. the “SYNC” signal is approximately 4ns delayed from the “FIN” input signal. 6.11 Slave Mode: If the XRT8001 is operating in the “Slave” Mode, then there is a specific phase relationship between the “FIN” and the “CLK1, CLK2” outputs. The reasons are as follows. Each of the two PLLs “lock” onto the “SYNC” signal, for frequency synthesis. For Slave Mode Operation, the XRT8001 accepts a 8kHz clock signal (which it will also synthesize and output via the SYNC output signal). Each of the two PLLs (within the XRT8001) will be configured to generate either a “K x 56kHz” or a “K x 64kHz” clock signal. NOTES: 1. Table 9 presents the timing relationship between the “FIN” and the “CLK1, CLK2” if the PLLs are configured generate a “K x 64kHz” clock signal. This timing relationship (between FIN and the CLK1, CLK2 signals) depends upon the “CLK1” and “CLK2” signal frequencies and as listed in the following tables. 2. Table 10 presents the timing relationship between the “FIN” and the “CLK1, CLK2” if the PLLs are configured to generate a “K x 56kHz” clock signal. Hence, in the “Slave Mode”, the “SYNC” output, is simply a buffered version of the “FIN” input. Therefore, generate a “K x 56kHz” clock signal. FIN T CLK1 or CLK2 Figure 20: Timing Relationship between the FIN and the “CLK1/CLK2” outputs Rev. 1.01 32 XRT8001 Values written into 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 Value for K “SEL1[4:0] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 CLK1/CLK2 (K x 64kHz) 64kHz 128kHz 192kHz 256kHz 320kHz 384kHz 448kHz 512kHz 576kHz 640kHz 704kHz 768kHz 832kHz 896kHz 960kHz 1.024MHz 1.088Mhz 1.152MHz 1.214MHz 1.280MHz 1.344MHz 1.408MHz 1.472MHz 1.536MHz 1.600MHz 1.664MHz 1.728MHz 1.792MHz 1.856MHz 1.920MHz 1.984MHz 2.048MHz T (ns) Output Frequency 330 330 330 330 395 330 283 247 438 305 359 330 305 283 264 248 464 438 415 395 376 359 344 330 316 305 293 283 283 264 256 248 Table 9: Timing Relationship (T), from the rising edge of “CLK1/CLK2” to the rising edge of “FIN” with the XRT8001 in Slave Mode, and FIN = 8kHz Rev. 1.01 33 XRT8001 Values written into Value for K “SEL1[4:0] CLK1/CLK2 (K x 56kHz) T (ns) Output Frequency 00000 1 56kHz 376 00001 2 112kHz 376 00010 3 168kHz 376 00011 4 224kHz 376 00100 5 280kHz 450 00101 6 336kHz 376 00110 7 392kHz 323 00111 8 448kHz 283 01000 9 504kHz 500 01001 10 560kHz 450 01010 11 616kHz 410 01011 12 672kHz 376 01100 13 728kHz 347 01101 14 784kHz 323 01110 15 840kHz 302 01111 16 896kHz 283 10000 17 952kHz 529 10001 18 1.008MHz 500 10010 19 1.064MHz 474 10011 20 1.120MHz 450 10100 21 1.176MHz 429 10101 22 1.232MHz 410 10110 23 1.288MHz 392 10111 24 1.344MHz 376 11000 25 1.400MHz 361 11001 26 1.456MHz 347 11010 27 1.512MHz 335 11011 28 1.568MHz 323 11100 29 1.624MHz 312 11101 30 1.680MHz 302 11110 31 1.756MHz 292 11111 32 1.812MHz 283 Table 10: Timing Relationship (T), from the rising edge of “CLK1/CLK2” to the rising edge of “FIN” with the XRT8001 in Slave Mode, and FIN = 8kHz 6.12 Master Mode: If the XRT8001 is operating in the “Master” Mode, then the timing relationship between the “Reference signal” (e.g., a signal applied to the “FIN” and the “CLK1” or “CLK2” output is not readily available. This is because the “FIN” signal is internally divided down, via a Programmable Divider, which generates the “SYNC” signal. The internal Phase Locked Loops (within the XRT8001) are “locked” onto the “SYNC” signal. Hence, there is definitely a phase relationship between the “SYNC” and the “CLK1, CLK2” outputs. Rev. 1.01 34 XRT8001 7.0 Phase Relationship Between SYNC and CLK1 0r CLK2 Table 11, presents information on the delay between the rising edge of SYNC and CLK1 or CLK2 output signals. It is important to Note that this delay behaves as a function of the settings within the CR3 register. SEL14~SEL10 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 K 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 t Values (nS) Kx56 MODE 372 372 372 372 446 372 319 279 496 446 406 372 343 319 298 279 525 496 470 446 425 406 388 372 357 343 331 319 308 298 288 279 Kx64 MODE 326 326 326 326 391 326 279 244 434 301 355 326 301 279 260 244 460 434 411 391 372 355 340 326 312 301 289 279 279 260 252 244 Table 11. Delay Time Between SYNC and CLK1 or CLK2 Note: This table only applies when the XRT8001 is configured to operate in the "Forward/Master" or "Forward/Slave" Modes. Rev. 1.01 35 XRT8001 7.1 Synthesizing an “M x 2.048MHz” clock signal, such that “M” can take on the value of “1”, “2”, “4”, or “8” with a clock signal of 2.048MHz Figure 21 presents a possible approach that can be used. In this example, the user takes the 2.048MHz clock signal, and runs it through an external “Divideby-32” counter (which is realized with two 74AHCT193). This “Divide-by-32” counter generates a 64kHz clock signal, which is applied to the “FIN” input pin of the XRT8001. If the user configures the XRT8001 WAN Clock to operate in the “High Speed – Reverse” Mode, then it will accepts a 64kHz clock signal (via the FIN input) and generates an “M x 2.048MHz” clock signal via both the CLK1 and CLK2 outputs. NOTES: 1. In this configuration, “M” can be configured to be of value “1”, “2”, “4” or “8”. 2. The steps required to configure the XRT8001 into the “High Speed – Reverse” Mode are presented below. 1 +5V U2 15 1 10 9 2 R1 1K 2.048MHz_CLOCK 5 4 11 14 A B C D QA QB QC QD UP DN LOAD CLR CO BO 3 2 6 7 12 13 74AHCT193 U1 U3 15 1 10 9 5 4 11 14 Clear_Counter A B C D QA QB QC QD UP DN LOAD CLR CO BO 3 2 6 7 64kHz Clock Signal 3 18 1 16 17 12 13 8 FIN CLK1 SCLK SDO SDI CS CLK2 13 M x 2.048MHz_CLOCK M x 2.048MHz_CLOCK MSB 74AHCT193 LOCKDET Serial_Clock Serial_Data_Out Serial_Data_In XRT8000_Select 6 11 WAN_CLOCK_PLL_LOCK_STATUS XRT8001 Figure 21: Circuit that inputs a 2.048MHz clock and generates a “M” x 2.048MHz clock 7.2 Configuring the XRT8001 WAN Clock to operate in the “High Speed – Reverse” Mode. The following is a “six-step” procedure to configure the XRT8001 WAN Clock into the “High Speed – Reverse” Mode. STEP 2 – Write the binary expression “1101” into bitfields D4 through D1, within Command Register, CR0, as indicated below. STEP 1 – Configure the XRT8001 to operate in the “SLAVE” Mode, by pulling the “MSB” input pin (pin 8) to GND (low). Command Register, CR1 (Address = 0x01) D4 D3 D2 D1 D0 M4 M3 M2 M1 PL2EN 1 1 0 1 X Rev. 1.01 36 XRT8001 STEP 5 – Specify the value for “M” (e.g., as in the “M x 2.048MHz” clock signal) which is to output via the “CLK2” output pin. This step configures the XRT8001 to operate in the “High Speed – Reverse” Mode. NOTE: If the user wishes to output a clock signal via the “CLK1” output pin, then he/she should also write a “1” into the “PL1EN” bit-field within Command Register, CR0. This is accomplished by reviewing Table 4 to determine the 5 bit binary value corresponding with the desired value of “M”. Afterwards, the user should write this value into Command Register, CR3. STEP 3 – Write the binary expression “0000” into bit-fields D4 through D1, within Command Register, CR1, as illustrated below. Value of “M” 1 2 4 8 Command Register, CR1 (Address = 0x01) D4 D3 D2 D1 D0 M4 M3 M2 M1 PL2EN 0 0 0 0 X NOTE: If the user wishes to output a clock signal via the CLK2 output pin, then he/she should also write a “1” into the “PL2EN” bit-field within Command Register Table 13, The Relationship between the value of “M”, and Value to be written into Command Register, CR2 to configure the “CLK2” output frequency STEP 4 – Specify the value for “M” (e.g., as in the “M x 2.048MHz” clock signal) which is to output via the “CLK1” output pin. STEP 6 – Enable the desired output signals: “SYNC”, “CLK1”, “CLK2” and “LOCKDET”. This is accomplished by reviewing Table 3 to determine the 5 bit binary value which corresponds with the desired value of “M”. Afterwards, the user should write this value into Command Register, CR2. Value of “M” 1 2 4 8 Value to be written into the Command Register, CR3 0000x 0001x 001xx x1xx or 1xxx This is accomplished by writing a “1” into the corresponding bit-fields, within Command Register CR4, as illustrated below. Value to be written into the Command Register, CR2 0000x 0001x 001xx x1xx or 1xxx Command Register, CR4 (Address = 0x04) Table 12: Relationship between the value of “M”, and Value to be written into Command Register, CR2 to configure the “CLK1” output frequency Rev. 1.01 37 D4 D3 D2 SYNCEN 1 CLK1EN 1 CLK2EN 1 D1 D0 LDETDIS2 LDETDIS1 0 0 XRT8001 8.0 Generating 2.048MHz from 1.55MHz Optional 1 N.C. 2 SDO SCLK 18 SYNC CSB 17 SDI 16 Vcc 15 GND 14 CKL1 CLK 2 13 N.C. VCC VCC 12 + 5V 8/64 kHz out 3 4 5 2.048 MHz 6 + 5V 7 +5V 8 9 FIN GND GND MSB GND XRT8001 1.544 MHz LOCKDET VCC + 5V 11 10 + 5V Serial Port Control Clock and Data In Reset Optional PLD or µP Busy VER_REQ VER_PASS/FAIL Figure 22. Typical Application Example: Generating 2.048MHz from 1.544MHz Serial Port Programming in Four Steps Step Procedure Result 1 Set the "MSB_OUT" output pin to "high" Configures XRT8001 to operate in "Master" mode 2 Write the value "00101" into Command Register CR0 (located at 0x00) Configures XRT8001 to accept an "N x 1.544MHz clock signal via the "FIN" input pin., and output a "K x 64kHz" clock signal via the "CLK1" output pin. (For this application N = 1 and K = 32). This step also enables "PLL #1" within the XRT8001 3 Write the value "00000" into Command Register CR1 (located at 0x01) Sets "N" (as in "N x 1.544MHz") to be "1" 4 Write the value "11111" into Command Register CR2 (located at 0x02) Sets "K" (as in "K x 64kHz") to be "32" 5 Write the value "01000" into Command Register CR4 (located at 0x04) Enables the output driver for CLK1 Rev. 1.01 38 XRT8001 Also, note the XRT8001 WAN Clock can be configured to accept a 2.048MHz clock signal (via the “FIN” input) and generate a 1.544MHz clock signal if it configured to operate in the “E1 to T1 Forward/Master” Mode. The XRT8001 can similarly be configured to accept an 8kHz clock signal (via the same “FIN” input pin) and generate a 1.544MHz clock signal if it is configured to operate in the “Reverse/Slave” Mode. 9.0 Generating a 1.544MHz clock signal via the “CLK1/CLK2” outputs from either a 1.544MHz, or a 2.048MHz clock signal When approaching this problem, be aware that the XRT8001 WAN Clock can be configured to accept a 2.048MHz clock signal via the “FIN” input pin and generate a 1.544MHz clock signal. However, the XRT8001 WAN Clock cannot be configured to accept a 1.544MHz clock signal, and generate a 1.544MHz clock signal. Based upon these two points, the necessary circuitry (in order to synthesize a 1.544MHz clock signal, from either a 1.544MHz or a 2.048MHz clock signal) can be achieved by the approach shown below in a block diagram. 1.544MHz or 2.048MHz Clock Signal 2.048MHz or 8kHz Clock Signal 2 : 1 MUX 8kHz Divide Divideby by 193 193 FIN CLK1 1.544MHz MSB CLK2 1.544MHz SE SEL L XRT8001 WAN Clock E1/T1* SELECT Figure 23: Synthesizing a 1.544MHz clock signal from a 1.544MHz or 2.048MHz clock In Figure 23, the 1.544MHz or 2.048MHz input clock signal is routed to two locations. • One of the inputs of a “2:1 MUX”. In this case, the user must set the “E1/T1* SELECT” signal to “LOW”, order to select “T1 rates” (1.544MHz). By doing this, the 8kHz output from the “Divide-by-193” block is selected and will be applied to the “FIN” input of the XRT8001; and the XRT8001 will be configured to operate in the “Slave” Mode. • The “CU” input of a “Divide-by-193” Block. Figure 23 also includes a digital “E1/T1* SELECT” signal. This signal is connected to both the “SEL” input of the “2:1 MUX” and the “MSB” input of the XRT8001 WAN Clock. The basic idea behind this schematic is as follows: 1. If the incoming clock signal (from the T1/E1 LIU for example) is a 1.544MHz clock signal, then this signal will be divided by 193. As it passes through the “Divideby-193” block a 8kHz clock signal is generated. This 8kHz clock signal will be applied to one of the inputs to the “2:1 MUX”. (NOTE: A 1.544MHz clock signal is applied to the other input to the “2:1 MUX”). At this point, the user will need to execute the appropriate steps in order to configure the XRT8001 into the “Reverse-Slave” Mode. 2. If the incoming clock signal (from the T1/E1 LIU) is a 2.048MHz clock signal, then this signal will also be divided by 193. As it passes through the “Divide-by193” block, it generates a clock signal of a strange (and undesirable frequency). This clock signal will be applied to one of the inputs to the “2:1 MUX” (NOTE: The 2.048MHz clock will also be applied to the other input of the “2:1 MUX). Rev. 1.01 39 XRT8001 “E1 to T1 Forward/Master” Mode. In this case, the user must set the “E1/T1* SELECT” signal to “HIGH”, order to select “E1 rates” (2.048MHz). By doing this, the 2.048MHz clock signal (from the T1/ E1 LIU) is selected and will be applied to the “FIN” input of the XRT8001, and the XRT8001 will configured to operate in the “Master” Mode. 9.1 Hardware and Software Implementation Details Figure x presents a simple block diagram of a design that can accept either a 1.544MHz or a 2.048MHz clock signal, and synthesize a 1.544MHz clock signal. Now we need to provide some details. Hence, Figure 24 presents a circuit schematic which realizes the function, depicted in Figure 23. At this point, the user will need to execute the appropriate steps in order to configure the XRT8001 into the U2 Divide-by-193 1.544MHz or 2.048MHz 2 1.544MHz or 2.048MHz U5A 74AHCT04 1 15 5 4 11 14 A B C D QA QB QC QD UP DN LOAD CLR CO BO 3 2 6 7 1 U3 15 1 10 9 2 3 5 6 11 10 14 13 1A 1B 2A 2B 3A 3B 4A 4B 1Y 2Y 3Y 4Y 4 8kHz or 2.048MHz 7 9 12 A/B G 74AHCT157 12 13 U1 3 FIN CLK1 SCLK SDO SDI CS CLK2 6 1.544MHz 74AHCT193 +5V U4 15 1 10 9 5 4 11 14 18 1 16 17 8001_SCLK 8001_SDO 8001_SDI 8001_CS A B C D QA QB QC QD UP DN LOAD CLR CO BO 3 2 6 7 E1/T1* SELECT 8 13 1.544MHz MSB LOCKDET 11 LOCK_DET 12 13 XRT8001 74AHCT193 Load-in-64 E1/T1* SELECT Figure 24: Hardware Design Implementation of Figure 23. XRT8001 WAN Clock into the “Master Mode”. Next, we describe how to configure the circuitry in Figure 24 to accept a 2.048MHz clock signal, and configure it to synthesize a 1.544MHz clock signal by executing five steps. We also describe how to accept a 1.544MHz clock signal and configure it to synthesize a 1.544MHz clock. NOTE: The next steps are devoted to configuring the XRT8001 WAN Clock into the “E1 to T1 Forward/Master” Mode. STEP 2 – Write the binary value “1000” into Command Register CR0 (within the XRT8001 WAN Clock) as indicated below. 9.2 Configuring the Circuitry in Figure 6 to accept a 2.048MHz clock in order to synthesize a 1.544MHz output clock. Command Register, CR0 (Address = 0x00) D4 D3 D2 D1 D0 IOC4 IOC3 IOC2 IOC1 PL1EN 1 0 0 0 1 STEP 1 – Drive the “E1/T1* SELECT” input pin to “HIGH”. This step configures the “2:1 MUX” to select and apply the 2.048MHz clock to the “FIN” input of the XRT8001 WAN Clock, as well as configuring the Rev. 1.01 40 XRT8001 NOTE: In order to synthesize and output a clock signal via the “CLK1” output pin, the user must write a “1” into the D0 (PL1EN) bit-field within Command Register, CR0, as indicated above. Once the user has executed these five steps, then the circuitry (in Figure 6) is now configured to accept a 2.048MHz clock signal (from the T1/E1 LIU) and synthesize a 1.544MHz clock signal. This step configures the XRT8001 WAN to operate in the “E1 to T1 Forward/Master” Mode. In this mode, the XRT8001 WAN Clock will be configured to accept a “Q x 2.048MHz” clock signal via the “FIN” input and will synthesize a 1.544MHz clock signal via both the “CLK1” and “CLK2” output pins. Configuring the Circuitry in Figure 24 to accept a 1.544MHz clock signal and synthesize a 1.544MHz clock signal. The user can configure the circuitry (within Figure 6) to accept a 1.544MHz clock signal, and synthesize a 1.544MHz clock signal, by executing the following four (4) steps. STEP 3 – Next specify the value for “Q” (e.g., as in “Q x 2.048MHz” clock signal, which will be applied to the “FIN” input). STEP 1 – Drive the “E1/T1* SELECT” input pin to “LOW”. This step configures the “2:1 MUX” to select and apply the 8kHz clock signal to the “FIN” input of the XRT8001 WAN Clock, and configures the XRT8001 WAN Clock into the “Slave” Mode. In this application, the value for “Q” is “1”. Hence, the user must configure the XRT8001 WAN Clock to use this value for “Q”, by writing the binary value for “Q – 1” into Command Register, CR1. In this application, the user should write “0000” into the Command Register, as indicated below. NOTE: The next few steps will be devoted to configuring the XRT8001 WAN Clock into the “Reverse/Slave” Mode. STEP 2 – Write the binary value “1000” into Command Register CR0, within the XRT8001 WAN Clock, as indicated below. Command Register, CR1 (Address = 0x01) D4 D3 D2 D1 D0 M4 M3 M2 M1 PL2EN 0 0 0 0 1 Command Register, CR0 (Address = 0x00) NOTE: In order to synthesize and output a clock signal via the “CLK2” output pin, the user must write a “1” into the “D0 (PL2EN) bit-field within Command Register, CR1, as indicated above. Command Register, CR4 (Address = 0x04) D2 D1 1 1 1 D1 D0 IOC4 IOC3 IOC2 IOC1 PL1EN 1 0 0 0 1 STEP 3 – Write the binary expression “0000” into bitfields D4 through D1, within Command Register CR1, as illustrated below. D0 SYNCEN CLK1EN CLK2EN LDETDIS2 LDETDIS1 1 D2 This step configures the XRT8001 WAN to operate in the “Reverse/Slave” Mode. In this mode, the XRT8001 WAN Clock will be configured to accept an 8kHz clock signal via the “FIN” input and will synthesize a 1.544MHz clock signal via both the “CLK1” and “CLK2” output pins. STEP 5 – Enable the desired output signals: SYNC, CLK1, CLK2, and LOCKDET. This is accomplished by writing a “1” into the corresponding bit-field, within Command Register, CR4, as illustrated below. D3 D3 NOTE: In order to synthesize and output a clock signal via the “CLK1” output pin, the user must write a “1” into the “D0 (PL1EN) bit-field within Command Register, CR0, as indicated above. STEP 4 – Write the binary value “11111” into both Command Registers CR2 and CR3. This is necessary in order to ensure proper operation of the XRT8001 WAN Clock. D4 D4 1 Rev. 1.01 41 XRT8001 Command Register, CR1 (Address = 0x01) D4 D3 D2 D1 D0 M4 M3 M2 M1 PL2EN 0 0 0 0 1 NOTE: In order to synthesize and output a clock signal via the “CLK2” output, the user must write a “1” into the “D0 (PL2EN) bit-field within Command Register, CR1, as illustrated above. The values within Command Registers CR2 and CR3 are “don’t care”. STEP 4 – Enable the desired output signals: SYNC, CLK1, CLK2, and LOCKDET. This is accomplished by writing a “1” into the corresponding bit-field, within Command Register, CR4, as illustrated below. Command Register, CR4 (Address = 0x04) D4 SYNCEN 1 D3 D2 D1 D0 CLK1EN CLK2EN LDETDIS2 LDETDIS1 1 1 1 1 Once the user has executed these four (4) steps, then the circuitry in Figure 24 is configured to accept a 1.544MHz clock signal (from the T1/E1 LIU) and synthesize a 1.544MHz clock signal. Rev. 1.01 42 XRT8001 10.0 Jitter Transfer Characteristics of the XRT8001 The “Jitter Transfer Characteristics” of the XRT8001 are presented in Figure 25 (for 3.3V applications) and Figure 26(for 5.0V applications). The definition of “Jitter Transfer Characteristics” (of the XRT8001) is the amount of “output” jitter that the XRT8001 produces (at the “CLK1” and “CLK2” outputs), when provided with a certain amount of jitter at the FIN input pin. 1.6 1.4 1.2 Jitter Gain 1 0.8 Normalized Wideband Output Jitter 0.6 0.4 0.2 0 100 300 500 700 900 1100 1300 1500 1700 1900 Frequency Figure 25: Jitter Transfer Characteristics of the XRT8001 WAN Clock for 3.3V Applications 1.6 1.4 1.2 Jitter Gain 1 Normalized Wideband Output Jitter 0.8 0.6 0.4 0.2 0 100 300 500 700 900 1100 1300 1500 1700 1900 Frequency Figure 26: Jitter Transfer Characteristics of the XRT8001 WAN Clock for 5V Applications Rev. 1.01 43 XRT8001 11.0 PCB layout guidelines for the XRT8001 10.1 Reading Figures 25 and 26 Figures 25 and 26 are linear (as opposed to logarithmic) plots. The Jitter Gain is computed via the following equation. Jitter Gain (at Jitter Frequency f) (Jitter_Amplitude_CLK)/(Jitter_Amplitude_FIN) • Use a multi-layer circuit board with separate plane layers for “+5V” (or 3.3V) and “Ground” . • Bypass the Analog VDD pin to ground with a 6.9mF = “ceramic” capacitor. Where: • Jitter_Amplitude_FIN = The Jitter Amplitude applied to the “FIN” input (at Jitter Frequency f). • Jitter_Amplitude_CLK = The Jitter Amplitude measured at the “CLK1” or “CLK2” output, when “Jitter_Amplitude_FIN” is applied to the FIN input in of the XRT8001. • Use large “vias” located close to the IC package to ensure that Digital VDD (e.g., pins 7, 12 and 15) and Digital Ground (e.g., pins 4, 5 and 14) have a low inductance path to the +5V (+3.3V) and Ground Planes, respectively. • Bypass the Digital VDD pins (pin 10) to ground with a 0.1mF ceramic capacitors that are located as close as possible to the IC package. Hence, the Jitter Gain is not expressed in terms of dB, but simply a ratio of two numbers. 12.0 Comparing the XRT8001 with the earlier pincompatible XRT8000 Wherever the Jitter Gain exceeds “1.0” in value, then, for those “Jitter Frequencies” the XRT8001 amplifies Jitter (e.g., the amplitude of the jitter, as it propagates from the “FIN” input to the “CLK1” or CLK2” output, increases). The XRT8001 is pin-to-pin compatible with the XRT8000. However, there are some functional differences between these two products. These differences are summarized below. Conversely, wherever the Jitter Gain falls below “1.0” in value, then for those “Jitter Frequencies” the XRT8001 attenuates jitter (e.g., the amplitude of the jitter, as it propagates from the “FIN” input to the “CLK1” or “CLK2” output, decreases). 1) The XRT8001 can be configured to generate frequencies up to 2.048MHz, 4.096MHz, 8.192MHz or 16.384MHz. The Maximum Frequency that the XRT8000 can generate is either 2.048MHz or 1.544MHz Figures 25 and 26 indicate that for Jitter Frequencies, ranging between 100Hz and 1100Hz, the XRT8001 amplifies Jitter. Further, these figures also indicate that for Jitter Frequencies greater than 1100Hz, that the XRT8001 attenuates Jitter. 2) The XRT8001 can be configured to accept an E1 rate clock signal and synthesize a T1 rate clock signal. The XRT8001 can also synthesize an E1 rate clock signal, when provided with a T1 rate clock signal 10.2 Test Conditions for Measurements associated with Figures 25 and 26 • Power Supply voltage either 3.3V or 5.V • • • • The XRT8000 can be configured to accept a T1 rate clock signal (e.g., 1.544MHz) and can be easily configured to synthesize an E1 rate clock signal (e.g., 2.048MHz). Input Clock Frequency = 2.048MHz Output Clock Frequency = 2.048MHz Input Jitter Amplitude = 0.25Upp. However, the XRT8000 cannot be configured to accept an E1 rate clock signal and synthesize a T1 rate clock signal. Ambient Temperature = 25°C. Rev. 1.01 44 XRT8001 3) Both the XRT8001 and XRT8000 can be configured to accept “Fractional T1/E1” rate clock signals (e.g., K x 64kHz) and synthesize either a 1.544MHz or 2.048MHz clock signal. 4) The XRT8001 permits the user to determine the exact role of the LOCKDET output pin. The on-chip Command Register (within the XRT8001) permits the user to configure the LOCKDET output pin to have the functions listed below. However, the XRT8001 can also synthesize “Fractional T1/E1” rate clock signals, when provided with either a 1.544MHz or 2.048MHz clock signal LOCKDET Pin Function LOCK Condition of both PLL1 AND PLL2 In the XRT8000, the LOCKDET output pin is pulled HIGH only when both XRT8000 PLLs are “in-lock”. Description of LOCKDET pin’s role The LOCKDET output pin toggles “HIGH” only if both (of if the only enabled) PLLs are “In-LOCK”. The LOCKDET output pin will toggle “LOW” if any one of the PLLs are out of LOCK. NOTE: In this case, the LOCKDET output of the XRT8001 behaves identical to that of the XRT8000. LOCK Condition of PLL1 Only LOCK Condition of PLL2 Only Forced to “LOW” The LOCKDET output pin toggles “HIGH” only if PLL1 is in the “InLOCK” condition. The LOCKDET output pin toggles “HIGH” only if PLL2 is in the “InLOCK” condition. The LOCKDET output pin is pulled “LOW” regardless of the “Lock” condition of the two PLLs. NOTE: The XRT8000 has an additional divide by 8 block which is not included in the XRT8001. Table 15: Selectable Functions of the LOCKDET Output Pin in the XRT8001 Rev. 1.01 45 XRT8001 Rev. 1.01 46 XRT8001 Rev. 1.01 47 XRT8001 NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for in accuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 2001 EXAR Corporation DatasheetOctober 2001 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. Rev. 1.01 48