XRT83L34IVTR-F

厂商：
SIPEX(迈凌)
封装：
LQFP128
描述：
IC TELECOM INTERFACE 128TQFP

数据手册：

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数据手册
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XRT83L34IVTR-F 数据手册

xr XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR FEBRUARY 2005 REV. 1.0.1 GENERAL DESCRIPTION The XRT83L34 is a fully integrated Quad (four channel) long-haul and short-haul line interface unit for T1 (1.544Mbps) 100Ω, E1 (2.048Mbps) 75Ω or 120Ω, or J1 110Ω applications. In long-haul applications the XRT83L34 accepts signals that have been attenuated from 0 to 36dB at 772kHz in T1 mode (equivalent of 0 to 6000 feet of cable loss) or 0 to 43dB at 1024kHz in E1 mode. In T1 applications, the XRT83L34 can generate five transmit pulse shapes to meet the short-haul Digital Cross-Connect (DSX-1) template requirements as well as for Channel Service Units (CSU) Line Build Out (LBO) filters of 0dB, -7.5dB -15dB and -22.5dB as required by FCC rules. It also provides programmable transmit pulse generators for each channel that can be used for output pulse shaping allowing performance improvement over a wide variety of conditions. The XRT83L34 provides both a parallel Host microprocessor interface as well as a Hardware mode for programming and control. Both the B8ZS and HDB3 encoding and decoding functions are selectable as well as AMI. An on-chip crystal-less jitter attenuator with a 32 or 64 bit FIFO can be placed either in the receive or the transmit path with loop bandwidths of less than 3Hz. The XRT83L34 provides a variety of loop-back and diagnostic features as well as transmit driver short circuit detection and receive loss of signal monitoring. It supports internal impedance matching for 75Ω, 100Ω, 110Ω and 120Ω for both transmitter and receiver. In the absence of the power supply, the transmit outputs and receive inputs are tri-stated allowing for redundancy applications The chip includes an integrated programmable clock multiplier that can synthesize T1 or E1 master clocks from a variety of external clock sources. APPLICATIONS • T1 Digital Cross-Connects (DSX-1) • ISDN Primary Rate Interface • CSU/DSU E1/T1/J1 Interface • T1/E1/J1 LAN/WAN Routers • Public switching Systems and PBX Interfaces • T1/E1/J1 Multiplexer and Channel Banks Features (See Page 2) FIGURE 1. BLOCK DIAGRAM OF THE XRT83L34 T1/E1/J1 LIU (HOST MODE) MCLKE1 MCLKT1 MCLKO UT MAST ER CLOCK SYNT HESIZER One of four channels, CHANNEL_n - (n= 0:3) TPOS_n/TDATA_n TNEG_n/CO DES_n TCLK_n QRSS PAT TERN G ENERATO R HDB3/ B8ZS ENCODER T AO S ENABLE T X/RX JIT TER AT TENUAT OR DRIVE MO NIT OR DFM TIMING CO NT ROL T X FILT ER & PULSE SHAPER DMO_n TTIP_n LINE DRIVER TRING_n QRSS ENABLE REMO TE LOOPBACK QRSS DET ECT OR RCLK_n RNEG_n/LCV_n RPOS_n/RDATA_n HDB3/ B8ZS DECODER NET W ORK LO OP DET ECT OR NLCD ENABLE JA SELECT LBO[3:0] LO OPBACK ENABLE TIMING & DAT A RECOVERY T X/RX JIT TER AT TENUAT OR LOS DET ECTO R TXON_n LOCAL ANALOG LOOPBACK DIGIT AL LO OPBACK AIS DET ECTO R PEAK DET ECTO R & SLICER RTIP_n RRING_n RX EQ UALIZER EQUALIZER CO NT ROL RLOS_n HW /HOST W R_R/W RD_DS ALE_AS CS RDY_DT ACK INT TEST MICROPROCESSOR CONT RO LLER ICT µ PTS1 µ PTS2 D[7:0] µ PCLK A[7:0] RESET Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com xr XRT83L34 REV. 1.0.1 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR FIGURE 2. BLOCK DIAGRAM OF THE XRT83L34 T1/E1/J1 LIU (HARDWARE MODE) MCLKE1 MCLKT1 CLKSEL[2:0] MCLKO UT MASTER CLOCK SYNT HESIZER TAO S_n One of four Channels, CHANNEL_n - (n=0 : 3) TPOS_n/TDATA_n TNEG_n/CODES_n TCLK_n QRSS PATT ERN GENERATO R HDB3/ B8ZS ENCO DER DRIVE MO NITO R DFM T X/RX JIT T ER ATT ENUATOR TIMING CONTROL TX FILT ER & PULSE SHAPER DMO _n TT IP_n LINE DRIVER TRING _n LBO[3:0] REMOT E LO OPBACK Q RSS DET ECT OR RCLK_n RNEG_n/LCV_n RPOS_n/RDATA_n HDB3/ B8ZS DECO DER NETW O RK LO OP DET ECT OR NLCD ENABLE LOCAL ANALOG LOO PBACK DIGITAL LOO PBACK JA SELECT QRSS ENABLE TXON_n LOOPBACK ENABLE TIMING & DATA RECOVERY T X/RX JIT T ER ATT ENUATOR LOS DET ECTOR AIS DET ECT OR PEAK DET ECT OR & SLICER RTIP_n RRING_n RX EQUALIZER LO OP1_n LO OP0_n EQUALIZER CONTROL RLOS_n HW /HO ST GAUGE JASEL1 JASEL0 RXT SEL T XT SEL T ERSEL1 T ERSEL0 RXRES1 RXRES0 T EST HARW ARE CONTROL ICT RESET TRAT IO SR/DR EQ C[4:0] TCLKE RCLKE RXMUTE AT AOS FEATURES • Fully integrated four channel long-haul or short-haul transceivers for E1,T1 or J1 applications • Adaptive Receive Equalizer for up to 36dB cable attenuation • Programable Transmit Pulse Shaper for E1,T1 or J1 short-haul interfaces • Five fixed transmit pulse settings for T1 short-haul applications plus a fully programmable waveform generator for transmit output pulse shaping that can be used for both T1 and E1 modes. • Transmit Line Build-Outs (LBO) for T1 long-haul application from 0dB to -22.5dB in three 7.5dB steps • Selectable receiver sensitivity from 0 to 36dB cable loss for T1 @772kHz and 0 to 43dB for E1 @1024kHz • Receive monitor mode handles 0 to 29dB resistive attenuation along with 0 to 6dB of cable attenuation for E1 and 0 to 3dB of cable attenuation for T1 modes • Supports 75Ω and 120Ω (E1), 100Ω (T1) and 110Ω (J1) applications • Internal and/or external impedance matching for 75Ω, 100Ω, 110Ω and 120Ω • Tri-State transmit output and receive input capability for redundancy applications • Provides High Impedance for Tx and Rx during power off • Transmit return loss meets or exceeds ETSI 300-166 standard • On-chip digital clock recovery circuit for high input jitter tolerance • Crystal-less digital jitter attenuator with 32-bit or 64-bit FIFO selectable either in transmit or receive path • On-chip frequency multiplier generates T1 or E1 Master clocks from variety of external clock sources • High receiver interference immunity • On-chip transmit short-circuit protection and limiting, and driver fail monitor output (DMO) • Receive loss of signal (RLOS) output • On-chip HDB3/B8ZS/AMI encoder/decoder functions • QRSS pattern generator and detection for testing and monitoring 2 xr XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 • Error and Bipolar Violation Insertion and Detection • Receiver Line Attenuation Indication Output in 1dB steps • Network Loop-Code Detection for automatic Loop-Back Activation/Deactivation • Transmit All Ones (TAOS) and In-Band Network Loop Up and Down code generators • Supports Local Analog, Remote, Digital and Dual Loop-Back Modes • Meets or exceeds T1 and E1 short-haul and long-haul network access specifications in ITU G.703, G.775, G.736 and G.823; TR-TSY-000499; ANSI T1.403 and T1.408; ETSI 300-166 and AT&T Pub 62411 • Supports both Hardware and Host (parallel Microprocessor) interface for programming • Programmable Interrupt • Low power dissipation • Logic inputs accept either 3.3V or 5V levels • Single 3.3V Supply Operation • 128 pin TQFP package • -40°C to +85°C Temperature Range ORDERING INFORMATION PART NUMBER PACKAGE OPERATING TEMPERATURE RANGE XRT83L34IV 128 Lead TQFP (14 x 20 x 1.4mm) -40°C to +85°C 3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 TCLK_2 TP O S _2/TD ATA_2 TNE G _2/CO DE S_2 uP TS 1/R CLKE uP TS 2/TCLKE RX RE S0 RX RE S1 RXTS EL TX TS EL TE RS EL1 TE RS EL0 G ND DV DD DV DD DG ND DG ND INT/TRA TIO IC T R ES E T TX O N_0 TX O N_1 TX O N_2 TX O N_3 TNE G _1/CO DE S_1 TP O S _1/TD ATA_1 TCLK_1 T CLK _0 TPO S _0/TD AT A_0 TN E G _0/CO D E S_0 RLO S_0 RCLK _ 0 RN E G _0/LC V_0 R P O S _0/R DA TA_ 0 R VD D_0 RTIP_0 RR IN G _0 R G N D_ 0 TG N D _0 T TIP _0 TVD D_0 TRIN G _0 S R /D R TRIN G _1 TVD D _1 TT IP _1 TG N D_1 R G N D_1 RR IN G _1 RTIP_1 R VD D _1 RP O S _1/R DA TA_ 1 RN EG _1/LCV _1 RCLK _1 RLO S_1 D VD D V D D PLL_1 V D D PLL_2 M C LKE 1 M C LK T1 G N DP LL_1 G N DP LL_2 M C LK O UT CLK S E L0 CLK SE L1 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 TCLK_3 TPOS_3/TDATA_3 TNEG_3/CO DES_3 RLOS_3 RCLK_3 RNEG_3/LCV_3 RPOS_3/RDATA _3 RVDD_3 RTIP_3 RRING_3 RGND_3 TGND_3 TTIP_3 TVDD_3 TRING_3 GAUGE TRING _2 TVDD_2 TTIP_2 TGND_2 RGND_2 RRING_2 RTIP_2 RVDD_2 RPOS_2/RDATA_2 RNEG_2/LCV_2 RCLK_2 RLOS_2 DGND RDY_DTACK/RXM UTE CS/TAOS_3 ALE_AS/TAOS _2 RD_DS/TAO S_1 W R_R/W /TAOS_0 HW _HO ST DM O _3 DM O_2 DM O_1 XRT83L34 REV. 1.0.1 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR xr FIGURE 3. PIN OUT OF THE XRT83L34 XRT83L34 4 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 D M O _0 A [0]/E Q C0 A [1]/E Q C1 A [2]/E Q C2 A [3]/E Q C3 A [4]/E Q C4 A [5]/JA S EL0 A [6]/JA S EL1 D G ND D G ND D G ND D VD D D VD D D VD D uP CLK /A TAO S D [0]/LO O P 0_3 D [1]/LO O P 1_3 D [2]/LO O P 0_2 D [3]/LO O P 1_2 D [4]/LO O P 0_1 D [5]/LO O P 1_1 D [6]/LO O P 0_0 D [7]/LO O P 1_0 A G ND A V DD C LKS EL2 xr XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 TABLE OF CONTENTS GENERAL DESCRIPTION....................................................................................................1 APPLICATIONS ................................................................................................................................................ 1 Figure 1. Block Diagram of the XRT83L34 T1/E1/J1 LIU (Host Mode) ........................................... 1 Figure 2. Block Diagram of the XRT83L34 T1/E1/J1 LIU (Hardware Mode)................................... 2 FEATURES ..................................................................................................................................................... 2 ORDERING INFORMATION ....................................................................................................................... 3 Figure 3. Pin Out of the XRT83L34.................................................................................................... 4 TABLE OF CONTENTS ..................................................................................................... I PIN DESCRIPTION BY FUNCTION......................................................................................5 RECEIVE SECTIONS ........................................................................................................................................ 5 TRANSMITTER SECTIONS ................................................................................................................................ 9 MICROPROCESSOR INTERFACE ..................................................................................................................... 13 JITTER ATTENUATOR .................................................................................................................................... 19 CLOCK SYNTHESIZER ................................................................................................................................... 20 ALARM FUNCTION//REDUNDANCY SUPPORT .................................................................................................. 21 POWER AND GROUND ................................................................................................................................... 25 FUNCTIONAL DESCRIPTION ............................................................................................ 26 MASTER CLOCK GENERATOR ....................................................................................................................... 26 Figure 4. Two Input Clock Source................................................................................................... 26 Figure 5. One Input Clock Source ................................................................................................... 26 TABLE 1: MASTER CLOCK GENERATOR ................................................................................................ 27 RECEIVER........................................................................................................................... 27 RECEIVER INPUT .......................................................................................................................................... 27 RECEIVE MONITOR MODE............................................................................................................................. 28 RECEIVER LOSS OF SIGNAL (RLOS)............................................................................................................. 28 Figure 6. Simplified Diagram of -15dB T1/E1 Short Haul Mode and RLOS Condition ............... 28 Figure 7. Simplified Diagram of -29dB T1/E1 Gain Mode and RLOS Condition.......................... 29 Figure 8. Simplified Diagram of -36dB T1/E1 Long Haul Mode and RLOS Condition ................ 29 Figure 9. Simplified Diagram of Extended RLOS mode (E1 Only) ............................................... 30 RECEIVE HDB3/B8ZS DECODER ................................................................................................................. 30 RECOVERED CLOCK (RCLK) SAMPLING EDGE .............................................................................................. 30 Figure 10. Receive Clock and Output Data Timing ....................................................................... 30 JITTER ATTENUATOR .................................................................................................................................... 30 GAPPED CLOCK (JA MUST BE ENABLED IN THE TRANSMIT PATH) .................................................................. 31 TABLE 2: MAXIMUM GAP WIDTH FOR MULTIPLEXER/MAPPER APPLICATIONS ......................................... 31 ARBITRARY PULSE GENERATOR FOR T1 AND E1 ........................................................................................... 32 Figure 11. Arbitrary Pulse Segment Assignment .......................................................................... 32 TRANSMITTER ................................................................................................................... 32 DIGITAL DATA FORMAT ................................................................................................................................. 32 TRANSMIT CLOCK (TCLK) SAMPLING EDGE .................................................................................................. 32 Figure 12. Transmit Clock and Input Data Timing ......................................................................... 33 TRANSMIT HDB3/B8ZS ENCODER................................................................................................................ 33 TABLE 3: EXAMPLES OF HDB3 ENCODING ........................................................................................... 33 TABLE 4: EXAMPLES OF B8ZS ENCODING ............................................................................................ 33 DRIVER FAILURE MONITOR (DMO) ............................................................................................................... 33 TRANSMIT PULSE SHAPER & LINE BUILD OUT (LBO) CIRCUIT ........................................................................ 34 TABLE 5: RECEIVE EQUALIZER CONTROL AND TRANSMIT LINE BUILD-OUT SETTINGS ............................ 34 TRANSMIT AND RECEIVE TERMINATIONS .................................................................... 36 RECEIVER (CHANNELS 0 - 3) ..................................................................................................................... 36 Internal Receive Termination Mode ............................................................................................................ 36 TABLE 6: RECEIVE TERMINATION CONTROL .......................................................................................... 36 Figure 13. Simplified Diagram for the Internal Receive and Transmit Termination Mode......... 36 I xr XRT83L34 REV. 1.0.1 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR TABLE 7: RECEIVE TERMINATIONS ........................................................................................................ 37 Figure 14. Simplified Diagram for T1 in the External Termination Mode (RXTSEL= 0) .............. 37 Figure 15. Simplified Diagram for E1 in External Termination Mode (RXTSEL= 0) .................... 38 TRANSMITTER (CHANNELS 0 - 3) .............................................................................................................. 38 Transmit Termination Mode ........................................................................................................................ 38 TABLE 8: TRANSMIT TERMINATION CONTROL ........................................................................................ 38 TABLE 9: TERMINATION SELECT CONTROL ............................................................................................ 38 External Transmit Termination Mode .......................................................................................................... 38 TABLE 10: TRANSMIT TERMINATION CONTROL ...................................................................................... 39 TABLE 11: TRANSMIT TERMINATIONS .................................................................................................... 39 REDUNDANCY APPLICATIONS ............................................................................................................... 39 TYPICAL REDUNDANCY SCHEMES ....................................................................................................... 40 Figure 16. Simplified Block Diagram of the Transmit Section for 1:1 & 1+1 Redundancy ........ 41 Figure 17. Simplified Block Diagram - Receive Section for 1:1 and 1+1 Redundancy ............... 41 Figure 18. Simplified Block Diagram - Transmit Section for N+1 Redundancy .......................... 42 Figure 19. Simplified Block Diagram - Receive Section for N+1 Redundancy ............................ 43 PATTERN TRANSMIT AND DETECT FUNCTION ................................................................................................. 44 TABLE 12: PATTERN TRANSMISSION CONTROL....................................................................................... 44 TRANSMIT ALL ONES (TAOS) ....................................................................................................................... 44 NETWORK LOOP CODE DETECTION AND TRANSMISSION................................................................................. 44 TABLE 13: LOOP-CODE DETECTION CONTROL ...................................................................................... 44 TRANSMIT AND DETECT QUASI-RANDOM SIGNAL SOURCE (TDQRSS) ........................................................... 45 LOOP-BACK MODES...................................................................................................................................... 46 TABLE 14: LOOP-BACK CONTROL IN HARDWARE MODE ......................................................................... 46 TABLE 15: LOOP-BACK CONTROL IN HOST MODE................................................................................... 46 LOCAL ANALOG LOOP-BACK (ALOOP).......................................................................................................... 46 Figure 20. Local Analog Loop-back signal flow............................................................................. 46 REMOTE LOOP-BACK (RLOOP) .................................................................................................................... 47 Figure 21. Remote Loop-back mode with jitter attenuator selected in receive path .................. 47 Figure 22. Remote Loop-back mode with jitter attenuator selected in Transmit path ............... 47 DIGITAL LOOP-BACK (DLOOP) ..................................................................................................................... 48 Figure 23. Digital Loop-back mode with jitter attenuator selected in Transmit path ................. 48 DUAL LOOP-BACK ........................................................................................................................................ 48 Figure 24. Signal flow in Dual loop-back mode.............................................................................. 48 THE MICROPROCESSOR INTERFACE............................................................................ 49 THE PINS OF THE MICROPROCESSOR INTERFACE ............................................................................................ 49 TABLE 16: MICROPROCESSOR INTERFACE SIGNAL DESCRIPTION ............................................................ 49 ...................................... 52 TABLE 17: THE ROLES OF THE VARIOUS MICROPROCESSOR INTERFACE PINS, WHEN CONFIGURED TO OPERATE IN THE INTEL-ASYNCHRONOUS MODE.............................................................................. 52 CONFIGURING THE MICROPROCESSOR INTERFACE TO OPERATE IN THE INTEL-ASYNCHRONOUS MODE .............. 53 THE INTEL-ASYNCHRONOUS READ CYCLE ....................................................................................................... 53 Figure 25. Illlustration of an Intel-Asynchronous Mode Read Operation .................................... 54 THE INTEL-ASYNCHRONOUS WRITE CYCLE...................................................................................................... 54 Figure 26. Illustration of an Intel-Asynchronous Mode Write Operation ..................................... 55 OPERATING THE MICROPROCESSOR INTERFACE IN THE MOTOROLA-ASYNCHRONOUS MODE .......................... 55 .................................................................................................................................................................... 56 TABLE _, THE ROLES OF VARIOUS MICROPROCESSOR INTERFACE PINS, WHEN CONFIGURED TO OPERATE IN THE MOTOROLA-ASYNCHRONOUS MODE ................................................................................................................ 56 CONFIGURING THE MICROPROCESSOR INTERFACE TO OPERATE IN THE MOTOROLA-ASYNCHRONOUS MODE ....... 57 THE MOTOROLA-ASYNCHRONOUS READ-CYCLE:..............................................................................................57 Figure 27. Illlustration of a Motorola-Asynchronous Mode Read Operation............................... 58 THE MOTOROLA-ASYNCHRONOUS WRITE CYCLE ............................................................................................. 58 Figure 28. Illustration of a Motorola-Asynchronous Write Operation.......................................... 59 MICROPROCESSOR REGISTER TABLES .......................................................................................................... 60 OPERATING THE MICROPROCESSOR INTERFACE IN THE INTEL-ASYNCHRONOUS MODE II xr XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 TABLE 18: MICROPROCESSOR REGISTER ADDRESS .............................................................................. 60 TABLE 19: MICROPROCESSOR REGISTER BIT DESCRIPTION .................................................................. 60 MICROPROCESSOR REGISTER DESCRIPTIONS ............................................................................................... 63 TABLE 20: MICROPROCESSOR REGISTER #0, BIT DESCRIPTION ............................................................ 63 TABLE 21: MICROPROCESSOR REGISTER #1, BIT DESCRIPTION ............................................................ 64 TABLE 22: MICROPROCESSOR REGISTER #2, BIT DESCRIPTION ............................................................ 66 TABLE 23: MICROPROCESSOR REGISTER #3, BIT DESCRIPTION ............................................................ 68 TABLE 24: MICROPROCESSOR REGISTER #4, BIT DESCRIPTION ............................................................ 70 TABLE 25: MICROPROCESSOR REGISTER #5, BIT DESCRIPTION ............................................................ 71 TABLE 26: MICROPROCESSOR REGISTER #6, BIT DESCRIPTION ............................................................ 73 TABLE 27: MICROPROCESSOR REGISTER #7, BIT DESCRIPTION ............................................................ 74 TABLE 28: MICROPROCESSOR REGISTER #8, BIT DESCRIPTION ............................................................ 75 TABLE 29: MICROPROCESSOR REGISTER #9, BIT DESCRIPTION ............................................................ 75 TABLE 30: MICROPROCESSOR REGISTER #10, BIT DESCRIPTION .......................................................... 76 TABLE 31: MICROPROCESSOR REGISTER #11, BIT DESCRIPTION .......................................................... 76 TABLE 32: MICROPROCESSOR REGISTER #12, BIT DESCRIPTION .......................................................... 77 TABLE 33: MICROPROCESSOR REGISTER #13, BIT DESCRIPTION .......................................................... 77 TABLE 34: MICROPROCESSOR REGISTER #14, BIT DESCRIPTION .......................................................... 78 TABLE 35: MICROPROCESSOR REGISTER #15, BIT DESCRIPTION .......................................................... 78 TABLE 36: MICROPROCESSOR REGISTER #64, BIT DESCRIPTION .......................................................... 79 CLOCK SELECT REGISTER.............................................................................................. 80 Figure 29. Register 0x81h Sub Registers ....................................................................................... 80 TABLE 37: MICROPROCESSOR REGISTER #65, BIT DESCRIPTION .......................................................... 81 TABLE 38: MICROPROCESSOR REGISTER #66, BIT DESCRIPTION .......................................................... 82 ELECTRICAL CHARACTERISTICS...................................................................................84 TABLE 39: TABLE 40: TABLE 41: TABLE 42: TABLE 43: TABLE 44: TABLE 45: TABLE 46: Figure 30. TABLE 47: Figure 31. TABLE 48: TABLE 49: Figure 32. Figure 33. ABSOLUTE MAXIMUM RATINGS ............................................................................................ 84 DC DIGITAL INPUT AND OUTPUT ELECTRICAL CHARACTERISTICS ......................................... 84 XRT83L34 POWER CONSUMPTION..................................................................................... 84 E1 RECEIVER ELECTRICAL CHARACTERISTICS ..................................................................... 85 T1 RECEIVER ELECTRICAL CHARACTERISTICS ..................................................................... 86 E1 TRANSMIT RETURN LOSS REQUIREMENT ........................................................................ 86 E1 TRANSMITTER ELECTRICAL CHARACTERISTICS ............................................................... 87 T1 TRANSMITTER ELECTRICAL CHARACTERISTICS ............................................................... 87 ITU G.703 Pulse Template.............................................................................................. 88 TRANSMIT PULSE MASK SPECIFICATION .............................................................................. 88 DSX-1 Pulse Template (normalized amplitude) ........................................................... 89 DSX1 INTERFACE ISOLATED PULSE MASK AND CORNER POINTS ........................................... 89 AC ELECTRICAL CHARACTERISTICS .................................................................................... 90 Transmit Clock and Input Data Timing ......................................................................... 90 Receive Clock and Output Data Timing ....................................................................... 91 MICROPROCESSOR INTERFACE I/O TIMING .................................................................................................... 91 Intel Interface Timing - Asynchronous ........................................................................................................ 91 Figure 34. Intel Asynchronous Programmed I/O Interface Timing .............................................. 91 TABLE 50: ASYNCHRONOUS MODE 1 - INTEL 8051 AND 80188 INTERFACE TIMING ................................ 92 Motorola Asychronous Interface Timing ..................................................................................................... 93 Figure 35. Motorola 68K Asynchronous Programmed I/O Interface Timing ............................... 93 TABLE 51: ASYNCHRONOUS - MOTOROLA 68K - INTERFACE TIMING SPECIFICATION .............................. 93 Figure 36. Microprocessor Interface Timing - Reset Pulse Width ............................................... 93 ORDERING INFORMATION ............................................................................................... 94 PACKAGE DIMENSIONS - 14X20 MM, 128 PIN PACKAGE ................................................................................. 94 REVISIONS ................................................................................................................................................... 95 NOTES:.......................................................................................................................................... 96 III xr XRT83L34 REV. 1.0.1 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR PIN DESCRIPTION BY FUNCTION RECEIVE SECTIONS SIGNAL NAME PIN # TYPE DESCRIPTION RLOS_0 RLOS_1 RLOS_2 RLOS_3 4 28 75 99 O Receiver LOS (Loss of Signal) Defect Indicator Output for Channel _n This output pin indicates whether or not the Receive Section associated with Channel n (within the LIU device) is declaring the LOS defect condition, as depicted below. LOGIC LOW - Indicates that this particular channel is currently not declaring the LOS defect condition. LOGIC HIGH - Indicates that this particular channel is currently declaring the LOS defect condition. See “Receiver Loss of Signal (RLOS)” on page 28. RCLK_0 RCLK_1 RCLK_2 RCLK_3 5 27 76 98 O Receiver Clock Output for Channel _n The Receive Section (of a given channel within the XRT83L34 device) will update the RPOS_n and RNEG_n/LCV_n output pins upon either the rising or falling edge of this output clock signal (depending upon user configuration). RNEG_0/ LCV_0 RNEG_1/ LCV_1 RNEG_2/ LCV_2 RNEG_3/ LCV_3 6 O Receiver Negative-Polarity Data Output/Line Code Violation Indicator Output - Channel n: The exact function of this output pin depends upon whether the XRT83L34 device has been configured to operate in the Single-Rail or Dual-Rail Mode, as described below. Dual-Rail Mode Operation - Receive Negative-Polarity Data Output RNEG_n: The Receive Section of Channel n will output the negative-polarity portion of the recovered incoming DS1/E1 data (from the remote terminal equipment) via this output pin. Each channel (within the XRT83L34 device) will update this incoming DS1/E1 data upon the "user-selected" edge of the RCLK_n output signal. The "Positive-Polarity Portion" of the recovered incoming DS1/E1 data will be output via the RPOS_n output pin. Single-Rail Mode Operation - Line Code Violation Indicator Output LCV_n: The Receive Section of Channel n will pulse this output pin "high" (for one RCLK_n period) each time it detects a Line Code Violation within the incoming DS1/E1 line signal. Each channel (within the XRT83L34 device) will update this output pin upon the "user-selected" edge of the RCLK_n output signal. 26 77 97 5 xr XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 SIGNAL NAME PIN # TYPE DESCRIPTION RPOS_0/ RDATA_0 RPOS_1/ RDATA_1 RPOS_2/ RDATA_2 RPOS_3/ RDATA_3 7 O Receiver Positive-Polarity Data Output/Receive Data Output - Channel n: The exact function of this output pin depends upon whether the XRT83L34 device has been configured to operate in the Single-Rail or Dual-Rail Mode as described below. Dual-Rail Mode Operation - Receive Positive-Polarity Data Output Pin RPOS_n: The Receive Section of Channel n will output the positive-polarity portion of the Recovered incoming DS1/E1 data (from the remote terminal equipment) via this output pin. Each Channel (within the XRT83L34 device) will update the data (that is output via this output pin) upon the "user-selected" edge of the RCLK_n output clock signal. The "Negative-Portion" of this recovered incoming DS1/E1 data (from the remote terminal equipment) will be output via the corresponding RNEG_n output pin. Single-Rail Mode Operation - Receive Data Output Pin - RDATA_n If Channel n has been configured to operate in the Single-Rail Mode, then the entire incoming DS1/E1 data (that has been recovered by the Receive Section of Channel n) will be output via this output pin upon the "userselected" edge of the RCLK_n output clock signal. 25 78 96 RTIP_0 RTIP_1 RTIP_2 RTIP_3 9 23 80 94 I Receiver Differential Tip Positive Input for Channel _n: This input pin, along with the corresponding RRING_n input pin functions as the "Receive DS1/E1 Line Signal" for Channel n, within the XRT83L34 device. The user is expected to connect this signal and the corresponding RRING_n input signal to a 1:1 transformer. Whenever the RTIP_n/RRING_n input pins are receiving a positive-polarity pulse within the incoming DS1 or E1 line signal, then this input pin will be pulsed to a "higher-voltage" than that of the corresponding RRING_n input pin. Conversely, whenever the RTIP_n/RRING_n input pins are receiving a negative-polarity pulse within the incoming DS1 or E1 line signal, then this input pin will be pulsed to a "lower-voltage" than that of the corresponding RRING_n input pin. RRING_0 RRING_1 RRING_2 RRING_3 10 22 81 93 I Receiver Differential Ring Negative Input for Channel _n: This input pin, along with the corresponding RTIP_n input pin functions as the "Receive DS1/E1 Line Signal" for Channel n, within the XRT83L34 device. The user is expected to connect this signal and the corresponding RTIP_n input signal to a 1:1 transformer. Whenever the RTIP_n/RRING_n input pins are receiving a positive-polarity pulse within the incoming DS1 or E1 line signal, then this input pin will be pulsed to a "lower-voltage" than that of the corresponding RTIP_n input pin. Conversely, whenever the RTIP_n/RRING_n input pins are receiving a negative-polarity pulse within the incoming DS1 or E1 line signal, then this input pin will be pulsed to a "higher-voltage" than that of the corresponding RTIP_n input pin. 6 xr XRT83L34 REV. 1.0.1 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR SIGNAL NAME PIN # TYPE DESCRIPTION RXMUTE 73 I Receive Muting upon LOS Command Input/READY or DTACK Output: The exact function of this Input/Output pin depends upon whether the XRT83L34 device has been configured to operate in the HOST or Hardware Mode, as described below. Hardware Mode Operation - Receive Muting upon LOS Command Input pin: This input pin permits the user to enable or disable the "Muting upon LOS" feature within the XRT83L34 device. If the user enables the "Muting upon LOS" feature, then the Receive Section of each channel (within the XRT83L34 device) will automatically MUTE their own RPOS_n/RNEG_n output pins (e.g., force to ground) for the duration that they are declaring the LOS defect condition, as described below. LOW - Disables the "Muting upon LOS" feature for all four (4) HIGH - Enables the "Muting upon LOS" feature. NOTES: RDY_DTACK 73 O 1. Internally pulled "Low" with 50kΩ resistor. 2. In Hardware mode, all receive channels share the same RXMUTE control function. HOST Mode Operation - Ready or DTACK Output See “Ready or DTACK Output/Receive Muting upon LOS Command Input pin:” on page 16. 7 xr XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 SIGNAL NAME RXRES0 RXRES1 PIN # TYPE 108 109 I DESCRIPTION Receive External Resistor Control Pins - Hardware mode Receive External Resistor Control Pin 0 Receive External Resistor Control Pin 1 These pins are used to determine the value of the external Receive fixed resistor according to the following table: RXRES1 RXRES0 Required Fixed External RX Resistor 0 0 No External Fixed Resistor 0 1 240 Ω 1 0 210 Ω 1 1 150 Ω NOTE: These pins are internally pulled “Low” with 50kΩ resistor. RCLKE µPTS1 106 I Receive Clock Edge Select/Microprocessor Type Select Input pin: The exact function of this input pin depends upon whether the XRT83L34 device has been configured to operate in the HOST or Hardware Mode, as described below. Hardware Mode Operation - Receive Clock Edge Select Input pin RCLKE: This input pin permits the user to configure the Receive Section (of each channel within the XRT83L34 device) to update the data (that is output via the RPOS_n/RDATA_n and RNEG_n/LCV_n output pins) upon either the rising edge or falling edge of the RCLK_n output clock signal, as depicted below. LOW - Configures all four channels to update the RPOS_n/RDATA_n and RNEG_n/LCV_n output pins upon rising edge of RCLK_n. HIGH - Configures all four channels to update the RPOS_n/RDATA_n and RNEG_n/LCV_n output pins upon the falling edge of RCLK_n. HOST Mode Operation - Microprocessor Type Select Input pin # 1: This pin is used to select the microprocessor type. See “Microprocessor Type Select Input Pins/Receive Clock Edge Select/Transmit Clock Edge Select Input Pin:” on page 17. NOTE: This pin is internally pulled "Low" with a 50kΩ resistor. 8 xr XRT83L34 REV. 1.0.1 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR TRANSMITTER SECTIONS SIGNAL NAME PIN # TYPE DESCRIPTION TCLKE 107 I Transmit Clock Edge - Hardware Mode With this pin set to a "High", transmit input data of all channels are sampled at the rising edge of TCLK_n. With this pin tied "Low", input data are sampled at the falling edge of TCLK_n. Microprocessor Type Select Input pin 2 - Host Mode This pin should be tied to GND. µPTS1(pin 106) selects the microprocessor type. See “Microprocessor Type Select Input Pins/Receive Clock Edge µPTS2 Select/Transmit Clock Edge Select Input Pin:” on page 17. NOTE: This pin is internally pulled "Low" with a 50kΩ resistor. TTIP_0 TTIP_1 TTIP_2 TTIP_3 13 O 19 84 90 Transmitter Tip Output for Channel _n: This output pin, along with the corresponding TRING_n output pin, functions as the Transmit DS1/E1 Output signal drivers for the XRT83L34 device. The user is expected to connect this signal and the corresponding TRING_n output signal to a "1:2.45" step-up transformer. Whenever the Transmit Section of (a given channel within the XRT83L34 device) generates and transmits a "positive-polarity" pulse (onto the line), this output pin will be pulsed to a "higher-voltage" than its corresponding TRING_n output pins. Conversely, whenever the Transmit Section (of a given channel within the XRT83L34 device) generates and transmits a "negative-polarity" pulse (onto the line), then this output pin will be pulsed to a "lower-voltage" than that of the TRING_n output pin. NOTE: This output pin will be tri-stated whenever the user sets the "TxON" input pin (or bit-field) to "0". TRING_0 TRING_1 TRING_2 TRING_3 15 17 86 88 O Transmitter Ring Output for Channel _n: This output pin, along with the corresponding TTIP_n output pin, functions as the Transmit DS1/E1" output signal drivers for the XRT83L34 device. The user is expected to connect this signal and the corresponding TTIP_n output signal to a "1:2.45" step-up transformer. Whenever the Transmit Section (of a given channel, within the XRT83L34 device) generates and transmits a "positive-polarity" pulse (onto the line), this output pin will be pulsed to a "lower-voltage" than its corresponding TTIP_n output pin. Conversely, whenever the Transmit Section (of a given channel, within the XRT83L34 device) generates and transmits a "negative-polarity" pulse (onto the line) this output pin will be pulsed to a "higher-voltage" than that of the TTIP_n output pin. NOTE: This output pin will be tri-stated whenever the user sets the "TxON" input pin (or bit-field) to "0". 9 xr XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 SIGNAL NAME PIN # TYPE DESCRIPTION TPOS_0/ TDATA_0 TPOS_1/ TDATA_1 TPOS_2/ TDATA_2 TPOS_3/ TDATA_3 2 I Transmit Positive-Polarity Data Input pin/Transmit Data Input pin: The exact function of this input pin depends upon whether the XRT83L34 device has been configured to operate in the Single-Rail or Dual-Mode, as described below. Dual-Rail Mode Operation - Transmit Positive-Polarity Data Output TPOS_n: For Dual-Rail Applications, the System-Side Terminal Equipment should apply the "positive-polarity" portion of the outbound DS1/E1 data-stream to this input pin. Likewise, the System-Side Terminal Equipment should also apply the "negative-polarity" portion of the outbound DS1/E1 data-stream to the TNEG_n input pin. The Transmit Section of Channel n will sample this input pin (along with TNEG_n) upon the "user-selected" edge of TCLK_n. The Transmit Section of Channel n will generate a "positive-polarity" pulse (via the outbound DS1/E1 line signal) anytime it samples this input pin at a logic "HIGH" level. The Transmit Section of Channel n will NOT generate a "positive-polarity" pulse (via the outbound DS1/E1 line signal) anytime it samples this input pin at a logic "LOW" level. 127 104 101 Single-Rail Mode Operation - Transmit Data Output - TDATA_n: For Single-Rail Applications, the System-Side Terminal Equipment should apply the entire "outbound" DS1/E1 data-stream to this input pin. The Transmit Section of Channel n will sample this input pin upon the "user-selected" edge of TCLK_n. In the Single-Rail Mode, the internal B8ZS/HDB3 Encoder will be enabled, and the Transmit Section of the Channel will generate and transmit "positive" and "negative-polarity" pulses within the outbound DS1/E1 line signal, based upon this "B8ZS/HDB3 Encoder. NOTE: This pin is internally pulled “Low” with a 50kΩ resistor for each channels. 10 xr XRT83L34 REV. 1.0.1 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR SIGNAL NAME PIN # TYPE TNEG_0/ CODES_0 TNEG_1/ CODES_1 TNEG_2/ CODES_2 TNEG_3/ CODES_3 3 I 126 DESCRIPTION Transmitter Negative-Polarity Data Input/Line Code Select Input: The exact function of this input pin depends upon the following. • Whether the XRT83L34 device has been configured to operate in the Single-Rail or Dual Mode 105 • Whether the XRT83L34 device has been configure to operate in the HOST or Hardware Mode, as described below 100 Dual-Rail Mode Operation - Transmit Negative-Polarity Data Input TNEG_n: For Dual-Rail Applications, the System-Side Terminal Equipment should apply the "negative-polarity" portion of the outbound DS1/E1 data-stream to this input pin. Likewise, the System-Side Terminal Equipment should also apply the "positive-polarity" portion of the outbound DS1/E1 data-stream to the TPOS_n input pin. The Transmit Section of Channel n will sample this input pin (along with TPOS_n) upon the "user-selected" edge of TCLK_n. The Transmit Section of Channel n will generate a "negative-polarity" pulse (via the outbound DS1/E1 line signal) anytime it samples this input pin at a logic "HIGH" level. The Transmit Section of Channel n will NOT generate a "negative-polarity" pulse (via the outbound DS1/E1 line signal) anytime it samples this input pin at a logic LOW" level. Single-Rail Mode Operation - Line Code Select Input/NO FUNCTION: If the XRT83L34 device has been configured to operate in the Single-Rail Mode, then the exact function of this input pin depends upon whether the chip has been configured to operate in the HOST or Hardware Mode, as described below. HOST Mode Operation - NO FUNCTION: If the XRT83L34 device has been configured to operate in both the HOST Mode, and Single-Rail Modes, then this input pin has no function. Since this input pin has an internal pull-down resistor, the user can either leave this pin floating, or he/she can tie this pin to GND. Hardware Mode Operation - Line Code Select Input pin - CODES_n: If the XRT83L34 device has been configured to operate in both the Hardware and Single-Rail Modes, then this input pin permits the user to configure a given channel to enable or disable the HDB3/B8ZS Encoder and Decoder blocks as described below. If the user enables the HDB3/B8ZS Encoder and Decoder blocks then the Channel will support the HDB3 line code (for E1 applications) and the B8ZS line code (for T1 applications). If the user disables the HDB3/B8ZS Encoder and Decoder blocks, then the Channel will support the AMI line code (for either T1 and E1 applications). LOW - Enables the HDB3/B8ZS Encoder and Decoder blocks within Channel n. HIGH - Disables the HDB3/B8ZS Encoder and Decoder blocks within Channel n. NOTE: Internally pulled “Low” with a 50kΩ resistor for channel _n 11 xr XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 SIGNAL NAME PIN # TYPE DESCRIPTION TCLK_0 TCLK_1 TCLK_2 TCLK_3 1 128 103 102 I Transmit Line Clock Input - Channel n: The Transmit Section of Channel n will use this input pin to sample and latch the data that is present on the "TPOS_n/TDATA_n" and "TNEG_n" input pins. This input clock signal also functions as the timing source for the "Transmit Direction" signal within the Channel. For T1 Applications, the user is expected to apply a 1.544MHz clock signal to this input pin. Similarly, for E1 Applications, the user is expected to apply a 2.048MHz clock signal to this input pin. NOTE: Internally pulled “Low” with a 50kΩ resistor for all channels. TAOS_0 TAOS_1 TAOS_2 TAOS_3 69 70 71 72 WR_R/W RD_DS ALE_AS CS 69 70 71 72 I Transmit All Ones Command Input - Channel n: (Hardware Mode ONLY) The exact function of these input pins depend upon whether the XRT83L34 device has been configured to operate in the HOST or Hardware Modes, as described below. Hardware Mode Operation - Transmit All Ones Command Input - Channel n - TAOS_n: These input pins permits the user to command a given Channel to transmit an "Unframed, All Ones" pattern (via the outbound DS1/E1 line signal) to the remote terminal equipment. Setting this pin to the logic "HIGH" level configures the Transmit Section (of the corresponding channel) to transmit an Unframed, All Ones pattern via the outbound DS1/E1 line signal. Setting this pin to the logic "LOW" level, configures the Transmit Section (of the corresponding channel) to transmit normal traffic via the outbound DS1/E1 line signal. Host Mode Operation: These pins act as various microprocessor functions. See “Microprocessor Interface” on page 13. NOTE: These pins are internally pulled “Low” with a 50kΩ resistor. TXON_0 122 I Transmitter Turn On for Channel _0 Hardware mode Setting this pin "High" turns on the Transmit Section of Channel _0 and has no control of the Channel_0 receiver. When TXON_0 = “0” then TTIP_0 and TRING_0 driver outputs will be tri-stated. NOTE: In Hardware mode only, all receiver channels will be turned on upon power-up and there is no provision to power them off. The receive channels can only be independently powered on or off in Host mode. TXON_1 TXON_2 TXON_3 123 124 125 In Host mode The TXON_n bits in the channel control registers turn each channel Transmit section ON or OFF. However, control of the on/off function can be transferred to the Hardware pins by setting the TXONCTL bit (bit 6) to “1” in the register at address hex 0x42. Transmitter Turn On for Channel _1 Transmitter Turn On for Channel _2 Transmitter Turn On for Channel _3 NOTE: Internally pulled "Low" with a 50kΩ resistor for all channels. 12 xr XRT83L34 REV. 1.0.1 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR MICROPROCESSOR INTERFACE SIGNAL NAME PIN # TYPE DESCRIPTION HW_HOST 68 I HOST/HARDWARE Mode Control Input pin: This pin permits the user to configure the XRT83L34 device to operate in either the HOST or the Hardware Mode. If the user configures the XRT83L34 device to operate in the HOST Mode, then the Microprocessor Interface block will become active and virtually all configuration settings (within the XRT83L34 device) will be achieved by writing values into the on-chip registers (via the Microprocessor Interface). If the user configures the XRT83L34 device to operate in the Hardware Mode, then the Microprocessor Interface block will be disabled, and all configuration settings (within the XRT83L34 device) will be achieved by setting various input pins to logic HIGH or LOW settings. LOGIC LOW - Configures the XRT83L34 device to operate in the HOST Mode. LOGIC HIGH or FLOATING - Configures the XRT83L34 device to operate in the Hardware Mode. NOTE: Internally pulled “High” with a 50kΩ resistor. WR_R/W 69 I Write Strobe/Read-Write Operation Identifier/Transmit All Ones Input Pin - Channel 0: The exact function of this input pin depends upon whether the XRT83L34 device has been configured to operate in the HOST or the Hardware Mode, as described below. HOST Mode Operation - Write Strobe/Read-Write Operation Identifier: Assuming that the XRT83L34 device has been configured to operate in the Host Mode, then the exact function of the this input pin depends upon which mode the Microprocessor Interface has been configured to operate in, as described below. Intel-Asynchronous Mode - WR* - Write Strobe Input pin: If the Microprocessor Interface is configured to operate in the Intel-Asynchronous Mode, then this input pin functions as the WR* (Active-Low WRITE Strobe) input signal from the Microprocessor. Once this active-low signal is asserted, then the input buffers (associated with the Bi-Direction Data bus pins, D[7:0]) will be enabled. The Microprocessor Interface will latch the contents on the Bi-Directional Data Bus (into the "target" register or address location, within the XRT83L34) upon the rising edge of this input pin. Motorola-Asynchronous Mode - R/W* - Read/Write Operation Identification Input pin: If the Microprocessor Interface is operating in the "Motorola-Asynchronous" Mode, then this pin is functionally equivalent to the R/W* input pin. In the Motorola-Asynchronous Mode, a READ operation occurs if this pin is held at a logic "1", coincident to a falling edge of the RD/DS* (Data Strobe) input pin. Similarly, a WRITE operation occurs if this input is at a logic "0", coincident to a falling edge of the RD/DS* (Data Strobe) input pin. TAOS_0 69 Hardware Mode Operation - Transmit All “Ones” Channel_0 - Hardware Mode See “Transmit All Ones Command Input - Channel n: (Hardware Mode ONLY)” on page 12. NOTE: Internally pulled “Low” with a 50kΩ resistor. 13 xr XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 SIGNAL NAME PIN # TYPE DESCRIPTION RD_DS 70 I TAOS_1 70 Read Strobe/Data Strobe/Transmit All Ones Command Input - Channel 1: The exact function of this input pin depends upon whether the XRT83L34 device has been configure to operate in the HOST or Hardware Mode, as described below. HOST Mode Operation - READ Strobe/Data Strobe Input: The exact function of this input pin depends upon which mode the Microprocessor Interface has been configured to operate in, as described below. Intel-Asynchronous Mode - RD* - READ Strobe Input: If the MIcroprocessor Interface is operating in the Intel-Asynchronous Mode, then this input pin will function as the RD* (Active Low READ Strobe) input signal from the Microprocessor. Once this active-low signal is asserted, then the XRT83L34 device will place the contents of the addressed register on the Microprocessor Interface Bi-Directional Data Bus (D[7:0]). When this signal is negated, then the Bi-Directional Data Bus will be tri-stated. Motorola-Asynchronous Mode - DS* - Data Strobe Input: If the Microprocessor Interface is operating in the Motorola-Asynchronous Mode, then this input pin will function as the DS* (Data Strobe) input signal . Hardware Mode Operation - Transmit All One Command Input - Channel 1: See “Transmit All Ones Command Input - Channel n: (Hardware Mode ONLY)” on page 12. NOTE: Internally pulled “Low” with a 50kΩ resistor. 14 xr XRT83L34 REV. 1.0.1 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR SIGNAL NAME PIN # TYPE DESCRIPTION ALE_AS 71 I TAOS_2 71 Address Latch Enable/Address Strobe/Transmit All Ones Input - Channel 2: The exact function of this input pin depend upon whether the XRT83L34 device has been configured to operate in the HOST or Hardware Mode, as described below. HOST Mode Operation - Address Latch Enable/Address Strobe Input Pin: The exact function of this input pin depends upon which mode the Microprocessor Interface has been configured to operate in, as described below. Intel-Asynchronous Mode - ALE - Address Latch Enable: If the Microprocessor Interface (of the XRT83L34 device) has been configured to operate in the Intel-Asynchronous Mode, then this active-high input pin is used to latch the address (present at the Microprocessor Interface Address Bus pins (A[6:0]) into the XRT83L34 Microprocessor Interface bloc and to indicate the start of a READ or WRITE cycle. Pulling this input pin "high" enables the input bus drivers for the Address Bus Input pins (A[6:0]). The contents of the Address Bus will be latched into the XRT83L34 Microprocessor Interface circuitry, upon the falling edge of this input signal. Motorola Asynchronous Mode - AS* - Address Strobe Input: If the Microprocessor Interface has been configured to operate in the Motorola-Asynchronous Mode, then pulling this input pin "LOW enables the "input" bus drivers for the Address Bus Input pins. During each READ or WRITE operation, the user is expected to drive this input pin "LOW" after (or around the time that) he/she has places the address (of the "target" register) onto the Address Bus pins (A[6:0]). The user is then expected to hold this input pin "LOW" for the remainder of the READ or WRITE cycle. NOTE: It is permissible to tie the ALE_AS* and CS* input pins together.. Read and Write operations will be performed properly if ALE_AS is driven "LOW" coincident to whenever CS* is also driven "LOW". Hardware Mode Operation - Transmit All “Ones” Channel_2 - Hardware Mode See “Transmit All Ones Command Input - Channel n: (Hardware Mode ONLY)” on page 12. NOTE: Internally pulled “Low” with a 50kΩ resistor. CS 72 TAOS_3 72 I Chip Select Input/Transmit All Ones Input - Channel 3: The exact function of this input pin depends upon whether the XRT83L34 device has been configured to operate in the HOST or Hardware Mode, as described below. HOST Mode Operation - Chip Select Input pin: The user must assert this active-low signal in order to select the Microprocessor Interface for READ and WRITE operations between the Microprocessor and the XRT83L34 on-chip registers. Hardware Mode Operation - Transmit All Ones Input - Channel 3: See “Transmit All Ones Command Input - Channel n: (Hardware Mode ONLY)” on page 12. NOTE: Internally pulled “Low” with a 50kΩ resistor. 15 xr XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 SIGNAL NAME PIN # TYPE DESCRIPTION RDY_DTACK 73 O RXMUTE 73 I Ready or DTACK Output/Receive Muting upon LOS Command Input pin: The exact function of this input pin depends upon whether the XRT83L34 device has been configured to operate in the HOST or Hardware Mode, as described below. HOST Mode Operation - READY or DTACK Output Pin: The exact function of this input pin depends upon which mode the Microprocessor Interface has been configured to operate in, as described below. Intel-Asynchronous Mode - RDY* - Ready Output: If the Microprocessor Interface has been configured to operate in the IntelAsynchronous Mode, then this output pin will function as the "active-low" READY output. During a READ or WRITE cycle, the Microprocessor Interface block will toggle this output pin to the logic low level, ONLY when it (the Microprocessor Interface) is ready to complete or terminate the current READ or WRITE cycle. Once the Microprocessor has determined that this input pin has toggled to the logic "low" level, then it is now safe for it to move on and execute the next READ or WRITE cycle. If (during a READ or WRITE cycle) the Microprocessor Interface block is holding this output pin at a logic "high" level, then the Microprocessor is expected to extend this READ or WRITE cycle, until it detects this output pin being toggled to the logic low level. Motorola-Asynchronous Mode - DTACK* - Data Transfer Acknowledge Output: If the Microprocessor interface has been configured to operate in the Motorola-Asynchronous Mode, then this output pin will function as the "active-low" DTACK output. During a READ or WRITE cycle, the Microprocessor Interface block will toggle this output pin to the logic low level, ONLY when it (the Microprocessor Interface) is ready to complete or terminate the current READ or WRITE cycle. Once the Microprocessor Interface has determined that this input pin has toggled to the logic "low" level, then it is now safe for it to move on and execute the next READ or WRITE cycle. If (during a READ or WRITE cycle) the Microprocessor Interface block is holding this output pin at a logic "HIGH" level, then the MIcroprocessor is expected to extend this READ or WRITE cycle, until it detects this output pin being toggled to the logic "LOW" level. Receive Muting - Hardware mode See “Receive Muting upon LOS Command Input/READY or DTACK Output:” on page 7. NOTE: Internally pulled “Low” with a 50kΩ resistor. 16 xr XRT83L34 REV. 1.0.1 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR SIGNAL NAME PIN # TYPE DESCRIPTION µPTS1 µPTS2 106 107 I Microprocessor Type Select Input Pins/Receive Clock Edge Select/ Transmit Clock Edge Select Input Pin: The exact function of these input pins depends upon whether the XRT83L34 device has been configured to operate in the HOST or Hardware Mode, as described below. HOST Mode Operation - Microprocessor Type Select Input Bits 2 and 1 µPTS[2:1]: These two input pins permit the user to configure the Microprocessor Interface to operate in either of the following modes. • Intel-Asynchronous Mode • Motorola-Asynchronous Mode The relationship between the settings of these input pins and the corresponding Microprocessor Interface configuration is presented below. NOTE: RCLKE 106 TCLKE 107 µPTS2 µPTS1 µP Type 0 0 Intel Asynchronous Mode 0 1 Motorola Asynchronous Mode The µPTS2 (pin107) should be tied to GND. The µPTS1(pin 106) input pin permits the user to selects either the Intel-Asynchronous or the Motorola Asynchronous Modes. Hardware Mode Operation - Receive Clock Edge Select Input pin: See “Receive Clock Edge Select/Microprocessor Type Select Input pin:” on page 8. Hardware Mode Operation - Transmit Clock Edge Select Input pin: See “Transmit Clock Edge - Hardware Mode” on page 9. NOTE: These pins are internally pulled “Low” with a 50kΩ resistor. D[7] D[6] D[5] D[4] D[3] D[2]/ D[1]/ D[0]/ 42 43 44 45 46 47 48 49 LOOP1_0 LOOP0_0 LOOP1_1 LOOP0_1 LOOP1_2 LOOP0_2 LOOP1_3 LOOP0_3 42 43 44 45 46 47 48 49 I/O Bi-Directional Data Bus Pins/Loop-back Control Input Pins - D[7:0]: The exact function of these input/output pins depends upon whether the XRT83L34 device has been configured to operate in the HOST or Hardware Mode, as described below. HOST Mode Operation - Bi-Directional Data Bus Input/Output Pins (Microprocessor Interface block) - D[7:0]: These pins are used to drive and receive data over the bi-directional data bus, whenever the Microprocessor performs a READ or WRITE operation with the Microprocessor Interface of the XRT83L34 device. Hardware Mode Operation - Loop-back Control pin, Bits [1:0]_Channel_n - Hardware Mode Pins 42 - 49 control which Loop-Back mode is selected per channel. See “Loop-Back Control Pins - Hardware Mode:” on page 22. NOTE: Internally pulled “Low” with a 50kΩ resistor. 17 xr XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 SIGNAL NAME PIN # TYPE A[6] A[5] A[4] A[3] A[2] A[1] A[0] 57 58 59 60 61 62 63 I JASEL1 JASEL0 57 58 EQC4 EQC3 EQC2 EQC1 EQC0 59 60 61 62 63 DESCRIPTION Address Bus Input Pins/Jitter Attenuator Select Input Pins/Equalizer Control Input pins: The exact function of these input pins depends upon whether the XRT83L34 device has been configured to operate in the HOST or Hardware Mode, as described below. HOST Mode Operation - Address Bus Input Pins - A[6:0]: These pins permits the Microprocessor to identity on-chip registers (within the XRT83L34 device0 whenever it performs READ and WRITE operations with the XRT83L34 device. Microprocessor Interface Address Bus[6] Microprocessor Interface Address Bus[5] Microprocessor Interface Address Bus[4] Microprocessor Interface Address Bus[3] Microprocessor Interface Address Bus[2] Microprocessor Interface Address Bus[1] Microprocessor Interface Address Bus[0] Jitter Attenuator Select Pins - Hardware Mode Jitter Attenuator select pin 1 Jitter Attenuator select pin 0 See “Jitter Attenuator” on page 19. Equalizer Control Pins - Hardware Mode Equalizer Control Input pin 4 Equalizer Control Input pin 3 Equalizer Control Input pin 2 Equalizer Control Input pin 1 Equalizer Control Input pin 0 Pins EQC[4:0] select the Receive Equalizer and Transmitter Line Build Out. See “Alarm Function//Redundancy Support” on page 21. NOTE: Internally pulled “Low” with a 50kΩ resistor. INT 119 TRATIO 119 I Interrupt Output - Host Mode This pin goes “Low” to indicate an alarm condition has occurred within the device. Interrupt generation can be globally disabled by setting the GIE bit to "0" in the command control register. Transmitter Transformer Ratio Select - Hardware mode The function of this pin is to select the transmitter transformer ratio. See “Alarm Function//Redundancy Support” on page 21. NOTE: This pin is an open drain output and requires an external 10kΩ pullup resistor. 18 xr XRT83L34 REV. 1.0.1 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR JITTER ATTENUATOR SIGNAL NAME PIN # TYPE JASEL0 JASEL1 58 57 I A[6] A[5] 57 58 DESCRIPTION Jitter Attenuator Select Pins - Hardware Mode Jitter Attenuator select pin 0 Jitter Attenuator select pin 1 JASEL[1:0] pins are used to place the jitter attenuator in the transmit path, the receive path or to disable it. JASEL1 JASEL0 JA Path JA JABW BWHz T1 MHz E1 0 0 Disabled ----T1 ----E1 T1/E1 -------- 0 0 1 Transmit 3 10 32/32 0 1 1 0 Receive 3 10 32/32 0 1 1 Receive 3 1.5 64/64 FIFO Size Microprocessor Address Bits A[6:5] -Host Mode See “Address Bus Input Pins/Jitter Attenuator Select Input Pins/ Equalizer Control Input pins:” on page 18. NOTE: Internally pulled “Low” with a 50kΩ resistor. 19 xr XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 CLOCK SYNTHESIZER SIGNAL NAME PIN # TYPE DESCRIPTION MCLKE1 32 I E1 Master Clock Input A 2.048MHz clock for with an accuracy of better than ±50ppm and a duty cycle of 40% to 60% can be provided at this pin. In systems that have only one master clock source available (E1 or T1), that clock should be connected to both MCLKE1 and MCLKT1 inputs for proper operation. NOTES: CLKSEL0 CLKSEL1 CLKSEL2 37 38 39 I 1. All channels of the XRT83L34 must be operated at the same clock rate, either T1, E1 or J1. 2. Internally pulled “Low” with a 50kΩ resistor. Clock Select inputs for Master Clock Synthesizer - Hardware mode CLKSEL[2:0] are input signals to a programmable frequency synthesizer that can be used to generate a master clock from an accurate external clock source according to the following table. The MCLKRATE control signal is generated from the state of EQC[4:0] inputs. See Table 4 for description of Transmit Equalizer Control bits. Host Mode: The state of these pins are ignored and the master frequency PLL is controlled by the corresponding interface bits. See register address 1000001. MCLKE1 (kHz) MCLKT1 (kHz) CLKSEL2 CLKSEL1 CLKSEL0 MCLKRATE CLKOUT (KHz) 2048 2048 0 0 0 0 2048 2048 2048 0 0 0 1 1544 2048 1544 0 0 0 0 2048 1544 1544 0 0 1 1 1544 1544 1544 0 0 1 0 2048 2048 1544 0 0 1 1 1544 8 X 0 1 0 0 2048 8 X 0 1 0 1 1544 16 X 0 1 1 0 2048 16 X 0 1 1 1 1544 56 X 1 0 0 0 2048 56 X 1 0 0 1 1544 64 X 1 0 1 0 2048 64 X 1 0 1 1 1544 128 X 1 1 0 0 2048 128 X 1 1 0 1 1544 256 X 1 1 1 0 2048 256 X 1 1 1 1 1544 NOTE: These pins are internally pulled "Low" with a 50kΩ resistor. 20 xr XRT83L34 REV. 1.0.1 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR SIGNAL NAME PIN # TYPE MCLKT1 33 I DESCRIPTION T1 Master Clock Input This signal is an independent 1.544MHz clock for T1 systems with required accuracy of better than ±50ppm and duty cycle of 40% to 60%. MCLKT1 input is used in the T1 mode. NOTES: MCLKOUT 36 O 1. All channels of the XRT83L34 must be operated at the same clock rate, either T1, E1 or J1. 2. See pin 32 description for further explanation for the usage of this pin. 3. Internally pulled “Low” with a 50kΩ resistor. Synthesized Master Clock Output This signal is the output of the Master Clock Synthesizer PLL which is at T1 or E1 rate based upon the mode of operation. ALARM FUNCTION//REDUNDANCY SUPPORT SIGNAL NAME PIN # TYPE GAUGE 87 I DESCRIPTION Twisted Pair Cable Wire Gauge Select - Hardware mode Connect this pin "High" to select 26 Gauge wire. Connect this pin “Low” to select 22 and 24 gauge wire for all channels. NOTE: Internally pulled “Low” with a 50kΩ resistor. DMO_0 64 DMO_1 DMO_2 DMO_3 65 66 67 ATAOS 50 O Driver Failure Monitor Channel _0 This pin transitions "High" if a short circuit condition is detected in the transmit driver of Channel _0, or no transmit output pulse is detected for more than 128 TCLK_0 cycles. Driver Failure Monitor Channel _1 Driver Failure Monitor Channel _2 Driver Failure Monitor Channel _3 I Automatic Transmit “All Ones” Pattern - Hardware Mode Only: A "High" level on this pin enables the automatic transmission of an "All Ones" AMI pattern from the transmitter of any channel that the receiver of that channel has detected an LOS condition. A "Low" level on this pin disables this function. NOTE: All channels share the same ATAOS input control function. Microprocessor Clock Input - Host Mode This pin should be tied to GND for asynchronous microprocessor modes. NOTE: This pin is internally pulled “Low” for asynchronous microprocessor interface when no clock is present. 21 xr XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 SIGNAL NAME PIN # TYPE DESCRIPTION TRATIO 119 I Transmitter Transformer Ratio Select - Hardware Mode In external termination mode (TXSEL = 0), setting this pin "High" selects a transformer ratio of 1:2 for the transmitter. A "Low" on this pin sets the transmitter transformer ratio to 1:2.45. In the internal termination mode the transmitter transformer ratio is permanently set to 1:2 and the state of this pin is ignored. Interrupt Output - Host Mode INT O This pin is asserted “Low” to indicate an alarm condition. See “Micropro- cessor Interface” on page 13. NOTE: This pin is an open drain output and requires an external 10kΩ pullup resistor. RESET 121 I Hardware Reset (Active "Low") When this pin is tied “Low” for more than 10µs, the device is put in the reset state. Pulling RESET and ICT pins “Low” simultaneously will put the chip in factory test mode. This condition should not be permitted during normal operation. NOTE: Internally pulled “High” with a 50kΩ resistor. SR/DR 16 I Single-Rail/Dual-Rail Data Format Connect this pin "Low" to select transmit and receive data format in Dual-rail mode. In this mode, HDB3 or B8ZS encoder and decoder are not available. Connect this pin "High" to select single-rail data format. NOTE: Internally pulled "Low" with a 50kΩ resistor. LOOP1_0 LOOP0_0 LOOP1_1 LOOP0_1 LOOP1_2 LOOP0_2 LOOP1_3 LOOP0_3 D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] 42 43 44 45 46 47 48 49 42 43 44 45 46 47 48 49 I/O Loop-Back Control Pins - Hardware Mode: Loop-back control pin 1 - Channel _0 Loop-back control pin 0 - Channel _0 Loop-back control pin 1 - Channel _1 Loop-back control pin 0 - Channel _1 Loop-back control pin 1 - Channel _2 Loop-back control pin 0 - Channel _2 Loop-back control pin 1 - Channel _3 Loop-back control pin 0 - Channel _3 LOOP1_n LOOP0_n MODE 0 0 Normal Mode No Loop-back Channel_n 0 1 Local Loop-Back Channel_n 1 0 Remote Loop-Back Channel_n 1 1 Digital Loop-Back Channel_n Microprocessor R/W Data bits [7:0] - Host Mode These pins are microprocessor data bus pins. See “Bi-Directional Data Bus Pins/Loop-back Control Input Pins - D[7:0]:” on page 17. NOTE: These pins are internally pulled “Low” with a 50kΩ resistor. 22 xr XRT83L34 REV. 1.0.1 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR SIGNAL NAME PIN # TYPE DESCRIPTION EQC4 59 I EQC3 EQC2 EQC1 EQC0 60 61 62 63 Equalizer Control Input 4 - Hardware Mode This pin together with EQC[3:0] are used for controlling the transmit pulse shaping, transmit line build-out (LBO), receive monitoring and also to select T1, E1 or J1 Modes of operation. See Table 4 for description of Transmit Equalizer Control bits. Equalizer Control Input 3 Equalizer Control Input 2 Equalizer Control Input 1 Equalizer Control Input 0 A[4] A[3] A[2] A[1] A[0] 59 60 61 62 63 RXTSEL 110 NOTES: 1. In Hardware mode all transmit channels share the same pulse setting controls function. 2. All channels of an XRT83L34 must operate at the same clock rate, either the T1, E1 or J1 modes. Microprocessor Address bits [4:0] - Host Mode See “Address Bus Input Pins/Jitter Attenuator Select Input Pins/ Equalizer Control Input pins:” on page 18. NOTE: Internally pulled “Low” with a 50kΩ resistor for all channels. I Receiver Termination Select In Hardware mode, when this pin is “Low” the receive line termination is determined only by the external resistor. When “High”, the receive termination is realized by internal resistors or the combination of internal and external resistors. These conditions are described in the table below. NOTE: In Hardware mode all channels share the same RXTSEL control function. RXTSEL RX Termination 0 External 1 Internal In Host mode, the RXTSEL_n bits in the channel control registers determines if the receiver termination is external or internal. However the function of RXTSEL can be transferred to the Hardware pin by setting the TERCNTL bit (bit 4) to “1” in the register 66 address hex 0x42. NOTE: Internally pulled “Low” with a 50kΩ resistor. TXTSEL 111 I Transmit Termination Select - Hardware Mode When this pin is “Low” the transmit line termination is determined only by an external resistor. When “High”, the transmit termination is realized only by the internal resistor. TXTSEL TX Termination 0 External 1 Internal NOTES: 1. This pin is internally pulled "Low" with a 50kΩ resistor. 2. In Hardware Mode all channels share the same TXTSEL control function. 23 xr XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 SIGNAL NAME PIN # TYPE DESCRIPTION TERSEL0 TERSEL1 113 112 I Termination Impedance Select pin 0 Termination Impedance Select pin 1 In the Hardware mode and in the internal termination mode (TXTSEL=”1” and RXTSEL=”1”), TERSEL[1:0] control the transmit and receive termination impedance according to the following table. TERSEL1 TERSEL0 Termination 0 0 100Ω 0 1 110Ω 1 0 75Ω 1 1 120Ω In the internal termination mode, the receiver termination of each receiver is realized completely by internal resistors or by the combination of internal and one fixed external resistor (see description of RXRES[1:0] pins). In the internal termination mode the transformer ratio of 1:2 and 1:1 is required for transmitter and receiver respectively with the transmitter output AC coupled to the transformer. NOTES: ICT 120 I 1. This pin is internally pulled "Low" with a 50kΩ resistor. 2. In Hardware Mode all channels share the same TERSEL control function. In-Circuit Testing (active "Low"): When this pin is tied “Low”, all output pins are forced to a “High” impedance state for in-circuit testing. Pulling RESET and ICT pins “Low” simultaneously will put the chip in factory test mode. For normal operation, the user should either leave this input pin "floating" or pull it to a logic "HIGH" level. NOTE: Internally pulled “High” with a 50kΩ resistor. 24 xr XRT83L34 REV. 1.0.1 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR POWER AND GROUND SIGNAL NAME PIN # TYPE DESCRIPTION TGND_0 TGND_1 TGND_2 TGND_3 12 20 83 91 **** Transmitter Analog Ground for Channel _0 Transmitter Analog Ground for Channel _1 Transmitter Analog Ground for Channel _2 Transmitter Analog Ground for Channel _3 TVDD_0 TVDD_1 TVDD_2 TVDD_3 14 18 85 89 **** Transmitter Analog Positive Supply (3.3V + 5%) for Channel _0 Transmitter Analog Positive Supply (3.3V + 5%) for Channel _1 Transmitter Analog Positive Supply (3.3V + 5%) for Channel _2 Transmitter Analog Positive Supply (3.3V + 5%) for Channel _3 RVDD_0 RVDD_1 RVDD_2 RVDD_3 8 24 79 95 **** Receiver Analog Positive Supply (3.3V± 5%) for Channel _0 Receiver Analog Positive Supply (3.3V± 5%) for Channel _1 Receiver Analog Positive Supply (3.3V± 5%) for Channel _2 Receiver Analog Positive Supply (3.3V± 5%) for Channel _3 RGND_0 RGND_1 RGND_2 RGND_3 11 21 82 92 **** Receiver Analog Ground for Channel _0 Receiver Analog Ground for Channel _1 Receiver Analog Ground for Channel _2 Receiver Analog Ground for Channel _3 VDDPLL_1 VDDPLL_2 AVDD 30 31 40 **** Analog Positive Supply for Master Clock Synthesizer PLL (3.3V± 5%) Analog Positive Supply for Master Clock Synthesizer PLL (3.3V± 5%) Analog Positive Supply (3.3V± 5%) GNDPLL_1 GNDPLL_2 AGND 34 35 41 **** Analog Ground for Master Clock Synthesizer PLL Analog Ground for Master Clock Synthesizer PLL Analog Ground DVDD DVDD DVDD DVDD DVDD DVDD 29 51 52 53 115 116 **** Digital Positive Supply (3.3V± 5%) Digital Positive Supply (3.3V± 5%) Digital Positive Supply (3.3V± 5%) Digital Positive Supply (3.3V± 5%) Digital Positive Supply (3.3V± 5%) Digital Positive Supply (3.3V± 5%) DGND DGND DGND DGND GND DGND DGND 54 55 56 74 114 117 118 **** Digital Ground Digital Ground Digital Ground Digital Ground Ground Digital Ground Digital Ground 25 xr XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 FUNCTIONAL DESCRIPTION The XRT83L34 is a fully integrated four-channel long-haul and short-haul transceiver intended for T1, J1 or E1 systems. Simplified block diagrams of the device are shown in Figure 1, Host mode and Figure 2, Hardware mode. The XRT83L34 can receive signals that have been attenuated from 0 to 36dB at 772kHz (0 to 6000 feet cable loss) for T1 and from 0 to 43dB at 1024kHz for E1 systems. In T1 applications, the XRT83L34 can generate five transmit pulse shapes to meet the short-haul Digital Crossconnect (DSX-1) template requirement as well as four CSU Line Build-Out (LBO) filters of 0dB, -7.5dB, -15dB and -22.5dB as required by FCC rules. It also provides programmable transmit output pulse generators for each channel that can be used for output pulse shaping allowing performance improvement over a wide variety of conditions. The operation and configuration of the XRT83L34 can be controlled through a parallel microprocessor Host interface or, by Hardware control. MASTER CLOCK GENERATOR Using a variety of external clock sources, the on-chip frequency synthesizer generates the T1 (1.544MHz) or E1 (2.048MHz) master clocks necessary for the transmit pulse shaping and receive clock recovery circuit. There are two master clock inputs MCLKE1 and MCLKT1. In systems where both T1 and E1 master clocks are available these clocks can be connected to the respective pins. All channels of a given XRT83L34 must be operated at the same clock rate, either T1, E1 or J1 modes. In systems that have only one master clock source available (E1 or T1), that clock should be connected to both MCLKE1 and MCLKT1 inputs for proper operation. T1 or E1 master clocks can be generated from 8kHz, 16kHz, 56kHz, 64kHz, 128kHz and 256kHz external clocks under the control of CLKSEL[2:0] inputs according to Table 1. NOTE: EQC[4:0] determine the T1/E1 operating mode. See Table 5 for details. FIGURE 4. TWO INPUT CLOCK SOURCE Two Input Clock Sources 2.048MHz +/-50ppm MCLKE1 MCLKOUT 1.544MHz +/-50ppm MCLKT1 1.544MHz or 2.048MHz FIGURE 5. ONE INPUT CLOCK SOURCE Input Clock Options 8kHz 16kHz 56kHz 64kHz 128kHz 256kHz 1.544MHz 2.048MHz One Input Clock Source MCLKE1 MCLKOUT MCLKT1 26 1.544MHz or 2.048MHz xr XRT83L34 REV. 1.0.1 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR TABLE 1: MASTER CLOCK GENERATOR MCLKE1 KHZ MCLKT1 KHZ CLKSEL2 CLKSEL1 CLKSEL0 MCLKRATE MASTER CLOCK KHZ 2048 2048 0 0 0 0 2048 2048 2048 0 0 0 1 1544 2048 1544 0 0 0 0 2048 1544 1544 0 0 1 1 1544 1544 1544 0 0 1 0 2048 2048 1544 0 0 1 1 1544 8 x 0 1 0 0 2048 8 x 0 1 0 1 1544 16 x 0 1 1 0 2048 16 x 0 1 1 1 1544 56 x 1 0 0 0 2048 56 x 1 0 0 1 1544 64 x 1 0 1 0 2048 64 x 1 0 1 1 1544 128 x 1 1 0 0 2048 128 x 1 1 0 1 1544 256 x 1 1 1 0 2048 256 x 1 1 1 1 1544 In Host mode the programming is achieved through the corresponding interface control bits, the state of the CLKSEL[2:0] control bits and the state of the MCLKRATE interface control bit. RECEIVER RECEIVER INPUT At the receiver input, a cable attenuated AMI signal can be coupled to the receiver through a capacitor or a 1:1 transformer. The input signal is first applied to a selective equalizer for signal conditioning. The maximum equalizer gain is up to 36dB for T1 and 43dB for E1 modes. The equalized signal is subsequently applied to a peak detector which in turn controls the equalizer settings and the data slicer. The slicer threshold for both E1 and T1 is typically set at 50% of the peak amplitude at the equalizer output. After the slicers, the digital representation of the AMI signals are applied to the clock and data recovery circuit. The recovered data subsequently goes through the jitter attenuator and decoder (if selected) for HDB3 or B8ZS decoding before being applied to the RPOS_n/RDATA_n and RNEG_n/LCV_n pins. Clock recovery is accomplished by a digital phase-locked loop (DPLL) which does not require any external components and can tolerate high levels of input jitter that meets or exceeds the ITU-G.823 and TR-TSY000499 standards. In Hardware mode only, all receive channels are turned on upon power-up and are always on. In Host mode, each receiver channel can be individually turned on or off with the respective channel RXON_n bit. See “Microprocessor Register #0, Bit Description” on page 63. 27 xr XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 RECEIVE MONITOR MODE In applications where Monitor mode is desired, the equalizer can be configured in a gain mode which handles input signals attenuated resistively up to 29dB, along with 0 to 6dB cable attenuation for both T1 and E1 applications, refer to Table 5 for details. This feature is available in both Hardware and Host modes. RECEIVER LOSS OF SIGNAL (RLOS) For compatibility with ITU G.775 requirements, the RLOS monitoring function is implemented using both analog and digital detection schemes. If the analog RLOS condition occurs, a digital detector is activated to count for 32 consecutive zeros in E1 (4096 bits in Extended Los mode, EXLOS = “1”) or 175 consecutive zeros in T1 before RLOS is asserted. RLOS is cleared when the input signal rises +3dB (built in hysteresis) above the point at which it was declared and meets 12.5% ones density of 4 ones in a 32 bit window, with no more than 16 consecutive zeros for E1. In T1 mode, RLOS is cleared when the input signal rises +3dB (built in hysteresis) above the point at which it was declared and contains 16 ones in a 128 bit window with no more than 100 consecutive zeros in the data stream. When loss of signal occurs, RLOS register indication and register status will change. If the RLOS register enable is set high (enabled), the alarm will trigger an interrupt causing the interrupt pin (INT) to go low. Once the alarm status register has been read, it will automatically reset upon read (RUR), and the INT pin will return high. Analog RLOS Setting the Receiver Inputs to -15dB T1/E1 Short Haul Mode By setting the receiver inputs to -15dB T1/E1 short haul mode, the equalizer will detect the incoming amplitude and make adjustments by adding gain up to a maximum of +15dB normalizing the T1/E1 input signal. NOTE: This is the only setting that refers to cable loss (frequency), not flat loss (resistive). Once the T1/E1 input signal has been normalized to 0dB by adding the maximum gain (+15dB), the receiver will declare RLOS if the signal is attenuated by an additional -9dB. The total cable loss at RLOS declaration is typically -24dB (-15dB + -9dB). A 3dB hysteresis was designed so that transients will not trigger the RLOS to clear. Therefore, the RLOS will typically clear at a total cable attenuation of -21dB. See Figure 6 for a simplified diagram. FIGURE 6. SIMPLIFIED DIAGRAM OF -15dB T1/E1 SHORT HAUL MODE AND RLOS CONDITION Norm alized up to +15dB Max -9dB Clear LOS +3dB Declare LOS Declare LOS +3dB Clear LOS -9dB Norm alized up to +15dB Max Setting the Receiver Inputs to -29dB T1/E1 Gain Mode By setting the receiver inputs to -29dB T1/E1 gain mode, the equalizer will detect the incoming amplitude and make adjustments by adding gain up to a maximum of +29dB normalizing the T1/E1 input signal. NOTE: This is the only setting that refers to flat loss (resistive). All other modes refer to cable loss (frequency). Once the T1/E1 input signal has been normalized to 0dB by adding the maximum gain (+29dB), the receiver will declare RLOS if the signal is attenuated by an additional -9dB. The total cable loss at RLOS declaration is 28 xr XRT83L34 REV. 1.0.1 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR typically -38dB (-29dB + -9dB). A 3dB hysteresis was designed so that transients will not trigger the RLOS to clear. Therefore, the RLOS will typically clear at a total flat loss of -35dB. See Figure 7 for a simplified diagram. FIGURE 7. SIMPLIFIED DIAGRAM OF -29dB T1/E1 GAIN MODE AND RLOS CONDITION Norm alized up to +29dB Max -9dB Clear LOS +3dB Declare LOS Declare LOS +3dB Clear LOS -9dB Norm alized up to +29dB Max Setting the Receiver Inputs to -36dB T1/E1 Long Haul Mode By setting the receiver inputs to -36dB T1/E1 long haul mode, the equalizer will detect the incoming amplitude and make adjustments by adding gain up to a maximum of +36dB normalizing the T1 input signal. This setting refers to cable loss (frequency), not flat loss (resistive). Once the T1/E1 input signal has been normalized to 0dB by adding the maximum gain (+36dB), the receiver will declare RLOS if the signal is attenuated by an additional -9dB. The total cable loss at RLOS declaration is typically -45dB (-36dB + -9dB). A 3dB hysteresis was designed so that transients will not trigger the RLOS to clear. Therefore, the RLOS will typically clear at a total cable attenuation of -42dB. See Figure 8 for a simplified diagram. FIGURE 8. SIMPLIFIED DIAGRAM OF -36dB T1/E1 LONG HAUL MODE AND RLOS CONDITION Norm alized up to +36dB Max -9dB Clear LOS +3dB Declare LOS Declare LOS +3dB Clear LOS -9dB Norm alized up to +36dB Max E1 Extended RLOS E1: Setting the Receiver Inputs to Extended RLOS By setting the receiver inputs to extended RLOS, the equalizer will detect the incoming amplitude and make adjustments by adding gain up to a maximum of +43dB normalizing the E1 input signal. This setting refers to cable loss (frequency), not flat loss (resistive). Once the E1 input signal has been normalized to 0dB by adding the maximum gain (+43dB), the receiver will declare RLOS if the signal is attenuated by an additional -9dB. The total cable loss at RLOS declaration is typically -52dB (-43dB + -9dB). A 3dB hysteresis was designed so 29 xr XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 that transients will not trigger the RLOS to clear. Therefore, the RLOS will typically clear at a total cable attenuation of -49dB. See Figure 9 for a simplified diagram. FIGURE 9. SIMPLIFIED DIAGRAM OF EXTENDED RLOS MODE (E1 ONLY) Norm alized up to +45dB Max -9dB Clear LOS +3dB Declare LOS Declare LOS +3dB Clear LOS -9dB Norm alized up to +45dB Max RECEIVE HDB3/B8ZS DECODER The Decoder function is available in both Hardware and Host modes on a per channel basis by controlling the TNEG_n/CODES_n pin or the CODES_n interface bit. The decoder function is only active in single-rail Mode. When selected, receive data in this mode will be decoded according to HDB3 rules for E1 and B8ZS for T1 systems. Bipolar violations that do not conform to the coding scheme will be reported as Line Code Violation at the RNEG_n/LCV_n pin of each channel. The length of the LCV pulse is one RCLK cycle for each code violation. In E1mode only, an excessive number of zeros in the receive data stream is also reported as an error at the same output pin. If AMI decoding is selected in single rail mode, every bipolar violation in the receive data stream will be reported as an error at the RNEG_n/LCV_n pin. RECOVERED CLOCK (RCLK) SAMPLING EDGE This feature is available in both Hardware and Host modes on a global basis. In Host mode, the sampling edge of RCLK output can be changed through the interface control bit RCLKE. If a “1” is written in the RCLKE interface bit, receive data output at RPOS_n/RDATA_n and RNEG_n/LCV_n are updated on the falling edge of RCLK for all eight channels. Writing a “0” to the RCLKE register, updates the receive data on the rising edge of RCLK. In Hardware mode the same feature is available under the control of the RCLKE pin. FIGURE 10. RECEIVE CLOCK AND OUTPUT DATA TIMING RCLKR RDY RCLK RPOS or RNEG RHO JITTER ATTENUATOR 30 RCLKF xr XRT83L34 REV. 1.0.1 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR To reduce phase and frequency jitter in the recovered clock, the jitter attenuator can be placed in the receive signal path. The jitter attenuator uses a data FIFO (First In First Out) with a programmable depth that can vary between 2x32 and 2x64. The jitter attenuator can also be placed in the transmit signal path or disabled altogether depending upon system requirements. The jitter attenuator, other than using the master clock as reference, requires no external components. With the jitter attenuator selected, the typical throughput delay from input to output is 16 bits for 32 bit FIFO size or 32 bits for 64 bit FIFO size. When the read and write pointers of the FIFO in the jitter attenuator are within two bits of over-flowing or under-flowing, the bandwidth of the jitter attenuator is widened to track the short term input jitter, thereby avoiding data corruption. When this situation occurs, the jitter attenuator will not attenuate input jitter until the read/write pointer's position is outside the two bits window. Under normal condition, the jitter transfer characteristic meets the narrow bandwidth requirement as specified in ITU- G.736, ITU- I.431 and AT&T Pub 62411 standards. In T1 mode the Jitter Attenuator Bandwidth is always set to 3Hz. In E1 mode, the bandwidth can be reduced through the JABW control signal. When JABW is set “High” the bandwidth of the jitter attenuator is reduced from 10Hz to 1.5Hz. Under this condition the FIFO length is automatically set to 64 bits and the 32 bits FIFO length will not be available in this mode. Jitter attenuator controls are available on a per channel basis in the Host mode and on a global basis in the Hardware mode. GAPPED CLOCK (JA MUST BE ENABLED IN THE TRANSMIT PATH) The XRT83L34 LIU is ideal for multiplexer or mapper applications where the network data crosses multiple timing domains. As the higher data rates are de-multiplexed down to T1 or E1 data, stuffing bits are removed which can leave gaps in the incoming data stream. If the jitter attenuator is enabled in the transmit path, the 32Bit or 64-Bit FIFO is used to smooth the gapped clock into a steady T1 or E1 output. The maximum gap width of the 8-Channel LIU is shown in Table 2. TABLE 2: MAXIMUM GAP WIDTH FOR MULTIPLEXER/MAPPER APPLICATIONS FIFO DEPTH MAXIMUM GAP WIDTH 32-Bit 20 UI 64-Bit 50 UI NOTE: If the LIU is used in a loop timing system, the jitter attenuator should be enabled in the receive path. 31 xr XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 ARBITRARY PULSE GENERATOR FOR T1 AND E1 The arbitrary pulse generator divides the pulse into eight individual segments. Each segment is set by a 7-Bit binary word by programming the appropriate channel register. This allows the system designer to set the overshoot, amplitude, and undershoot for a unique line build out. The MSB (bit 7) is a sign-bit. If the sign-bit is set to “1”, the segment will move in a positive direction relative to a flat line (zero) condition. If this sign-bit is set to “0”, the segment will move in a negative direction relative to a flat line condition. A pulse with numbered segments is shown in Figure 11. FIGURE 11. ARBITRARY PULSE SEGMENT ASSIGNMENT 1 2 3 Segment 1 2 3 4 5 6 7 8 4 Register 0xn8 0xn9 0xna 0xnb 0xnc 0xnd 0xne 0xnf 8 7 6 5 NOTE: By default, the arbitrary segments are programmed to 0x00h. The transmitter outputs will result in an all zero pattern to the line. TRANSMITTER DIGITAL DATA FORMAT Both the transmitter and receiver can be configured to operate in dual or single-rail data formats. This feature is available under both Hardware and Host control modes, on a global basis. The dual or single-rail data format is determined by the state of the SR/DR pin in Hardware mode or SR/DR interface bit in the Host mode. In single-rail mode, transmit clock and NRZ data are applied to TCLK_n and TPOS_n/TDATA_n pins respectively. In single-rail and Hardware mode the TNEG_n/CODES_n input can be used as the CODES function. With TNEG_n/CODES_n tied “Low”, HDB3 or B8ZS encoding and decoding are enabled for E1 and T1 modes respectively. With TNEG_n/CODES_n tied “High”, the AMI coding scheme is selected. In both dual or singlerail modes of operations, the transmitter converts digital input data to a bipolar format before being transmitted to the line. TRANSMIT CLOCK (TCLK) SAMPLING EDGE Serial transmit data at TPOS_n/TDATA_n and TNEG_n/CODES_n are clocked into the XRT83L34 under the synchronization of TCLK_n. With a “0” written to the TCLKE interface bit, or by pulling the TCLKE pin “Low”, input data is sampled on the falling edge of TCLK_n. The sampling edge is inverted with a “1” written to TCLKE interface bit, or by connecting the TCLKE pin “High”. 32 xr XRT83L34 REV. 1.0.1 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR FIGURE 12. TRANSMIT CLOCK AND INPUT DATA TIMING TCLKR TCLKF TCLK TPOS/TDATA or TNEG THO TSU TRANSMIT HDB3/B8ZS ENCODER The Encoder function is available in both Hardware and Host modes on a per channel basis by controlling the TNEG_n/CODES_n pin or CODES interface bit. The encoder is only available in single-rail mode. In E1 mode and with HDB3 encoding selected, any sequence with four or more consecutive zeros in the input serial data from TPOS_n/TDATA_n, will be removed and replaced with 000V or B00V, where “B” indicates a pulse conforming with the bipolar rule and “V” representing a pulse violating the rule. An example of HDB3 Encoding is shown in Table 3. In a T1 system, an input data sequence with eight or more consecutive zeros will be removed and replaced using the B8ZS encoding rule. An example of Bipolar with 8 Zero Substitution (B8ZS) encoding scheme is shown in Table 4. Writing a “1” into the CODES_n interface bit or connecting the TNEG_n/ CODES_n pin to a “High” level selects the AMI coding for both E1 or T1 systems. TABLE 3: EXAMPLES OF HDB3 ENCODING NUMBER OF PULSE BEFORE NEXT 4 ZEROS Input NEXT 4 BITS 0000 HDB3 (case1) odd 000V HDB3 (case2) even B00V TABLE 4: EXAMPLES OF B8ZS ENCODING CASE 1 PRECEDING PULSE NEXT 8 BITS Input + 00000000 B8ZS AMI Output 000VB0VB + 000+ -0- + - 00000000 CASE 2 Input B8ZS AMI Output 000VB0VB - DRIVER FAILURE MONITOR (DMO) 33 000- +0+ - xr XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 The driver monitor circuit is used to detect transmit driver failure by monitoring the activities at TTIP and TRING outputs. Driver failure may be caused by a short circuit in the primary transformer or system problems at the transmit input. If the transmitter of a channel has no output for more than 128 clock cycles, the corresponding DMO pin goes “High” and remains “High” until a valid transmit pulse is detected. In Host mode, the failure of the transmit channel is reported in the corresponding interface bit. If the DMOIE bit is also enabled, any transition on the DMO interface bit will generate an interrupt. The driver failure monitor is supported in both Hardware and Host modes on a per channel basis. TRANSMIT PULSE SHAPER & LINE BUILD OUT (LBO) CIRCUIT The transmit pulse shaper circuit uses the high speed clock from the Master timing generator to control the shape and width of the transmitted pulse. The internal high-speed timing generator eliminates the need for a tightly controlled transmit clock (TCLK) duty cycle. With the jitter attenuator not in the transmit path, the transmit output will generate no more than 0.025Unit Interval (UI) peak-to-peak jitter. In Hardware mode, the state of the A[4:0]/EQC[4:0] pins determine the transmit pulse shape for all eight channels. In Host mode transmit pulse shape can be controlled on a per channel basis using the interface bits EQC[4:0]. The chip supports five fixed transmit pulse settings for T1 Short-haul applications plus a fully programmable waveform generator for arbitrary transmit output pulse shapes. Transmit Line Build-Outs for T1 long-haul application are supported from 0dB to -22.5dB in three 7.5dB steps. The choice of the transmit pulse shape and LBO under the control of the interface bits are summarized in Table 5. For CSU LBO transmit pulse design information, refer to ANSI T1.403-1993 Network-to-Customer Installation specification, Annex-E. NOTE: EQC[4:0] determine the T1/E1 operating mode of the XRT83L34. When EQC4 = “1” and EQC3 = “1”, the XRT83L34 is in the E1 mode, otherwise it is in the T1/J1 mode. TABLE 5: RECEIVE EQUALIZER CONTROL AND TRANSMIT LINE BUILD-OUT SETTINGS EQC4 EQC3 EQC2 EQC1 EQC0 E1/T1 MODE & RECEIVE SENSITIVITY TRANSMIT LBO CABLE CODING 0 0 0 0 0 T1 Long Haul/36dB 0dB 100Ω/ TP B8ZS 0 0 0 0 1 T1 Long Haul/36dB -7.5dB 100Ω/ TP B8ZS 0 0 0 1 0 T1 Long Haul/36dB -15dB 100Ω/ TP B8ZS 0 0 0 1 1 T1 Long Haul/36dB -22.5dB 100Ω/ TP B8ZS 0 0 1 0 0 T1 Long Haul/45dB 0dB 100Ω/ TP B8ZS 0 0 1 0 1 T1 Long Haul/45dB -7.5dB 100Ω/ TP B8ZS 0 0 1 1 0 T1 Long Haul/45dB -15dB 100Ω/ TP B8ZS 0 0 1 1 1 T1 Long Haul/45dB -22.5dB 100Ω/ TP B8ZS 0 1 0 0 0 T1 Short Haul/15dB 0-133 ft./ 0.6dB 100Ω/ TP B8ZS 0 1 0 0 1 T1 Short Haul/15dB 133-266 ft./ 1.2dB 100Ω/ TP B8ZS 0 1 0 1 0 T1 Short Haul/15dB 266-399 ft./ 1.8dB 100Ω/ TP B8ZS 0 1 0 1 1 T1 Short Haul/15dB 399-533 ft./ 2.4dB 100Ω/ TP B8ZS 0 1 1 0 0 T1 Short Haul/15dB 533-655 ft./ 3.0dB 100Ω/ TP B8ZS 0 1 1 0 1 T1 Short Haul/15dB Arbitrary Pulse 100Ω/ TP B8ZS 34 xr XRT83L34 REV. 1.0.1 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR TABLE 5: RECEIVE EQUALIZER CONTROL AND TRANSMIT LINE BUILD-OUT SETTINGS EQC4 EQC3 EQC2 EQC1 EQC0 E1/T1 MODE & RECEIVE SENSITIVITY 0 1 1 1 0 T1 Gain Mode/29dB 0 1 1 1 1 1 0 0 0 1 0 0 1 0 1 CABLE CODING 0-133 ft./ 0.6dB 100Ω/ TP B8ZS T1 Gain Mode/29dB 133-266 ft./ 1.2dB 100Ω/ TP B8ZS 0 T1 Gain Mode/29dB 266-399 ft./ 1.8dB 100Ω/ TP B8ZS 0 1 T1 Gain Mode/29dB 399-533 ft./ 2.4dB 100Ω/ TP B8ZS 0 1 0 T1 Gain Mode/29dB 533-655 ft./ 3.0dB 100Ω/ TP B8ZS 0 0 1 1 T1 Gain Mode/29dB Arbitrary Pulse 100Ω/ TP B8ZS 1 0 1 0 0 T1 Gain Mode/29dB 0dB 100Ω/ TP B8ZS 1 0 1 0 1 T1 Gain Mode/29dB -7.5dB 100Ω/ TP B8ZS 1 0 1 1 0 T1 Gain Mode/29dB -15dB 100Ω/ TP B8ZS 1 0 1 1 1 T1 Gain Mode/29dB -22.5dB 100Ω/ TP B8ZS 1 1 0 0 0 E1 Long Haul/36dB ITU G.703 75Ω Coax HDB3 1 1 0 0 1 E1 Long Haul/36dB ITU G.703 120Ω TP HDB3 1 1 0 1 0 E1 Long Haul/43dB ITU G.703 75Ω Coax HDB3 1 1 0 1 1 E1 Long Haul/43dB ITU G.703 120Ω TP HDB3 1 1 1 0 0 E1 Short Haul ITU G.703 75Ω Coax HDB3 1 1 1 0 1 E1 Short Haul ITU G.703 120Ω TP HDB3 1 1 1 1 0 E1 Gain Mode ITU G.703 75Ω Coax HDB3 1 1 1 1 1 E1 Gain Mode ITU G.703 120Ω TP HDB3 35 TRANSMIT LBO xr XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 TRANSMIT AND RECEIVE TERMINATIONS The XRT83L34 is a versatile LIU that can be programmed to use one Bill of Materials (BOM) for worldwide applications for T1, J1 and E1. For specific applications the internal terminations can be disabled to allow the use of existing components and/or designs. RECEIVER (CHANNELS 0 - 3) INTERNAL RECEIVE TERMINATION MODE In Hardware mode, RXTSEL (Pin 83) can be tied “High” to select internal termination mode for all receive channels or tied “Low” to select external termination mode. Individual channel control can only be done in Host mode. By default the XRT83L34 is set for external termination mode at power up or at Hardware reset. TABLE 6: RECEIVE TERMINATION CONTROL RXTSEL RX TERMINATION 0 EXTERNAL 1 INTERNAL In Host mode, bit 7 in the appropriate channel register, (Table 21, “Microprocessor Register #1, Bit Description,” on page 64), is set “High” to select the internal termination mode for that specific receive channel. FIGURE 13. SIMPLIFIED DIAGRAM FOR THE INTERNAL RECEIVE AND TRANSMIT TERMINATION MODE Channel _n TTIP TPO S 1 R int T1 5 0.68 µ F TTIP TNEG TCLK 75 Ω , 100 Ω TX Line Driver 110 Ω or 120 Ω TRING TRING 4 8 1:2 R int RTIP RPO S 5 T2 1 RNEG RCLK RX Equalizer RTIP 75 Ω , 100 Ω R int 110 Ω or 120 Ω RRING 8 4 1:1 RRING If the internal termination mode (RXTSEL = “1”) is selected, the effective impedance for E1, T1 or J1 can be achieved either with an internal resistor or a combination of internal and external resistors as shown in Table 7. NOTE: In Hardware mode, pins RXRES[1:0] control all channels. 36 xr XRT83L34 REV. 1.0.1 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR TABLE 7: RECEIVE TERMINATIONS RXTSEL TERSEL1 TERSEL0 RXRES1 RXRES0 Rext Rint MODE 0 x x x x Rext ∞ T1/E1/J1 1 0 0 0 0 ∞ 100Ω T1 1 0 1 0 0 ∞ 110Ω J1 1 1 0 0 0 ∞ 75Ω E1 1 1 1 0 0 ∞ 120Ω E1 1 0 0 0 1 240Ω 172Ω T1 1 0 1 0 1 240Ω 204Ω J1 1 1 0 0 1 240Ω 108Ω E1 1 1 1 0 1 240Ω 240Ω E1 1 0 0 1 0 210Ω 192Ω T1 1 0 1 1 0 210Ω 232Ω J1 1 1 0 1 0 210Ω 116Ω E1 1 1 1 1 0 210Ω 280Ω E1 1 0 0 1 1 150Ω 300Ω T1 1 0 1 1 1 150Ω 412Ω J1 1 1 0 1 1 150Ω 150Ω E1 1 1 1 1 1 150Ω 600Ω E1 Figure 14 is a simplified diagram for T1 (100Ω) in the external receive termination mode. Figure 15 is a simplified diagram for E1 (75Ω) in the external receive termination mode. FIGURE 14. SIMPLIFIED DIAGRAM FOR T1 IN THE EXTERNAL TERMINATION MODE (RXTSEL= 0) X R T 8 3 L 3 4 L IU 3 .1 Ω 1 :2 .4 5 T T IP 100Ω 3 .1 Ω T R IN G R T IP 100Ω 100Ω R R IN G 1 :1 37 xr XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 FIGURE 15. SIMPLIFIED DIAGRAM FOR E1 IN EXTERNAL TERMINATION MODE (RXTSEL= 0) X R T 8 3 L 3 4 L IU 9 .1 Ω 1 :2 .4 5 T T IP 75Ω 9 .1 Ω T R IN G R T IP 75Ω 75Ω R R IN G 1 :1 TRANSMITTER (CHANNELS 0 - 3) TRANSMIT TERMINATION MODE In Hardware mode, TXTSEL (Pin 84) can be tied “High” to select internal termination mode for all transmit channels or tied “Low” for external termination. Individual channel control can be done only in Host mode. In Host mode, bit 6 in the appropriate register for a given channel is set “High” to select the internal termination mode for that specific transmit channel, see Table 21, “Microprocessor Register #1, Bit Description,” on page 64. TABLE 8: TRANSMIT TERMINATION CONTROL TXTSEL TX TERMINATION TX TRANSFORMER RATIO 0 EXTERNAL 1:2.45 1 INTERNAL 1:2 For internal termination, the transformer turns ratio is always 1:2. In internal mode, no external resistors are used. An external capacitor of 0.68µF is used for proper operation of the internal termination circuitry, see Figure 13. TABLE 9: TERMINATION SELECT CONTROL TERSEL1 TERSEL0 TERMINATION 0 0 100Ω 0 1 110Ω 1 0 75Ω 1 1 120Ω EXTERNAL TRANSMIT TERMINATION MODE By default the XRT83L34 is set for external termination mode at power up or at Hardware reset. When external transmit termination mode is selected, the internal termination circuitry is disabled. The value of the external resistors is chosen for a specific application according to the turns ratio selected by TRATIO (Pin 127) in Hardware mode or bit 0 in the appropriate register for a specific channel in Host mode, see Table 10 and Table 23, “Microprocessor Register #3, Bit Description,” on page 68. Figure 14 is a simplified block diagram for T1 (100Ω) in the external termination mode. Figure 15 is a simplified block diagram for E1 (75Ω) in the external termination mode. 38 xr XRT83L34 REV. 1.0.1 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR TABLE 10: TRANSMIT TERMINATION CONTROL TRATIO TURNS RATIO 0 1:2 1 1:2.45 Table 11 summarizes the transmit terminations. TABLE 11: TRANSMIT TERMINATIONS TERSEL1 TERSEL0 TXTSEL TRATIO 0=EXTERNAL Rint Ω SET BY CONTROL 1=INTERNAL T1 100 Ω J1 110 Ω E1 75 Ω E1 120 Ω n Rext Ω Cext n, Rext, AND Cext ARE SUGGESTED SETTINGS BITS 0 0 0 0 0Ω 2.45 3.1Ω 0 0 0 0 1 0Ω 2 3.1Ω 0 0 0 1 x 12.5Ω 2 0Ω 0.68µF 0 1 0 0 0Ω 2.45 3.1Ω 0 0 1 0 1 0Ω 2 3.1Ω 0 0 1 1 x 13.75Ω 2 0Ω 0.68µF 1 0 0 0 0Ω 2.45 6.2Ω 0 1 0 0 1 0Ω 2 9.1Ω 0 1 0 1 x 9.4Ω 2 0Ω 0.68µF 1 1 0 0 0Ω 2.45 6.2Ω 0 1 1 0 1 0Ω 2 9.1Ω 0 1 1 1 x 15Ω 2 0Ω 0.68µF REDUNDANCY APPLICATIONS Telecommunication system design requires signal integrity and reliability. When a T1/E1 primary line card has a failure, it must be swapped with a backup line card while maintaining connectivity to a backplane without losing data. System designers can achieve this by implementing common redundancy schemes with the XRT83L34 Line Interface Unit (LIU). The XRT83L34 offers features that are tailored to redundancy applications while reducing the number of components and providing system designers with solid reference designs. These features allow system designers to implement redundancy applications that ensure reliability. The Internal Impedance mode eliminates the need for external relays when using the 1:1 and 1+1 redundancy schemes. 39 xr XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 PROGRAMMING CONSIDERATIONS In many applications switching the control of the transmitter outputs and the receiver line impedance to hardware control will provide faster transmitter ON/OFF switching. In Host Mode, there are two bits in register 130 (82H) that control the transmitter outputs and the Rx line impedance select, TXONCNTL (Bit 7) and TERCNTL (Bit 6). Setting bit-7 (TXONCNTL) to a “1” transfers the control of the Transmit On/Off function to the TXON_n Hardware control pins. (Pins 90 through 93 and pins 169 through 172). Setting bit-6 (TERCNTL) to a “1” transfers the control of the Rx line impedance select (RXTSEL) to the RXTSEL Hardware control pin (pin 83). Either mode works well with redundancy applications. The user can determine which mode has the fastest switching time for a unique application. TYPICAL REDUNDANCY SCHEMES n n n ·1:1 One backup card for every primary card (Facility Protection) ·1+1 One backup card for every primary card (Line Protection) ·N+1One backup card for N primary cards 1:1 REDUNDANCY A 1:1 facility protection redundancy scheme has one backup card for every primary card. When using 1:1 redundancy, the backup card has its transmitters tri-stated and its receivers in high impedance. This eliminates the need for external relays and provides one bill of materials for all interface modes of operation. The transmit and receive sections of the LIU device are described separately. 1+1 REDUNDANCY A 1+1 line protection redundancy scheme has one backup card for every primary card, and the receivers on the backup card are monitoring the receiver inputs. Therefore, the receivers on both cards need to be active. The transmit outputs require no external resistors. The transmit and receive sections of the LIU device are described separately. TRANSMIT 1:1 & 1+1 REDUNDANCY For 1:1 and 1+1 redundancy, the transmitters on the primary and backup card should be programmed for Internal Impedance mode. The transmitters on the backup card should be tri-stated. Select the appropriate impedance for the desired mode of operation, T1/E1/J1. A 0.68uF capacitor is used in series with TTIP for blocking DC bias. See Figure 16 for a simplified block diagram of the transmit section for 1:1 and 1+1 redundancy scheme. NOTE: For simplification, the over voltage protection circuitry was omitted. 40 xr XRT83L34 REV. 1.0.1 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR FIGURE 16. SIMPLIFIED BLOCK DIAGRAM OF THE TRANSMIT SECTION FOR 1:1 & 1+1 REDUNDANCY B ackplane Interface Line Interface C ard P rim ary C ard X R T83L34 1:2 or 1:2.45 0.68 µ F Tx T1/E 1 Line T xT SEL=1, In ternal B ackup C ard X R T83L34 0.68 µ F Tx T xT SEL=1, In ternal RECEIVE 1:1 & 1+1 REDUNDANCY For 1:1 and 1+1 redundancy, the receivers on the primary card should be programmed for Internal Impedance mode. The receivers on the backup card should be programmed for External Impedance mode. Since there is no external resistor in the circuit, the receivers on the backup card will be high impedance. This key design feature eliminates the need for relays and provides one bill of materials for all interface modes of operation. Select the impedance for the desired mode of operation, T1/E1/J1. To swap the primary card, set the backup card to Internal Impedance mode, then the primary card to External Impedance mode. See Figure 17 for a simplified block diagram of the receive section for a 1:1 and 1+1 redundancy scheme. NOTE: For simplification, the over voltage protection circuitry was omitted. FIGURE 17. SIMPLIFIED BLOCK DIAGRAM - RECEIVE SECTION FOR 1:1 AND 1+1 REDUNDANCY B ackplane Interface P rim ary C ard Line Interface C ard X R T83L34 1:1 Rx T1/E 1 Line R xT SEL=1, Internal B ackup C ard X R T83L34 Rx R xT SEL=0, E xternal N+1 REDUNDANCY 41 xr XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 N+1 redundancy has one backup card for N primary cards. Due to impedance mismatch and signal contention, external relays are necessary when using this redundancy scheme. The advantage of relays is that they create complete isolation between the primary cards and the backup card. This allows all transmitters and receivers on the primary cards to be configured in internal impedance mode, providing one bill of materials for all interface modes of operation. The transmit and receive sections of the XRT83L34 are described separately. TRANSMIT For N+1 redundancy, the transmitters on all cards should be programmed for internal impedance mode providing one bill of materials for T1/E1/J1. The transmitters on the backup card do not have to be tri-stated. To swap the primary card, close the desired relays, and tri-state the transmitters on the failed primary card. A 0.68µF capacitor is used in series with TTIP for blocking DC bias. See Figure 18 for a simplified block diagram of the transmit section for an N+1 redundancy scheme. NOTE: For simplification, the over voltage protection circuitry was omitted. FIGURE 18. SIMPLIFIED BLOCK DIAGRAM - TRANSMIT SECTION FOR N+1 REDUNDANCY Backplane Interface Line Interface C ard P rim ary C ard X R T83L4 1:2 or 1:2.45 Tx 0.68 µ F T1/E1 Line T xT S EL =1, Internal Prim ary C ard XR T83L34 1:2 or 1:2.45 Tx 0.68 µ F T1/E 1 Line T xT S EL =1, Internal P rim ary C ard X R T83L34 1:2 or 1:2.45 Tx 0.68 µ F T1/E 1 Line T xT S EL =1, Internal B ackup C ard X R T83L34 Tx 0.68 µ F T xT S EL=1, Inte rnal 42 xr XRT83L34 REV. 1.0.1 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR RECEIVE For N+1 redundancy, the receivers on the primary cards should be programmed for internal impedance mode. The receivers on the backup card should be programmed for external impedance mode. Since there is no external resistor in the circuit, the receivers on the backup card will be high impedance. Select the impedance for the desired mode of operation, T1/E1/J1. To swap the primary card, set the backup card to internal impedance mode, then the primary card to external impedance mode. See Figure 19. for a simplified block diagram of the receive section for a N+1 redundancy scheme. NOTE: For simplification, the over voltage protection circuitry was omitted. FIGURE 19. SIMPLIFIED BLOCK DIAGRAM - RECEIVE SECTION FOR N+1 REDUNDANCY B ackp lane Interface P rim ary C ard Line Interface C ard X R T83L34 1:1 Rx T1/E 1 Line R xT S EL=1, Internal P rim ary C ard X R T83L34 1:1 Rx T1/E 1 Line R xT S EL=1, Internal P rim ary C ard X R T83L34 1:1 T1/E 1 Line Rx R xT S EL=1, Internal B a ckup C ard X R T83L34 Rx R xT S EL=1, External 43 xr XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 PATTERN TRANSMIT AND DETECT FUNCTION Several test and diagnostic patterns can be generated and detected by the chip. In Hardware mode each channel can be independently programmed to transmit an All Ones pattern by applying a “High” level to the corresponding TAOS_n pin. In Host mode, the three interface bits TXTEST[2:0] control the pattern generation and detection independently for each channel according to Table 12. TABLE 12: PATTERN TRANSMISSION CONTROL TXTEST2 TXTEST1 TXTEST0 TEST PATTERN 0 x x None 1 0 0 TDQRSS 1 0 1 TAOS 1 1 0 TLUC 1 1 1 TLDC TRANSMIT ALL ONES (TAOS) This feature is available in both Hardware and Host modes. With the TAOS_n pin connected to a “High” level or when interface bits TXTEST2=“1”, TXTEST1=“0” and TXTEST0=“1” the transmitter ignores input from TPOS_n/TDATA_n and TNEG_n/CODES_n pins and sends a continuous AMI encoded all “Ones” signal to the line, using TCLK_n clock as the reference. In addition, when the Hardware pin and interface bit ATAOS is activated, the chip will automatically transmit the All “Ones” data from any channel that detects an RLOS condition. This feature is not available on a per channel basis. TCLK_n must NOT be tied “Low”. NETWORK LOOP CODE DETECTION AND TRANSMISSION This feature is available in Host mode only. When the interface bits TXTEST2=”1”, TXTEST1=”1” and TXTEST0=”0” the chip is enabled to transmit the “00001” Network Loop-Up Code from the selected channel requesting a Loop-Back condition from the remote terminal. Simultaneously setting the interface bits NLCDE1=”0” and NLCDE0=”1” enables the Network Loop-Up code detection in the receiver. If the “00001” Network Loop-Up code is detected in the receive data for longer than 5 seconds, the NLCD bit in the interface register is set indicating that the remote terminal has activated remote Loop-Back and the chip is receiving its own transmitted data. When the interface bits TXTEST2=”1”, TXTEST1=”1” and TXTEST0=”1” the chip is enabled to transmit the Network Loop-Down Code (TLDC) “001” from the selected channel requesting the remote terminal the removal of the Loop-Back condition. In the Host mode each channel is capable of monitoring the contents of the receive data for the presence of Loop-Up or Loop-Down code from the remote terminal. In the Host mode the two interface bits NLCDE[1:0] control the Loop-Code detection independently for each channel according to Table 13. TABLE 13: LOOP-CODE DETECTION CONTROL NLCDE1 NLCDE0 CONDITION 0 0 Disable Loop-Code Detection 0 1 Detect Loop-Up Code in Receive Data 1 0 Detect Loop-Down Code in Receive Data 1 1 Automatic Loop-Code detection and Remote Loop-Back Activation Setting the interface bits to NLCDE1=”0” and NLCDE0=”1” activates the detection of the Loop-Up code in the receive data. If the “00001” Network Loop-Up code is detected in the receive data for longer than 5 seconds, the NLCD interface bit is set to “1” and stays in this state for as long as the receiver continues to receive the Network Loop-Up Code. In this mode if the NLCD interrupt is enabled, the chip will initiate an interrupt on every 44 xr XRT83L34 REV. 1.0.1 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR transition of NLCD. The host has the option to ignore the request from the remote terminal, or to respond to the request and manually activate Remote Loop-Back. The host can subsequently activate the detection of the Loop-Down Code by setting NLCDE1=”1” and NLCDE0=”0”. In this case, receiving the “001” Loop-Down Code for longer than 5 seconds will set the NLCD bit to “1” and if the NLCD interrupt is enabled, the chip will initiate an interrupt on every transition of NLCD. The host can respond to the request from the remote terminal and remove Loop-Back condition. In the manual Network Loop-Up (NLCDE1=”0” and NLCDE0=”1”) and LoopDown (NLCDE1=”1” and NLCDE0=”0”) Code detection modes, the NLCD interface bit will be set to “1” upon receiving the corresponding code in excess of 5 seconds in the receive data. The chip will initiate an interrupt any time the status of the NLCD bit changes and the Network Loop-code interrupt is enabled. In the Host mode, setting the interface bits NLCDE1=”1” and NLCDE0=”1” enables the automatic Loop-Code detection and Remote Loop-Back activation mode if, TXTEST[2:0] is NOT equal to “110”. As this mode is initiated, the state of the NLCD interface bit is reset to “0” and the chip is programmed to monitor the receive input data for the Loop-Up Code. If the “00001” Network Loop-Up Code is detected in the receive data for longer than 5 seconds in addition to the NLCD bit in the interface register being set, Remote Loop-Back is automatically activated. The chip stays in remote Loop-Back even if it stops receiving the “00001” pattern. After the chip detects the Loop-Up code, sets the NLCD bit and enters Remote Loop-Back, it automatically starts monitoring the receive data for the Loop-Down code. In this mode however, the NLCD bit stays set even if the receiver stops receiving the Loop-Up code, which is an indication to the host that the Remote Loop-Back is still in effect. Remote Loop-Back is removed if the chip detects the “001” Loop-Down code for longer than 5 seconds. Detecting the “001” code also results in resetting the NLCD interface bit and initiating an interrupt. The Remote Loop-Back can also be removed by taking the chip out of the Automatic detection mode by programming it to operate in a different state. The chip will not respond to remote Loop-Back request if Local Analog Loop-Back is activated locally. When programmed in Automatic detection mode the NLCD interface bit stays “High” for the whole time the Remote Loop-Back is activated and initiates an interrupt any time the status of the NLCD bit changes provided the Network Loop-code interrupt is enabled. TRANSMIT AND DETECT QUASI-RANDOM SIGNAL SOURCE (TDQRSS) Each channel of XRT83L34 includes a QRSS pattern generation and detection block for diagnostic purposes that can be activated only in the Host mode by setting the interface bits TXTEST2=”1”, TXTEST1=”0” and TXTEST0=”0”. For T1 systems, the QRSS pattern is a 220-1pseudo-random bit sequence (PRBS) with no more than 14 consecutive zeros. For E1 systems, the QRSS pattern is 215 -1 PRBS with an inverted output. With QRSS and Analog Local Loop-Back enabled simultaneously, and by monitoring the status of the QRPD interface bit, all main functional blocks within the transceiver can be verified. When the receiver achieves QRSS synchronization with fewer than 4 errors in a 128 bits window, QRPD changes from “Low” to “High”. After pattern synchronization, any bit error will cause QRPD to go “Low” for one clock cycle. If the QRPDIE bit is enabled, any transition on the QRPD bit will generate an interrupt. With TDQRSS activated, a bit error can be inserted in the transmitted QRSS pattern by transitioning the INSBER interface bit from “0” to “1”. Bipolar violation can also be inserted either in the QRSS pattern, or input data when operating in the single-rail mode by transitioning the INSBPV interface bit from “0” to “1”. The state of INSBER and INSBPV bits are sampled on the rising edge of the TCLK_n. To insure the insertion of the bit error or bipolar violation, a “0” should be written in these bit locations before writing a “1”. 45 xr XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 LOOP-BACK MODES The XRT83L34 supports several Loop-Back modes under both Hardware and Host control. In Hardware mode the two LOOP[1:0] pins control the Loop-Back functions for each channel independently according to Table 14. TABLE 14: LOOP-BACK CONTROL IN HARDWARE MODE LOOP1 LOOP0 LOOP-BACK MODE 0 0 None 0 1 Analog 1 0 Remote 1 1 Digital In Host mode the Loop-Back functions are controlled by the three LOOP[2:0] interface bits. Each channel can be programmed independently according to Table 15. TABLE 15: LOOP-BACK CONTROL IN HOST MODE LOOP2 LOOP1 LOOP0 LOOP-BACK MODE 0 X X None 1 0 0 Dual 1 0 1 Analog 1 1 0 Remote 1 1 1 Digital LOCAL ANALOG LOOP-BACK (ALOOP) With Local Analog Loop-Back activated, the transmit data at TTIP and TRING are looped-back to the analog input of the receiver. External inputs at RTIP/RRING in this mode are ignored while valid transmit data continues to be sent to the line. Local Analog Loop-Back exercises most of the functional blocks of the XRT83L34 including the jitter attenuator which can be selected in either the transmit or receive paths. Local Analog Loop-Back is shown in Figure 20. FIGURE 20. LOCAL ANALOG LOOP-BACK SIGNAL FLOW TPOS TNEG Encoder TTIP Timing Control JA Tx TRING TCLK RCLK RPOS Decoder Data & Clock Recovery RNEG Rx RTIP RRING In this mode, the jitter attenuator (if selected) can be placed in the transmit or receive path. 46 xr XRT83L34 REV. 1.0.1 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REMOTE LOOP-BACK (RLOOP) With Remote Loop-Back activated, receive data after the jitter attenuator (if selected in the receive path) is looped back to the transmit path using RCLK as transmit timing. In this mode transmit clock and data are ignored, while RCLK and receive data will continue to be available at their respective output pins. Remote Loop-Back with jitter attenuator selected in the receive path is shown in Figure 21. FIGURE 21. REMOTE LOOP-BACK MODE WITH JITTER ATTENUATOR SELECTED IN RECEIVE PATH TPOS TNEG Timing Control Encoder TTIP Tx TRING TCLK RCLK RPOS Decoder Data & Clock Recovery JA RTIP Rx RRING RNEG In the Remote Loop-Back mode if the jitter attenuator is selected in the transmit path, the receive data from the Clock and Data Recovery block is looped back to the transmit path and is applied to the jitter attenuator using RCLK as transmit timing. In this mode the transmit clock and data are also ignored, while RCLK and received data will continue to be available at their respective output pins. Remote Loop-Back with the jitter attenuator selected in the transmit path is shown in Figure 22. FIGURE 22. REMOTE LOOP-BACK MODE WITH JITTER ATTENUATOR SELECTED IN TRANSMIT PATH TPOS TNEG Encoder Timing Control JA TTIP Tx TRING TCLK RCLK RPOS Clock & Data Recovery Decoder RNEG 47 RTIP Rx RRING xr XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 DIGITAL LOOP-BACK (DLOOP) Digital Loop-Back or Local Loop-Back allows the transmit clock and data to be looped back to the corresponding receiver output pins through the encoder/decoder and jitter attenuator. In this mode, receive data and clock are ignored, but the transmit data will be sent to the line uninterrupted. This loop back feature allows users to configure the line interface as a pure jitter attenuator. The Digital Loop-Back signal flow is shown in Figure 23. FIGURE 23. DIGITAL LOOP-BACK MODE WITH JITTER ATTENUATOR SELECTED IN TRANSMIT PATH TPOS TNEG Encoder Timing Control JA TTIP Tx TRING TCLK RCLK RPOS Data & Clock Recovery Decoder RTIP Rx RRING RNEG DUAL LOOP-BACK Figure 24 depicts the data flow in dual-loopback. In this mode, selecting the jitter attenuator in the transmit path will have the same result as placing the jitter attenuator in the receive path. In dual Loop-Back mode the recovered clock and data from the line are looped back through the transmitter to the TTIP and TRING without passing through the jitter attenuator. The transmit clock and data are looped back through the jitter attenuator to the RCLK and RPOS/RDATA and RNEG pins. FIGURE 24. SIGNAL FLOW IN DUAL LOOP-BACK MODE TPOS TNEG Timing Control Encoder TTIP Tx TRING TCLK JA RCLK RPOS Data & Clock Recovery Decoder RNEG 48 RTIP Rx RRING xr XRT83L34 REV. 1.0.1 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR THE MICROPROCESSOR INTERFACE XRT83L34 is equipped with a microprocessor interface for easy device configuration. The parallel port of the XRT83L34 is compatible with both the Intel-Asynchronous and the Motorola-Asynchronous address and data buses. The XRT83L34 has an 7-bit address A[6:0] input and 8-bit bi-directional data bus D[7:0]. THE PINS OF THE MICROPROCESSOR INTERFACE Table 16 presents a list and a brief description of each of the pins that make up the Microprocessor Interface block, within the XRT83L34 device. TABLE 16: MICROPROCESSOR INTERFACE SIGNAL DESCRIPTION D[7:0] Bi-Directional Data Bus pins: These pins are used to drive and receive data over the bi-directional data bus, whenever the Microprocessor performs READ or WRITE operations with the Microprocessor Interface of the XRT83L34 device. A[6:0] Address Bus Input pins: These input pins permit the Microprocessor to identify on-chip registers (within the XRT83L34 device) whenever it performs READ and WRITE operations with the XRT83L34 device. µPTS1 µPTS2 Microprocessor Type Select: µPTS2 µPTS1 µP Type 0 0 Intel Asynchronous Mode 0 1 Motorola Asynchronous Mode µPTS2 should be tied to GND. µPTS1 selects the microprocessor type. µPCLK Microprocessor Clock Input: This pin should be tied to GND for asychronous microprocessor interface. NOTE: This pin is internally pulled “Low” for asynchronous microprocessor operation when no clock is present. 49 xr XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 TABLE 16: MICROPROCESSOR INTERFACE SIGNAL DESCRIPTION ALE_AS Address Latch Enable/Address Strobe Input: The exact function of this input pin depends upon which mode the Microprocessor Interface has been configured to operate in, as described below. Intel-Asynchronous Mode - Address Latch Enable - ALE: If the Microprocessor Interface has been configured to operate in the Intel-Asynchronous Mode, then this active-high input pin is used to latch the data (residing on the Address Bus, A[6:0] into the Microprocessor Interface circuitry of the XRT83L34 device and to indicate the start of a READ or WRITE cycle. Pulling this input pin "high" enables the input bus drivers for the Address Bus input pins. The contents of the Address Bus will be latched into the Microprocessor Interface circuitry, upon the falling edge of this input signal. Motorola-Asynchronous Mode - Address Strobe - AS*: If the Microprocessor Interface has been configured to operate in the Motorola-Asynchronous Mode, then pulling this input pin "LOW enables the "input" bus drivers for the Address Bus Input pins. During each READ or WRITE operation, the user is expected to drive this input pin "LOW" after (or around the time that) he/she has places the address (of the "target" register) onto the Address Bus pins (A[6:0]). The user is then expected to hold this input pin "LOW" for the remainder of the READ or WRITE cycle. NOTE: It is permissible to tie the ALE_AS* and CS* input pins together.. Read and Write operations will be performed properly if ALE_AS is driven "LOW" coincident to whenever CS* is also driven "LOW". CS RD_DS Chip Select Input: The user must assert this active-low signal in order to select the Microprocessor Interface for READ and WRITE operations between the Microprocessor and the XRT83L34 on-chip registers. Read Strobe/Data Strobe Input Pin: The exact function of this input pin depends upon which mode the Microprocessor Interface has been configured to operate in, as described below. Intel-Asynchronous Mode - READ Strobe Input - RD*: If the Microprocessor Interface is operating in the Intel-Asynchronous Mode, then this input pin will function as the RD* (Active-Low READ Strobe) input signal from the Microprocessor. Once this active-low signal is asserted, then the XRT83L34 device will place the contents of the addressed register on the Microprocessor Interface Bi-Directional Data Bus (D[7:0]). When this signal is negated, then the Data Bus will be tri-stated. Motorola-Asynchronous Mode - Data Strobe Input - DS*: If the Microprocessor Interface is operating in the Motorola-Asynchronous Mode, then this input pin will function as the DS* (Data Strobe) input signal. . 50 xr XRT83L34 REV. 1.0.1 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR TABLE 16: MICROPROCESSOR INTERFACE SIGNAL DESCRIPTION WR_R/W Write Strobe/Read-Write Operation Identifier: The exact function of this input pin depends upon which mode the Microprocessor Interface has been configured to operate in, as described below. Intel-Asynchronous Mode - Write Strobe Input - WR*: If the Microprocessor Interface is configured to operate in the Intel-Asynchronous Mode, then this input pin functions as the WR* (Active-Low, Write Strobe) input signal form the Microprocessor. Once this active-low signal is asserted then the input buffers (associated with the Bi-Directional Data Bus pins, D[7:0]) will be enabled. The Microprocessor Interface will latch the contents of the Bi-Directional Data Bus (into the "target" register or address location, within the XRT83L34 device) upon the rising edge of this input pin. Motorola-Asynchronous Mode - Read/Write Operation Identification Input - R/W* If the Microprocessor Interface is operating in the "Motorola-Asynchronous" Mode, then this pin is functionally equivalent to the "R/W*" input pin. In the Motorola-Asynchoronous Mode, a READ operation occurs if this pin is held at a logic "1", coincident to a falling edge of the RD/DS* (Data Strobe) input pin. Similarly, a WRITE operation occurs if this pin is at a logic "0", coincident to a falling edge of the RD/DS* (Data Strobe) input pin. RDY_DTACK Ready or DTACK (Data Transfer Acknowledge) Output pin: The exact function of this output pin depends upon which mode the Microprocessor Interface has been configured to operate in, as described below. Intel-Asynchronous Mode - READY Output - RDY*: If the Microprocessor Interface has been configured to operate in the Intel-Asynchronous Mode, then this output pin will function as the "Active-low" READY Output: During a READ or WRITE cycle, the Microprocessor Interface block will toggle this output pin to the logic low level, ONLY when it (the Microprocessor Interface) is ready to complete or terminate the current READ or WRITE cycle. If (during a READ or WRITE cycle) the Microprocessor Interface block is holding this output pin at a logic "HIGH" level, then the Microprocessor is expected to extend this READ or WRITE cycle, until it detects this output pin being toggled to the logic "LOW" level. Motorola-Asynchronous Mode - Data Transfer Acknowledge Output - DTACK*: If the Microprocessor Interface has been configured to operate in the Motorola-Asynchronous Mode, then this output pin will function as the "active-low" DTACK output. During a READ or WRITE cycle, the Microprocessor Interface will toggle this output pin to the logic "LOW" level, ONLY when it (the Microprocessor Interface) is ready to complete or terminate the current READ or WRITE cycle. Once the Microprocessor has determined that this input pin has toggled to the logic "low" level, then it is now safe for it to move on and execute the next READ or WRITE cycle. If (during a READ or WRITE cycle) the Microprocessor Interface block is holding this output pin at a logic "HIGH" level, then the Microprocessor is expected to extend this READ or WRITE cycle, until it detects this output pin being toggled to the logic "LOW" level. INT Interrupt Output: This active-low output signal will be asserted (pulled to a logic "LOW" level) whenever the XRT83L34 device is requesting interrupt service from the Microprocessor. The activation of this pin can be blocked by setting the GIE bit to “0” in the Command Control register. 51 xr XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 OPERATING THE MICROPROCESSOR INTERFACE IN THE INTEL-ASYNCHRONOUS MODE If the Microprocessor Interface has been configured to operate in the Intel-Asynchronous Mode, then the following Microprocessor Interface pins will assume the role that is described below in Table 17. TABLE 17: THE ROLES OF THE VARIOUS MICROPROCESSOR INTERFACE PINS, WHEN CONFIGURED TO OPERATE IN THE INTEL-ASYNCHRONOUS MODE PIN NAME DESCRIPTION TYPE PIN/BALL ALE/AS Address Latch Enable - ALE: If the Microprocessor Interface has been configured to operate in the Intel-Asynchronous Mode, then this active-high input pin is used to latch the data (residing on the Address Bus, A[6:0]) into the MIcroprocessor Interface circuitry of the XRT83L34 device and to indicate the start of a READ or WRITE cycle. Pulling this input pin "HIGH" enables the input bus drivers for the Address Bus input pins. The contents of the Address Bus will be latched into the Microprocessor Interface circuitry upon the falling edge of this input signal. I 71 RD*/DS* Read Strobe Input - RD*: If the Microprocessor Interface is operating in the Intel-Asynchronous Mode, then this input pin will function as the RD* (Active-Low READ Strobe) input signal from the Microprocessor. Once this active-low signal is asserted, then the XRT83L34 device will place the contents of the addressed register on the Microprocessor Interface Bi-Directional Data Bus (D[7:0]). When this signal is negated, then the Bi-Directional Data Bus will be tri-stated. I 70 O 73 I 69 RDY_DTACK* Active Low READY Output pin - RDY: If the Microprocessor Interface has been configured to operate in the Intel-Asynchronous Mode, then this output pin will function as the "active-low" READY output. During a READ or WRITE cycle, the Microprocessor Interface block will toggle this output pin to the logic "LOW" level, ONLY when it (the Microprocessor Interface) is ready to complete or terminate the current READ or WRITE cycle. Once the Microprocessor has determined that this input pin has toggled to the logic "LOW" level, then it is now safe for it to move on and execute the next READ or WRITE cycle. If (during a READ or WRITE cycle) the Microprocessor Interface block is holding this output pin at a logic "HIGH" level, then the Microprocessor is expected to extend this READ or WRITE cycle, until it detects this output pin being toggled to the logic "LOW" level. WR*/R/W* Write Strobe Input - WR*: If the Microprocessor Interface is configured to operate in the IntelAsynchronous Mode, then this input pin functions as the WR* (Active LOW WRITE Strobe) input signal from the Microprocessor. Once this active-low signal is asserted, then the input buffers (associated with the Bi-Directional Data bus, D[7:0]) will be enabled. The Microprocessor Interface will latch the contents on the Bi-Directional Data Bus (into the "target" register or address location, within the XRT83L34 device) upon the rising edge of this input pin. 52 xr XRT83L34 REV. 1.0.1 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR CONFIGURING THE MICROPROCESSOR INTERFACE TO OPERATE IN THE INTEL-ASYNCHRONOUS MODE The user can configure the Microprocessor Interface to operate in the Intel-Asynchronous Mode by tying the UPTS1 (Pin 106) to GND. Finally, if the Microprocessor Interface has been configured to operate in the Intel-Asynchronous Mode, then it will perform READ and WRITE operations as described below. THE INTEL-ASYNCHRONOUS READ CYCLE If the Microprocessor Interface (of the XRT83L34 device) has been configured to operate in the IntelAsynchronous Mode, then the Microprocessor should do all of the following, anytime it wishes to read out the contents of a register. 1. Place the address of the "target" register (within the XRT83L34 device) on the Address Bus input pins, A[6:0]. 2. While the Microprocessor is placing this address value on the Address Bus, the Address Decoding circuitry (within the user’s system) should assert the CS* (Chip Select) input pin of the XRT83L34 device, by toggling it "LOW". This action enables further communication between the Microprocessor and the XRT83L34 Microprocessor Interface block 3. Toggle the ALE/AS (Address Latch Enable) input pin "HIGH". This step enables the "Address Bus" input drivers, within the Microprocessor Interface block of the XRT83L34 device. 4. After allowing the data on the Address Bus pins to settle (by waiting the appropriate "Address Data Setup time"), the Microprocessor should toggle the ALE/AS input pin "LOW". This step causes the XRT83L34 device to "latch" the contents of the "Address Bus" into its internal circuitry. At this point, the address of the register (within the XRT83L34 device) has now been selected. 5. Next, the Microprocessor should indicate that this current bus cycle is a "READ" operation by toggling the "RD*/DS*" (Read Strobe) input pin "LOW". This action also enable the bi-directional data bus output drivers of the XRT83L34 device. At this point, the "Bi-Directional" Data Bus output drivers will proceed to drive the contents of the "latched" addressed onto the bi-directional data bus, D[7:0]. 6. Immediately after the Microprocessor toggles the "Read Strobe" (RD*/DS*) signal "low", the XRT83L34 device will continue to drive the RDY*/DTACK* output pin "high". The XRT83L34 device does this in order to inform the Microprocessor that the data (to be read from the data bus) is "NOT READY" to be "latched" into the Microprocessor. In this case, the Microprocessor should continue to hold the "Read Strobe" (RD*/ DS*) signal "LOW" until it detects the "RDY*/DTACK*" output pin toggling "LOW". 7. After some settling time, the data on the "Bi-Directional" data bus will stabilize and can be read by the Microprocessor. At this time, the XRT83L34 device will indicate that this data can be read by toggling the RDY*/DTACK* (READY) signal "LOW". 8. After the Microprocessor detects the RDY*/DTACK* signal (from the XRT83L34 device) toggling "LOW", it can then terminate the READ cycle by toggling the RD*/DS* (READ Strobe) input pin "HIGH". Figure 25 presents a timing diagram that illustrates the behavior of the Microprocessor Interface signals, during an "Intel- 53 xr XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 Asynchronous" Mode Read Operation. FIGURE 25. ILLLUSTRATION OF AN INTEL-ASYNCHRONOUS MODE READ OPERATION Microprocessor places “target” Address value on A[6:0] Microprocessor Interface latches contents on A[6:0] upon falling edge of ALE ALE/AS A[6:0] Address of Target Register CS* D[7:0] Not Valid Valid Data RD*/DS* WR*/R/W* RDY/DTACK* Address Decoding Circuitry asserts CS* Read Operation begins Here RDY* toggles “low” to indicate that Valid data can be read from D[7:0] Read Operation is Terminated Here RDY* toggle “high” after Completion Of Read Operation THE INTEL-ASYNCHRONOUS WRITE CYCLE If the Microprocessor Interface (of the XRT83L34 device) has been configured to operate in the IntelAsynchronous Mode, then the Microprocessor should do all of the following anytime that it wishes to write a byte of data into a register within the XRT83L34 device. 1. Place the address of the "target" register (within the XRT83L34 device) on the Address Bus Input pins, A[6:0]. 2. While the Microprocessor is placing the address value on the Address bus, the Address Decoding circuitry (within the user’s system) should assert the CS* (Chip Select) input pin of the XRT83L34 device by toggling it "LOW". This action enables further communication between the Microprocessor and the XRT83L34 Microprocessor Interface. 3. Toggle the ALE/AS (Address Latch Enable) input pin "HIGH". This step enables the "Address Bus" input drivers, within the Microprocessor Interface block of the XRT83L34 device. 4. After allowing the data on the Address Bus pins to settle (by waiting the appropriate "Address Set-up" time) the Microprocessor should toggle the ALE/AS input pin "LOW". This step causes the XRT83L34 device to "latch" the contents of the "Address Bus" into its internal circuitry. At this point, the address of the register (within the XRT83L34 device) has now been selected. 5. Next, the Microprocessor should then place the byte that it intends to write into the "target" register (within the XRT83L34 device), on the Bi-Direction Data Bus pins (D[7:0]). 6. Afterwards, the Microprocessor should then indicate that this current bus cycle is a "Write" Operation; by toggling the WR*/R/W (Write Strobe) input pin "LOW". This active also enables the "Bi-Directional" Data Bus Input Drivers of the XRT83L34 device. At this point, the "Bi-Directional" data bus input drivers will proceed to drive the contents (currently residing on the Bi-Directional Data Bus into the register that corresponds with the "latched" address. 7. Immediately after the Microprocessor toggles the "Write Strobe" (WR*/R/W*) signal "LOW" the XRT83L34 device will continue to drive the "RDY*/DTACK*" output pin "high". The XRT83L34 device does this in order to inform the Microprocessor that the data (to be written into the "target" address location, within the XRT83L34 device) is "NOT READY" to be latched into the Microprocessor Interface block circuitry (within 54 xr XRT83L34 REV. 1.0.1 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR the XRT83L34 device). In this case, the Microprocessor should continue to hold the "Write Strobe" (WR*/ R/W*) input pin "LOW" until it detects the "RDY*/DTACK*" output pin toggling "HIGH". 8. After waiting the appropriate amount of time for the data (on the Bi-Directional Data Bus) to stabilize and can be safely accepted by the Microprocessor Interface block circuitry (within the XRT83L34 device); the XRT83L34 device will indicate that this data can be latched into the "target" address location by toggling the RDY*/DTACK* output pin "LOW". 9. After the Microprocessor detects the RDY*/DTACK* signal (from the XRT83L34 device) toggling "LOW", it can then terminate the WRITE cycle by toggling the WR*/R/W* (Write Strobe) input pin "HIGH". NOTE: Once the user toggles the "WR*/R/W* (Write Strobe) input pin "HIGH", then the Microprocessor Interface (of the XRT83L34 device) will latch the contents of the Bi-Directional Data Bus (D[7:0]) into the "target" address location o of the chip. Figure _ presents a timing diagram that illustrates the behavior of the Microprocessor Interface signals during an Intel-Asynchronous Mode Write Operation. FIGURE 26. ILLUSTRATION OF AN INTEL-ASYNCHRONOUS MODE WRITE OPERATION Microprocessor places “target” Address value on A[6:0] Microprocessor Interface latches contents on A[6:0] upon falling edge of ALE ALE/AS A[6:0] Address of Target Register CS* D[7:0] Data to be Written RD*/DS* WR*/R/W* RDY/DTACK* Address Decoding Circuitry asserts CS* Write Operation is Terminated Here Write Operation begins Here RDY* toggles “low” to indicate that Valid data can be latched into “target” Address location of chip RDY* toggles “high” after Completion Of Write Operation OPERATING THE MICROPROCESSOR INTERFACE IN THE MOTOROLA-ASYNCHRONOUS MODE If the Microprocessor Interface has been configured to operate in the Motorola-Asynchronous Mode, then the following Microprocessor Interface pins will assume the role that is described below in Table _. 55 xr XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 TABLE _, THE ROLES OF VARIOUS MICROPROCESSOR INTERFACE PINS, WHEN CONFIGURED TO OPERATE IN THE MOTOROLA-ASYNCHRONOUS MODE PIN NAME PIN NUMBER TYPE DESCRIPTION ALE/AS 71 I Address Strobe Input - AS*: If the Microprocessor Interface has been configured to operate in the Motorola-Asynchronous Mode, then pulling this input pin "LOW enables the "input" bus drivers for the Address Bus Input pins. During each READ or WRITE operation, the user is expected to drive this input pin "LOW" after (or around the time that) he/she has places the address (of the "target" register) onto the Address Bus pins (A[6:0]). The user is then expected to hold this input pin "LOW" for the remainder of the READ or WRITE cycle. NOTE: It is permissible to tie the ALE_AS* and CS* input pins together.. Read and Write operations will be performed properly if ALE_AS is driven "LOW" coincident to whenever CS* is also driven "LOW". RD*/DS* 70 I Data Strobe Input - RD*: If the MIcroprocessor Interface is operating in the Motorola-Asynchronous Mode, then this input pin will function as the DS* (Data Strobe) Input signal. RDY*/ DTACK 73 O Data Transfer Acknowledge Output - DTACK*: If the Microprocessor Interface has been configured to operate in the Motorola-Asynchronous Mode, then this output pin will function as the "active-low" DTACK Output. During a READ or WRITE cycle, the Microprocessor Interface block will toggle this output pin to the logic low level, ONLY when it (the Microprocessor Interface) is ready to complete or terminate the current READ or WRITE cycle. Once the Microprocessor has determined that this input pin has toggled to the logic "LOW" level, then it is now safe for it to move on and execute the next READ or WRITE cycle. If (during a READ or WRITE cycle) the Microprocessor Interface block is output pin at a logic "HIGH" level, then the Microprocessor is expected to extend this READ or WRITE cycle, until it detects this output pin being toggled to the logic "LOW" level. WR*/ R/W* 69 I Read/Write Operation Identification Input - R/W*: If the Microprocessor Interface is operating in the "Motorola-Asynchronous" Mode, then this pin is functionally equivalent to the R/W* input pin. In the Motorola Mode, a READ operation occurs if this pin is held at a logic "1" level, coincident to a falling edge of the RD/DS* (Data Strobe) input pin. Similarly, a WRITE operation occurs if this pin is at a logic "0" level, coincident to a falling edge of the RD/DS* (Data Strobe) input pin. 56 xr XRT83L34 REV. 1.0.1 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR CONFIGURING THE MICROPROCESSOR ASYNCHRONOUS MODE INTERFACE TO OPERATE IN THE MOTOROLA- The user can configure the Microprocessor Interface to operate in the Motorola-Asynchronous Mode by tying the UPTS1 (Pin 106) to the logic "HIGH" level. Finally, if the Microprocessor Interface has been configured to operate in the Motorola-Asynchronous Mode, then it will perform READ and WRITE operations as described below. THE MOTOROLA-ASYNCHRONOUS READ-CYCLE: If the Microprocessor Interface (of the XRT83L34 device) has been configured to operate in the MotorolaAsynchronous Mode, then the Microprocessor Interface should do all of the following, anytime it wishes to read out the contents of a register within the XRT83L34 device. 1. Place the address of the "target" register within the XRT83L34 device, on the Address Bus Input pins, A[6:0]. 2. While the Microprocessor is placing the address value on the Address Bus, the Address Decoding circuitry (within the user’s system) should assert the CS* (Chip Select input) pin of the XRT83L34 device, by toggling it "LOW". This action enables further communication between the MIcroprocessor and the XRT83L34 Microprocessor Interface block. 3. Assert the ALE/AS (Address Strobe) input pin by toggling it "LOW". This step enables the Address Bus input drivers, within the Microprocessor Interface block of the XRT83L34 device. 4. Afterwards, the Microprocessor should indicate that this cycle is a "READ" cycle by setting the WR*/R/W* (R/W*) input pin "HIGH". 5. Next, the Microprocessor should initiate the current bus cycle by toggling the RD*/DS* (Data Strobe) input pin "LOW". This step enables the bi-directional data bus output drivers, within the XRT83L34 device. At this point, the bi-directional data bus output drivers will proceed to drive the contents of the "Addressed" register onto the bi-directional data bus, D[7:0]. 6. Immediately after the Microprocessor toggles the "Data Strobe" (RD*/DS*) signal "LOW", the XRT83L34 device will continue to drive the RDY*/DTACK* output pin "HIGH". The XRT83L34 device does this in order to inform the Microprocessor that the data (to be read from the data bus) is "NOT READY" to be latched into the Microprocessor. In this case, the Microprocessor should continue to hold the "Data Strobe" (RD*/ DS*) signal "LOW" until it detects the "RDY*/DTACK*" output pin toggling "LOW". 7. After some settling time, the data on the "Bi-Directional" Data Bus will stabilize and can be read by the Microprocessor. The XRT83L34 device will indicate that this data can be read by asserting the RDY*/ DTACK* (DTACK) output signal (by toggling it "LOW"). 8. After the Microprocessor detects the RDY*/DTACK* signal (from the XRT83L34 device) toggling "LOW", it can now terminate the Ready Cycle by toggling the "RD*/DS*" (Data Strobe) input pin "HIGH". Figure _ presents a timing diagram that illustrates the behavior of the Microprocessor Interface signals during a "Motorola- 57 xr XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 Asynchronous" READ Operation. FIGURE 27. ILLLUSTRATION OF A MOTOROLA-ASYNCHRONOUS MODE READ OPERATION Microprocessor places “target” Address value on A[6:0] ALE/AS Address of Target Register A[6:0] CS* D[7:0] Not Valid Valid Data RD*/DS* WR*/R/W* RDY/DTACK* Address Decoding Circuitry asserts CS* Read Operation begins Here Microprocessor keeps R/W* “high” To denote READ Operation Read Operation is Terminated Here DTACK* toggles “low” to indicate That valid data can be read from D[7:0] THE MOTOROLA-ASYNCHRONOUS WRITE CYCLE If the Microprocessor Interface (of the XRT83L34 device) has been configured to operate in the MotorolaAsynchronous Mode, then the Microprocessor should do all of the following, anytime it wishes to write a byte of data into a register within the XRT83L34 device. 1. Place the address of the "target" register within the XRT83L34 device, on the Address Bus input pins, A[6:0]. 2. While the Microprocessor is placing the address value on the Address Bus, the Address Decoding circuitry (within the user’s system) should assert the CS* (Chip Select) input pin of the XRT83L34 device, by toggling it "LOW". This action enables further communication between the Microprocessor and the XRT83L34 Microprocessor Interface. 3. Assert the ALE/AS (Address Strobe) input pin by toggling it "LOW". This step enables the "Address Bus" input drivers, within the Microprocessor Interface block of the XRT83L34 device. 4. Afterwards, the Microprocessor Interface should indicate that this current bus cycle is a "WRITE" operation by toggling the WR*/R/W* (R/W*) input pin "LOW". 5. The Microprocessor should then place the byte or word that it intends to write into the "target" register, on the bi-direction data bus, D[7:0]. 6. Next, the Microprocessor should initiate the bus cycle by toggling the RD*/DS* (Data Strobe) input pin "LOW". When the XRT83L34 device senses that the WR/R/W* (R/W*) input pin is "HIGH" and that the RD*/DS* (Data Strobe) input pin has toggled "LOW", it will enable the "input drivers" of the bi-directional data bus, D[7:0]. 7. Immediately after the Microprocessor toggles the RD*/DS* (Data Strobe) signal "LOW", the XRT83L34 device will continue to drive the "RDY*/DTACK* output pin "HIGH". The XRT83L34 device does this in order to inform the Microprocessor that the data (to be written into the "target" address location, within the XRT83L34 device) is "NOT READY" to be latched into the Microprocessor Interface circuitry (within the XRT83L34 device). In this case, the Microprocessor should continue to hold the "Data Strobe" (RD*/DS*) input pin "LOW" until it detects the "RDY*/DTACK* output pin toggling "HIGH". 58 xr XRT83L34 REV. 1.0.1 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR 8. After waiting the appropriate time for the data (on the bi-directional data bus) to settle and can be safely accepted by the Microprocessor, the XRT83L34 device will indicate that this data can now be latched into the "target" address location by toggling the "RDY*/DTACK*" output pin "LOW. 9. After the Microprocessor detects the RDY*/DTACK* signal (from the XRT83L34 device) toggling "LOW", it can then terminate the WRITE cycle by toggling the "RD*/DS*" (Data Strobe) input pin "HIGH". NOTE: Once the user toggles the "RD*/DS* (Data Strobe) input pin "HIGH", then the following two things will happen. 1. The XRT83L34 device will latch the contents of the bi-directional data bus into the Microprocessor Interface block. 2. The XRT83L34 device will terminate the "WRITE" cycle. Figure _ presents a timing diagram that illustrates the behavior of the Microprocessor Interface signals, during a "MotorolaAsynchronous" Write Operation. FIGURE 28. ILLUSTRATION OF A MOTOROLA-ASYNCHRONOUS WRITE OPERATION Microprocessor places “target” Address value on A[6:0] ALE/AS* A[6:0] Address of Target Register CS* D[7:0] Data to be Written RD*/DS* WR/R/W* RDY*/DTACK* Write Operation is Terminated Here Address Decoding Circuitry asserts CS* Write Operation begins Here DTACK* toggles “low” to indicate That valid data can be latched into “target” Address location of chip Microprocessor toggles “R/W*” low To Denote WRITE operation 59 xr XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 MICROPROCESSOR REGISTER TABLES The microprocessor interface consists of 256 addressable locations. Each channel uses 16 dedicated 7 bit registers for independent programming and control. There are four additional registers for global control of all channels and two registers for device identification and revision numbers. The remaining registers are for factory test and future expansion. The control register map and the function of the individual bits are summarized in Table 18 and Table 19 respectively. TABLE 18: MICROPROCESSOR REGISTER ADDRESS REGISTER ADDRESS REGISTER NUMBER FUNCTION HEX BINARY 0 - 15 0x00 - 0x0F 0000000 - 0001111 Channel 0 Control Registers 16 - 31 0x10 -0x1F 0010000 - 0011111 Channel 1 Control Registers 32 - 47 0x20 - 0x2F 0100000 - 0101111 Channel 2 Control Registers 48 - 63 0x30 - 0x3F 0110000 - 0111111 Channel 3 Control Registers 64 - 67 0x40 - 0x43 1000000 - 1000011 Command Control Registers for All 4 Channels 68 - 75 0x44 - 0x4B 1000100 - 1001011 R/W registers reserved for testing purpose. 76-125 0x4C - 0x7D 1001100 - 1111101 Reserved 126 0x7E 1111110 Device ID 127 0x7F 1111111 Device Revision ID TABLE 19: MICROPROCESSOR REGISTER BIT DESCRIPTION REG. # ADDRESS REG. TYPE BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Channel 0 Control Registers 0 0000000 Hex 0x00 R/W Reserved Reserved RXON_n EQC4_n EQC3_n EQC2_n EQC1_n EQC0_n 1 0000001 Hex 0x01 R/W RXTSEL_n TXTSEL_n TERSEL1_n TERSEL0_n JASEL1_n JASEL0_n JABW_n FIFOS_n 2 0000010 Hex 0x02 R/W INVQRSS_n TXTEST2_n TXTEST1_n TXTEST0_n TXON_n LOOP2_n LOOP1_n LOOP0_n 3 0000011 Hex 0x03 R/W NLCDE1_n NLCDE0_n CODES_n RXRES1_n RXRES0_n INSBPV_n INSBER_n TRATIO_n 4 0000100 Hex 0x04 R/W Reserved DMOIE_n FLSIE_n LCVIE_n NLCDIE_n AISDIE_n RLOSIE_n QRPDIE_n 5 0000101 Hex 0x05 RO Reserved DMO_n FLS_n LCV_n NLCD_n AISD_n RLOS_n QRPD_n 6 0000110 Hex 0x06 RUR Reserved DMOIS_n FLSIS_n LCVIS_n NLCDIS_n AISDIS_n RLOSIS_n QRPDIS_n 7 0000111 Hex 0x07 RO Reserved Reserved CLOS5_n CLOS4_n CLOS3_n CLOS2_n CLOS1_n CLOS0_n 8 0001000 Hex 0x08 R/W X B6S1_n B5S1_n B4S1_n B3S1_n B2S1_n B1S1_n B0S1_n 60 xr XRT83L34 REV. 1.0.1 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR TABLE 19: MICROPROCESSOR REGISTER BIT DESCRIPTION REG. TYPE BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 0001001 Hex 0x09 R/W X B6S2_n B5S2_n B4S2_n B3S2_n B2S2_n B1S2_n B0S2_n 10 0001010 Hex 0x0A R/W X B6S3_n B5S3_n B4S3_n B3S3_n B2S3_n B1S3_n B0S3_n 11 0001011 Hex 0x0B R/W X B6S4_n B5S4_n B4S4_n B3S4_n B2S4_n B1S4_n B0S4_n 12 0001100 Hex 0x0C R/W X B6S5_n B5S5_n B4S5_n B3S5_n B2S5_n B1S5_n B0S5_n 13 0001101 Hex 0x0D R/W X B6S6_n B5S6_n B4S6_n B3S6_n B2S6_n B1S6_n B0S6_n 14 0001110 Hex 0x0E R/W X B6S7_n B5S7_n B4S7_n B3S7_n B2S7_n B1S7_n B0S7_n 15 0001111 Hex 0x0F R/W X B6S8_n B5S8_n B4S8_n B3S8_n B2S8_n B1S8_n B0S8_n Reset = 0 Reset = 0 Reset = 0 Reset = 0 Reset = 0 Reset = 0 Reset = 0 Reset = 0 REG. # ADDRESS 9 Command Control Global Registers for all 8 channels 16-31 001xxxx Hex 0x100x1F R/W Channel 1Control Register (see Registers 0-15 for description) 32-47 010xxxx Hex 0x20ox2F R/W Channel 2 Control Register (see Registers 0-15 for description) 48-63 011xxxx Hex 0x300x3F R/W Channel 3 Control Register (see Registers 0-15 for description) Command Control Global Registers 64 1000000 Hex 0x40 R/W SR/DR ATAOS RCLKE TCLKE DATAP Reserved GIE SRESET 65 1000001 Hex 0x41 R/W E1arben CLKSEL2 CLKSEL1 CLKSEL0 MCLKRATE RXMUTE EXLOS ICT 66 1000010 Hex 0x42 R/W GAUGE1 Gauge2 TXONCNTL TERCNTL SL_1 SL_0 EQG_1 EQG_0 67 1000011 Hex 0x43 R/W Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Test Registers for channels 0 - 3 68 1000100 Hex 0x44 R/W Test byte 0 69 1000101 Hex 0x45 R/W Test byte 1 70 1000110 Hex 0x46 R/W Test byte 2 71 1000111 Hex 0x47 R/W Test byte 3 72 1001000 Hex 0x48 R/W Test byte 4 73 1001001 Hex 0x49 R/W Test byte 5 61 xr XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 TABLE 19: MICROPROCESSOR REGISTER BIT DESCRIPTION REG. TYPE REG. # ADDRESS BIT 7 74 1001010 Hex 0x4A R/W Test byte 6 75 1001011 Hex 0x4B R/W Test byte 7 BIT 6 BIT 5 BIT 4 Unused Registers 76 1001100 Hex 0x4C …. 125 1111101 Hex 0x7D ID Registers 126 1111110 Hex 0x7E DEVICE ID: HEX = FB, Binary = 1111011 127 1111111 Hex 0x7F DEVICE Revision ID 62 BIT 3 BIT 2 BIT 1 BIT 0 xr XRT83L34 REV. 1.0.1 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR MICROPROCESSOR REGISTER DESCRIPTIONS TABLE 20: MICROPROCESSOR REGISTER #0, BIT DESCRIPTION REGISTER ADDRESS 0000000 0010000 0100000 0110000 CHANNEL_n CHANNEL_0 CHANNEL_1 CHANNEL_2 CHANNEL_3 BIT # NAME D7 REGISTER TYPE RESET VALUE Reserved R/W 0 D6 Reserved R/W D5 RXON_n FUNCTION Receiver ON: Writing a “1” into this bit location turns on the Receive Section of channel n. Writing a “0” shuts off the Receiver Section of channel n. R/W 0 R/W 0 NOTES: 1. This bit provides independent turn-off or turn-on control of each receiver channel. 2. In Hardware mode all receiver channels are always on. D4 EQC4_n Equalizer Control bit 4: This bit together with EQC[3:0] are used for controlling transmit pulse shaping, transmit line buildout (LBO) and receive monitoring for either T1 or E1 Modes of operation. See Table 5 for description of Equalizer Control bits. D3 EQC3_n Equalizer Control bit 3: See bit D4 description for function of this bit R/W 0 D2 EQC2_n Equalizer Control bit 2: See bit D4 description for function of this bit R/W 0 D1 EQC1_n Equalizer Control bit 1: See bit D4 description for function of this bit R/W 0 D0 EQC0_n Equalizer Control bit 0: See bit D4 description for function of this bit R/W 0 63 xr XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 TABLE 21: MICROPROCESSOR REGISTER #1, BIT DESCRIPTION REGISTER ADDRESS 0000001 0010001 0100001 0110001 CHANNEL_n CHANNEL_0 CHANNEL_1 CHANNEL_2 CHANNEL_3 BIT # NAME D7 RXTSEL_n D6 D5 TXTSEL_n FUNCTION Receiver Termination Select: In Host mode, this bit is used to select between the internal and external line termination modes for the receiver according to the following table; RXTSEL RX Termination 0 External 1 Internal Transmit Termination Select: In Host mode, this bit is used to select between the internal and external line termination modes for the transmitter according to the following table; TXTSEL TX Termination 0 External 1 Internal TERSEL1_n Termination Impedance Select1: In Host mode and in internal termination mode, (TXTSEL = “1” and RXTSEL = “1”) TERSEL[1:0] control the transmit and receive termination impedance according to the following table; TERSEL1 TERSEL0 REGISTER TYPE RESET VALUE R/W 0 R/W 0 R/W 0 R/W 0 Termination 0 0 100Ω 0 1 110Ω 1 0 75Ω 1 1 120Ω In the internal termination mode, the receiver termination of each receiver is realized completely by internal resistors or by the combination of internal and one fixed external resistor. In the internal termination mode, the transmitter output should be AC coupled to the transformer. D4 TERSEL0_n Termination Impedance Select bit 0: See description of bit D5 for the function of this bit. 64 xr XRT83L34 REV. 1.0.1 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR TABLE 21: MICROPROCESSOR REGISTER #1, BIT DESCRIPTION D3 JASEL1_n Jitter Attenuator select bit 1: The JASEL1 and JASEL0 bits are used to disable or place the jitter attenuator of each channel independently in the transmit or receive path. JASEL1 bit D3 JASEL0 bit D2 0 0 JA Disabled 0 1 JA in Transmit Path 1 0 JA in Receive Path 1 1 JA in Receive Path R/W 0 JA Path D2 JASEL0_n Jitter Attenuator select bit 0: See description of bit D3 for the function of this bit. R/W 0 D1 JABW_n Jitter Attenuator Bandwidth Select: In E1 mode, set this bit to “1” to select a 1.5Hz Bandwidth for the Jitter Attenuator. The FIFO length will be automatically set to 64 bits. Set this bit to “0” to select 10Hz Bandwidth for the Jitter Attenuator in E1 mode. In T1 mode the Jitter Attenuator Bandwidth is permanently set to 3Hz, and the state of this bit has no effect on the Bandwidth. R/W 0 R/W 0 D0 FIFOS_n Mode JABW bit D1 FIFOS_n bit D0 JA B-W Hz FIFO Size T1 0 0 3 32 T1 0 1 3 64 T1 1 0 3 32 T1 1 1 3 64 E1 0 0 10 32 E1 0 1 10 64 E1 1 0 1.5 64 E1 1 1 1.5 64 FIFO Size Select: See table of bit D1 above for the function of this bit. 65 xr XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 TABLE 22: MICROPROCESSOR REGISTER #2, BIT DESCRIPTION REGISTER ADDRESS 0000010 0010010 0100010 0110010 CHANNEL_n CHANNEL_0 CHANNEL_1 CHANNEL_2 CHANNEL_3 BIT # NAME FUNCTION REGISTER TYPE RESET VALUE D7 INVQRSS_n Invert QRSS Pattern: When TQRSS is active, Writing a “1” to this bit inverts the polarity of transmitted QRSS pattern. Writing a “0” sends the QRSS pattern with no inversion. R/W 0 D6 TXTEST2_n Transmit Test Pattern bit 2: This bit together with TXTEST1 and TXTEST0 are used to generate and transmit test patterns according to the following table: R/W 0 TXTEST2 TXTEST1 TXTEST0 Test Pattern 0 X X No Pattern 1 0 0 TDQRSS 1 0 1 TAOS 1 1 0 TLUC 1 1 1 TLDC TDQRSS (Transmit/Detect Quasi-Random Signal): This condition when activated enables Quasi-Random Signal Source generation and detection for the selected channel number n. In a T1 system QRSS pattern is a 220-1 pseudorandom bit sequence (PRBS) with no more than 14 consecutive zeros. In a E1 system, QRSS is a 215-1 PRBS pattern. TAOS (Transmit All Ones): Activating this condition enables the transmission of an All Ones Pattern from the selected channel number n. TLUC (Transmit Network Loop-Up Code): Activating this condition enables the Network Loop-Up Code of “00001” to be transmitted to the line for the selected channel number n. When Network Loop-Up code is being transmitted, the XRT83L34 will ignore the Automatic Loop-Code detection and Remote Loop-Back activation (NLCDE1 =“1”, NLCDE0 =“1”, if activated) in order to avoid activating Remote Digital LoopBack automatically when the remote terminal responds to the Loop-Back request. TLDC (Transmit Network Loop-Down Code): Activating this condition enables the network Loop-Down Code of “001” to be transmitted to the line for the selected channel number n. D5 TXTEST1_n Transmit Test pattern bit 1: See description of bit D6 for the function of this bit. R/W 0 D4 TXTEST0_n Transmit Test Pattern bit 0: See description of bit D6 for the function of this bit. R/W 0 66 xr XRT83L34 REV. 1.0.1 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR TABLE 22: MICROPROCESSOR REGISTER #2, BIT DESCRIPTION D3 TXON_n Transmitter ON: Writing a “1” into this bit location turns on the Transmit Section of channel n. Writing a “0” shuts off the Transmit Section of channel n. In this mode, TTIP_n and TRING_n driver outputs will be tri-stated for power reduction or redundancy applications. R/W 0 NOTE: This bit provides independent turn-off or turn-on control for each transmitter channel. D2 LOOP2_n Loop-Back control bit 2: This bit together with the LOOP1 and LOOP0 bits control the Loop-Back modes of the chip according to the following table: LOOP2 LOOP1 LOOP0 Loop-Back Mode 0 X X No Loop-Back 1 0 0 Dual Loop-Back 1 0 1 Analog Loop-Back 1 1 0 Remote Loop-Back 1 1 1 Digital Loop-Back D1 LOOP1_n Loop-Back control bit 1: See description of bit D2 for the function of this bit. R/W 0 D0 LOOP0_n Loop-Back control bit 0: See description of bit D2 for the function of this bit. R/W 0 67 xr XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 TABLE 23: MICROPROCESSOR REGISTER #3, BIT DESCRIPTION REGISTER ADDRESS 0000011 0010011 0100011 0110011 CHANNEL_n CHANNEL_0 CHANNEL_1 CHANNEL_2 CHANNEL_3 BIT # NAME D7 NLCDE1_n FUNCTION Network Loop Code Detection Enable Bit 1: This bit together with NLCDE0_n control the Loop-Code detection of each channel. NLCDE1 NLCDE0 0 0 0 1 1 0 1 1 REGISTER TYPE RESET VALUE R/W 0 Function Disable Loop-code detection Detect Loop-Up code in receive data Detect Loop-Down code in receive data Automatic Loop-Code detection When NLCDE1 =”0” and NLCDE0 = “1” or NLCDE1 = “1” and NLCDE0 = “0”, the chip is manually programmed to monitor the receive data for the Loop-Up or Loop-Down code respectively.When the presence of the “00001” or “001” pattern is detected for more than 5 seconds, the status of the NLCD bit is set to “1” and if the NLCD interrupt is enabled, an interrupt is initiated.The Host has the option to control the Loop-Back function manually. Setting the NLCDE1 = “1” and NLCDE0 = “1” enables the Automatic Loop-Code detection and Remote Loop-Back activation mode. As this mode is initiated, the state of the NLCD interface bit is reset to “0” and the chip is programmed to monitor the receive data for the Loop-Up code. If the “00001” pattern is detected for longer than 5 seconds, the NLCD bit is set “1”, Remote Loop-Back is activated and the chip is automatically programmed to monitor the receive data for the LoopDown code. The NLCD bit stays set even after the chip stops receiving the Loop-Up code. The Remote Loop-Back condition is removed when the chip receives the Loop-Down code for more than 5 seconds or if the Automatic Loop-Code detection mode is terminated. D6 NLCDE0_n Network Loop Code Detection Enable Bit 0: See description of D7 for function of this bit. R/W 0 D5 CODES_n Encoding and Decoding Select: Writing a “0” to this bits selects HDB3 or B8ZS encoding and decoding for channel number n. Writing “1” selects an AMI coding scheme. This bit is only active when single rail mode is selected. R/W 0 68 xr XRT83L34 REV. 1.0.1 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR TABLE 23: MICROPROCESSOR REGISTER #3, BIT DESCRIPTION D4 RXRES1_n Receive External Resistor Control Pin 1: In Host mode, this bit along with the RXRES0_n bit selects the value of the external Receive fixed resistor according to the following table; RX RES 1_n RX RES 0_n R equired Fixed E xternal RX Resistor 0 0 No external Fixed Resistor 0 1 240 Ω 1 0 210 Ω 1 1 150 Ω R/W 0 D3 RXRES0_n Receive External Resistor Control Pin 0: For function of this bit see description of D4 the RXRES1_n bit. R/W 0 D2 INSBPV_n Insert Bipolar Violation: When this bit transitions from “0” to “1”, a bipolar violation is inserted in the transmitted data stream of the selected channel number n. Bipolar violation can be inserted either in the QRSS pattern, or input data when operating in single-rail mode. The state of this bit is sampled on the rising edge of the respective TCLK_n. R/W 0 R/W 0 R/W 0 NOTE: To ensure the insertion of a bipolar violation, a “0” should be written in this bit location before writing a “1”. D1 INSBER_n Insert Bit Error: With TDQRSS enabled, when this bit transitions from “0” to “1”, a bit error will be inserted in the transmitted QRSS pattern of the selected channel number n. The state of this bit is sampled on the rising edge of the respective TCLK_n. NOTE: To ensure the insertion of bit error, a “0” should be written in this bit location before writing a “1”. D0 TRATIO_n Transformer Ratio Select: In the external termination mode, writing a “1” to this bit selects a transformer ratio of 1:2 for the transmitter. Writing a “0” sets the transmitter transformer ratio to 1:2.45. In the internal termination mode the transmitter transformer ratio is permanently set to 1:2 and the state of this bit has no effect. 69 xr XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 TABLE 24: MICROPROCESSOR REGISTER #4, BIT DESCRIPTION REGISTER ADDRESS 0000100 0010100 0100100 0110100 CHANNEL_n CHANNEL_0 CHANNEL_1 CHANNEL_2 CHANNEL_3 BIT # NAME D7 Reserved D6 DMOIE_n D5 REGISTER TYPE RESET VALUE RO 0 DMO Interrupt Enable: Writing a “1” to this bit enables DMO interrupt generation, writing a “0” masks it. R/W 0 FLSIE_n FIFO Limit Status Interrupt Enable: Writing a “1” to this bit enables interrupt generation when the FIFO limit is within to 3 bits, writing a “0” to masks it. R/W 0 D4 LCVIE_n Line Code Violation Interrupt Enable: Writing a “1” to this bit enables Line Code Violation interrupt generation, writing a “0” masks it. R/W 0 D3 NLCDIE_n Network Loop-Code Detection Interrupt Enable: Writing a “1” to this bit enables Network Loop-code detection interrupt generation, writing a “0” masks it. R/W 0 D2 AISDIE_n AIS Interrupt Enable: Writing a “1” to this bit enables Alarm Indication Signal detection interrupt generation, writing a “0” masks it. R/W 0 D1 RLOSIE_n Receive Loss of Signal Interrupt Enable: Writing a “1” to this bit enables Loss of Receive Signal interrupt generation, writing a “0” masks it. R/W 0 D0 QRPDIE_n QRSS Pattern Detection Interrupt Enable: Writing a “1” to this bit enables QRSS pattern detection interrupt generation, writing a “0” masks it. R/W 0 FUNCTION 70 xr XRT83L34 REV. 1.0.1 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR TABLE 25: MICROPROCESSOR REGISTER #5, BIT DESCRIPTION REGISTER ADDRESS 0000101 0010101 0100101 0110101 CHANNEL_n CHANNEL_0 CHANNEL_1 CHANNEL_2 CHANNEL_3 BIT # NAME D7 Reserved D6 DMO_n D5 D4 REGISTER TYPE RESET VALUE RO 0 Driver Monitor Output: This bit is set to a “1” to indicate transmit driver failure is detected. The value of this bit is based on the current status of DMO for the corresponding channel. If the DMOIE bit is enabled, any transition on this bit will generate an Interrupt. RO 0 FLS_n FiFO Limit Status: This bit is set to a “1” to indicate that the jitter attenuator read/write FIFO pointers are within +/- 3 bits. If the FLSIE bit is enabled, any transition on this bit will generate an Interrupt. RO 0 LCV_n Line Code Violation: This bit is set to a “1” to indicate that the receiver of channel n is currently detecting a Line Code Violation or an excessive number of zeros in the B8ZS or HDB3 modes. If the LCVIE bit is enabled, any transition on this bit will generate an Interrupt. RO 0 FUNCTION 71 xr XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 TABLE 25: MICROPROCESSOR REGISTER #5, BIT DESCRIPTION D3 NLCD_n Network Loop-Code Detection: This bit operates differently in the Manual or the Automatic Network Loop-Code detection modes. In the Manual Loop-Code detection mode, (NLCDE1 = “0” and NLCDE0 = “1” or NLCDE1 = “1” and NLCDE0 = “0”) this bit gets set to “1” as soon as the Loop-Up (“00001”) or LoopDown (“001”) code is detected in the receive data for longer than 5 seconds. The NLCD bit stays in the “1” state for as long as the chip detects the presence of the Loop-code in the receive data and it is reset to “0” as soon as it stops receiving it. In this mode, if the NLCD interrupt is enabled, the chip will initiate an interrupt on every transition of the NLCD. When the Automatic Loop-code detection mode, (NLCDE1 = “1” and NLCDE0 =”1”) is initiated, the state of the NLCD interface bit is reset to “0” and the chip is programmed to monitor the receive input data for the Loop-Up code. This bit is set to a “1” to indicate that the Network Loop Code is detected for more than 5 seconds. Simultaneously the Remote Loop-Back condition is automatically activated and the chip is programmed to monitor the receive data for the Network Loop Down code. The NLCD bit stays in the “1” state for as long as the Remote Loop-Back condition is in effect even if the chip stops receiving the Loop-Up code. Remote Loop-Back is removed if the chip detects the “001” pattern for longer than 5 seconds in the receive data.Detecting the “001” pattern also results in resetting the NLCD interface bit and initiating an interrupt provided the NLCD interrupt enable bit is active. When programmed in Automatic detection mode, the NLCD interface bit stays “High” for the entire time the Remote Loop-Back is active and initiate an interrupt anytime the status of the NLCD bit changes. In this mode, the Host can monitor the state of the NLCD bit to determine if the Remote LoopBack is activated. RO 0 D2 AISD_n Alarm Indication Signal Detect: This bit is set to a “1” to indicate All Ones Signal is detected by the receiver. The value of this bit is based on the current status of Alarm Indication Signal detector of channel n. If the AISDIE bit is enabled, any transition on this bit will generate an Interrupt. RO 0 D1 RLOS_n Receive Loss of Signal: This bit is set to a “1” to indicate that the receive input signal is lost. The value of this bit is based on the current status of the receive input signal of channel n. If the RLOSIE bit is enabled, any transition on this bit will generate an Interrupt. RO 0 D0 QRPD_n Quasi-random Pattern Detection: This bit is set to a “1” to indicate the receiver is currently in synchronization with QRSS pattern. The value of this bit is based on the current status of Quasi-random pattern detector of channel n. If the QRPDIE bit is enabled, any transition on this bit will generate an Interrupt. RO 0 72 xr XRT83L34 REV. 1.0.1 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR TABLE 26: MICROPROCESSOR REGISTER #6, BIT DESCRIPTION REGISTER ADDRESS 0000110 0010110 0100110 0110110 CHANNEL_n CHANNEL_0 CHANNEL_1 CHANNEL_2 CHANNEL_3 BIT # NAME D7 Reserved D6 DMOIS_n FUNCTION Driver Monitor Output Interrupt Status: This bit is set to a “1” every time the DMO status has changed since last read. REGISTER TYPE RESET VALUE RO 0 RUR 0 RUR 0 RUR 0 RUR 0 RUR 0 RUR 0 RUR 0 NOTE: This bit is reset upon read. D5 FLSIS_n FIFO Limit Interrupt Status: This bit is set to a “1” every time when FIFO Limit (Read/Write pointer with +/- 3 bits apart) status has changed since last read. NOTE: This bit is reset upon read. D4 LCVIS_n Line Code Violation Interrupt Status: This bit is set to a “1” every time when LCV status has changed since last read. NOTE: This bit is reset upon read. D3 NLCDIS_n Network Loop-Code Detection Interrupt Status: This bit is set to a “1” every time when NLCD status has changed since last read. NOTE: This bit is reset upon read. D2 AISDIS_n AIS Detection Interrupt Status: This bit is set to a “1” every time when AISD status has changed since last read. NOTE: This bit is reset upon read. D1 RLOSIS_n Receive Loss of Signal Interrupt Status: This bit is set to a “1” every time RLOS status has changed since last read. NOTE: This bit is reset upon read. D0 QRPDIS_n Quasi-Random Pattern Detection Interrupt Status: This bit is set to a “1” every time when QRPD status has changed since last read. NOTE: This bit is reset upon read. 73 xr XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 TABLE 27: MICROPROCESSOR REGISTER #7, BIT DESCRIPTION REGISTER ADDRESS 0000111 0010111 0100111 0110111 CHANNEL_n CHANNEL_0 CHANNEL_1 CHANNEL_2 CHANNEL_3 BIT # NAME D7 REGISTER TYPE RESET VALUE Reserved RO 0 D6 Reserved RO 0 D5 CLOS5_n Cable Loss bit 5: CLOS[5:0]_n are the six bit receive selective equalizer setting which is also a binary word that represents the cable attenuation indication within ±1dB. CLOS5_n is the most significant bit (MSB) and CLOS0_n is the least significant bit (LSB). RO 0 D4 CLOS4_n Cable Loss bit 4: See description of D5 for function of this bit. RO 0 D3 CLOS3_n Cable Loss bit 3: See description of D5 for function of this bit. RO 0 D2 CLOS2_n Cable Loss bit 2: See description of D5 for function of this bit. RO 0 D1 CLOS1_n Cable Loss bit 1: See description of D5 for function of this bit. RO 0 D0 CLOS0_n Cable Loss bit 0: See description of D5 for function of this bit. RO 0 FUNCTION 74 xr XRT83L34 REV. 1.0.1 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR TABLE 28: MICROPROCESSOR REGISTER #8, BIT DESCRIPTION REGISTER ADDRESS 0001000 0011000 0101000 0111000 CHANNEL_n CHANNEL_0 CHANNEL_1 CHANNEL_2 CHANNEL_3 BIT # NAME D7 Reserved D6-D0 B6S1_n B0S1_n FUNCTION Arbitrary Transmit Pulse Shape, Segment 1:The shape of each channel's transmitted pulse can be made independently user programmable by selecting “Arbitrary Pulse” mode in Table 5. The arbitrary pulse is divided into eight time segments whose combined duration is equal to one period of MCLK. This 7 bit number represents the amplitude of the nth channel's arbitrary pulse during the first time segment. B6S1_nB0S1_n is in signed magnitude format with B6S1_n as the sign bit and B0S1_n as the least significant bit (LSB). REGISTER TYPE RESET VALUE R/W 0 R/W 0 REGISTER TYPE RESET VALUE R/W 0 R/W 0 TABLE 29: MICROPROCESSOR REGISTER #9, BIT DESCRIPTION REGISTER ADDRESS 0001001 0011001 0101001 0111001 CHANNEL_n CHANNEL_0 CHANNEL_1 CHANNEL_2 CHANNEL_3 BIT # NAME D7 Reserved D6-D0 B6S2_n B0S2_n FUNCTION Arbitrary Transmit Pulse Shape, Segment 2 The shape of each channel's transmitted pulse can be made independently user programmable by selecting “Arbitrary Pulse” mode in Table 5. The arbitrary pulse is divided into eight time segments whose combined duration is equal to one period of MCLK. This 7 bit number represents the amplitude of the nth channel's arbitrary pulse during the second time segment. B6S2_nB0S2_n is in signed magnitude format with B6S2_n as the sign bit and B0S2_n as the least significant bit (LSB). 75 xr XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 TABLE 30: MICROPROCESSOR REGISTER #10, BIT DESCRIPTION REGISTER ADDRESS 0001010 0011010 0101010 0111010 CHANNEL_n CHANNEL_0 CHANNEL_1 CHANNEL_2 CHANNEL_3 BIT # NAME D7 Reserved D6-D0 B6S3_n B0S3_n FUNCTION Arbitrary Transmit Pulse Shape, Segment 3 The shape of each channel's transmitted pulse can be made independently user programmable by selecting “Arbitrary Pulse” mode in Table 5. The arbitrary pulse is divided into eight time segments whose combined duration is equal to one period of MCLK. This 7 bit number represents the amplitude of the nth channel's arbitrary pulse during the third time segment. B6S3_nB0S3_n is in signed magnitude format with B6S3_n as the sign bit and B0S3_n as the least significant bit (LSB). REGISTER TYPE RESET VALUE R/W 0 R/W 0 REGISTER TYPE RESET VALUE R/W 0 R/W 0 TABLE 31: MICROPROCESSOR REGISTER #11, BIT DESCRIPTION REGISTER ADDRESS 0001011 0011011 0101011 0111011 CHANNEL_n CHANNEL_0 CHANNEL_1 CHANNEL_2 CHANNEL_3 BIT # NAME D7 Reserved D6-D0 B6S4_n B0S4_n FUNCTION Arbitrary Transmit Pulse Shape, Segment 4 The shape of each channel's transmitted pulse can be made independently user programmable by selecting “Arbitrary Pulse” mode in Table 5. The arbitrary pulse is divided into eight time segments whose combined duration is equal to one period of MCLK. This 7 bit number represents the amplitude of the nth channel's arbitrary pulse during the fourth time segment. B6S4_nB0S4_n is in signed magnitude format with B6S4_n as the sign bit and B0S4_n as the least significant bit (LSB). 76 xr XRT83L34 REV. 1.0.1 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR TABLE 32: MICROPROCESSOR REGISTER #12, BIT DESCRIPTION REGISTER ADDRESS 0001100 0011100 0101100 0111100 CHANNEL_n CHANNEL_0 CHANNEL_1 CHANNEL_2 CHANNEL_3 BIT # NAME D7 Reserved D6-D0 B6S5_n B0S5_n FUNCTION Arbitrary Transmit Pulse Shape, Segment 5 The shape of each channel's transmitted pulse can be made independently user programmable by selecting “Arbitrary Pulse” mode in Table 5. The arbitrary pulse is divided into eight time segments whose combined duration is equal to one period of MCLK. This 7 bit number represents the amplitude of the nth channel's arbitrary pulse during the fifth time segment. B6S5_nB0S5_n is in signed magnitude format with B6S5_n as the sign bit and B0S5_n as the least significant bit (LSB). REGISTER TYPE RESET VALUE R/W 0 R/W 0 REGISTER TYPE RESET VALUE R/W 0 R/W 0 TABLE 33: MICROPROCESSOR REGISTER #13, BIT DESCRIPTION REGISTER ADDRESS 0001101 0011101 0101101 0111101 CHANNEL_n CHANNEL_0 CHANNEL_1 CHANNEL_2 CHANNEL_3 BIT # NAME D7 Reserved D6-D0 B6S6_n B0S6_n FUNCTION Arbitrary Transmit Pulse Shape, Segment 6 The shape of each channel's transmitted pulse can be made independently user programmable by selecting “Arbitrary Pulse” mode in Table 5. The arbitrary pulse is divided into eight time segments whose combined duration is equal to one period of MCLK. This 7 bit number represents the amplitude of the nth channel's arbitrary pulse during the sixth time segment. B6S6_nB0S6_n is in signed magnitude format with B6S6_n as the sign bit and B0S6_n as the least significant bit (LSB). 77 xr XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 TABLE 34: MICROPROCESSOR REGISTER #14, BIT DESCRIPTION REGISTER ADDRESS 0001110 0011110 0101110 0111110 CHANNEL_n CHANNEL_0 CHANNEL_1 CHANNEL_2 CHANNEL_3 BIT # NAME D7 Reserved D6-D0 B6S7_n B0S7_n FUNCTION Arbitrary Transmit Pulse Shape, Segment 7 The shape of each channel's transmitted pulse can be made independently user programmable by selecting “Arbitrary Pulse” mode in Table 5. The arbitrary pulse is divided into eight time segments whose combined duration is equal to one period of MCLK. This 7 bit number represents the amplitude of the nth channel's arbitrary pulse during the seventh time segment. B6S7_n-B0S7_n is in signed magnitude format with B6S7_n as the sign bit and B0S7_n as the least significant bit (LSB). REGISTER TYPE RESET VALUE R/W 0 R/W 0 REGISTER TYPE RESET VALUE R/W 0 R/W 0 TABLE 35: MICROPROCESSOR REGISTER #15, BIT DESCRIPTION REGISTER ADDRESS 0001111 0011111 0101111 0111111 CHANNEL_n CHANNEL_0 CHANNEL_1 CHANNEL_2 CHANNEL_3 BIT # NAME D7 Reserved D6-D0 B6S8_n B0S8_n FUNCTION Arbitrary Transmit Pulse Shape, Segment 8 The shape of each channel's transmitted pulse can be made independently user programmable by selecting “Arbitrary Pulse” mode in Table 5. The arbitrary pulse is divided into eight time segments whose combined duration is equal to one period of MCLK. This 7 bit number represents the amplitude of the nth channel's arbitrary pulse during the eighth time segment. B6S8_nB0S8_n is in signed magnitude format with B6S8_n as the sign bit and B0S8_n as the least significant bit (LSB). 78 xr XRT83L34 REV. 1.0.1 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR TABLE 36: MICROPROCESSOR REGISTER #64, BIT DESCRIPTION REGISTER ADDRESS 1000000 REGISTER TYPE RESET VALUE Single-rail/Dual-rail Select: Writing a “1” to this bit configures all 8 channels in the XRT83L34 to operate in the Single-rail mode. Writing a “0” configures the XRT83L34 to operate in Dual-rail mode. R/W 0 ATAOS Automatic Transmit All Ones Upon RLOS: Writing a “1” to this bit enables the automatic transmission of All "Ones" data to the line for the channel that detects an RLOS condition. Writing a “0” disables this feature. R/W 0 D5 RCLKE Receive Clock Edge: Writing a “1” to this bit selects receive output data of all channels to be updated on the negative edge of RCLK. Wring a “0” selects data to be updated on the positive edge of RCLK. R/W 0 D4 TCLKE Transmit Clock Edge: Writing a “0” to this bit selects transmit data at TPOS_n/TDATA_n and TNEG_n/CODES_n of all channels to be sampled on the falling edge of TCLK_n. Writing a “1” selects the rising edge of the TCLK_n for sampling. R/W 0 D3 DATAP DATA Polarity: Writing a “0” to this bit selects transmit input and receive output data of all channels to be active “High”. Writing a “1” selects an active “Low” state. R/W 0 D2 Reserved D1 GIE D0 SRESET NAME FUNCTION D7 SR/DR D6 BIT # 0 Global Interrupt Enable: Writing a “1” to this bit globally enables interrupt generation for all channels. Writing a “0” disables interrupt generation. R/W 0 Software Reset µP Registers: Writing a “1” to this bit longer than 10µs initiates a device reset through the microprocessor interface. All internal circuits are placed in the reset state with this bit set to a “1” except the microprocessor register bits. R/W 0 79 xr XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 CLOCK SELECT REGISTER The input clock source is used to generate all the necessary clock references internally to the LIU. The microprocessor timing is derived from a PLL output which is chosen by programming the Clock Select Bits and the Master Clock Rate in register 0x41h. Therefore, if the clock selection bits or the MCLRATE bit are being programmed, the frequency of the PLL output will be adjusted accordingly. During this adjustment, it is important to "Not" write to any other bit location within the same register while selecting the input/output clock frequency. For best results, whenever the user is changing bits D[6:3] (within the Clock Select Register), he/ she should execute a "Masked-Write" Operation, such that he/she will not change the remaining bits within this register (e.g., D[7] and D[2:0] as shown below in Figure 29). FIGURE 29. REGISTER 0X81H SUB REGISTERS D7 E1arben D6 D5 D4 D3 Clock Selection Bits D2 D1 D0 ExLOS, ICT Programming Examples: Example 1: Changing bits D[6:3] If bits D[6:3] are the only values within the register that will change in a WRITE process, the microprocessor only needs to initiate ONE write operation. Example 2: Changing bits D[7] and D[2:0] If bits D[7] and D[2:0] are the only values within the register that will change in a WRITE process, the microprocessor only needs to initiate ONE write operation. Example 3: Changing bits within D[6:3] and the other bits In this scenario, one must initiate TWO write operations such that bits D[6:3] and the other bits do not change within ONE write cycle. It is recommended that bits D[6:0] and the other bits be treated as two independent sub-registers. One can either change the clock selection bits and then change bits D[7] and D[2:0] on the SECOND write, or vice-versa. No order or sequence is necessary. 80 xr XRT83L34 REV. 1.0.1 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR TABLE 37: MICROPROCESSOR REGISTER #65, BIT DESCRIPTION REGISTER ADDRESS 1000001 REGISTER TYPE RESET VALUE E1 Arbitrary Pulse Enable This bit is used to enable the Arbitrary Pulse Generators for shaping the transmit pulse shape when E1 mode is selected. If this bit is set to "1", all 8 channels will be configured for the Arbitrary Mode. However, each channel is individually controlled by programming the channel registers 0xn8 through 0xnF, where n is the number of the channel. "0" = Disabled (Normal E1 Pulse Shape ITU G.703) "1" = Arbitrary Pulse Enabled R/W 0 Clock Select Inputs for Master Clock Synthesizer bit 2: In Host mode, CLKSEL[2:0] are input signals to a programmable frequency synthesizer that can be used to generate a master clock from an external accurate clock source according to the following table; R/W 0 NAME FUNCTION D7 E1arben D6 CLKSEL2 BIT # M CLKE1 kHz M CLKT1 kHz CLKSEL2 CLKSEL1 CLKSEL0 M CLKRATE CLKOUT/ kHz 2048 2048 0 0 0 0 2048 2048 2048 0 0 0 1 1544 2048 1544 0 0 0 0 2048 1544 1544 0 0 1 1 1544 1544 1544 0 0 1 0 2048 2048 1544 0 0 1 1 1544 8 X 0 1 0 0 2048 8 X 0 1 0 1 1544 16 X 0 1 1 0 2048 16 X 0 1 1 1 1544 56 X 1 0 0 0 2048 56 X 1 0 0 1 1544 64 X 1 0 1 0 2048 64 X 1 0 1 1 1544 128 X 1 1 0 0 2048 128 X 1 1 0 1 1544 256 X 1 1 1 0 2048 256 X 1 1 1 1 1544 In Hardware mode, the state of these signals are ignored and the master frequency PLL is controlled by the corresponding Hardware pins. D5 CLKSEL1 Clock Select inputs for Master Clock Synthesizer bit 1: See description of bit D6 for function of this bit. R/W 0 D4 CLKSEL0 Clock Select inputs for Master Clock Synthesizer bit 0: See description of bit D6 for function of this bit. R/W 0 D3 MCLKRATE Master clock Rate Select: The state of this bit programs the Master Clock Synthesizer to generate the T1/J1 or E1 clock. The Master Clock Synthesizer will generate the E1 clock when MCLKRATE = “0”, and the T1/J1 clock when MCLKRATE = “1”. R/W 0 81 xr XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 TABLE 37: MICROPROCESSOR REGISTER #65, BIT DESCRIPTION D2 RXMUTE Receive Output Mute: Writing a “1” to this bit, mutes receive outputs at RPOS/RDATA and RNEG/LCV pins to a “0” state for any channel that detects an RLOS condition. R/W 0 NOTE: RCLK is not muted. D1 EXLOS Extended LOS: Writing a “1” to this bit extends the number of zeros at the receive input of each channel before RLOS is declared to 4096 bits. Writing a “0” reverts to the normal mode (175+75 bits for T1 and 32 bits for E1). R/W 0 D0 ICT In-Circuit-Testing: Writing a “1” to this bit configures all the output pins of the chip in high impedance mode for In-CircuitTesting. Setting the ICT bit to “1” is equivalent to connecting the Hardware ICT pin 88 to ground. R/W 0 REGISTER TYPE RESET VALUE R/W 0 Wire Gauge Selector Bit 0: See bit D7. R/W 0 Transmit On Control: In Host mode, setting this bit to “1” transfers the control of the Transmit On/Off function to the TXON_n Hardware control pins. R/W 0 R/W 0 TABLE 38: MICROPROCESSOR REGISTER #66, BIT DESCRIPTION REGISTER ADDRESS 1000010 NAME FUNCTION GAUGE1 Wire Gauge Selector Bit 1: This bit together with bit D6 are used to select wire gauge size as shown in the table below. BIT # D7 D6 GAUGE0 D5 TXONCNTL GAUGE1 GAUGE0 Wire Size 0 0 22 and 24 Gauge 0 1 22 Gauge 1 0 24 Gauge 1 1 26 Gauge NOTE: This provides a faster On/Off capability for redundancy application. D4 TERCNTL Termination Control. In Host mode, setting this bit to “1” transfers the control of the RXTSEL to the RXTSEL Hardware control pin. NOTE: This provides a faster On/Off capability for redundancy application. 82 xr XRT83L34 REV. 1.0.1 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR TABLE 38: MICROPROCESSOR REGISTER #66, BIT DESCRIPTION D3 SL_1 D2 SL_0 D1 EQG_1 D0 EQG_0 Slicer Level Control bit 1: This bit and bit D2 control the slicing level for the slicer per the following table. R/W 0 Slicer Level Control bit 0: See description bit D3. R/W 0 Equalizer Gain Control bit 1: This bit together with bit D0 control the gain of the equalizer as shown in the table below. R/W 0 R/W 0 SL_1 SL_0 Slicer Mode 0 0 Normal 0 1 Decrease by 5% from Normal 1 0 Increase by 5% from Normal 1 1 Normal EQG_1 EQG_0 Equalizer Gain 0 0 Normal 0 1 Reduce Gain by 1 dB 1 0 Reduce Gain by 3 dB 1 1 Normal Equalizer Gain Control bit 0: See description of bit D1 83 xr XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 ELECTRICAL CHARACTERISTICS TABLE 39: ABSOLUTE MAXIMUM RATINGS Storage Temperature...................-65°C to + 150°C Operating Temperature.............-40°C to + 85°C Supply Voltage..........................-0.5V to + 3.8V VIn.................................................-0.5V to + 5.5V TABLE 40: DC DIGITAL INPUT AND OUTPUT ELECTRICAL CHARACTERISTICS VDD=3.3V±5%, TA=25°C, UNLESS OTHERWISE SPECIFIED PARAMETER SYMBOL MIN. TYP. MAX. UNITS VDD 3.13 3.3 3.46 V Input High Voltage VIH 2.0 - 5.0 V Input Low Voltage VIL -0.5 - 0.8 V Output High Voltage @ IOH = 2.0mA VOH 2.4 - - V Output Low Voltage @IOL = 2mA. VOL - - 0.4 V Input Leakage Current (except Input pins with Pull-up or Pull- down resistor). IL - - ±10 µA Input Capacitance CI - 5.0 - pF Output Load Capacitance CL - - 25 pF Power Supply Voltage TABLE 41: XRT83L34 POWER CONSUMPTION VDD=3.3V±5%, TA=25°C, UNLESS OTHERWISE SPECIFIED TERMINATION TRANSFORMER RATIO RESISTOR RECEIVER TRANSMITTER SUPPLY VOLTAGE IMPEDANCE E1 3.3V 75Ω Internal 1:1 E1 3.3V 120Ω Internal T1 3.3V 100Ω --- 3.3V --- MODE TEST CONDITIONS TYP. MAX. UNIT 1:2 925 1100 mW 100% “1’s” 1:1 1:2 890 1025 mW 100% “1’s” Internal 1:1 1:2 980 1150 mW 100% “1’s” External --- --- 230 265 mW All transmitters off 84 xr XRT83L34 REV. 1.0.1 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR TABLE 42: E1 RECEIVER ELECTRICAL CHARACTERISTICS VDD=3.3V±5%, TA= -40° TO 85°C, UNLESS OTHERWISE SPECIFIED PARAMETER MIN. TYP. MAX. UNIT Receiver loss of signal: Cable attenuation @1024kHz Number of consecutive zeros before RLOS is set 10 175 Input signal level at RLOS 15 20 RLOS De-asserted Receiver Sensitivity (Short Haul with cable loss) Receiver Sensitivity (Long Haul with cable loss) Nominal Extended 255 dB ITU-G.775, ETSI 300 233 12.5 dB 11 dB With nominal pulse amplitude of 3.0V for 120W and 2.37V for 75W application. With -18dB interference signal added. dB With nominal pulse amplitude of 3.0V for 120W and 2.37V for 75W application. With -18dB interference signal added. 0 0 Input Impedance Input Jitter Tolerance: 1 Hz 10kHz-100kHz TEST CONDITIONS 36 43 kW 13 37 0.2 UIpp UIpp ITU G.823 kHz dB ITU G.736 Recovered Clock Jitter Transfer Corner Frequency Peaking Amplitude - Jitter Attenuator Corner Frequency (-3dB curve) (JABW=0) (JABW=1) - 10 1.5 - Hz Hz ITU G.736 14 20 16 - - dB dB dB ITU-G.703 Return Loss: 51kHz - 102kHz 102kHz - 2048kHz 2048kHz - 3072kHz 36 -0.5 85 xr XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 TABLE 43: T1 RECEIVER ELECTRICAL CHARACTERISTICS VDD=3.3V±5%, TA=-40° TO 85°C, UNLESS OTHERWISE SPECIFIED PARAMETER MIN. TYP. MAX. UNIT TEST CONDITIONS Receiver loss of signal: Number of consecutive zeros before RLOS is set 100 175 250 Input signal level at RLOS 15 20 - dB 12.5 - - % ones 12 - RLOS Clear Receiver Sensitivity (Short Haul with cable loss) Receiver Sensitivity (Long Haul with cable loss) dB Jitter Attenuator Corner Frequency (-3dB curve) Return Loss: 51kHz - 102kHz 102kHz - 2048kHz 2048kHz - 3072kHz With nominal pulse amplitude of 3.0V for 100Ω termination 36 With nominal pulse amplitude of 3.0V for 100W termination 13 - kW 138 0.4 - - UIpp AT&T Pub 62411 - 9.8 0.1 KHz dB TR-TSY-000499 - 6 -Hz AT&T Pub 62411 - 20 25 25 Input Impedance Recovered Clock Jitter Transfer Corner Frequency Peaking Amplitude ITU-G.775, ETSI 300 233 0 dB dB Jitter Tolerance: 1Hz 10kHz - 100kHz Cable attenuation @772kHz - dB dB dB TABLE 44: E1 TRANSMIT RETURN LOSS REQUIREMENT RETURN LOSS FREQUENCY G.703/CH-PTT ETS 300166 51-102kHz 8dB 6dB 102-2048kHz 14dB 8dB 2048-3072kHz 10dB 8dB 86 xr XRT83L34 REV. 1.0.1 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR TABLE 45: E1 TRANSMITTER ELECTRICAL CHARACTERISTICS VDD=3.3V±5%, TA=-40° TO 85°C, UNLESS OTHERWISE SPECIFIED PARAMETER MIN. TYP. MAX. UNIT 2.185 2.76 2.37 3.00 2.555 3.24 V V Output Pulse Width 224 244 264 ns Output Pulse Width Ratio 0.95 - 1.05 - ITU-G.703 Output Pulse Amplitude Ratio 0.95 - 1.05 - ITU-G.703 - 0.025 0.05 UIpp 8 14 10 - - dB dB dB AMI Output Pulse Amplitude: 75W Application 120W Application Jitter Added by the Transmitter Output Output Return Loss: 51kHz -102kHz 102kHz-2048kHz 2048kHz-3072kHz TEST CONDITIONS Transformer with 1:2 ratio and 9.1W resistor in series with each end of primary. Broad Band with jitter free TCLK applied to the input. ETSI 300 166, CHPTT TABLE 46: T1 TRANSMITTER ELECTRICAL CHARACTERISTICS VDD=3.3V±5%, TA=-40° TO 85°C, UNLESS OTHERWISE SPECIFIED PARAMETER MIN. TYP. MAX. UNIT AMI Output Pulse Amplitude: 2.5 3.0 3.5 V Use transformer with 1:2.45 ratio and measured at DSX-1 Output Pulse Width 338 350 362 ns ANSI T1.102 Output Pulse Width Imbalance - - 20 - ANSI T1.102 Output Pulse Amplitude Imbalance - - +200 mV ANSI T1.102 Jitter Added by the Transmitter Output - 0.025 0.05 UIpp - 15 15 15 - dB dB dB Output Return Loss: 51kHz -102kHz 102kHz-2048kHz 2048kHz-3072kHz 87 TEST CONDITIONS Broad Band with jitter free TCLK applied to the input. xr XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 FIGURE 30. ITU G.703 PULSE TEMPLATE 10% 20% 269 ns (244 + 25) 194 ns (244 – 50) 20% 10% V = 100% Nominal pulse 50% 20% 10% 0% 10% 10% 219 ns (244 – 25) 10% 244 ns 488 ns (244 + 244) Note – V corresponds to the nominal peak value. TABLE 47: TRANSMIT PULSE MASK SPECIFICATION Test Load Impedance 75W Resistive (Coax) 120W Resistive (twisted Pair) 2.37V 3.0V 0 + 0.237V 0 + 0.3V 244ns 244ns 0.95 to 1.05 0.95 to 1.05 Nominal Peak Voltage of a Mark Peak voltage of a Space (no Mark) Nominal Pulse width Ratio of Positive and Negative Pulses Imbalance 88 xr XRT83L34 REV. 1.0.1 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR FIGURE 31. DSX-1 PULSE TEMPLATE (NORMALIZED AMPLITUDE) TABLE 48: DSX1 INTERFACE ISOLATED PULSE MASK AND CORNER POINTS MINIMUM CURVE MAXIMUM CURVE TIME (UI) NORMALIZED AMPLITUDE TIME (UI) NORMALIZED AMPLITUDE -0.77 -.05V -0.77 .05V -0.23 -.05V -0.39 .05V -0.23 0.5V -0.27 .8V -0.15 0.95V -0.27 1.15V 0.0 0.95V -0.12 1.15V 0.15 0.9V 0.0 1.05V 0.23 0.5V 0.27 1.05V 0.23 -0.45V 0.35 -0.07V 0.46 -0.45V 0.93 0.05V 0.66 -0.2V 1.16 0.05V 0.93 -0.05V 1.16 -0.05V 89 xr XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 TABLE 49: AC ELECTRICAL CHARACTERISTICS VDD=3.3V±5%, TA=25°C, UNLESS OTHERWISE SPECIFIED PARAMETER SYMBOL MIN. TYP. E1 MCLK Clock Frequency - 2.048 MHz T1 MCLK Clock Frequency - 1.544 MHz MCLK Clock Duty Cycle 40 - 60 % MCLK Clock Tolerance - ±50 - ppm TCDU 30 50 70 % Transmit Data Setup Time TSU 50 - - ns Transmit Data Hold Time THO 30 - - ns TCLK Rise Time(10%/90%) TCLKR - - 40 ns TCLK Fall Time(90%/10%) TCLKF - - 40 ns RCLK Duty Cycle RCDU 45 50 55 % Receive Data Setup Time RSU 150 - - ns Receive Data Hold Time RHO 150 - - ns RCLK to Data Delay RDY - - 40 ns RCLK Rise Time(10% to 90%) with 25pF Loading. RCLKR - - 40 ns RCLK Fall Time(90% to 10%) with 25pF Loading. RCLKF 40 ns TCLK Duty Cycle MAX. UNITS FIGURE 32. TRANSMIT CLOCK AND INPUT DATA TIMING TCLKR TCLK TPOS/TDATA or TNEG TSU THO 90 TCLKF xr XRT83L34 REV. 1.0.1 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR FIGURE 33. RECEIVE CLOCK AND OUTPUT DATA TIMING RCLKR RDY RCLKF RCLK RPOS or RNEG RHO MICROPROCESSOR INTERFACE I/O TIMING INTEL INTERFACE TIMING - ASYNCHRONOUS The signals used for the Intel microprocessor interface are: Address Latch Enable (ALE), Read Enable (RD), Write Enable (WR), Chip Select (CS), Address and Data bits. The microprocessor interface uses minimum external glue logic and is compatible with the timings of the 8051 or 80188 family of microprocessors. The interface timing shown in Figure 34 and Figure 36 is described in Table 50. FIGURE 34. INTEL ASYNCHRONOUS PROGRAMMED I/O INTERFACE TIMING R E A D O P E R A T IO N W R IT E O P E R A T IO N A LE _A S t0 t0 A D D R [6:0] V alid A ddress V alid A ddress t5 t5 CS D A TA [7:0] V alid D ata for R eadback D ata A vailable to W rite Into the LIU t1 R D _D S t3 W R _R /W t2 t4 R D Y _D TA C K 91 xr XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 TABLE 50: ASYNCHRONOUS MODE 1 - INTEL 8051 AND 80188 INTERFACE TIMING SYMBOL PARAMETER MIN MAX UNITS t0 Valid Address to CS Falling Edge 0 - ns t1 CS Falling Edge to RD Assert 65 - ns t2 RD Assert to RDY Assert - 50 ns RD Pulse Width (t2) 50 - ns t3 CS Falling Edge to WR Assert 65 - ns t4 WR Assert to RDY Assert - 50 ns WR Pulse Width (t2) 50 - ns CS Falling Edge to AS Falling Edge 0 - ns NA NA t5 Reset pulse width - both Motorola and Intel Operations (see Figure 36) t9 Reset pulse width 30 92 xr XRT83L34 REV. 1.0.1 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR MOTOROLA ASYCHRONOUS INTERFACE TIMING The signals used in the Motorola microprocessor interface mode are: Address Strobe (AS), Data Strobe (DS), Read/Write Enable (R/W), Chip Select (CS), Address and Data bits. The interface is compatible with the timing of a Motorola 68000 microprocessor family. The interface timing is shown in Figure 35 and Figure 36. The I/O specifications are shown in Table 51. FIGURE 35. MOTOROLA 68K ASYNCHRONOUS PROGRAMMED I/O INTERFACE TIMING R E A D O P E R A T IO N W R IT E O P E R A T IO N ALE _A S t0 t0 V a lid A d dress A D D R [6:0 ] V a lid A d dress t3 t3 CS Va lid D ata fo r R eadb ack D A TA [7:0] D ata Ava ilable to W rite In to the LIU t1 t1 R D _D S W R _R /W t2 R D Y _D TA C K t2 TABLE 51: ASYNCHRONOUS - MOTOROLA 68K - INTERFACE TIMING SPECIFICATION SYMBOL PARAMETER MIN MAX UNITS t0 Valid Address to CS Falling Edge 0 - ns t1 CS Falling Edge to DS Assert 65 - ns t2 DS Assert to DTACK Assert - 50 ns DS Pulse Width (t2) 50 - ns CS Falling Edge to AS Falling Edge 0 - ns NA t3 Reset pulse width - both Motorola and Intel Operations (see Figure 36) t9 Reset pulse width 30 FIGURE 36. MICROPROCESSOR INTERFACE TIMING - RESET PULSE WIDTH t9 Reset 93 xr XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 ORDERING INFORMATION PART NUMBER PACKAGE OPERATING TEMPERATURE RANGE XRT83L34IV 128 Pin TQFP(14x20x1.4mm) -40°C to +85°C PACKAGE DIMENSIONS - 14X20 MM, 128 PIN PACKAGE D D1 102 65 103 64 E1 128 E 39 A2 1 38 B e A α C A1 L Note: The control dimensions are the millimeter column INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX A 0.0551 0.0630 1.40 1.60 A1 0.0020 0.0059 0.05 0.15 A2 0.0531 0.0571 1.35 1.45 B 0.0067 0.0106 0.17 0.27 C 0.0035 0.0079 0.09 0.20 D 0.8583 0.8740 21.80 22.20 D1 0.7835 0.7913 19.90 20.10 E 0.6220 0.6378 15.80 16.20 E1 0.5472 0.5551 13.90 14.10 e 0.0197 BSC 0.50 BSC L 0.0177 0.0295 0.45 0.75 α 0o 7o 0o 7o 94 xr XRT83L34 REV. 1.0.1 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REVISIONS REVISION DESCRIPTION A1.0.1 thru A1.0.7 Advanced Versions P1.1.0 Preliminary release version P1.2.0 Added GHCI_n, SL_1, SL_0, EQG_1 and EQG_0 to Control Global Register 131. Separated Microprocessor description table by register number. Moved absolute maximum and Dc electrical characteristics before AC electrical characteristics. Replaced TBD’s in electrical ables. Reformated table of contents. P1.2.1 Added GAUGE1 and GAUGE0 to Control Global Register 131. Corrected control register binary bits. P1.2.2 Renamed FIFO pin to GAUGE, edited definition and edited defintion of JASEL[1:0] to reflect the FIFO size is selected by the jitter attenuator select. P1.2.3 Redefined bits D3, D2 and D0 of register 1, in combination these bits set the jitter attenuator path and FIFO size. P1.2.4 Corrected typos in figures 6 and 8. Added Jitter attenuator tables in microprocessor register tables. Modified microprocessor descrptions, timing diagrams and electrical characteristics. P1.2.5 Replaced GCHIE with Reserved in Tables 18, 23, 24,25. In the pin list description for INT, replace IMASK bit to a “1” with GIE bit to a “0”. P1.2.6 New description for bits D6 - D0 in Tables 27 - 34 Microprocessor Registers. P1.2.7 Revised Microprocessor interface timing diagrams and data. P1.2.8 Corrected microprocessor timing information and edited Redundancy section. P1.2.9 Edited section on RLOS for more detailed explanation. P1.3.0 Changed definition of TXON_n pin. RXON_n bit included in register tables. Rx transformer ratio changed from 2:1 to 1:1. Description of Arbitrary Pulse and Gap Clock support added. P1.3.1 Minor edits to block diagram, changed issue date to January, corrected register 67 in table 18, corrected table 37. P1.3.2 Swapped the function of µPTS1 and µPTS2. Replaced µProcessor timing diagrams and timing information, (Figures 29 and 30 -- Tables 49 and 50). P1.3.3 Updated the Power Consumption numbers. P1.3.4 Added the New E1 Arbitrary Pulse Feature. Added descriptions to the global registers. 1.0.0 Final Release. 1.0.1 Added Microprocessor Section. Removed Sychronous Microprocessor modes. 95 xr XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 NOTES: NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 2005 EXAR Corporation Datasheet February 2005. Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. 96

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