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XRT85L61
BITS (BUILDING INTEGRATED TIMING SUPPLY) CLOCK EXTRACTOR
OCTOBER 2004
REV. 1.0.2
GENERAL DESCRIPTION
The XRT85L61 is an integrated E1, T1, 64KHz
Centralized Clock interface for T1 (1.544Mbps) 100Ω,
E1 (2.048Mbps) 75Ω or 120Ω applications.
The XRT85L61 extracts either 2048kHz or 1544 kHz
clock signals from an E1 (2.048 MHz), T1 (1.544
Mhz) inputs respectively or 64 KHz, 8kHz or 400 Hz
clock signals from the 64kHz reference clock input.
The XRT85L61 includes an on-chip crystal-less jitter
attenuator with 32 bit FIFO that can either be enabled
or disabled.
FEATURES
• Fully integrated single chip solution for E1,T1 or 64
kHz clock synchronization applications.
• Extracts 2048 kHz, 1544 kHz clock and data
components
• Extracts 64 KHz and 8 kHz, 400 Hz clock
information
• On-chip digital clock recovery circuit
• Supports 75Ω and 120Ω (E1), 100Ω (T1)
applications.
• Crystal-less digital jitter attenuator with 32-bit FIFO
that can either be enabled or disabled
• Receive loss of signal (RLOS) output
• Meets Telcordia GR-1244-CORE Section 3.4.1 R327 specification
• Meets or exceeds T1 and E1 specifications in ITU
G.703, G.775
• Single +3.3V Supply Operation
• Logic inputs accept either 3.3 V or 5 V levels
• 28 pin TSSOP package
APPLICATIONS
• Universal Clock Synchronization for G.703 Telecom
Formats
• T1/E1 Line Receiver with Clock and Data Recovery
• DSLAM
• Line Code Violation alarms
FIGURE 1. BLOCK DIAGRAM OF THE XRT85L61
RCLKINV
DATA_INV
DATAMUT
JAEN
Reference Inputs
MCLK1
(1.544 MHz for T1)
Master Clock
Generator
MCLK2
(2.048 MHz for E1
or 64 kbps)
RTIP
Line Side
(T1 or E1 or 64 kbps input)
RRING
S1
S2
S3
Clock
Extractor
Rx
Equalizer
Mode Select
T1, E1 or 64 kbps
Peak Detector
and Slicer
Clock and
Data
Recovery
Jitter
Attenuator
LOS
Detector
RPOS
RNEG
RCLK
(64kHz,1544kHz or 2048kHz)
Line code
and clock
violation
Detector
8 kHz (for 64 kbps)
400 Hz (for 64 kbps)
RCLK_LCV/AIS
8 kHz_LCV/BPV
400 Hz_LCV
RLOS
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
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XRT85L61
BITS (BUILDING INTEGRATED TIMING SUPPLY) CLOCK EXTRACTOR
REV. 1.0.2
ORDERING INFORMATION
PART NUMBER
PACKAGE
OPERATING TEMPERATURE RANGE
XRT85L61IG
28 Lead TSSOP
-40°C to +85°C
FIGURE 2. PIN OUT OF THE XRT85L61
MCLK1
1
JAEN
2
MCLK2
MCLK1
1
28
MCLK2
2
27
JAEN
3
26
JAVDD
4
25
3
JAGND
5
24
ICT
6
23
JAVDD
4
RTIP
7
22
JAGND
5
RRING
8
21
AVDD
9
20
ICT
6
AGND
10
19
S1
11
18
S2
12
17
S3
13
16
14
15
RTIP
7
RCLKINV
28
RCLKINV
DATA_LCV
RCLK_LCV
27
DATA_INV
8 KHz_LCV
26400 Hz_LCV
RCLK_LCV/ AIS
8 KHz
25400 Hz 8 KHz_LCV/ BPV
RLOS
24
DVDD
DGND
23
400 Hz_LCV
8 KHz
RCLK
22RPOS 400 Hz
RNEG
21DATMUTRLOS
RRING
8
AVDD
9
20
DVDD
AGND
10
19
DGND
S1
11
18
RCLK
S2
12
17
RPOS
S3
13
16
RNEG
NC
14
15
DATMUT
NC
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XRT85L61
BITS (BUILDING INTEGRATED TIMING SUPPLY) CLOCK EXTRACTOR
REV. 1.0.2
TABLE OF CONTENTS
GENERAL DESCRIPTION................................................................................................. 1
APPLICATIONS ............................................................................................................................................... 1
FIGURE 1. BLOCK DIAGRAM OF THE XRT85L61 ............................................................................................................................... 1
ORDERING INFORMATION .................................................................................................................... 2
FIGURE 2. PIN OUT OF THE XRT85L61............................................................................................................................................ 2
PIN DESCRIPTIONS .......................................................................................................... 3
ELECTRICAL CHARACTERISTICS.................................................................................. 5
ABSOLUTE MAXIMUM RATINGS ............................................................................................................. 5
TABLE 1: DC Electrical Characteristics .................................................................................................. 5
TABLE 2: E1 RECEIVER SENSITIVITY................................................................................................................................................. 5
TABLE 3: T1 RECEIVER SENSITIVITY ................................................................................................................................................. 6
TABLE 4: 64KBITS/SEC RECEIVER SENSITIVITY ................................................................................................................................. 6
FIGURE 3. TIMING DIAGRAM FOR SYSTEM INTERFACE ....................................................................................................................... 6
TABLE 5: AC ELECTRICAL SPECIFICATIONS....................................................................................................................................... 7
FUNCTIONAL DESCRIPTION ........................................................................................... 8
1.0 OPERATING MODE: ............................................................................................................................. 8
TABLE 6: OPERATING MODE SELECTION ........................................................................................................................................... 8
1.1 64 KHZ CLOCK MODE: ................................................................................................................................... 8
TABLE 7: G.703 SPECIFICATION FOR THE 64 KHZ CLOCK SIGNAL AT INPUT PORT ............................................................................... 8
TABLE 8: G.703 SPECIFICATION FOR THE 64 KHZ CLOCK SIGNAL AT OUTPUT PORT ............................................................................ 9
1.1.1 64 KHZ + 8 KHZ CLOCK EXTRACTION ...................................................................................................................... 9
FIGURE 4. INPUT DATA 64 KHZ + 8 KHZ OPERATION (S1 = 0, S2 = 0, S3 = 0)................................................................................... 9
1.1.2 64 KHZ + 8 KHZ + 400 HZ CLOCK EXTRACTION ...................................................................................................... 9
FIGURE 5. INPUT DATA 64 KHZ + 8 KHZ + 400 HZ OPERATION (S1 = 0, S2 = 0, S3 = 1) ................................................................. 10
1.2 2048 KHZ RZ E1 MODE ................................................................................................................................. 10
FIGURE 6. E1 PULSE MASK (G.703) .............................................................................................................................................. 10
TABLE 9: G.703 SPECIFICATION E1 ............................................................................................................................................... 11
1.3 2048 KHZ NRZ MODE .................................................................................................................................... 12
FIGURE 7. E1 CLOCK SIGNAL WAVE SHAPE - G.703 ...................................................................................................................... 12
TABLE 10: G.703 2048 KHZ CLOCK INTERFACE ............................................................................................................................. 12
1.4 1544 KHZ T1 MODE ....................................................................................................................................... 13
FIGURE 8. G.703 DS1 WAVE FORM ............................................................................................................................................... 13
2.0
AIS DETECTION TIMING ................................................................................................................... 14
FIGURE 9. AIS DETECTION FOR E1 MODE ...................................................................................................................................... 14
FIGURE 10. AIS DETECTION FOR T1 MODE .................................................................................................................................... 14
3.0 LOSS OF SIGNAL ............................................................................................................................... 14
4.0 APPLICATIONS ................................................................................................................................... 15
FIGURE 11. CEPT APPLICATION FOR TWISTED PAIR INTERFACE ..................................................................................................... 15
FIGURE 12. CEPT APPLICATION FOR COAXIAL INTERFACE .............................................................................................................. 15
FIGURE 13. T1 APPLICATION FOR TWISTED PAIR INTERFACE........................................................................................................... 15
FIGURE 14. 64KBPS APPLICATION FOR TWISTED PAIR...................................................................................................................... 16
TRANSFORMER RECOMENDATION ................................................................................................................. 16
FIGURE 15. CONNECTING THE PULSE ENGINEERING PE-65535 1:2CT TRANSFORMER TO THE XRT85L61 ...................................... 16
ORDERING INFORMATION .................................................................................................................. 17
REVISION HISTORY ............................................................................................................................ 18
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XRT85L61
BITS (BUILDING INTEGRATED TIMING SUPPLY) CLOCK EXTRACTOR
REV. 1.0.2
PIN DESCRIPTIONS
PIN #
SYMBOL
TYPE
DESCRIPTION
1
MCLK1
I
Reference T1 Clock input:
This signal is an independent 1544 kHz clock with accuracy better than
+ 32 ppm and duty cycle within 40% to 60%. This clock provides timing
source for the PLL clock recovery circuit in T1 mode. This signal must be
available for the device to operate.
2
JAEN
I
Jitter Attenuator Enable:
Tie this pin “High” to enable the Jitter Attenuator. When enabled, a 32 bit
FIFO is included in the data path for all modes of operation.
NOTE: Internally Pulled down with 50 kΩ resistor
3
MCLK2
I
Reference E1 and 64 kHz Clock Input:
This signal is an independent 2048 kHz clock with accuracy better than +
50 ppm and duty cycle within 40% to 60%. This clock provides timing
source for the PLL clock recovery circuit in E1 and 64 kHz mode. This
signal must be available for the device to operate.
NOTE: To reduce intrinsic jitter when JA is enabled, it is recommended to
have reference clock with an accuracy of ± 25 ppm or better.
4
JAVDD
***
VDD for Jitter Attenuator (3.3V ± 5%)
5
JAGND
***
Jitter Attenuator Ground
6
ICT
I
In circuit Testing
When this pin is grounded, all output pins are Tri-stated for testing purposes.
NOTE: Internally Pulled up with 50 kΩ resistor
7
RTIP
I
Receive Positive Input
8
RRING
I
Receive Negative Input
9
AVDD
***
Analog VDD (3.3V ± 5%)
10
AGND
***
Analog Ground
11
S1
I
Mode Select
S1
S2
S3
0
0
0
64 kHz + 8 kHz
0
0
1
64kHz+8kHz+400Hz
0
1
0
E1 RZ
0
1
1
E1 NRZ
1
0
0
T1
1
0
1
T1 (output full width data)
1
1
0
E1
1
1
1
Reserved
MODE
(output full width data)
NOTE: T1 NRZ or E1 NRZ means the output data at RPOS and RNEG
are 1 RCLK wide.
3
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XRT85L61
BITS (BUILDING INTEGRATED TIMING SUPPLY) CLOCK EXTRACTOR
REV. 1.0.2
PIN DESCRIPTIONS
PIN #
SYMBOL
TYPE
DESCRIPTION
12
S2
I
Mode Select
13
S3
I
Mode Select
14
NC
***
15
DATMUT
I
This pin must be grounded for normal operation
Data Muting:
Connect this pin “High” to mute data output to “Low” state at RPOS/
RNEG. The RLOS pin can be connected to this pin to mute the output
when RLOS occurs.
NOTE: Internally Pulled down with 50 kΩ resistor
16
RNEG
O
Receive Negative Data Output:
The data is half clock cycle wide.
17
RPOS
O
Receive Positive Data Output:
The data is half clock cycle wide
18
RCLK
O
Receive Clock Output
Outputs either 1.544 MHz or 2.048 MHz or 64 kHz clock
19
DGND
***
Digital Supply Ground
20
DVDD
***
Digital Supply Voltage (3.3V ± 5%)
21
RLOS
O
Receive Loss of Signal Output
22
400Hz
O
400 Hz Clock output for 64 kHz Operation
23
8 kHz
O
8 kHz clock output for 64 kHz Operation
24
400Hz_LCV
O
Line Code Violation for 400 Hz
This pin will stay “High” when 400 Hz is not in sync.
25
8 kHz_LCV/
BPV
O
Line Code Violation for 8 kHz in 64 kHz operation
Bipolar Violation:
In E1RZ or T1 mode, every Bipolar violation valid or not valid is indicated
at this pin.
This pin will stay “High” when 8 kHz is not in sync.
26
RCLK_LCV/AIS
O
Receive Clock Violation.
In 64 kbps operation, every missing pulse will cause this pin to go “High”
for half the clock cycle
AIS Indication
In E1RZ or T1 mode, this output serves as an AIS indicator. AIS will stay
“High” for 250 µs in E1 RZ mode, and in T1 mode, AIS will stay “High” for
3 ms.
27
DATA_INV
I
Data Invert:
Connect this pin “High” to output active “Low” data at RPOS/RNEG.
NOTE: Internally Pulled down with 50 kΩ resistor
28
RCLK_INV
I
Receive Clock Invert:
Connect this pin “High” to align the data to change at the falling edge of
RCLK.
NOTE: Internally Pulled down with 50 kΩ resistor
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XRT85L61
BITS (BUILDING INTEGRATED TIMING SUPPLY) CLOCK EXTRACTOR
REV. 1.0.2
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
- 65°C to + 150°C
Operating Temperature
- 40°C to + 85°C
Supply Voltage Range
-0.5V to +6.0V
ESD
2000 V
Theta-JA
68°C/W
Theta-JC
13°C/W
TABLE 1: DC Electrical Characteristics
(TA = -40°C TO 85°C, VDD = 3.3 V + 5%, unless otherwise specified)
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNITS
VDDD
DC Supply Voltage (Digital)
3.135
3.3
3.465
V
VDDA
DC Supply Voltage (Analog)
3.135
3.3
3.465
V
42
50
mW
0.8
V
2.0
VDD
V
-
Power Consumption
VIL
Input Low Voltage
VIH
Input High Voltage
VOL
Output Low Voltage, IOUT = -4.0mA
0
0.4
V
VOH
Output High Voltage, IOUT = 4.0mA
2.4
VDD
V
±10
µA
IL
Input Leakage Current*
CI
Input Capacitance
CL
Output Load Capacitance
5
pF
25
NOTE: * Not applicable to pins with pull-down resistors.
TABLE 2: E1 RECEIVER SENSITIVITY
Vdd = 3.3V+5%, TA = -40°C to 85°C, Unless Otherwise Specified
PARAMETER
MIN
CABLE
LOSS
TYP
MAX
UNIT
TEST CONDITION
Receiver Sensitivity with PBRS
223-1 pattern
9
dB
9dB Cable Loss
6
dB
6dB Cable Loss + 6dB Flat Loss
NOTE: 0dB = 2.37Vp
4
dB
4dB Cable Loss + 8dB Flat Loss
5
pF
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XRT85L61
BITS (BUILDING INTEGRATED TIMING SUPPLY) CLOCK EXTRACTOR
REV. 1.0.2
TABLE 3: T1 RECEIVER SENSITIVITY
Vdd = 3.3V+5%, TA = -40°C to 85°C, Unless Otherwise Specified
MIN
CABLE
LOSS
PARAMETER
TYP
MAX
UNIT
TEST CONDITION
Receiver Sensitivity with PBRS
215-1 pattern
9
dB
9dB Cable Loss
6
dB
6dB Cable Loss + 6dB Flat Loss
NOTE: 0dB = 3.0Vp
4
dB
4dB Cable Loss + 8dB Flat Loss
TABLE 4: 64KBITS/SEC RECEIVER SENSITIVITY
Vdd = 3.3V+5%, TA = -40°C to 85°C, Unless Otherwise Specified
PARAMETER
MIN
TYP
MAX
UNIT
Receiver Sensitivity with Bipolar Violation Encoded "All 1’s"
Pattern
9
dB
9dB Cable Loss
6
dB
6dB Cable Loss + 6dB Flat Loss
4
dB
4dB Cable Loss + 8dB Flat Loss
NOTE: 0dB = 1.0Vp
FIGURE 3. TIMING DIAGRAM FOR SYSTEM INTERFACE
RClk tf
RClk tr
RClk
RPOS/RNEG
RZ Mode
tRp
tRp
RPOS/RNEG
NRZ Mode
tDS
tDH
6
TEST CONDITION
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XRT85L61
BITS (BUILDING INTEGRATED TIMING SUPPLY) CLOCK EXTRACTOR
REV. 1.0.2
TABLE 5: AC ELECTRICAL SPECIFICATIONS
Vdd = 3.3V+5%, TA = -40°C to 85°C, Unless Otherwise Specified
SYMBOL
MIN
TYP
MAX
UNITS
45
50
55
%
Receive Clock Rise/Fall time (10 - 90%)
-
3.0
-
ns
tRp
RClk to RPOS/RNEG Delay
0
-
10
ns
tDS
Receive Data Setup Time
20
-
-
ns
tDH
Receive Data Hold Time
20
-
-
ns
RClk tr/RClk tf
PARAMETER
Receive Clock Duty Cycle
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XRT85L61
BITS (BUILDING INTEGRATED TIMING SUPPLY) CLOCK EXTRACTOR
REV. 1.0.2
FUNCTIONAL DESCRIPTION
The XRT85L61 is an integrated BITS (Building Integrated Timing Supply) Clock Generator. Simplified block
diagram of the chip is shown in Figure 1.
The XRT85L61 extracts the clock signals from the following synchronization lines:
■
■
■
■
■
Balanced 100 Ω lines with 1544 kbps DS1 pattern.
Balanced 120 Ω or unbalanced 75 Ω lines with 2048 kbps RZ pattern.
Balanced 120 Ω or unbalanced 75 Ω line with 2048 kbps NRZ pattern.
Balanced 110 Ω line with 64 kbps having 8 kHz violations; a “64 kHz + 8 kHz sync pattern.
Balanced 110 Ω line with a 64 kbps pattern having both 8 kHz and 400 Hz violations; a “64 kHz + 8 kHz
+ 400 Hz” sync pattern.
1.0 OPERATING MODE:
The operating mode for the XRT85L61 is shown in Table 6.
TABLE 6: OPERATING MODE SELECTION
1.1
S1
S2
S3
MODE
DATA OUTPUT AT
RPOS / RNEG
0
0
0
64 kHz + 8 kHz
RZ
0
0
1
64 kHz + 8 kHz + 400 Hz
RZ
0
1
0
E1RZ
RZ
0
1
1
E1NRZ
RZ
1
0
0
T1
RZ
1
0
1
T1 (full width)
NRZ
1
1
0
E1 (full width)
NRZ
1
1
1
Reserved
64 kHz Clock Mode:
The XRT85L61 receives the 64 kbps ternary RZ signal. Two modes of 64 kHz operation is possible by
selecting S1, S2 and S3 as shown in Table 1.
TABLE 7: G.703 SPECIFICATION FOR THE 64 KHZ CLOCK SIGNAL AT INPUT PORT
FREQUENCY
Signal Format
Alarm Condition
(A) 64 KHZ + 8 KHZ OR (B) 64 KHZ + 8 KHZ + 400 HZ
(a) AMI with 8 kHz Bipolar Violation
(b) AMI with 8 kHz Bipolar Violation removed at every 400 Hz.
Alarm should not occur against the amplitude range from 0.63 V to 1.1 V
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XRT85L61
BITS (BUILDING INTEGRATED TIMING SUPPLY) CLOCK EXTRACTOR
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REV. 1.0.2
TABLE 8: G.703 SPECIFICATION FOR THE 64 KHZ CLOCK SIGNAL AT OUTPUT PORT
FREQUENCY
Load Impedance
(A) 64 KHZ + 8 KHZ OR (B) 64 KHZ + 8 KHZ + 400 HZ
110 Ω resistive
Transmission Media
Symmetric Pair Cable
Pulse Width (FWHM)
< 7.8 ± 0.78 µs
Amplitude
< 1 V ± 0.1 V
1.1.1
64 kHz + 8 kHz Clock Extraction
The input data is shown in Figure 4. The 64 kHz clock signal consist of AMI code with 8 kHz Bipolar Violation.
Both the 64 kHz and 8 kHz components are extracted from the composite received signal and presented at the
64 kHz and 8 kHz output pins.
FIGURE 4. INPUT DATA 64 KHZ + 8 KHZ OPERATION (S1 = 0, S2 = 0, S3 = 0)
Missing Pulse
RTIP/
RRING
Missing Pulse or Wrong Polarity Pulse
V
V
V
64kHz
Clock
Missing Pulse
RPOS
Not Valid Violation
RNEG
V
8kHz Clock
Missing Pulse
If Pulse Missing at RTIP/RRING
RClk_LCV
8kH_LCV
1.1.2
out of sync
Missing Pulse
Not Valid Violation
Missing Pulse or No Violation Bit
64 kHz + 8 kHz + 400 Hz Clock Extraction
Figure 4 shows the input data for this mode. The 64 kHz clock signal consist of AMI code with 8 kHz Bipolar
Violation removed every 400 Hz. The 64 kHz, 8 kHz and 400 Hz components are extracted from the composite
received signal and presented at the RClk, 8 kHz and 400 Hz output pins.
NOTE: The inputs are not aligned with all output signals. The above diagram is used to depict the output activity when the
input signals have errors.
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XRT85L61
BITS (BUILDING INTEGRATED TIMING SUPPLY) CLOCK EXTRACTOR
REV. 1.0.2
FIGURE 5. INPUT DATA 64 KHZ + 8 KHZ + 400 HZ OPERATION (S1 = 0, S2 = 0, S3 = 1)
nV
V1
V1
V2
125µ s
(8 kHz)
125µ s
(8 kHz)
V2
125µ s
(8 kHz)
nV
125µ s
(8 kHz)
(8 kHz)
(400 Hz)
(400 Hz)
LC V
if nV is
Missing
NOTES:
1.
1.2
V1 and V2 indicate AMI code-rule violations, and give the 8kHz timing.
2.
V1 and V2 have different violation polarity with respect to each other.
3.
nV indicates no violation (violation stealing) and gives the 400 Hz timing.
2048 kHz RZ E1 Mode
In this mode, the XRT85L61 receives a standard E1 signal as shown in Figure 6. Table 4 gives the details of
the E1 pulse.
FIGURE 6. E1 PULSE MASK (G.703)
19 4 ns
(2 4 4 – 5 0 )
20%
V = 10 0%
10%
10%
20%
26 9 ns
(2 4 4 + 2 5 )
N o m in a l p u ls e
50%
10%
20%
10%
10%
0%
21 9 ns
(2 4 4 – 2 5 )
10%
244 ns
488 ns
(2 4 4 + 2 4 4 )
N o te – V co r res p o n d s t o th e n o m in al p ea k v alu e.
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XRT85L61
BITS (BUILDING INTEGRATED TIMING SUPPLY) CLOCK EXTRACTOR
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REV. 1.0.2
TABLE 9: G.703 SPECIFICATION E1
PULSE
Pulse Shape (nominally rectangular)
Pair(s) in each direction
Test Load Impedance
INTERFACE
All Marks of a valid signal must conform with the mask irrespective of
the sign. The value V corresponds to the nominal peak value.
One coaxial pair
One symmetrical pair
75 Ω Resistive
120 Ω Resistive
2.37 V
3V
0 ± 0.237 V
0 ± 0.3 V
Nominal peak voltage of a mark (pulse)
Peak voltage of a space (no pulse)
Nominal Pulse Width
244 ns
Ratio of the amplitudes of positive and negative
pulses at the center of the pulse interval
0.95 to 1.05
Ratio of the widths of positive and negative
pulses at the nominal half amplitude
0.95 to 1.05
Maximum peak to peak jitter at an output port
Refer to ITU-T G.823 specification
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XRT85L61
BITS (BUILDING INTEGRATED TIMING SUPPLY) CLOCK EXTRACTOR
REV. 1.0.2
1.3
2048 kHz NRZ Mode
In this mode, XRT85L61 receives 2048 kbps synchronization signal as shown in Figure 7.
FIGURE 7. E1 CLOCK SIGNAL WAVE SHAPE - G.703
T
30
T
30
T
30
T
30
T
30
T
30
+ V
+ V 1
0
– V1
T
4
T
4
T
4
– V
T
4
T
T 1 8 1 8 9 0 0 -9 2
S h a d e d a r e a in w h ic h
s ig n a l s h o u ld b e
m o n o to n ic
T A v e r a g e p e rio d o f
s y n c h r o n iz in g s ig n a l
F IG U R E 2 1 /G .7 0 3
W a v e s h a p e a t a n o u tp u t p o rt
TABLE 10: G.703 2048 KHZ CLOCK INTERFACE
PULSE
INTERFACE
Frequency
2048 kHz ± 50 ppm
Pulse Shape
The signal must conform with the mask.
The value V corresponds to maximum peak value
The value V1 corresponds to minimum peak value
Pair(s) in each direction
Coaxial pair
Symmetrical pair
Test Load Impedance
75 Ω Resistive
120 Ω Resistive
Maximum peak value (Vop)
1.5
1.9
Minimum peak value (Vop)
0.75
1.0
Maximum jitter at an output port
0.05 UI peak to peak measured within the frequency range f1 = 20 Hz
to f4 = 100 kHz
NOTE: This value is valid for network timing distribution equipment.
Other values may be specified for timing output ports of digital
links carrying the network timing.
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BITS (BUILDING INTEGRATED TIMING SUPPLY) CLOCK EXTRACTOR
1.4
REV. 1.0.2
1544 kHz T1 Mode
In this mode, the XRT85L61 receives a standard DS1 signal as shown in Figure 8.
FIGURE 8. G.703 DS1 WAVE FORM
N o r m a l iz e d a m p li tu d e
1 .5
1 .0
0 .5
0
– 0 .5
– 1 .0
– 1 .0
– 0 .5
0
0 .5
1 .0
1 .5
T 1 5 2 8 6 7 0 -9 8
T im e , i n U n i t I n t e r v a l s
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BITS (BUILDING INTEGRATED TIMING SUPPLY) CLOCK EXTRACTOR
REV. 1.0.2
2.0
AIS DETECTION TIMING
In E1 mode, AIS is set when the received incoming signal has 2 or less Zero’s in a sequence of 512 bits. AIS
will stay “High” for 250 µs and AIS is cleared upon receiving three or more Zero’s in the subsequent 512 bits
(250µs) time-frame. Figure 9 shows the AIS timing.
FIGURE 9. AIS DETECTION FOR E1 MODE
250µs
250µs
E1
DATA
0
0
0
0
0
AIS
In T1 mode, AIS is detected if the received input signal has 4 or less Zero’s in a sequence of 4632 bits (3ms)
and AIS is cleared when 5 or more Zero’s are detected in the subsequent 4632 bits (3 ms) time-frame.
Figure 10 shows the AIS timing for T1 mode.
FIGURE 10. AIS DETECTION FOR T1 MODE
3 ms
3 ms
T1
DATA
0
0
0
0
0
0
0
0
0
AIS
3.0 LOSS OF SIGNAL
The XRT85L61 Receive Loss of Signal (RLOS) monitoring circuits consist of both analog and digital schemes.
Both E1 and T1 meet G.775 RLOS declare and clear criteria. In E1 and 64kb/s modes, RLOS will be set if the
input pattern exceeds 32 bit consecutive zeros. In T1 mode, RLOS will go "High" if the number of consecutive
zeros exceeds 175.
The XRT85L61 RLOS detection circuit also reports RLOS if the input signal level drops below 220mVp (typical)
and RLOS is cleared when the input signal level returns to more than 380mVp (typical) when the input pattern
meets 12.5% density over a 32 bit period.
14
xr
XRT85L61
BITS (BUILDING INTEGRATED TIMING SUPPLY) CLOCK EXTRACTOR
REV. 1.0.2
4.0 APPLICATIONS
FIGURE 11. CEPT APPLICATION FOR TWISTED PAIR INTERFACE
1:1
RPOS
RNEG
RxClk
RTP
120 Ω
Twisted Pair
Receive
Input
+3.3V
RRing
XRT59L81
BITS
Clock Extractor
DVDD
AVDD
0.1
uF
+
10
uF
FIGURE 12. CEPT APPLICATION FOR COAXIAL INTERFACE
1:1
RPOS
RNEG
RxClk
RTP
75 Ω
75 Ω Coaxial
Receive
Input
+3.3V
RRing
XRT59L81
BITS
Clock Extractor
DVDD
AVDD
0.1
uF
+
10
uF
FIGURE 13. T1 APPLICATION FOR TWISTED PAIR INTERFACE
1:1
RTP
Twisted Pair
100 Ω
Receive
Input
RRing
XRT59L81
BITS
Clock Extractor
15
RPOS
RNEG
RxClk
+3.3V
DVDD
AVDD
0.1
uF
10
uF
+
xr
REV. 1.0.2
XRT85L61
BITS (BUILDING INTEGRATED TIMING SUPPLY) CLOCK EXTRACTOR
FIGURE 14. 64KBPS APPLICATION FOR TWISTED PAIR
1:1
RPOS
RNEG
RxClk
RTP
110 Ω
Twisted Pair
Receive
Input
+3.3V
RRing
XRT59L81
BITS
Clock Extractor
DVDD
AVDD
0.1
uF
10
uF
+
TRANSFORMER RECOMENDATION
For all applications a 1:1 transformer ratio is required. 64kbps applications require a larger Inductance
transformer. Although E1 and T1 can use lower inductance transformers, Exar reccomends the use of the
PULSE ENGINEERING PE-65535 1:2CT transformer in a 1:1 mode by using pins 1 & 3 for the Line input and
Pins 6 & 5 as the secondary input to the XRT85L61. See Figure 15 below. Smaller transformers will be
evaluated in the future and recommendations will be published at that time.
FIGURE 15. CONNECTING THE PULSE ENGINEERING PE-65535 1:2CT TRANSFORMER TO THE XRT85L61
6
1
to
XRT59L81
to Line
Input
5
3
PE-65535
16
4
leave open
xr
XRT85L61
BITS (BUILDING INTEGRATED TIMING SUPPLY) CLOCK EXTRACTOR
REV. 1.0.2
ORDERING INFORMATION
PART NUMBER
PACKAGE
OPERATING TEMPERATURE RANGE
XRT85L61IG
28 Lead TSSOP
-40°C to +85°C
PACKAGE OUTLINE DRAWING
D
28
15
E1 E
14
1
C
Seating
Plane
A
A2
B
e
α
A1
L
Note: The control dimension is in the millimeter column
INCHES
SYMBOL
MIN
MILLIMETERS
MAX
MIN
MAX
A
0.033
0.047
0.85
1.20
A1
0.002
0.006
0.05
0.15
A2
0.031
0.041
0.80
1.05
B
0.007
0.012
0.19
0.30
C
0.004
0.008
0.09
0.20
D
0.378
0.386
9.60
9.80
E
0.248
0.260
6.30
6.60
E1
0.169
0.177
4.30
4.50
e
0.0256 BSC
0.65 BSC
L
0.018
0.030
0.45
0.75
α
0°
8°
0°
8°
17
xr
XRT85L61
BITS (BUILDING INTEGRATED TIMING SUPPLY) CLOCK EXTRACTOR
REV. 1.0.2
REVISION HISTORY
REVISION #
DATE
CHANGES
1.0.0
January 2004
Final Release
1.0.1
February 2004
Added description for MCLK1 and MCLK2
1.0.2
October 2004
Modified applications drawings. Added RLOS description. Added AC Electrical
characteristics. Added description for T1 AIS detection.
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to
improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any
circuits described herein, conveys no license under any patent or other right, and makes no representation that
the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration
purposes and may vary depending upon a user’s specific application. While the information in this publication
has been carefully checked; no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the
failure or malfunction of the product can reasonably be expected to cause failure of the life support system or
to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless
EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has
been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately
protected under the circumstances.
Copyright 2004 EXAR Corporation
Datasheet October 2004.
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
18
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