XRT91L31
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
SEPTEMBER 2018
REV. 1.0.3
GENERAL DESCRIPTION
synchronize the transmit section timing. The device
can internally monitor Loss of Signal (LOS) condition
and automatically mute received data upon LOS. An
on-chip SONET/SDH frame byte and boundary
detector and frame pulse generator offers the ability
recover SONET/SDH framing and to byte align the
receive serial data stream into the 8-bit parallel bus.
The XRT91L31 is a fully integrated SONET/SDH
transceiver for SONET/SDH 622.08 Mbps STS-12/
STM-4 or 155.52 Mbps STS-3/STM-1 applications.
The transceiver includes an on-chip Clock Multiplier
Unit (CMU), which uses a high frequency PhaseLocked Loop (PLL) to generate the high-speed
transmit serial clock from a slower external clock
reference. It also provides Clock and Data Recovery
(CDR) function by synchronizing its on-chip Voltage
Controlled Oscillator (VCO) to the incoming serial
data stream. The internal CDR unit can be disabled
and bypassed in lieu of an externally recovered
received clock from the optical module. Either the
internally recovered clock or the externally recovered
clock can be used for loop timing applications. The
chip provides serial-to-parallel and parallel-to-serial
converters using an 8-bit wide LVTTL system
interface in both receive and transmit directions.
The transmit section includes an option to accept a
parallel clock signal from the framer/mapper to
APPLICATIONS
SONET/SDH-based Transmission Systems
Add/Drop Multiplexers
Cross Connect Equipment
ATM and Multi-Service Switches, Routers and
Switch/Routers
DSLAMS
SONET/SDH Test Equipment
DWDM Termination Equipment
FIGURE 1. BLOCK DIAGRAM OF XRT91L31
STS-12/STM-4 or STS-3/STM-1
TRANSCEIVER
PISO
(Parallel Input
Serial Output)
TXDI[7:0]
8
TXOP/N
Re-Timer
ENB
MUX
ENB
TXPCLK_IO
Div by
8
XOR
REFCLKP/N
TTLREFCLK
CMU
MUX
SIPO
(Serial Input
Parallel Output)
RXDO[7:0]
ALOOP
DLOOP
MUX
CDRAUXREFCLK
RLOOPS
CDR
RXIP/N
MUX
8
XRXCLKIP/N
Div by 8
1
CDRDIS
PIO_CTRL
CDRREFSEL
CMUFREQSEL
LOSEXT
DLOSDIS
Clock Control
OOF
FRAMEPULSE
ALOOP
LOOPTIME
Reset
STS-12/STS-3
CAP2N
CAP2P
CAP1N
CAP1P
DLOOP
Control Block
Loop Filters
RLOOPS
RXPCLKO
XRT91L31
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
REV. 1.0.3
FEATURES
Targeted for SONET STS-12/STS-3 and SDH STM-4/STM-1 Applications
Selectable full duplex operation between STS-12/STM-4 standard rate of 622.08 Mbps or STS-3/STM-1
155.52 Mbps
Single-chip fully integrated solution containing parallel-to-serial converter, clock multiplier unit (CMU), serialto-parallel converter, clock data recovery (CDR) functions, and a SONET/SDH frame and byte boundary
detection circuit
Ability to disable and bypass onchip CDR for external based received reference clock recovery thru
Differential LVPECL input pins XRXCLKIP/N
8-bit LVTTL parallel data bus paths running at 77.76 Mbps in STS-12/STM-4 or 19.44 Mbps in STS-3/STM-1
mode of operation
Uses Differential LVPECL or Single-Ended LVTTL CMU reference clock frequencies of either 19.44 MHz or
77.76 MHz for both STS-12/STM-1 or STS-3/STM-1 operations
Optional use of 77.76 MHz Single-Ended LVTTL input for independent CDR reference clock operation
Able to Detect and Recover SONET/SDH frame boundary and byte align received data on the parallel bus
Diagnostics features include LOS monitoring and automatic received data mute upon LOS
Provides Local, Remote and Split Loop-Back modes as well as Loop Timing mode
Optional flexibility to re-configure the transmit parallel bus clock output to a clock input and accept timing
signal from the framer/mapper device to permit the framer/mapper device time domain to be synchronized
with the transceiver transmit timing.
Meets Telcordia, ANSI and ITU-T G.783 and G.825 SDH jitter requirements including T1.105.03 - 2002
SONET Jitter Tolerance specification, Bellcore TR-NWT-000253 and GR-253-CORE, GR-253 ILR SONET
Jitter specifications.
Complies with ANSI/TIA/EIA-644 and IEEE P1596.3 3.3V LVDS standard, 3.3V LVPECL, and JESD 8-B
LVTTL and LVCMOS standard.
Operates at 3.3V with 3.3V I/O
Less than 660mW in STS-3/STM-1 mode or 800mW in STS-12/STM-4 mode Typical Power Dissipation
Package: 10 x 10 x 2.0 mm 64-pin QFP
2
XRT91L31
REV. 1.0.3
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
49
5049
5150
5251
5352
5453
5554
5655
5756
5857
5958
6059
6160
6261
6362
6463
64
1
1 2
2 3
3 4
4 5
5 6
6 7
7 8
8 9
9 10
10 11
11 12
12 13
13 14
14 15
15 16
16
XRT91L30
XRT91L31
32
3132
3031
2930
2829
2728
2627
2526
2425
2324
2223
2122
2021
1920
1819
1718
17
AGND
FL_2
CDRAUXREFCLK
STS1_2
VDD3.3
DJA_2/CS
FRAMEPULSE
MCLK_2
RXPCLKO
GND
GND
RXDO7
RCLK_2
RXDO6
VDD
RXDO5
RNEG_2
RXDO4
RPOS_2
RXDO3
GND
RXDO2
DJA_0/SCLK
GND
DS3/E3_0
RXDO1
STS1_0
RXDO0
FL0
VDD3.3
AGND
REFCLKN
RESET
RESET
LOOPTM_NOJA
LOOPTIME
CMUFREQSEL
CMUFREQSEL
VDD_PECL
VDD_PECL
TXOP
TXOP
TXON
TXON
LOSDDIS
DLOSDIS
EXTRXCLKIP
XRXCLKIP
EXTRXCLKIN
XRXCLKIN
VDD_PECL
VDD_PECL
OOF
OOF
CDRDIS
CDRDIS
RXIP
RXIP
RXIN
RXIN
VDD3.3
VDD/CDR_BW
REFCLKP
REFCLKP
AGND
TXPCLK_IO
FL1
TXDI7
STS1_1
TXDI6
MCLK_1
GND
GND
TXDI5
RCLK_1
TXDI4
RPOS_1
TXDI3
RNEG_1
TXDI2
VDD
TXDI1
RNEG_0
TXDI0
RPOS_0
STS12/STS3
RCLK_0
CDRREFSEL
GND
VDD3.3
MCLK_0
DLOOP
DJA_1/SDI
RLOOPS
AGND
ALOOP
48
48 47
47 46
46 45
45 44
44 43
43 42
42 41
41 40
40 39
39 38
38 37
37 36
36 35
35 34
34 33
33
AVDD
PIO_CTRL
GND
VDD3.3
RRCLK_1
GND
RRPOS_1
GND
RRNEG_1
AGND_RX
RCLKES
AVDD3.3_RX
NC
CAP2P
VDD
CAP2N
DS3/E3_2
CAP1N
SDO
CAP1P
FSS
AVDD3.3_TX
RRNEG_2
AGND_TX
RRPOS_2
TTLREFCLK
RRCLK_2
GND
GND
VDD3.3
AVDD
LOSEXT
FIGURE 2. 64 QFP PIN OUT OF THE XRT91L31 (TOP VIEW)
TABLE 1: ORDERING INFORMATION(1)
PART NUMBER
OPERATING TEMPERATURE RANGE
LEAD-FREE
PACKAGE
PACKAGING METHOD
XRT91L31IQ-F
-40°C to +85°C
Yes(2)
64 Pin Lead QFP
Tray
NOTES:
1. Refer to www.exar.com/XRT91L31 for most up-to-date Ordering Information.
2. Visit www.exar.com for additional information on Environmental Rating.
3
XRT91L31
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
REV. 1.0.3
GENERAL DESCRIPTION .................................................................................................1
APPLICATIONS ...........................................................................................................................................1
FIGURE 1. BLOCK DIAGRAM OF XRT91L31 ...................................................................................................................................... 1
FEATURES ......................................................................................................................................................2
FIGURE 2. 64 QFP PIN OUT OF THE XRT91L31 (TOP VIEW)............................................................................................................ 3
TABLE 1: ORDERING INFORMATION ................................................................................................................................................... 3
PIN DESCRIPTIONS ..........................................................................................................6
.....................................................................................................................................................................6
TABLE 2: HARDWARE CONTROL ....................................................................................................................................................... 6
TRANSMITTER SECTION ..................................................................................................................................9
RECEIVER SECTION ......................................................................................................................................11
POWER AND GROUND ..................................................................................................................................12
1.0 FUNCTIONAL DESCRIPTION .............................................................................................................14
1.1 STS-12/STM-4 AND STS-3/STM-1 MODE OF OPERATION ......................................................................... 14
1.2 CLOCK INPUT REFERENCE FOR CLOCK MULTIPLIER (SYNTHESIZER) UNIT ...................................... 14
TABLE 3: CMU REFERENCE FREQUENCY OPTIONS (DIFFERENTIAL OR SINGLE-ENDED) ................................................................... 14
1.3 DATA LATENCY ............................................................................................................................................. 14
TABLE 4: DATA INGRESS TO DATA EGRESS LATENCY ....................................................................................................................... 14
2.0 RECEIVE SECTION .............................................................................................................................15
2.1 RECEIVE SERIAL INPUT ............................................................................................................................... 15
FIGURE 3. RECEIVE SERIAL INPUT INTERFACE BLOCK ..................................................................................................................... 15
2.2 RECIEVE SERIAL DATA INPUT TIMING ...................................................................................................... 16
FIGURE 4. RECEIVE HIGH-SPEED SERIAL DATA INPUT TIMING DIAGRAM .......................................................................................... 16
TABLE 5: RECEIVE HIGH-SPEED SERIAL DATA INPUT TIMING (STS-12/STM-4 OPERATION) ............................................................. 16
TABLE 6: RECEIVE HIGH-SPEED SERIAL DATA INPUT TIMING (STS-3/STM-1 OPERATION) ............................................................... 16
...................................................................................................................................................................16
2.3 RECEIVE CLOCK AND DATA RECOVERY .................................................................................................. 17
TABLE 7: CLOCK DATA RECOVERY UNIT REFERENCE CLOCK SETTINGS ............................................................................................ 17
TABLE 8: CDR AUXREFCLK REFERENCE FREQUENCY REQUIREMENT FOR CLOCK AND DATA RECOVERY ..................................... 17
2.3.1 INTERNAL CLOCK AND DATA RECOVERY BYPASS ............................................................................................ 17
FIGURE 5. INTERNAL CLOCK AND DATA RECOVERY BYPASS ............................................................................................................ 18
2.4 EXTERNAL RECEIVE LOOP FILTER CAPACITORS ................................................................................... 19
FIGURE 6. EXTERNAL LOOP FILTERS .............................................................................................................................................. 19
2.5 LOSS OF SIGNAL .......................................................................................................................................... 19
FIGURE 7. LOS DECLARATION CIRCUIT .......................................................................................................................................... 19
2.6 SONET FRAME BOUNDARY DETECTION AND BYTE ALIGNMENT RECOVERY .................................... 20
2.7 RECEIVE SERIAL INPUT TO PARALLEL OUTPUT (SIPO) ......................................................................... 20
FIGURE 8. SIMPLIFIED BLOCK DIAGRAM OF SIPO ........................................................................................................................... 20
2.8 RECEIVE PARALLEL OUTPUT INTERFACE ............................................................................................... 21
FIGURE 9. RECEIVE PARALLEL OUTPUT INTERFACE BLOCK ............................................................................................................. 21
2.9 DISABLE PARALLEL RECEIVE DATA OUTPUT UPON LOS ..................................................................... 21
2.10 RECEIVE PARALLEL DATA OUTPUT TIMING .......................................................................................... 22
FIGURE 10. RECEIVE PARALLEL OUTPUT TIMING ............................................................................................................................ 22
TABLE 9: RECEIVE PARALLEL DATA OUTPUT TIMING (STS-12/STM-4 OPERATION) ......................................................................... 22
TABLE 10: RECEIVE PARALLEL DATA OUTPUT TIMING (STS-3/STM-1 OPERATION) ......................................................................... 22
TABLE 11: PECL AND TTL RECEIVE OUTPUTS TIMING SPECIFICATION ............................................................................................ 23
3.0 TRANSMIT SECTION ..........................................................................................................................24
3.1 TRANSMIT PARALLEL INPUT INTERFACE ................................................................................................. 24
FIGURE 11. TRANSMIT PARALLEL INPUT INTERFACE BLOCK ............................................................................................................. 24
3.2 TRANSMIT PARALLEL DATA INPUT TIMING .............................................................................................. 25
FIGURE 12. TRANSMIT PARALLEL INPUT TIMING .............................................................................................................................. 25
TABLE 12: TRANSMIT PARALLEL DATA INPUT TIMING (STS-12/STM-4 OPERATION)......................................................................... 25
...................................................................................................................................................................25
TABLE 13: TRANSMIT PARALLEL DATA INPUT TIMING (STS-3/STM-1 OPERATION)........................................................................... 25
...................................................................................................................................................................25
3.3 ALTERNATE TRANSMIT PARALLEL BUS CLOCK INPUT OPTION .......................................................... 26
FIGURE 13. ALTERNATE TRANSMIT PARALLEL INPUT INTERFACE BLOCK (PARALLEL CLOCK INPUT OPTION) ...................................... 26
3.4 ALTERNATE TRANSMIT PARALLEL DATA INPUT TIMING ....................................................................... 26
FIGURE 14. ALTERNATE TRANSMIT PARALLEL INPUT TIMING ............................................................................................................ 26
TABLE 14: ALTERNATE TRANSMIT PARALLEL DATA INPUT TIMING (STS-12/STM-4 OPERATION) ...................................................... 27
...................................................................................................................................................................27
4
XRT91L31
REV. 1.0.3
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
TABLE 15: ALTERNATE TRANSMIT PARALLEL DATA INPUT TIMING (STS-3/STM-1 OPERATION). ....................................................... 27
................................................................................................................................................................... 27
3.5 TRANSMIT PARALLEL INPUT TO SERIAL OUTPUT (PISO) ...................................................................... 27
FIGURE 15. SIMPLIFIED BLOCK DIAGRAM OF PISO ......................................................................................................................... 27
3.6 CLOCK MULTIPLIER UNIT (CMU) AND RE-TIMER ..................................................................................... 28
TABLE 16: CLOCK MULTIPLIER UNIT REQUIREMENTS FOR REFERENCE CLOCK .................................................................................. 28
3.7 LOOP TIMING AND CLOCK CONTROL ....................................................................................................... 29
TABLE 17: LOOP TIMING AND CLOCK RECOVERY CONFIGURATIONS ................................................................................................. 29
FIGURE 16. LOOP TIMING MODE USING INTERNAL CDR OR AN EXTERNAL RECOVERED CLOCK ....................................................... 30
3.8 TRANSMIT SERIAL OUTPUT CONTROL ..................................................................................................... 30
FIGURE 17. TRANSMIT SERIAL OUTPUT INTERFACE BLOCK .............................................................................................................. 30
4.0 DIAGNOSTIC FEATURES ................................................................................................................... 31
4.1 SERIAL REMOTE LOOPBACK ..................................................................................................................... 31
FIGURE 18. SERIAL REMOTE LOOPBACK ......................................................................................................................................... 31
4.2 DIGITAL LOCAL LOOPBACK ....................................................................................................................... 31
FIGURE 19. DIGITAL LOCAL LOOPBACK ........................................................................................................................................... 31
4.3 ANALOG LOCAL LOOPBACK ...................................................................................................................... 32
FIGURE 20. ANALOG LOCAL LOOPBACK .......................................................................................................................................... 32
4.4 SPLIT LOOPBACK ......................................................................................................................................... 32
FIGURE 21. SPLIT LOOPBACK ......................................................................................................................................................... 32
4.5 EYE DIAGRAM ............................................................................................................................................... 33
FIGURE 22. TRANSMIT ELECTRICAL OUTPUT EYE DIAGRAM............................................................................................................. 33
4.6 SONET JITTER REQUIREMENTS ................................................................................................................. 33
4.6.1 JITTER TOLERANCE: ................................................................................................................................................ 33
FIGURE 23. GR-253 JITTER TOLERANCE MASK .............................................................................................................................. 34
TABLE 18: XRT91L31 RECEIVER JITTER TOLERANCE PERFORMANCE ............................................................................................. 34
FIGURE 24. JITTER TOLERANCE FOR OC-12 WITH HIGH BANDWIDTH AND LOW BANDWIDTH SETTINGS ............................................ 35
FIGURE 25. JITTER TOLERANCE FOR OC-3 WITH HIGH BANDWIDTH AND LOW BANDWIDTH SETTINGS .............................................. 35
4.6.2 JITTER TRANSFER .................................................................................................................................................... 35
FIGURE 26. JITTER TRANSFER FOR OC-12 .................................................................................................................................... 36
FIGURE 27. JITTER TRANSFER FOR OC-3 ...................................................................................................................................... 36
4.6.3 JITTER GENERATION................................................................................................................................................ 36
TABLE 19: XRT91L31 OPTICAL JITTER GENERATION USING 223-1 PRBS PATTERN ........................................................................ 37
TABLE 20: XRT91L31 OPTICAL JITTER GENERATION USING 223-1 PRBS PATTERN USING ALTERNATE STANDARD FILTERS ............. 37
5.0 ELECTRICAL CHARACTERISTICS ................................................................................................... 37
ABSOLUTE MAXIMUM RATINGS .................................................................................................................. 37
ABSOLUTE MAXIMUM POWER AND INPUT/OUTPUT RATINGS ......................................................... 37
POWER AND CURRENT DC ELECTRICAL CHARACTERISTICS .................................................................... 38
................................................................................................................................................................... 38
LVPECL AND LVTTL LOGIC SIGNAL DC ELECTRICAL CHARACTERISTICS...................................... 39
FIGURE 28. DIFFERENTIAL VOLTAGE SWING DEFINITIONS (INPUT OR OUTPUT) FOR CLOCK AND DATA ................................................. 40
ORDERING INFORMATION .................................................................................................................. 40
.......................................................................................................................................... 40
MECHANICAL DIMENSIONS .......................................................................................... 40
FIGURE 29. PACKAGE DIMENSIONS ................................................................................................................................................ 40
................................................................................................................................................................... 41
TABLE 21: REVISION HISTORY TABLE ............................................................................................................................................. 41
5
XRT91L31
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
REV. 1.0.3
PIN DESCRIPTIONS
TABLE 2: HARDWARE CONTROL
PIN DESCRIPTION
NAME
LEVEL
TYPE
PIN
DESCRIPTION
RESET
LVTTL,
LVCMOS
I
1
Master Reset Input
Active "High." When this pin is pulled "High" , the internal state
machines are set to their default state.
"Low" = Normal Operation
"High" = Master Hardware Reset
STS12/STS3
LVTTL,
LVCMOS
I
59
Data Rate Selection
Selects SONET/SDH transmission and reception speed rate
"Low" = STS-3/STM-1 155.52 Mbps
"High" = STS-12/STM-4 622.08 Mbps
CMUFREQSEL
LVTTL,
LVCMOS
I
3
Clock Multiplier Unit Reference Frequency Select
This pin is used to select the frequency of the REFCLKP/N or
TTLREFCLK input to the CMU.
"Low" = 77.76 MHz reference clock
"High" = 19.44 MHz reference
clock
CMUFREQSEL
STS12/
STS3
REFCLKP/N OR
TTLREFCLK
REFERENCE
DATA RATE
FREQUENCY
0
0
77.76 MHz
STS-3/STM-1
155.52 Mbps
0
1
77.76 MHz
STS-12/STM-4
622.08 Mbps
1
0
19.44 MHz
STS-3/STM-1
155.52 Mbps
1
1
19.44 MHz
STS-12/STM-4
622.08 Mbps
NOTE: REFCLKP/N or TTLREFCLK input should be generated
from an LVPECL/LVTTL crystal oscillator which has a
frequency accuracy better than 20ppm in order for the
transmitted data rate frequency to have the necessary
accuracy required for SONET systems..
CDR_BW/VDD
LVTTL,
LVCMOS
I
15
CDR Bandwidth Select
This pin is used to select the CDR Bandwidth
"Low" = Narrow BW, (Meets SONET jitter transfer requirement)
"High" (VDD) = Wide Band Width.
6
XRT91L31
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
REV. 1.0.3
PIN DESCRIPTION
NAME
LEVEL
TYPE
PIN
DESCRIPTION
CDRREFSEL
LVTTL,
LVCMOS
I
60
Clock and Data Recover Unit Reference Frequency Select
Selects the Clock and Data Recovery Unit reference frequency
based on the table below.
"Low" = CDR uses CMU’s reference clock
"High" = CDR reference clock from CDRAUXREFCLK
CDRREFSEL
STS12/
STS3
0
NOTE:
CDRAUXREFCLK Frequency
Data Rate
CDR uses CMU’s reference clock
(see CMUFREQSEL pin)
1
0
77.76 MHz
STS-3/STM-1
155.52 Mbps
1
1
77.76 MHz
STS-12/STM-4
622.08 Mbps
CDRAUXREFCLK requires accuracy of 77.76 MHz
200 ppm.
LOOPTIME
LVTTL,
LVCMOS
I
2
Loop Timing Mode
When the loop timing mode is activated the external reference
clock to the input of the Retimer is replaced with the high-speed
recovered receive clock from the CDR.
"Low" = Disabled
"High" = Loop timing Activated
CDRDIS
LVTTL,
LVCMOS
I
12
Clock and Data Recovery Unit Disable
Active "High." Disables internal Clock and Data Recovery unit.
Received serial data bypasses the integrated CDR block.
RXINP/N is then sampled on the rising edge of externally
recovered differential clock XRXCLKIP/N coming from the optical module.
"Low" = Internal CDR unit is Enabled
"High" = Internal CDR unit is Disabled and Bypassed
7
XRT91L31
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
REV. 1.0.3
PIN DESCRIPTION
NAME
LEVEL
TYPE
PIN
DESCRIPTION
PIO_CTRL
LVTTL,
LVCMOS
I
48
Transmit Parallel Clock Directional Control
Transmit Parallel Clock Output Operation
If this pin is asserted "High", TXPCLK_IO is a parallel bus clock
output. Data on the TXDI[7:0] must be synchronously applied
prior to the sampling by the PISO at the rising edge of TXPCLK_IO clock output driven by the XRT91L31.
Alternate Transmit Parallel Clock Input Operation
Asserting this control pin "Low" or if left unconnected, it configures TXPCLK_IO to serve as a parallel bus clock input rather
than a parallel bus clock output and permits the XRT91L31 to
accept the external clock input. Data on the TXDI[7:0] is then
sampled at the rising edge of the TXPCLK_IO clock input
driven by the framer/mapper device.
"Low" = TXPCLK_IO is a Parallel Clock Input.
"High" = TXPCLK_IO is a Parallel Clock Output.
NOTE:
Parallel Clock Input operation has the advantage of
permitting the framer/mapper device timing to be
synchronized with the transceiver transmitter timing.
This pin is provided with an internal pull-down.
RLOOPS
LVTTL,
LVCMOS
I
63
Serial Remote Loopback
The serial remote loopback mode interconnects the receive
serial data input to the transmit serial data output. If serial
remote loopback is enabled, the 8-bit parallel transmit data
input is ignored while the 8-bit parallel receive data output is
maintained.
"Low" = Disabled
"High" = Serial Remote Loopback Mode Enabled
NOTE: DLOOP and RLOOPS can be enabled simultaneously
to achieve a dual loopback diagnostic feature in normal
operation.
DLOOP
LVTTL,
LVCMOS
I
62
Digital Local Loopback
The digital local loopback mode interconnects the 8-bit parallel
transmit data input and TxCLK to the 8-bit parallel receive data
output and RxCLK respectively while maintaining the transmit
serial data output. If digital local loopback is enabled, the
receive serial data input is ignored.
"Low" = Disabled
"High" = Digital Local Loopback Mode Enabled
NOTE: DLOOP and RLOOPS can be enabled simultaneously
to achieve a dual loopback diagnostic feature in normal
operation.
ALOOP
LVTTL,
LVCMOS
I
64
Analog Local Loopback
This loopback feature serializes the 8-bit parallel transmit data
input and presents the data to the transmit serial output and in
addition it also internally routes the serialized data back to the
Clock and Data Recovery block for serial to parallel conversion.
The received serial data input is ignored.
"Low" = Disabled
"High" = Analog Local Loopback Mode Enabled
8
XRT91L31
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
REV. 1.0.3
TRANSMITTER SECTION
NAME
LEVEL
TYPE
PIN
DESCRIPTION
TXDI0
TXDI1
TXDI2
TXDI3
TXDI4
TXDI5
TXDI6
TXDI7
LVTTL,
LVCMOS
I
58
57
56
55
54
53
51
50
Transmit Parallel Data Input
Transmit Parallel Clock Output Operation
The 77.76 Mbps (STS-12/STM-4) / 19.44 Mbps (STS-3/STM-1)
8-bit parallel transmit data should be applied to the transmit
parallel bus and simultaneously referenced to the rising edge of
the TXPCLK_IO clock output. The 8-bit parallel interface is multiplexed into the transmit serial output interface with the MSB
first (TXDI[7:0]).
Alternate Transmit Parallel Clock Input Operation
When operating is this mode, TXPCLK_IO is no longer a parallel clock output reference but reverses direction and serves as
the parallel transmit clock input reference for the PISO (Parallel
Input to Serial Output) block. The 77.76 Mbps (STS-12/STM-4)
/ 19.44 Mbps (STS-3/STM-1) 8-bit parallel transmit data should
be applied to the transmit parallel bus and simultaneously referenced to the rising edge of the TXPCLK_IO clock input.
TXOP
TXON
LVPECL Diff
O
5
6
Transmit Serial Data Output
The transmit serial data stream is generated by multiplexing the
8-bit parallel transmit data input into a 622.08 Mbps STS-12/
STM-4 or 155.52 Mbps STS-3/STM-1 serial data stream.
TXPCLK_IO
LVTTL,
LVCMOS
I/O
49
Transmit Parallel Clock Input/Output (77.76/19.44 MHz)
Transmit Parallel Clock Output Operation
When the PIO_CTRL pin 48 is asserted "High," this pin will output a 77.76 MHz (STS-12/STM-4) or 19.44 MHz (STS-3/STM1) clock output reference for the 8-bit parallel transmit data
input TXDI[7:0]. This clock is used by the framer/mapper device
to present the TXDI[7:0] data which the XRT91L31 will latch on
the rising edge of this clock. This enables the framer/mapper
device and the XRT91L31 transceiver to be in synchronization.
Alternate Transmit Parallel Clock Input Operation
When the PIO_CTRL pin 48 is asserted "Low," this pin will
accept a 77.76 MHz (STS-12/STM-4) or 19.44 MHz (STS-3/
STM-1) clock input reference for the 8-bit parallel transmit data
input TXDI[7:0]. The XRT91L31 will latch data at TXDI[7:0] on
the rising edge of this clock. This has the enormous advantage
of enabling the framer/mapper device transmit timing to be synchronized with the transceiver transmit timing.
9
XRT91L31
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
REV. 1.0.3
TRANSMITTER SECTION
NAME
LEVEL
TYPE
PIN
DESCRIPTION
REFCLKP
REFCLKN
LVPECL Diff
I
16
17
Reference Clock Input (77.76 MHz or 19.44 MHz)
This differential clock input reference is used for the transmit
clock multiplier unit (CMU) and clock data recovery (CDR) to
provide the necessary high speed clock reference for this
device. It will accept either a 77.76 MHz or a 19.44 MHz Differential LVPECL clock source. Pin CMUFREQSEL determines
the value used as the reference. See Pin CMUFREQSEL for
more details. REFCLKP/N inputs are internally biased to 1.65V.
NOTE:
TTLREFCLK
LVTTL,
LVCMOS
I
36
In the event that TTLREFCLK LVTTL input is used
instead of these differential inputs for clock reference,
the REFCLKP should be tied to ground through a 1K
resistor and REFCLKN should be left unconnected or
connected to VCC through a 1K resistor.
Auxillary Reference Clock Input (77.76 MHz or 19.44 MHz)
This LVTTL clock input reference is used for the transmit clock
multiplier unit (CMU) and clock data recovery (CDR) to provide
the necessary high speed clock reference for this device. It will
accept either a 77.76 MHz or a 19.44 MHz LVTTL clock source.
Pin CMUFREQSEL determines the value used as the reference. See Pin CMUFREQSEL for more details.
NOTE: In the event that REFCLKP/N differential inputs is used
instead of this LVTTL input for clock reference, the
TTLREFCLK should be tied to ground.
10
XRT91L31
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
REV. 1.0.3
RECEIVER SECTION
PIN DESCRIPTION
NAME
LEVEL
TYPE
PIN
DESCRIPTION
RXDO0
RXDO1
RXDO2
RXDO3
RXDO4
RXDO5
RXDO6
RXDO7
LVTTL,
LVCMOS
O
19
20
22
23
24
25
26
27
Receive Parallel Data Output
77.76 Mbps (STS-12/STM-4) / 19.44 Mbps (STS-3/STM-1)
8-bit parallel receive data output is updated simultaneously on
the falling edge of the RXPCLKO output. The 8-bit parallel
interface is de-multiplexed from the receive serial data input
MSB first (RXDO[7]). The XRT91L31 will output the data on the
falling edge of RXPCLKO clock.
RXIP
RXIN
Diff LVPECL
I
13
14
Receive Serial Data Input
The differential receive serial data stream of 622.08 Mbps
STS-12/STM-1 or 155.52 Mbps STS-3/STM-1 is applied to
these input pins. These pins have internal LVPECL commonmode biasing circuit. External 100 termination is required
between RXIP/N pins.
XRXCLKIP
XRXCLKIN
Diff LVPECL
I
8
9
External Recovered Receive Clock Input
The differential receive serial data stream of 622.08 Mbps
STS-12/STM-1 or 155.52 Mbps STS-3/STM-1 is sampled on
the rising edge of this externally recovered differential clock
coming from the optical module. It is used when the internal
CDR unit is disabled and bypassed by the CDRDIS pin.
These pins have internal LVPECL common-mode biasing circuit. External 100 termination is required between XRXCLKIP/N pins.
NOTE: In the event that XRXCLKIP/N differential input pins are
unused, XRXCLKIP should be tied to VCC with a 1k
Ohm pull-up and XRXCLKIN should be tied to Ground
with a 1k Ohm pull-down.
RXPCLKO
LVTTL,
LVCMOS
O
29
Receive Parallel Clock Output (77.76 MHz or 19.44 MHz)
77.76 MHz (STS-12/STM-4) or 19.44 MHz (STS-3/STM-1)
clock output reference for the 8-bit parallel receive data output
RXDO[7:0]. The parallel received data output bus will be
updated on the falling edge of this clock.
CDRAUXREFCLK
LVTTL,
LVCMOS
I
32
Clock and Data Recovery Auxillary Reference Clock
77.76 MHz ± 200 ppm auxillary reference clock for the CDR.
NOTE: In the event that CDRAUXREFCLK LVTTL input pin is
unused, CDRAUXREFCLK should be tied to ground.
OOF
LVTTL,
LVCMOS
I
11
Out of Frame Input Indicator
This level sensitive input pin is used to initiate frame detection
and byte alignment recovery when OOF is declared by the
downstream device. When this pin is held High, FRAMEPULSE will pulse for a single RXPCLKO period upon the detection of every third frame alignment A2 byte in the incoming
SONET/SDH Frame.
"Low" = Normal Operation
"High" = OOF Indication initiating frame detection and byte
boundary recovery and activating FRAMEPULSE
11
XRT91L31
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
REV. 1.0.3
PIN DESCRIPTION
NAME
LEVEL
TYPE
PIN
DESCRIPTION
FRAMEPULSE
LVTTL,
LVCMOS
O
30
Sonet Frame Alignment Pulse
This pin will generate a single pulse for an RXPCLKO clock
period upon the detection of the third frame alignment A2 byte
whenever the OOF input pin is held High. The parallel received
data output bus will then be byte aligned to this newly recovered SONET/SDH frame.
CAP1P
CAP2P
Analog
-
39
42
CDR Non-polarized External Filter Capacitor
C1 = 0.47F ± 10% tolerance
(Isolate from noise and place close to pin)
CAP1N
CAP2N
Analog
-
40
41
CDR Non-polarized External Filter Capacitor
C2 = 0.47F ± 10% tolerance
(Isolate from noise and place close to pin)
DLOSDIS
LVTTL,
LVCMOS
I
7
LOS (Los of Signal) Detect Disable
Disables internal LOS monitoring and automatic muting of
RXDO[7:0] upon LOS detection. LOS is declared when a string
of 128 consecutive zeros occur on the line. LOS condition is
cleared when the 16 or more pulse transitions is detected for
128 bit period sliding window (see Figure 7.)
"Low" = Monitor and Mute received data upon LOS declaration
"High" = Disable internal LOS monitoring
LOSEXT
SE-LVPECL
I
33
LOS or Signal Detect Input from Optical Module
Active "Low." When active, this pin can force the received data
output bus RXDO[7:0] to a logic state of ’0’ per Figure 7.
"Low" = Forced LOS
"High" = Normal Operation
POWER AND GROUND
PIN DESCRIPTION
NAME
TYPE
PIN
DESCRIPTION
VDD3.3
PWR
18, 31, 34, 47, 61
3.3V CMOS Power Supply
VDD3.3 should be isolated from the Analog VDD power supplies.
Use a ferrite bead along with an internal power plane separation.
The VDD3.3 power supply pins should have bypass capacitors to
the nearest ground.
AVDD3.3_TX
PWR
38
Analog 3.3V Transmitter Power Supply
AVDD3.3_TX should be isolated from the digital power supplies.
For best results, use a ferrite bead along with an internal power
plane separation. The AVDD3.3_TX power supply pins should
have bypass capacitors to the nearest ground.
AVDD3.3_RX
PWR
43
Analog 3.3V Receiver Power Supply
AVDD3.3_RX should be isolated from the digital power supplies.
For best results, use a ferrite bead along with an internal power
plane separation. The AVDD3.3_RX power supply pins should
have bypass capacitors to the nearest ground.
12
XRT91L31
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
REV. 1.0.3
PIN DESCRIPTION
NAME
TYPE
PIN
DESCRIPTION
VDD_PECL
PWR
4, 10
3.3V Input/Output LVPECL Bus Power Supply
These pins require a 3.3V potential voltage for properly biasing
the Differential LVPECL input and output pins.
AGND_TX
PWR
37
Transmitter Analog Ground for 3.3V Analog Power Supplies
It is recommended that all ground pins of this device be tied
together.
AGND_RX
PWR
44
Receiver Analog Ground for 3.3V Analog Power Supplies
It is recommended that all ground pins of this device be tied
together.
GND
GND
21, 28, 35, 45, 46, 52
Power Supply and Thermal Ground
It is recommended that all ground pins of this device be tied
together.
13
XRT91L31
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
1.0.3
1.0 FUNCTIONAL DESCRIPTION
The XRT91L31 transceiver is designed to operate with a SONET Framer/ASIC device and provide a highspeed serial interface to optical networks. The transceiver converts 8-bit parallel data running at 77.76 Mbps
(STS-12/STM-4) or 19.44 Mbps (STS-3/STM-1) to a serial Differential LVPECL bit stream at 622.08 Mbps or
155.52 Mbps and vice-versa. It implements a clock multiplier unit (CMU), SONET/SDH serialization/deserialization (SerDes), receive clock and data recovery (CDR) unit and a SONET/SDH frame and byte
boundary detection circuit. The transceiver is divided into Transmit and Receive sections and is used to
provide the front end component of SONET equipment, which includes primarily serial transmit and receive
functions.
1.1
STS-12/STM-4 and STS-3/STM-1 Mode of Operation
Functionality of the transceiver can be configured by using the appropriate signal level on the STS-12/STS-3
pin. STS-3/STM-1 mode is selected by pulling STS-12/STS-3 "Low" as described in the Hardware Pin
Descriptions. However, if STS-12/STM-4 mode is desired, it is selected by pulling STS-12/STS-3 "High."
Therefore, the following sections describe the functionality rather than how each function is controlled. Hence,
the Hardware Pin and Register Bit Descriptions focus on device configuration.
1.2
Clock Input Reference for Clock Multiplier (Synthesizer) Unit
The XRT91L31 can accept both a 19.44 MHz or a 77.76 MHz Differential LVPECL clock input at REFCLKP/N
or a Single-Ended LVTTL clock at TTLREFCLK as its internal timing reference for generating higher speed
clocks. The REFCLKP/N or TTLREFCLK input should be generated from an LVPECL/LVTTL crystal oscillator
which has a frequency accuracy better than 20ppm in order for the transmitted data rate frequency to have the
necessary accuracy required for SONET systems. The reference clock can be provided with one of two
frequencies chosen by CMUFREQSEL. The reference frequency options for the XRT91L31 are listed in
Table 1.
TABLE 3: CMU REFERENCE FREQUENCY OPTIONS (DIFFERENTIAL OR SINGLE-ENDED)
1.3
REFCLKP/N OR TTLREFCLK
CMUFREQSEL
STS12/STS3
0
0
77.76 MHz
STS-3/STM-1
155.52 Mbps
0
1
77.76 MHz
STS-12/STM-4
622.08 Mbps
1
0
19.44 MHz
STS-3/STM-1
155.52 Mbps
1
1
19.44 MHz
STS-12/STM-4
622.08 Mbps
REFERENCE FREQUENCY
DATA RATE
Data Latency
Due to different operating modes and data logic paths through the device, there is an associated latency from
data ingress to data egress. Table 4 specifies the data latency for a typical path.
TABLE 4: DATA INGRESS TO DATA EGRESS LATENCY
Mode Of
Operation
Data Path
Clock Reference
Range Of Clock
Cycles
Thru-mode
MSB at RXIP/N to data on RXDO[7:0]
Recoved RXIP/N Clock
25 to 35
Serial Remote Loopback
MSB at RXIP/N to MSB at TXOP/N
Recoved RXIP/N Clock
2 to 4
14
XRT91L31
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
1.0.3
2.0 RECEIVE SECTION
The receive section of XRT91L31 include the inputs RXIP/N, followed by the clock and data recovery unit
(CDR) and receive serial-to-parallel converter. The receiver accepts the high speed Non-Return to Zero (NRZ)
serial data at 622.08 Mbps or 155.52 Mbps through the input interfaces RXIP/N. The clock and data recovery
unit recovers the high-speed receive clock from the incoming scrambled NRZ data stream. The recovered
serial data is converted into an 8-bit-wide, 77.76 Mbps or 19.44 Mbps parallel data and presented to the
RXDO[7:0] parallel interface. This parallel interface is designed for Single-Ended LVTTL operation. A divideby-8 version of the high-speed recovered clock RXPCLKOP/N, is used to synchronize the transfer of the 8-bit
RXDO[7:0] data with the receive portion of the framer/mapper device. Upon initialization or loss of signal or
loss of lock, the external reference clock signal of 19.44 MHz or 77.76 MHz is used to start-up the clock
recovery phase-locked loop for proper operation. In certain applications, the CDR block on the XRT91L31 can
be disabled and bypassed by enabling the CDRDIS pin to permit the flexibility of using an externally recovered
receive clock thru the XRXCLKIP/N pins.
2.1
Receive Serial Input
The receive serial inputs are applied to RXIP/N and originate from an AC coupled environement (i.e. ACcoupled SFP). A simplified block diagram is shown in Figure 3. Since this dievice has internal pull up/pull
down biasing resitors, a 100 line-to-line termination is the only resistor needed and must be installed as
close to the RXI pins as possible. See Applications note for further clarifications.
FIGURE 3. RECEIVE SERIAL INPUT INTERFACE BLOCK
Install terminators close to
RXIP and RXIN pins
RXIP
RXIN
SFP, Optical Module
100 Ohm
Optical Fiber
XRT91L31
STS- 12/ STM-4
or
STS-3/ STM-1
Transceiver
VCC
Internally AC coupled
1k
Tie unused differential input pins
to VCC and GND through 1KOhm
resistors as shown .
XRXCLKIP
XRXCLKIN
1k
15
XRT91L31
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
2.2
1.0.3
Recieve Serial Data Input Timing
The received High-Speed Serial Differential Data Input must adhere to the set-up and hold time timing
specifications below.
FIGURE 4. RECEIVE HIGH-SPEED SERIAL DATA INPUT TIMING DIAGRAM
tRXCLK
XRXCLKIP
XRXCLKIN
tRX_HD
tRX_SU
RXIP
RXIN
TABLE 5: RECEIVE HIGH-SPEED SERIAL DATA INPUT TIMING (STS-12/STM-4 OPERATION)
SYMBOL
PARAMETER
MIN
TYP
MAX
tRXCLK
Receive external recovered clock period
tRX_SU
Serial data setup time with respect to XRXCLKIP/N
400
ps
tRX_HD
Serial data hold time with respect to XRXCLKIP/N
100
ps
1.608
UNITS
ns
TABLE 6: RECEIVE HIGH-SPEED SERIAL DATA INPUT TIMING (STS-3/STM-1 OPERATION)
SYMBOL
PARAMETER
tRXCLK
Receive external recovered clock period
tRX_SU
Serial data setup time with respect to XRXCLKIP/N
1.5
ns
tRX_HD
Serial data hold time with respect to XRXCLKIP/N
1.5
ns
16
MIN
TYP
6.43
MAX
UNITS
ns
XRT91L31
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
1.0.3
2.3
Receive Clock and Data Recovery
The clock and data recovery (CDR) unit accepts the high speed NRZ serial data from the Differential LVPECL
receiver and generates a clock that is the same frequency as the incoming data. The clock recovery can either
utilize the transmitter’s CMU reference clock from either REFCLKP/N or TTLREFCLK (+/- 20ppm) or it can use
independent clock source CDRAUXREFCLK (+/- 200ppm) to train and monitor its clock recovery PLL. Initially
upon startup, the PLL locks to the local reference clock. Once this is achieved, the PLL then attempts to lock
onto the incoming receive data stream. Whenever the recovered clock frequency deviates from the local
reference clock frequency by more than approximately ±500 ppm, the clock recovery PLL will switch and lock
back onto the local reference clock. Whenever a Loss of Lock or a Loss of Signal event occurs, the CDR will
continue to supply a receive clock (based on the local reference) to the framer/mapper device. When the
LOSEXT is asserted by the optical module or when LOS is detected, the receive parallel data output will be
forced to a logic zero state for the entire duration that a LOS condition is detected. This acts as a receive data
mute upon LOS function to prevent random noise from being misinterpreted as valid incoming data. When the
LOSEXT becomes inactive and the recovered clock is determined to be within ±500 ppm accuracy with respect
to the local reference source and LOS is no longer declared, the clock recovery PLL will switch and lock back
onto the incoming receive data stream. Table 7 shows Clock and Data Recovery reference clock settings.
Table 8 specifies the Clock and Data Recovery Unit performance characteristics.
TABLE 7: CLOCK DATA RECOVERY UNIT REFERENCE CLOCK SETTINGS
CMUFREQSEL CDRREFSEL
STS12/
STS3
REFCLKP/N1OR
TTLREFCLK1
FREQUENCY (MHZ)
CDRAUXREFCLK2
FREQUENCY (MHZ)
CDR OUTPUT
FREQUENCY (MHZ)
0
0
0
77.76 MHz
not used
155.52
0
0
1
77.76 MHz
not used
622.08
1
0
0
19.44 MHz
not used
155.52
1
0
1
19.44 MHz
not used
622.08
X
1
0
not referenced by CDR
77.76 MHz
155.52
X
1
1
not referenced by CDR
77.76 MHz
622.08
1Requires frequency accuracy better than +/- 20 ppm in order for the transmitted data rate frequency
to have the necessary accuracy required for SONET systems.
2
CDRAUXREFCLK requires accuracy of 77.76 MHz +/- 200 ppm.
TABLE 8: CDR AUXREFCLK REFERENCE FREQUENCY REQUIREMENT FOR CLOCK AND DATA RECOVERY
NAME
PARAMETER
MIN
REFDUTY
Reference clock duty cycle
REFTOL
Reference clock frequency tolerance
2.3.1
TYP
MAX
UNITS
40
60
%
-200
+200
ppm
Internal Clock and Data Recovery Bypass
Optionally, the internal CDR unit can be disabled and bypassed in lieu of an externally recovered clock.
Asserting the CDRDIS "High" disables the internal Clock and Data Recovery unit and the received serial data
bypasses the integrated CDR block. RXINP/N is then sampled on the rising edge of the externally recovered
17
XRT91L31
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
1.0.3
differential clock XRXCLKIP/N coming from the optical module or an external clock recovery unit. Figure 5
shows the possible internal paths of the recovered clock and data.
FIGURE 5. INTERNAL CLOCK AND DATA RECOVERY BYPASS
MUX
XRXCLKIP
CLOCK
XRXCLKIN
CLK
CDRDIS
CDR
Parallel
Data
8
SIPO
DATA
RXIP
MUX
Div by 8
CLOCK
Data
18
RXIN
XRT91L31
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
1.0.3
2.4
External Receive Loop Filter Capacitors
These external loop filter 0.47F non-polarized capacitors provide the necessary components to achieve the
required receiver jitter performance. They must be well isolated to prohibit noise entering the CDR block and
should be placed as close to the pins as much as possible. Figure 6 shows the pin connections and external
loop filter components. These two non-polarized capacitors should be of +/- 10% tolerance.
FIGURE 6. EXTERNAL LOOP FILTERS
0.47uF
0.47uF
non-polarized
non-polarized
pin 39
pin 42
CAP1P
2.5
pin 40
CAP2P
CAP1N
pin 41
CAP2N
Loss Of Signal
XRT91L31 supports internal Loss of Signal detection (LOS) and external LOS detection. The internal Loss of
Signal Detector monitors the incoming data stream and if the incoming data stream has no transition
continuously for more than 128 bit periods, Loss of Signal is declared. This LOS detection will be removed
when the circuit detects 16 transitions in a 128 bit period sliding window. Pulling the corresponding DLOSDIS
signal to a high level will disable the internal LOS detection circuit. The external LOS function is supported by
the LOSEXT input. The Single-Ended LVPECL input usually comes from the optical module through an output
usually called “SD” or “FLAG” which indicates the lack or presence of optical power. Depending on the
manufacturer of these devices, the polarity of this signal can be either active "Low" or active "High". LOSEXT is
an active "Low" signal requiring a low level to assert or invoke a forced LOS. The external LOSEXT input pin
and internal LOS detector are gated to control detection and declaration of Loss of Signal (see Figure 7.)
Whenever LOS is internally detected or an external LOS is asserted thru the LOSEXT pin, and none of the
local loopback loops is enabled, the XRT91L31 will automatically force the receive parallel data output to a
logic state "0" for the entire duration that a LOS condition is declared. This acts as a receive data mute upon
LOS function to prevent random noise from being misinterpreted as valid incoming data. When the local
loopbacks DLOOP or ALOOP is enabled, then LOS conditions will not mute the RX parallel output.
FIGURE 7. LOS DECLARATION CIRCUIT
‘0’ = No LOS detection:
Do not mute Tx serial data output
‘1’ = LOS_detection: Mute Tx
serial data output
DLOS (internal signal)
RLOOPS
DLOSDIS
LOSEXT
RLPS_D_MUTE
(Internal Signal)
(Internal Signal)
ALOOP
DLOOP
‘0’ = No LOS detection: Do not
mute receive parallel data bus
‘1’ = LOS_detection: Mute
receive parallel data bus
During RLOOPS operation, the 91L31 mutes the RLOOPS data going to Tx output upon detection of DLOS
while DLOSDIS is not enabled. During RLOOPS operation, the 91L31 also mutes the RLOOPS data going to
19
XRT91L31
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
1.0.3
Tx output while the LOSEXT input is set to a “LOW” state. Note that the DLOSDIS control pin has no impact
on the CDR muting function due to LOSEXT. DLOSDIS only applies to muting as a result of DLOS detection.
Also, note that serial muting function (RLPS_D_MUTE) only impacts RLOOPS data going to Tx output.
2.6
SONET Frame Boundary Detection and Byte Alignment Recovery
A Frame and Byte Boundary Detection circuit searches the incoming data channel for three consecutive A1
(0xF6 Hex) bytes followed by three consecutive A2 (0x28 Hex) bytes. The detector operates under the control
of the OOF (Out of Frame) signals provided from the SONET Framer. Detection is enabled when OOF is held
"High" and remains active until OOF goes "Low." When framing pattern detection is enabled, the framing
pattern is used to locate byte and frame boundaries in the incoming receive data stream. The receive serial-toparallel converter block uses the located byte boundary to assemble the incoming data stream into bytes for
output on the parallel data output bus RXDO[7:0]. The frame boundary is reported on the frame pulse
(FRAMEPULSE) output at the onset of detecting the third A2 byte pattern when any serial 48-bit pattern
matching the framing pattern is detected on the incoming data stream. While in the pattern search and
detection state and so long is OOF is active, the frame pulse (FRAMEPULSE) output is activated for one byte
clock cycle (RXPCLKO = 12.86 ns pulse duration for STS-12/STM-4 or 51.44 ns pulse duration for STS-3/
STM-1) anytime a 48-bit pattern matching the framing pattern is detected on the incoming data stream. Once
the SONET Framer Overhead Circuitry has verified that frame and byte synchronization are correct, the OOF
input pin should be de-asserted by the SONET Framer to disable the XRT91L31 frame search process from
trying to synchronize repeatedly and to de-activate FRAMEPULSE. When the XRT91L31’s framing pattern
detection is disabled upon the de-assertion of OOF input pin from the SONET Framer, the byte boundary will
lock to the detected location and will remain locked to that location found when detection was previously
enabled.
2.7
Receive Serial Input to Parallel Output (SIPO)
During STS-12/STM-4 operation, the SIPO is used to convert the 622.08 Mbps serial data input to 77.76 Mbps
parallel data output which can interface to a SONET Framer/ASIC. If the XRT91L31 is operating in STS-3/
STM-1, the SIPO will convert the 155.52 Mbps serial data input to 19.44 Mbps parallel data output. The SIPO
bit de-interleaves the serial data input into an 8-bit parallel output to RXDO[7:0]. A simplified block diagram is
shown in Figure 8. XRT91L31 clocks data out on RXDO[7:0] at the falling edge of RXPCLKO.
FIGURE 8. SIMPLIFIED BLOCK DIAGRAM OF SIPO
8-bit Parallel LVTTL Output Data
b03 b02 b01 b00
RXDOn
bn3 bn2 bn1 bn0
RXDOn+
bn+3 bn+2 bn+1 bn+0
RXDO7
b73 b72 b71 b70
RXPCLKO
622.08 Mbps STS-12/STM-4 or
155.52 Mbps STS-3/STM-1 serial data rate
SIPO
RXDO0
b73 b63 b53 b43 b33 b23 b13
77.76 MHz (STS-12/STM-4) or 19.44 MHz (STS-3/STM-1)
20
b70 b60 b50 b40 b30 b20 b10 b00
RXIP/N
XRT91L31
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
1.0.3
2.8
Receive Parallel Output Interface
The 8-bit Single-Ended LVTTL running at 77.76 Mbps (STS-12/STM-4) or 19.44 Mbps (STS-3/STM-1) parallel
data output of the receive path is used to interface to a SONET Framer/ASIC synchronized to the recovered
clock. A simplified block diagram is shown in Figure 9.
FIGURE 9. RECEIVE PARALLEL OUTPUT INTERFACE BLOCK
RXDO[7:0]
8
RXPCLKO
XRT91L31
STS-12/STM-4
or
STS-3/STM-1
Transceiver
SONET Framer/ASIC
2.9
Disable Parallel Receive Data Output Upon LOS
The parallel receiver outputs are automatically pulled "Low" or forced to a logic state of "0" during a LOS
condition (DLOOP or ALOOP not activated) to prevent data chattering unless LOS detection is disabled by
asserting DLOSDIS and keeping LOSEXT input pin "high." In addition, the user can also assert LOSEXT input
pin from the optical module to force an LOS and mute the parallel receiver outputs as well when DLOSDIS is
not enabled (LOW), see Figure 7).
21
XRT91L31
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
2.10
1.0.3
Receive Parallel Data Output Timing
The receive parallel data output from the STS-12/STM-4 or STS-3/STM-1 receiver will adhere to the setup and
hold times shown in Figure 10 ,Table 9, and Table 10. Table 11 shows the PECL and TTL output timing
specifications.
FIGURE 10. RECEIVE PARALLEL OUTPUT TIMING
tRXCLK
RXIP
RXIN
tRXPCLKO
RXPCLKO
A1
RXDO[7:0]
A2
A2
A2
A2
tRXDO_VALID
FRAMEPULSE
tPULSE_WID
TABLE 9: RECEIVE PARALLEL DATA OUTPUT TIMING (STS-12/STM-4 OPERATION)
SYMBOL
PARAMETER
MIN
TYP
MAX
tRXCLK
Receive high-speed serial clock period
1.608
ns
tRXPCLKO
Receive parallel data output byte clock period
12.86
ns
tRXDO_VALID
Time the data is valid on RXDO[7:0] and FRAMEPULSE
before and after the rising edge of RXPCLKO
tPULSE_WID
Pulse width of frame detection pulse on FRAMEPULSE
4
UNITS
ns
12.86
ns
TABLE 10: RECEIVE PARALLEL DATA OUTPUT TIMING (STS-3/STM-1 OPERATION)
SYMBOL
PARAMETER
tRXCLK
Receive high-speed serial clock period
6.43
ns
tRXPCLKO
Receive parallel data output byte clock period
51.44
ns
tRXDO_VALID
Time the data is valid on RXDO[7:0] and FRAMEPULSE
before and after the rising edge of RXPCLKO
tPULSE_WID
Pulse width of frame detection pulse on FRAMEPULSE
22
MIN
TYP
22
MAX
UNITS
ns
51.44
ns
XRT91L31
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
1.0.3
TABLE 11: PECL AND TTL RECEIVE OUTPUTS TIMING SPECIFICATION
SYMBOL
PARAMETER
tR_PECL
PECL output rise time (20% to 80%)
350
ps
tF_PECL
PECL output fall time (80% to 20%)
350
ps
tR_TTL
TTL output rise time (10% to 90%)
2
ns
tF_TTL
TTL output fall time (90% to 10%)
1.5
ns
23
MIN
TYP
MAX
UNITS
XRT91L31
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
1.0.3
3.0 TRANSMIT SECTION
The transmit section of the XRT91L31 accepts 8-bit parallel data and converts it to serial Differential LVPECL
data output intented to interface to an optical module. It consists of an 8-bit parallel Single-Ended LVTTL
interface, Parallel-to-Serial Converter, a clock multiplier unit (CMU), a Low Voltage Positive-referenced EmitterCoupled Logic (LVPECL) differential line driver, and Loop Timing modes. The LVPECL serial data output rate is
622.08 Mbps for STS-12/STM-4 applications and 155.52 Mbps for STS-3/STM-1 applications. The high
frequency serial clock is synthesized by a PLL, which uses a low frequency clock as its input reference. In
order to synchronize the data transfer process, the synthesized 622.08 MHz for STS-12/STM-4 or 155.52 MHz
STS-3/STM-1 serial clock output is divided by eight and the 77.76 MHz (STS-12/STM-4) or 19.44 MHz (STS-3/
STM-1) clock respectively is presented to the framer/mapper device to be used as its timing source.
3.1
Transmit Parallel Input Interface
The parallel data from an framer/mapper device is presented to the XRT91L31 through an 8-bit Single-Ended
LVTTL parallel bus interface TXDI[7:0]. To directly interface to the XRT91L31, the SONET Framer/ASIC must
be synchronized to the same timing source TXPCLK_IO in presenting data on the parallel bus interface. The
data must meet setup and hold times with respect to TXPCLK_IO. This clock output source is used to
synchronize the SONET Framer/ASIC to the XRT91L31. The framer/mapper device should use TXPCLK_IO
as its timing source so that parallel data is phase aligned with the serial transmit data. The data is latched into
a parallel input register on the rising edge of TXPCLK_IO. TXPCLK_IO is derived from a divide-by-8 of the high
speed synthesized clock resulting in a 77.76/ 19.44 MHz Single-Ended LVTTL clock output source to be used
by the framer/mapper device for parallel bus synchronization. A simplified block diagram of the transmit
parallel bus clock output system interface is shown in Figure 11.
FIGURE 11. TRANSMIT PARALLEL INPUT INTERFACE BLOCK
TXDI[7:0]
XRT91L31
STS-12/STM-4
or
STS-3/STM-1
Transceiver
8
TXPCLK_IO
SONET Framer/ASIC
VDD+
CMUREFSEL
PIO_CTRL
REFCLKN
REFCLKP
TTLREFCLK
24
XRT91L31
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
1.0.3
3.2
Transmit Parallel Data Input Timing
When applying parallel data input to the transmitter, the setup and hold times should be followed as shown in
Figure 12, Table 12 and Table 13.
FIGURE 12. TRANSMIT PARALLEL INPUT TIMING
Transmit Parallel
Clock driven by
XRT91L31 Device
Transmit Parallel Clock Output
tTXPCLK_IO
TXPCLK_IO
tTXDI_HD
tTXDI_SU
TXDI[7:0]
TABLE 12: TRANSMIT PARALLEL DATA INPUT TIMING (STS-12/STM-4 OPERATION)
SYMBOL
PARAMETER
MIN
TYP
MAX
tTXPCLK_IO
Transmit Clock Output period
tTXDI_SU
Transmit data setup time with respect to TXPCLK_IO
2.0
ns
tTXDI_HD
Transmit data hold time with respect to TXPCLK_IO
1.0
ns
12.86
UNITS
ns
TABLE 13: TRANSMIT PARALLEL DATA INPUT TIMING (STS-3/STM-1 OPERATION).
SYMBOL
PARAMETER
tTXPCLK_IO
Transmit Clock Output period
tTXDI_SU
Transmit data setup time with respect to TXPCLK_IO
2.0
ns
tTXDI_HD
Transmit data hold time with respect to TXPCLK_IO
1.0
ns
25
MIN
TYP
51.44
MAX
UNITS
ns
XRT91L31
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
3.3
1.0.3
Alternate Transmit Parallel Bus Clock Input Option
To decouple transmit parallel clock domains of the framer/mapper device and the XRT91L31 transceiver and to
eliminate difficult timing issues between them, the transmit parallel clock TXPCLK_IO can also be optionally
configured as a clock input. Rather than provide a transmit parallel clock output reference to the framer/mapper
device, the XRT91L31 can instead accept a reference transmit parallel clock input signal from the framer/
mapper device to sample the transmit parallel bus. When PIO_CTRL pin 48 is asserted "Low," TXPCLK_IO
switches into a clock input and the XRT91L31 will now sample data on the transmit parallel bus TXDI[7:0]
based on TXPCLK_IO clock input reference coming from the framer/mapper device. The use of the alternate
transmit parallel bus clock input option permits the system to tolerate an arbitrary amount of phase mismatch
and jitter between framer/mapper transmit parallel clock timing and transceiver transmit timing. Figure 13
provides a detailed overview of the alternate transmit parallel bus clock input system interface.
FIGURE 13. ALTERNATE TRANSMIT PARALLEL INPUT INTERFACE BLOCK (PARALLEL CLOCK INPUT OPTION)
TXDI[7:0]
8
TXPCLK_IO
XRT91L31
STS-12/STM-4
or
STS-3/STM-1
Transceiver
(Parallel Clock Input Option)
SONET Framer/ASIC
CMUREFSEL
PIO_CTRL
REFCLKN
REFCLKP
TTLREFCLK
3.4
Alternate Transmit Parallel Data Input Timing
When applying parallel data input to the transmitter in the alternate transmit parallel bus clock input mode of
operation, the setup and hold times should be followed as shown in Figure 14 and Table 14, Table 15.
FIGURE 14. ALTERNATE TRANSMIT PARALLEL INPUT TIMING
Transmit Parallel
Clock driven by
Framer/Mapper
Device
Alternate Transmit Parallel Clock Input Option
tTXPCLK_IO
TXPCLK_IO
tTXDI_HD
tTXDI_SU
TXDI[7:0]
26
XRT91L31
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
1.0.3
TABLE 14: ALTERNATE TRANSMIT PARALLEL DATA INPUT TIMING (STS-12/STM-4 OPERATION)
SYMBOL
PARAMETER
MIN
TYP
MAX
tTXPCLK_IO
Transmit Clock Input period
tTXDI_SU
Transmit data setup time with respect to TXPCLK_IO
2.0
ns
tTXDI_HD
Transmit data hold time with respect to TXPCLK_IO
1.0
ns
12.86
UNITS
ns
TABLE 15: ALTERNATE TRANSMIT PARALLEL DATA INPUT TIMING (STS-3/STM-1 OPERATION).
3.5
SYMBOL
PARAMETER
MIN
TYP
tTXPCLK_IO
Transmit Clock Input period
tTXDI_SU
Transmit data setup time with respect to TXPCLK_IO
2.0
ns
tTXDI_HD
Transmit data hold time with respect to TXPCLK_IO
1.0
ns
51.44
MAX
UNITS
ns
Transmit Parallel Input to Serial Output (PISO)
The PISO is used to convert 77.76 Mbps or 19.44 Mbps parallel data input to 622.08 Mbps STS-12/STM-1 or
155.52 Mbps STS-3/STM-1 serial data output respectively, which can interface to an optical module. The
PISO bit interleaves parallel data input into a serial bit stream taking the first bit from TXDI7, then the first bit
from TXDI6, and so on as shown in Figure 15.
FIGURE 15. SIMPLIFIED BLOCK DIAGRAM OF PISO
8-bit Parallel LVTTL Input Data
TXDI0
b07 b06 b05 b04 b03 b02 b01 b00
TXDIn
bn7 bn6 bn5 bn4 bn3 bn2 bn1 bn0
TXDIn+
bn+7 bn+6 bn+5 bn+4 bn+3 bn+2 bn+1 bn+0
TXDI7
b77 b76 b75 b74 b73 b72 b71 b70
TXPCLK_IO
PISO
time (0)
622.08 Mbps STS-12/STM-4 or
155.52 Mbps STS-3/STM-1 serial data rate
b70 b60 b50 b40 b30 b20
77.76 MHz (STS-12/STM-4) or 19.44 MHz (STS-3/STM-1)
27
b77 b67 b57 b47 b37 b27 b17 b07
TXOP/N
XRT91L31
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
3.6
1.0.3
Clock Multiplier Unit (CMU) and Re-Timer
The clock synthesizer uses a 77.76 MHz or a 19.44 MHz reference clock to generate the 622.08 MHz (for STS12/STM-4) or 155.52 MHz (for STS-3/STM-1) SONET/SDH transmit serial data rate frequency. Differential
LVPECL input REFCLKP/N accepts a clock reference of 77.76 MHz or 19.44 MHz to synthesize a high speed
622.08 MHz clock for STS-12/STM-4 or 155.52 MHz clock for STS-3/STM-1 applications. Optionally, if a
Differential LVPECL clock source is not available, TTLREFCLK can accept an LVTTL clock signal. The clock
synthesizer uses a PLL to lock-on to the differential input REFCLKP/N or Single-Ended input TTLREFCLK
reference clock. The REFCLKP/N input should be generated from an LVPECL crystal oscillator which has a
frequency accuracy better than 20ppm in order for the transmitted data rate frequency to have the necessary
accuracy required for SONET systems. If the TTLREFCLK reference clock is used, the TTLREFCLK
reference input should be tied to a LVTTL crystal oscillator with 20ppm accuracy. The two reference clocks are
XNOR’ed and the choice between the LVPECL and LVTTL clocks are controlled tying either REFCLKP or
TTLREFCLK to ground. Table 3 shows the CMU reference clock frequency settings. Table 16 specifies the
Clock Multiplier Unit requirements for reference clock.
TABLE 16: CLOCK MULTIPLIER UNIT REQUIREMENTS FOR REFERENCE CLOCK
NAME
PARAMETER
MIN
REFDUTY
Reference clock duty cycle
40
REFJIT
MAX
UNITS
60
%
Reference clock jitter (rms) with 19.44 MHz reference1
5
ps
REFJIT
Reference clock jitter (rms) with 77.76 MHz reference1
13
ps
REFTOL
Reference clock frequency tolerance2
+20
ppm
-20
TYP
Jitter specification is defined using a 12kHz to 1.3/5MHz LP-HP single-pole filter.
1
These reference clock jitter limits are required for the outputs to meet SONET system level jitter
requirements (2000V
Storage Temperature ...............................-65°C to 150°C
ABSOLUTE MAXIMUM POWER AND INPUT/OUTPUT RATINGS
SYMBOL
TYPE
VDD3.3
PARAMETER
MIN.
TYP.
MAX.
UNITS
CMOS Digital Power Supply
-0.5
6.0
V
PECL I/O Power Supply
-0.5
6.0
V
3.3V Analog I/O and Power Supply
-0.5
6.0
V
LVPECL
DC logic signal input voltage
-0.5
VDDLVPECL +0.5
V
LVTTL
DC logic signal input voltage
-0.5
5.5
V
VDDLVPECL
AVDD_IO
37
XRT91L31
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
1.0.3
ABSOLUTE MAXIMUM POWER AND INPUT/OUTPUT RATINGS
SYMBOL
TYPE
LVTTL
PARAMETER
MIN.
TYP.
MAX.
UNITS
DC logic signal output voltage
-0.5
VDD3.3 +0.5
V
LVPECL
Input current
-100
100
mA
LVTTL
Input current
-100
100
mA
NOTE: Stresses listed under Absolute Maximum Power and I/O ratings may be applied to devices one at a time without
causing permanent damage. Functionality at or above the values listed is not implied. Exposure to these values for
extended periods will severely affect device reliability.
POWER AND CURRENT DC ELECTRICAL CHARACTERISTICS
Test Conditions: VDD = 3.3V + 5% unless otherwise specified
SYMBOL
TYPE
PARAMETER
MIN.
TYP.
MAX.
UNITS
VDD3.3
Power Supply Voltage
3.135
3.3
3.465
V
AVDD3.3
Transmit Power Supply Voltage (AVDD3.3_TX)
3.135
3.3
3.465
V
AVDD3.3
Receiver Power Supply Voltage (AVDD3.3_RX)
3.135
3.3
3.465
V
VDD
LVPECL
PECL I/O Power Supply Voltage
3.135
3.3
3.465
V
IDD-OC3
Total Power Supply Current
160
200
240
mA
IDD-OC12
Total Power Supply Current
180
242
270
mA
PDD-OC3
Total Power Consumption
502
660
831
mW
PDD-OC12
Total Power Consumption
564
800
986
mW
38
CONDITIONS
XRT91L31
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
1.0.3
LVPECL AND LVTTL LOGIC SIGNAL DC ELECTRICAL CHARACTERISTICS
ELECTRICAL CHARACTERISTICS
Test Conditions: VDD = 3.3V + 5% unless otherwise specified
SYMBOL
TYPE
VOH
LVPECL
Output High Voltage
VOL
LVPECL
Output Low Voltage
0.7
VOCOMM
LVPECL
Output Common Mode Voltage
1.1
VDDLVPECL 1.3
V
VODIFF
LVPECL
Peak-to-peak Output Differential Voltage (see Figure 28)
600
1300
mV
187 pull
down and 100
line-to-line termination. (see
Figure 17)
VIH
LVPECL
Input High Voltage
VDDLVPECL 0.9
VDDLVPECL 0.3
V
For
Single-Ended
VIL
LVPECL
Input Low Voltage
0
VDDLVPECL 1.72
V
For
Single-Ended
VIDIFF
LVPECL
Peak-to-peak Input PECL Differential Voltage (see
Figure 28)
400
1600
mV
100 line-toline termination. (see
Figure 3)
VICOMM
LVPECL
Input PECL Common Mode
Voltage
VDDLVPECL 1.0 -VIDIFF/2
V
Internal common mode
biasing.
VOH
LVTTL/
LVCMOS
Output High Voltage
2.4
VDD3.3
V
IOH = -1.0mA
VOL
LVTTL/
LVCMOS
Output Low Voltage
0
0.4
V
IOL = 1.0mA
VIH
LVTTL/
LVCMOS
Input High Voltage
2.0
VDD3.3
V
VIL
LVTTL/
LVCMOS
Input Low Voltage
0
0.8
V
IIH
LVTTL/
LVCMOS
Input High Current
500
A
LVTTL/
LVCMOS
Input Low Current
IIL
PARAMETER
MIN
1.5 - VIDIFF/2
TYP
MAX
UNITS
VDDLVPECL 0.9
V
CONDITIONS
V
1.7
50
2.0V
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