ISG4042EU-T

ISG4042EU-T 5 V CATV MODEM RF TUNER AND TRANSMITTER FEATURES • TWO WAY EURO DOCSIS BASED DESIGN: 112-858 MHz Downstream 5-65 MHz Upstream • SINGLE SUPPLY 5 V OPERATION: With Built-in Linear Regulation • SINGLE AGC CONTROL Simplifies Modem Calibration • ULTRA SMALL SIZE: 1.9 x 2.0 x 0.5 in., 1.9 in3 46.2 x 49.0 x 12.5 mm., 28.5 cc. • DIGITAL LINEAR RF TRANSMITTER: All Harmonics -55 dBc @ 58 dBmV (see note 2) > 56 dB Gain Range (0.5 dB steps) • INTERFACES DIRECTLY WITH QAM MOD/DEMOD IC's: (see note 3) DESCRIPTION AND APPLICATIONS The ISG4042EU-T is an RF tuner/transmitter designed for use in EURO DOCSIS cable modem applications. It is a complete solution that interfaces directly with QAM Mod/ Demod IC's. The tuner/transmitter integrates a diplex filter, dual conversion receiver, transmit AGC amplifier, and other RF filtering (see Figure 1). The diplex filter provides over 40 dB of isolation between the TX band and the RX band. The receiver channel selects and converts QAM signals in the RX band down to the IF sampling frequency. It also provides the necessary gain control to adjust the input power to the DSP chip. The RF transmitter section provides > 56 dB of digitally controlled range while maintaining excellent linearity performance. ELECTRICAL CHARACTERISTICS (VCC = 5 V, ±2 %, TA = 25°C) (see note 4) SYMBOLS PARAMETERS UNITS MHz dBmV dB dB V dB dBc/Hz dBm kHz msec. ohms dB MHz MHz dB dB ns dBc dBc kHz VPP KΩ MIN 112 -15 57 45 0 8 -85 -40 62.5 18 75 6 8 36.125 1 50 100 45 45 -35 50 50 +35 1 1 3.3 10 -82 TYP MAX 858 15 RF Performance (RX) fOP Operating Frequency Range (Center to Center) Input Signal Level Maximum Voltage Gain Automatic Voltage Gain Control Range IF Automatic Voltage Gain Control VAGC NFMAX Noise Figure (at Max Voltage Gain) Phase Noise at 10 kHz Offset LO Radiation at RF Input Resolution Lock Time (end to end channel) Input Impedance (Nominal) RLIN Input Return Loss Channel Bandwidth Output Frequency Passband Ripple over 6.952 MHz Bandwidth Image Rejection Inband Group Delay CSO1 CTB1 Output Frequency Offset Output IF Voltage Level Output IF Load Notes: 1. 110 Channels at +15 dBmV/tone. 2. 160K Symbol rate; under DOCSIS PHY - 17 high condition. 3. Application specification for TI 4040/4042. 4. Specifications apply to test conditions listed. * PHY 7/17/18 Data available upon request. Performance tests and ratings for Sirenza Microdevices’ products were performed internally by Sirenza and measured using specific computer systems and/or components and reflect the approximate performance of the products as measured by those tests. Any difference in circuit implementation, test software, or test equipment may affect actual performance. The information provided herein is believed to be reliable at press time and Sirenza Microdevices assumes no responsibility for the use of this information. All such use shall be entirely at the user’s own risk. Prices and specifications for Sirenza Microdevices’ products are subject to change without notice. Buyers should consult Sirenza Microdevices’ standard terms and conditions of sale for Sirenza’s limited warranty with regard to its products. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. Sirenza Microdevices does not authorize or warrant any product for use in lifesupport devices and/or systems. 2 303 S. Technology Court, Broomfield, CO 80021 303-327-3030 1 REV. A www.sirenza.com 4/1/2005 ISG4042EU-T ELECTRICAL CHARACTERISTICS (VCC = 5 V, ±2%, TA = 25°C) (see note 2) SYMBOLS PARAMETERS UNITS MHz dB dB dB dB dB dBmV dBmV Ω dB µs ns mV µs V V mV mA mA mA MIN 5 26 TYP MAX 65 27 -27 0.5 1.7 -48 -48 300 6.0 3.2 5 100 7 5 5.25 5.25 100 -26 2.5 0.6 -45 -45 RF Performance (TX) fOP Operating Frequency Range GMAX (Gain Word = 255) GMIN (Gain Word = 48) Output Step Size Flatness (5 to 65 MHz) Amplitude Ripple Over 1.28 MHz 2nd Harmonic Level (FIN = 65 MHz, POUT = +58 dBmV)1 3rd Harmonic Level (FIN = 65 MHz, POUT = +58 dBmV)1 Input Impedance RLOUT Output Return Loss TX ON/OFF On/Off Setting Time Group Delay (5-65 MHz) TX Transient Spurs TX Transient Duration Power Requirements Supply Voltage V1 RX Supply Voltage V1 TX Supply Ripple Voltage V1 RX Supply Current ICC1 (RX) ICC1 (TX) Supply Current 1 (RX) Supply Current 1 (TX) TXEN = High Supply Current 1 (TX) TXEN = Low Physical Interface To the CATV Network To the Motherboard Notes: 1. 160K Symbol rate; under DOCSIS PHY - 17 high condition. 2. Specifications apply to test conditions listed. 3.2 4.75 4.75 5 5 310 120 8 Female F-Connector 16 Pin Header 150 12 ABSOLUTE MAXIMUM RATINGS (TC = 25°C unless otherwise noted) SYMBOLS VIN VCC1 (RX) VCC (TX) TOP TSTG TSOL tSOL RF Input Voltage Supply Voltage (RX) Supply Voltage (TX) Operating Temperature Storage Temperature Soldering Temperature Soldering Time PARAMETERS UNITS dBmV V V °C °C °C sec. RATINGS 60 +6.5 +5.5 -40 to 75 -40 to 75 260 4 Note: 1. Operation in excess of any one of these parameters may result in permanent damage. 303 S. Technology Court, Broomfield, CO 80021 303-327-3030 2 REV. A www.sirenza.com 4/1/2005 ISG4042EU-T PIN FUNCTIONS PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIN NAME GND 5V_TX TXEN TXIN+ TXINLD_TX NC 5V_RX IFAGC GND CLOCK DATA LD_RX GND IFIF+ DESCRIPTION Ground. Provides low inductance to ground plane. Supply pin for the transmitter. Enable pin for the power amplifier. The amplifier is shutdown when this pin is set low. Non-inverted TX input. Inverted TX input. Latch enable pin for the transmitter serial interface. TTL-compatible inputs. No Connection Supply pin for the receiver. The AGC pin is used to adjust gain in the IF amplifier. The pin has a positive gain vs. voltage slope. 45 dB of gain control is available by the varying the voltage from 0 to 3.3 V. Ground. Provides low inductance to ground plane. Clock pin . High impedance CMOS input. Serial data pin. High impedance CMOS input. MSB entered first. Latch enable pin for the dual PLL. High impedance CMOS input. When LE goes HIGH, data stored in the shift registers is loaded into one of the 4 latches determined by the 2 control bits. Ground. Provides low inductance to ground plane. Inverted final IF output. Non-inverted final IF output. FIGURE 1 112-858 MHz 36.125 MHz QAM DEMOD PLL CABLE PLANT DC/DC QAM MOD 5-65 MHz Rx REGULATOR 303 S. Technology Court, Broomfield, CO 80021 303-327-3030 3 REV. A www.sirenza.com 4/1/2005 ISG4042EU-T APPLICATION INTERFACE CIRCUIT ISG4042/ TEXAS INSTRUMENTS TNET 4042 T1 TNET4042 ISG4042EU 1 GND VCC 2 5V_TX + 330µf - + 330µf - 120nH 1NF 0.1µf TUN_GND (TI Pin 20) AMP PD 2.7pf 7.5pf 3 TX_EN 75 Ω (TI Pin 6) IOUT + (TI Pin 3) IOUT - 270nH 30pf 24pf 270nH 2.7pf 270nH 24pf 270nH 7.5pf 4 TX_IN+ 30pf 75 Ω 5 TX_IN- (TI Pin 173) GENP(3) 6 LE2 7 5V_TX VCC + -330µf 24K 8 5V_RX 10uH + 330µf TUN_GND (TI Pin 166) TAGCS 50K TUN_GND 0.01µf 9 IF AGC 10 GND TUN_GND TUN_GND (TI Pin 168) GENP(1) 11 CLK (TI Pin 167) GENP(0) 12 DATA (TI Pin 172) GENP(2) 13 LD_EN 14 GND TUN_GND (TI Pin 189) VIN(TI Pin 190) VIN+ 15 IF_OUT+ 16 IF_OUT- 303 S. Technology Court, Broomfield, CO 80021 303-327-3030 4 REV. A www.sirenza.com 4/1/2005 ISG4042EU-T TYPICAL PERFORMANCE CURVES PASSBAND AMPLITUDE RIPPLE RES BW 300 KHz VBW 100 KHz SWP 20.0 msec 0 AGC RANGE 70 60 50 1 Gain (dB) 36.125 MHz SPAN 10.00 MHz 2 40 3 30 4 20 5 6 10 0 0 0.5 1 1.5 2 2.5 3 7 Volts (V) PHASE NOISE RES BW 1.0 KHz VBW 1 KHz SWP 275 msec Marker1 10 KHz -54.71 dB PHASE NOISE REF = -22.00 dB RES BW 1.0 KHz VBW 1 KHz SWP 625 msec Marker1 100 KHz -79.31 dB REF = -15.00 dB -54.71 dB -79.31 dB 36.125 MHz SPAN 25 KHz 36.125 MHz SPAN 250 KHz TX DIPLEXER RESPONSE 50 40 30 CONVERSION vs. FREQUENCY 60 59 58 Conversion Gain (dB) 20 57 56 55 25º C Gain (dB) 10 0 -10 -20 -30 -40 -50 5 25 45 65 85 105 125 145 165 185 205 70º C 54 53 52 51 50 80 180 280 380 480 580 680 780 880 Frequency (MHz) Frequency (MHz) 303 S. Technology Court, Broomfield, CO 80021 303-327-3030 5 REV. A www.sirenza.com 4/1/2005 ISG4042EU-T OUTLINE DIMENSIONS (Units in mm) Notes: 1. All tolerance ±0.50 mm unless otherwise specified. 303 S. Technology Court, Broomfield, CO 80021 303-327-3030 6 REV. A www.sirenza.com 4/1/2005 ISG4042EU-T PROGRAMMING INFORMATION FOR RX There are four 22-bit words needed to program the RX. PLL2 has the following words. LSB 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 MSB 0 R2 0 N2 PLL1 has the following words. LSB 0 1 1 Where N = and 1 0 A 0 A 0 A 0 A 1 A 0 A 0 A 0 B 0 B 0 B 0 B 0 B 0 B 0 B 0 B 0 B 0 B 0 B 0 0 MSB 0 R1 0 N1 [ Tune Frequency (MHz) + 1100 ] 0.25 N [ 64 [ B= N – Mod 64 A = N – 64 (B) They should be entered using the serial data input timing diagram below. Serial Data Input Timing DATA N20: MSB (R20: MSB) N19 (R19) N10 (R10) N9 C2 (R9) (R8) (C2) tCWL C1: LSB (C1: LSB) CLOCK LE OR LE Rx Timing Characteristics SYMBOLS VOH VOL tCS tCH tCWH tCWL tES tEW PARAMETERS MIN High-Level Output Voltage Low-Level Output Voltage Data to Clock Set Up Time Data to Clock Hold Time Clock Pulse Width High Clock Pulse Width Low Clock to Load Enable Set Up Time Load Enable Pulse Width 50 10 50 50 50 50 4.1 0.4 VALUE TYP MAX V V ns ns ns ns ns ns UNITS tCS tCH tCWH tES tEW Notes: 1. Parenthesis data indicates programmable reference divider data. 2. Data shifted into register on clock rising edge. 3. Data is shifted in MSB first. 4. Pin 6 LD_TX held high. Test Conditions: The Serial Data Input Timing is tested using a symmetrical waveform around VCC/2. The test waveform has an edge rate of 0.6V/ns with amplitudes of 2.2 V @ VCC = 2.7 V and 2.6 V @ VCC = 5.5 V. 303 S. Technology Court, Broomfield, CO 80021 303-327-3030 7 REV. A www.sirenza.com 4/1/2005 ISG4042EU-T PROGRAMMING INFORMATION FOR TX Serial Interface The serial interface has an active-low enable (LD_TX) to bracket the data, with data clocked in MSB first on the rising edge of CLK. Data is stored in the storage latch on the rising edge of LD_TX. The serial interface controls the state of the transmitter. Table 1 and 2 show the register format. Serial-interface timing is shown in Figure 2. LD_RX must not be toggled. Functional Modes There are three functional modes controlled through the serial interface or external pins (Table 2): transmit mode, transmit disable mode, and software shutdown mode. Transmit Mode Transmit mode is the normal active mode. The TXEN pin must be held high in this mode. Transmit-Disable Mode When in transmit-disable mode, the power amplifier is completely shut off. This mode is activated by taking TXEN low. This mode is typically used between bursts in TDMA systems. Transients are controlled by the action of the transformer balance. High Power and Low Noise Modes The upstream has two transmit modes, high power (HP) and low noise (LN) Each of these modes is actuated by the high-order bit D7 of the 8 bit programming word. When D7 is a logic 0, LN mode is enabled. Each of these modes is characterized by activation of a distinct output stage. In HP mode, the output stage exhibits 15 dB higher gain than LN mode. The lower gain of the LN output stage allows for significantly lower output noise and lower transmit-disable transients. The full range of gain codes (D6-D0) may be used in either mode. For DOCSIS applications, HP mode is recommended for output levels at or above +42 dBmV (D7 = 1, gain code = 87), LN mode when the output level is below +42 dBmV (D7 = 0, gain code = 115). Table 2. Chip-State Control Bits TXEN X 0 1 1 1 1 1 1 1 1 D7 X X 1 0 0 0 0 1 1 1 D6 X X X X 0 1 1 1 1 1 D5 X X X X 1 0 1 0 1 1 D4 X X X X 1 1 1 1 0 1 D3 X X X X 0 0 0 0 1 1 D2 X X X X 0 0 0 1 1 1 D1 X X X X 0 0 1 1 1 0 D0 X X X X 0 0 1 1 0 1 48 80 115 87 110 125 -26 -10 8 9 20 28 GAIN STATE (DECIMAL) GAIN (DB) STATES Shutdown Mode Transmit-Disable Mode Transmit Mode-Enable Mode, High Power Transmit Mode-Enable Mode, Low Noise A G B C DE F LD_TX (Pin 6) CLOCK (Pin 11) DATA (Pin 12) D7 D6 D5 D4 D3 D2 D1 D0 A. tSENS B. tSDAS C. tSDAH D. tSCKL E. tSCKH F. tSENH G. tDATAH/tDATAL Figure 2. Serial-Interface Timing Diagram. Tx Timing Characteristics PARAMETER SEN to SCLK Setup Time SEN to SCLK Hold Time SDA to SCLK Setup Time SDA to SCLK Hold Time SDA Pulse Width High SDA Pulse Width Low SCLK Pulse Width High SCLK Pulse Width Low SYMBOL MIN tSENS tSENH tSDAS tSDAH tDATAH tDATAL tSLKH tSLKL 20 10 10 20 50 50 50 50 TYP MAX UNITS ns ns ns ns ns ns ns ns Table 1. Serial-Interface Control Word BIT MSB 7 6 5 4 3 2 1 LSB 0 MNEMONIC D7 D6 D5 D4 D3 D2 D1 D0 DESCRIPTION High-power/low-noise mode select Gain Control, Bit 6 Gain Control, Bit 5 Gain Control, Bit 4 Gain Control, Bit 3 Gain Control, Bit 2 Gain Control, Bit 1 Gain Control, Bit 0 * Typical gain at +25OC and VCC = +5 V. 303 S. Technology Court, Broomfield, CO 80021 303-327-3030 8 REV. A www.sirenza.com 4/1/2005