SHF-0189Z

Product Description Sirenza Microdevices’ SHF-0189 is a high performance AlGaAs/GaAs Heterostructure FET (HFET) housed in a low-cost surface-mount plastic package. The HFET technology improves breakdown voltage while minimizing Schottky leakage current resulting in higher PAE and improved linearity. Output power at 1dB compression for the SHF-0189 is +27 dBm when biased for Class AB operation at 8V,100mA. The +40 dBm third order intercept makes it ideal for high dynamic range, high intercept point requirements. It is well suited for use in both analog and digital wireless communication infrastructure and subscriber equipment including 3G, cellular, PCS, fixed wireless, and pager systems. SHF-0189 SHF-0189Z Pb RoHS Compliant & Green Package 0.05 - 6 GHz, 0.5 Watt GaAs HFET The matte tin finish on Sirenza’s lead-free package utilizes a post annealing process to mitigate tin whisker formation and is RoHS compliant per EU Product Features Directive 2002/95. This package is also manufactured with green molding • Now available in Lead Free, RoHS compounds that contain no antimony trioxide nor halogenated fire retarCompliant, & Green Packaging dants. Typical Gain Performance (8V,100mA) 35 30 25 20 15 10 5 0 -5 0 1 2 3 4 5 6 Frequency (GHz) 7 8 Gain, Gmax (dB) Gmax • High Linearity Performance at 1.96 GHz +27 dBm P1dB +40 dBm Output IP3 +16.5 dB Gain • High Drain Efficiency • See App Note AN-031 for circuit details Gain Applications • Analog and Digital Wireless Systems • 3G, Cellular, PCS • Fixed Wireless, Pager Systems Sym bol D e v ic e C h a r a c t e r is t ic s ( u n le s s o t h e r w is e n o t e d ) T e s t C o n d it io n s , 2 5 C V D S = 8 V , ID Q = 1 0 0 m A Test F re q u e n c y 0 .9 0 G H z 1 .9 6 G H z 0 .9 0 G H z 1 .9 6 G H z 0 .9 0 G H z 1 .9 6 G H z 0 .9 0 G H z 1 .9 6 G H z 0 .9 0 G H z 1 .9 6 G H z 1 .9 6 G H z U n its M in Typ 2 3 .3 2 0 .1 1 8 .4 1 4 .7 1 8 .6 1 6 .7 40 40 2 7 .2 2 7 .5 3 .2 294 198 -1 .9 -1 7 -2 2 80 - M ax Gm ax S M a x i m u m A v a i la b le G a i n In s e r t i o n G a i n P o w e r G a in [2 ] [1 ] Z S= Z S*, Z L= Z L* Z S= Z L= 5 0 O hm s A p p li c a t i o n C i r c u i t [2 ] dB dB dBm dBm dBm dB mA mS V V V o 1 6 .6 2 0 .2 21 G a in O IP 3 P1dB NF ID g V BV BV SS 204 144 - 3 .0 - 384 252 -1 .0 -1 5 -1 7 8 .0 160 0 .8 O u t p u t T h i r d O r d e r In t e r c e p t P o i n t O u tp u t 1 d B C o m p r e s s i o n P o i n t N o is e F ig u re S a tu r a te d D r a i n C u r r e n t T r a n c o n d u c ta n c e P i n c h - O f f V o lt a g e [1 ] [2 ] A p p li c a t i o n C i r c u i t A p p li c a t i o n C i r c u i t A p p li c a t i o n C i r c u i t V V V DS =V DSP ,V GS = 0V m D =V S ,V DSP = - 0 .2 5 V GS P D = 2 . 0 V , ID S = 0 . 6 m A S GS G a t e - S o u r c e B r e a k d o w n V o lt a g e G a t e - D r a i n B r e a k d o w n V o lt a g e T h e rm a l R e s i s ta n c e O p e r a t i n g V o lt a g e O p e r a tin g C u rr e n t P o w e r D i s s i p a ti o n [3 ] [1 ] [1 ] IG S = 1 . 2 m A , d r a i n o p e n IG D = 1 . 2 m A , V GS GD = - 5 .0 V R th V DS ju n c t i o n - t o - le a d d ra in -s o u rc e d ra in -s o u rc e , q u ie s c e n t C /W V mA W ID Q P D IS S [3 ] [3 ] [1] 100% tested - Insertion gain tested using a 50 ohm contact board (no matching circuitry) during final production test. [2] Sample tested - Samples pulled from each wafer/package lot. Sample test specifications are based on statistical data from sample test measurements. The test fixture is an engineering application circuit board. The application circuit was designed for the optimum combination of linearity, P1dB, and VSWR. [3] Maximum recommended power dissipation is specified to maintain TJ