SHF-0589

Product Description Sirenza Microdevices’ SHF-0589 is a high performance AlGaAs/ GaAs Heterostructure FET (HFET) housed in a low-cost surface-mount plastic package. The HFET technology improves breakdown voltage while minimizing Schottky leakage current resulting in higher PAE and improved linearity. Output power at 1dB compression is +33.4 dBm when biased for Class AB operation at 7V,345mA at 1.96 GHz. The +46.5 dBm third order intercept makes it ideal for high dynamic range, high intercept point requirements. It is well suited for use in both analog and digital wireless communication infrastructure and subscriber equipment including 3G, cellular, PCS, fixed wireless, and pager systems. Typical Gain Performance (7V,345mA) SHF-0589 0 Symbol 1 D evice C haracteristics D E (unless otherw ise noted) Test C onditions, 25C VDS=7V, IDQ=345mA D Frequency (GHz) 2 3 4 5 6 FO 40 35 30 25 20 15 10 5 0 Gain, Gmax (dB) Gmax Gain Applications • Analog and Digital Wireless Systems • 3G, Cellular, PCS • Fixed Wireless, Pager Systems R Test Frequency 0.90 GHz 1.96 GHz 2.14 GHz 0.90 GHz 1.96 GHz 1.96 GHz 1.96 GHz 1.96 GHz 1.96 GHz N E • High Drain Efficiency (>50% at P1dB) W U nits dB dB dB dB dB m dB m dB m dB m dB mA mS V V V o +33.4 dBm P1dB +46.5 dBm OIP3 +26 dBm IS-95 Channel Power +11.5 dB Gain • +23.7 dBm W-CDMA Channel Power D E Min 14.1 10.3 44 31.9 816 576 -3.0 3.7 -17 -22 23 - S Typ 22.9 17.4 16.6 15.7 11.5 46.5 33.4 26.2 Max 17.3 12.7 1536 1008 -1.0 -15 -17 8.0 480 2.4 1176 792 -1.9 Product Features • High Linearity Performance at 1.96 GHz Gmax S 21 Gai n OIP3 P 1dB PCHAN NF IDSS gm VP Maxi mum Avai lable Gai n Inserti on Gai n Power Gai n [1] M M E [2] Output Thi rd Order Intercept Poi nt Output 1dB C ompressi on Poi nt [2] IS-95 C hannel Power (-45dBc AC PR) Saturated D rai n C urrent Tranconductance C O Noi se Fi gure [2] BVGS R E Pi nch-Off Voltage [1] [1] Gate-Source Breakdown Voltage [1] BVGD Rth V DS IDQ Gate-D rai n Breakdown Voltage Thermal Resi stance [3] [3] [3] N ZS=ZS*, ZL=ZL* ZS=ZL= 50 Ohms Appli cati on C i rcui t Appli cati on C i rcui t Appli cati on C i rcui t Appli cati on C i rcui t Appli cati on C i rcui t VDS= VDSP, VGS= 0V VDS= VDSP, VGS= -0.25V VDS= 2.0V, IDS= 2.4mA IGS= 4.8mA, drai n open IGD= 4.8mA, VGS= -5.0V juncti on-to-lead drai n-source drai n-source, qui escent [2] C /W V mA C N O T Operati ng Voltage Operati ng C urrent PDISS Power D i ssi pati on [1] 100% tested - Insertion gain tested using a 50 ohm contact board (no matching circuitry) during final production test. [2] Sample tested - Samples pulled from each wafer/package lot. Sample test specifications are based on statistical data from sample test measurements. The test fixture is an engineering application circuit board. The application circuit was designed for the optimum combination of linearity, P1dB, and VSWR. [3] Maximum recommended power dissipation is specified to maintain TJ