SLD-2083CZ

SLD-2083CZ Product Description Sirenza Microdevices’ SLD-2083CZ is a robust 12 Watt high performance LDMOS transistor designed for operation to 2700MHz. It is an excellent solution for applications requiring high linearity and efficiency at a low cost. The SLD-2083CZ is typically used in the design of driver stages for power amplifiers, repeaters, and RFID applications. The power transistor is fabricated using Sirenza’s high performance XeMOS IITM process. Pb RoHS Compliant & Green Package 12 Watt Discrete LDMOS FET in Ceramic Package Functional Schematic Diagram Product Features ESD Protection • • • • • • 12 Watt Output P1dB Single Polarity Supply Voltage High Gain: 18 dB at 915 MHz High Efficiency: 47% at 10W CW XeMOS II LDMOS Integrated ESD Protection, Class 1B Applications Case Flange = Ground RF Specifications Symbol Frequency Gain Efficiency IRL Parameter Frequency of Operation 10 Watt CW, 902 - 928MHz Drain Efficiency at 10 Watt CW, 915MHz • • • • • Base Station PA driver Repeaters RFID Military Communication GSM/CDMA Unit MHz dB % dB dBc Watt Watt Watt ºC/W Min 10 17 40 Typ 18 47 -15 -28 12 1.6 3.6 4 Max 2700 -10 -26 - Input Return Loss, 10 Watt Output Power, 915MHz 3rd Order IMD at 10 Watt PEP (Two Tone), 915MHz 1dB Compression (P1dB), 915MHz Linearity IS-95, 9 Ch Fwd, Offset=750KHz, ACPR Integrated Bandwidth, ACPR=-55dB IS-95, 9 Ch Fwd, Offset=750KHz, ACPR Integrated Bandwidth, ACPR=-45dB RTH Thermal Resistance (Junction-to-Case) Test Conditions VDS = 28.0V, IDQ = 125mA, TFlange = 25ºC T DC Specifications Symbol gm VGSThreshold VDS Breakdown Ciss Crss Coss RDSon Parameter Forward Transconductance @ 125mA IDS IDS=3mA 1mA IDS current Input Capacitance (Gate to Source) VGS=0V, VDS=28V Reverse Capacitance (Gate to Drain) VGS=0V, VDS=28V Output Capacitance (Drain to Source) VGS=0V, VDS=28V Drain to Source Resistance, VGS=10V, VDS=250mV Unit mA / V Volt Volt pF pF pF Ω Min Typical 590 3.8 65 27.5 0.81 14.65 0.6 Max The information provided herein is believed to be reliable at press time. Sirenza Microdevices assumes no responsibility for inaccuracies or ommisions. Sirenza Microdevices assumes no responsibility for the use of this information, and all such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. Sirenza Microdevices does not authorize or warrant any Sirenza Microdevices product for use in life-support devices and/or systems. Copyright 2005 Sirenza Microdevices, Inc. All worldwide rights reserved. 303 S. Technology Court, Broomfield, CO 80021 Phone: (800) SMI-MMIC 1 http://www.sirenza.com EDS-103754 Rev E SLD-2083CZ 12 Watt LDMOS FET Quality Specifications Parameter ESD Rating MTTF Description Human Body Model 85oC Leadframe, 200oC Channel Unit Volts Hours Typical 750 1.2 X 106 Pin Description Pin # 1 2 Flange Function Gate Drain Source, Gnd Description Transistor RF input and gate bias voltage. The gate bias voltage must be temperature compensated to maintain constant bias current over the operating temperature range. Care must be taken to protect against video transients that exceed the recommended maximum input power or voltage. . Transistor RF output and drain bias voltage. Typical voltage is 28V. Exposed area on the bottom side of the package needs to be mechanically attached to the ground plane of the board for optimum thermal and RF performance. See mounting instructions for recommendation. Pin Diagram ESD Protection Pin 1 Pin 2 Note 1: Gate voltage must be applied to VGS lead concurrently or after application of drain voltage to prevent potentially destructive oscillations. Bias voltages should never be applied to the transistor unless it is properly terminated on both input and output. Note 2: The required VGS corresponding to a specific IDQ will vary from device to device due to the normal die-to-die variation in threshold voltage withLDMOS transistors. Note 3: The threshold voltage (VGSTH) of LDMOS transistors varies with device temperature. External temperature compensation may be required. See Sirenza application notes AN-067 LDMOS Bias Temperature Compensation. Case Flange = Ground Absolute Maximum Ratings Parameters Drain Voltage (VDS ) Gate Voltage (VGS) RF Input Power Load Impedance for Continuous Operation Without Damage Output Device Channel Temperature Lead Temperature During Solder Reflow Operating Temperature Range Storage Temperature Range Value 35 20 +33 10:1 +200 +270 -20 to +90 -40 to +100 Unit V V dBm VSWR ºC ºC ºC ºC Operation of this device beyond any one of these limits may cause permanent damage. For reliable continuous operation see typical setup values specified in the table on page one. Caution: ESD Sensitive Appropriate precaution in handling, packaging and testing devices must be observed. 303 S. Technology Court Broomfield, CO 80021 Phone: (800) SMI-MMIC 2 http://www.sirenza.com EDS-103754 Rev E SLD-2083CZ 12 Watt LDMOS FET Typical Performance Curves in 900 MHz Application Circuit CW Gain, Efficiency vs Pout Vdd=28V, Idq=125mA, Freq=915 MHz CW Gain, Efficiency, IRL vs Frequency Vdd=28V, Idq=125mA, Pout=10W 25 24 23 22 Gain (dB) 21 20 19 18 17 16 15 0 2 60 55 50 45 Efficiency (%) 40 35 30 60 0 50 Gain (dB), Efficiency (%) -4 40 Gain Efficiency IRL -8 30 -12 Gain Efficiency 25 20 15 10 20 -16 10 -20 4 6 8 Pout (W) 10 12 14 16 0 900 905 910 915 920 -24 925 Frequency (MHz) 60 2 Tone Gain, Efficiency, Linearity and IRL vs Frequency Vdd=28V, Idq=125mA, Pout=10W PEP, Delta F=1 MHz Gain IM3 IM7 Efficiency IM5 IRL 0 45 40 35 2 Tone Gain, Efficiency, Linearity vs Pout Vdd=28V, Idq=125mA, Freq=915 MHz, Delta F=1 MHz -25 -30 -35 -40 -45 -50 -55 -60 IMD (dBc) 50 Gain (dB), Efficiency (%) -10 Gain (dB), Efficiency (%) 40 -20 IMD(dBc), IRL (dB) 30 25 20 15 10 5 30 -30 20 -40 10 -50 Gain IM3 IM7 1 3 5 7 Pout (W PEP) Efficiency IM5 -65 -70 0 900 905 910 915 920 Frequency (MHz) -60 925 0 9 11 13 To receive Gerber files, DXF drawings, and assembly recommendations for the test board with fixture, contact applications support at support@sirenza.com. 303 S. Technology Court Broomfield, CO 80021 Phone: (800) SMI-MMIC 3 http://www.sirenza.com EDS-103754 Rev E Input Return Loss (dB) SLD-2083CZ 12 Watt LDMOS FET 900 MHz Application Circuit Bill of Materials - 900 MHz Application Circuit Reference Designation C1, C2 L1 L2 L3 C10 C11,C20 C12, C21 C18 C19, C22 J1, J2 J3 R1 R2 R3 R30 R5 R7 R9 R90 RT1 U1 6 Screws 6 Washers PCB Heatsink Description CAP 68PF250V 5% 0603 IND, 5.1 Nh 5% 0603 IND, 2.7 nH +/- 0.3 nH 0603 IND, 4.7 nH 10% 0603 CAP 0.1 UF 16V 10% 0603 CAP 1000 PF 50V 10% 603 CAP 68PF 250V 5% 603 LF CAP 10 UF 35V 20% TAN T ELECT CAP 0.1 UF 50V 10% 805 Connector SMA END 0.037 Connector MTA SMD R/A 2 PIN RES 324 1/16W 1% 603 RES 49.9 1/10W 1% 805 POT TRIM 500 OHM 2MM RES 49.9 1/16W 1% 603 RES 130 1/16W 1% 603 RES 210 1/16W 1% 603 RES 0 1/16W 5% 603 RES 1.0K 1/16W 1% 603 THERMISTOR 100K 5% 603 IC VOLT REG 100 MA 5 V SOT-23 SCREW #2-56 PHILIPS PAN HEAD WASHER #2 FLAT SS PCB, 30 mils thick Dk=3.48 machined alumininum Mfg ATC coilcraft Toko Toko AVX AVX ATC Kemet Panasonic Johnson Amp Panasonic Panasonic Panasonic Panasonic Panasonic Phillips Panasonic Panasonic Panasonic National various various Rogers various Mfg part # 600S680JT250XT 0603CS-5N1XJB LL1608-F2N7S LL1608-F4N7K 0603YG104ZA2A 06035C102KAT2A 600S680JT250XT T494D106M035AS ECJ2YB1H104K 142-0751-821 640455-2 ERJ-3EKF3240V ERJ-6ENF49R9V EVM-2WSX80B52 ERJ-EKF49R9V ERJ-3EKF1300V 9C06031A2100FKHFT ERJ-3GSY0R00V ERJ-3EKF1001V ERT-J1VV104J LM3480IM3-5.0 4350 - 303 S. Technology Court Broomfield, CO 80021 Phone: (800) SMI-MMIC 4 http://www.sirenza.com EDS-103754 Rev E SLD-2083CZ 12 Watt LDMOS FET Impedance data Device under test Input Matching Network Z source Output Matching Network Z load Zsource and Zload are the optimal impedances presented to the SLD-2083CZ when operating at 28V, Idq=125mA, Pout=10 W PEP Impedance Data Frequency (MHz) 870 880 900 930 960 Zsource 0.50 + j 2.0 0.55 + j 1.9 0.60 + j 1.8 0.65 + j 1.7 0.80 + j 1.4 Zload 4.3+ j 1.9 4.3 + j 2.0 4.4+ j 2.0 4.5 + j 2.0 4.7 + j 2.0 303 S. Technology Court Broomfield, CO 80021 Phone: (800) SMI-MMIC 5 http://www.sirenza.com EDS-103754 Rev E SLD-2083CZ 12 Watt LDMOS FET Package Outline Drawing Chamferred Lead is FET Drain Lead Coplanarity Lead foot to backside 0.000 ± 0.002 0.000±0.002 0.290 0.160 R0.015 DETAIL A TOP VIEW 0.200 0.100 0.090 0.160 0.140 0.050 0.160 0.008 SIDE VIEW DETAIL A END VIEW Recommended Landing Pads for the RF083 Package All Dimensions are in inches Part Number Ordering Information Part Number SLD-2083CZ Devices Per Reel 500 Reel Size 7’’ 303 S. Technology Court Broomfield, CO 80021 Phone: (800) SMI-MMIC 6 http://www.sirenza.com EDS-103754 Rev E