SPF-3143

Product Description Sirenza Microdevices’ SPF-3143 is a high performance 0.5µm pHEMT Gallium Arsenide FET. This 600µm device is ideally biased at 3V,20mA for lowest noise performance and battery powered requirements. At 5V,40mA the device can deliver OIP3 of 31dBm. It provides ideal performance as a driver stage in many commercial and industrial LNA applications. Typical Gain Performance PPreliminary reliminary SPF-3143 Low Noise pHEMT GaAs FET Product Features • • • • • • • DC-10 GHz Operation 0.58 dB NFMIN @ 2 GHz 21 dB GMAX @ 2 GHz +31 dBm OIP3 (5V,40mA) +18 dBm P1dB (5V,40mA) Low Current, Low Cost Apps circuits available for key bands 40 35 30 25 20 15 10 5 0 0 2 5V 40mA 3V 20mA Gain, Gmax (dB) Gmax Gain Applications 6 8 10 • • • • Analog and Digital Wireless Systems 3G, Cellular, PCS Fixed Wireless, Pager Systems Driver Stage for Low Power Applications Test Frequency 0.9GHz 1.9GHz 0.9GHz 1.9GHz 0.9GHz 1.9GHz 1.9GHz 1.9GHz 1.9GHz 4 Frequency (GHz) Symbol Device Characteristics Test Condition VDS=5V, IDQ=40mA, 25C (unless otherwise noted) ZS=ZS*, ZL = ZL* ZS=ΓOPT, ZL = ZL* ZS=ZL=50Ω LNA Application Circuit Board LNA Application Circuit Board LNA Application Circuit Board LNA Application Circuit Board VDS=2V, IDS=0.1mA VDS=2V, VGS=0V VDS=2V, VGS=-0.3V IGS=300uA, drain open IGD=300uA, source open junction to lead drain-source drain-source Units Min Typ 23.3 19.9 0.36 0.58 20.1 0.9 15.1 31.0 17.7 Max GMAX NFMIN S21 NF Gain OIP3 P1dB VP IDSS gm BVGSO BVGDO Rth VDS IDS Maximum Available Gain Minimum Noise Figure Insertion Gain Noise Figure Gain Output 3rd Order Intercept Point Output 1dB Compression Point Pinchoff Voltage Saturated Drain Current Transconductance Gate-Source Breakdown Voltage Gate-Drain Breakdown Voltage Thermal Resistance Operating Voltage Operating Current dB dB dB dB dB dBm dBm V mA mS V V C/W V mA -1.4 -1.0 180 210 -10 -12 200 -0.6 -7 -10 5.5 55 The information provided herein is believed to be reliable at press time. Sirenza Microdevices assumes no responsibility for inaccuracies or omissions. Sirenza Microdevices assumes no responsibility for the use of this information, and all such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. Sirenza Microdevices does not authorize or warrant any Sirenza Microdevices product for use in life-support devices and/or systems. Copyright 2003 Sirenza Microdevices, Inc. All worldwide rights reserved. 303 Technology Court, Broomfield, CO 80021 Phone: (800) SMI-MMIC http://www.sirenza.com EDS-103162 Rev B 1 Junction Temperature Calculation MTTF is inversely proportional to the device junction temperature. For junction temperature and MTTF considerations the device operating conditions should also satisfy the following expression: PDC < (TJ - TL) / RTH where: PDC = IDS * VDS (W) TJ = Junction Temperature (C) TL = Lead Temperature (pin 2) (C) RTH = Thermal Resistance (C/W) Preliminary SPF-3143 Low Noise pHEMT GaAs FET Absolute Maximum Ratings Parameter Drain Current Forward Gate Current Reverse Gate Current Drain-to-Source Voltage Gate-to-Source Voltage RF Input Power Storage Temperature Range Power Dissipation Junction Temperature Symbol IDS IGSF IGSR VDS VGS PIN Tstor PDISS TJ Value 180 600 600 7 0 15 -40 to + 150 325 150 Unit mA uA uA V V dBm C mW C Biasing Details The SPF-3143 is a depletion mode FET and requires a negative gate voltage to achieve pinchoff. As such, power supply sequencing circuitry is strongly recommended to prevent damaging bias transients during turn-on. Active bias circuitry is also recommended to maintain a constant drain current from part-to-part. Operation of this device beyond any one of these limits may cause permanent damage. For reliable continuous operation, the device voltage and current must not exceed the maximum operating values specified in the table on page 1. Peak RF Performance Under Optimum Matching Conditions Freq (GHz ) 0.90 1.90 [4] VDS (V) 3 5 3 5 IDQ (mA) 20 40 20 40 NFMIN [4] (dB) 0.25 0.36 0.50 0.58 Gmax (dB) 21.5 23.3 18.3 19.1 P1dB [5] (dBm) 15 18 15 18 OIP3 [6] (dBm) 29 31 29 31 ZSOPT S G D Z LOPT ZS=ΓOPT, ZL=ZL*, The input matching circuit losses have been de-emebedded. [5] ZS=ZSOPT, ZL=ZLOPT, where ZSOPT and ZLOPT have been tuned for max P1dB [6] ZS=ZSOPT, ZL=ZLOPT, where ZSOPT and ZLOPT have been tuned for max OIP3 Note: Optimum NF, P1dB, and OIP3 performance cannot be achieved simultaneously. Typical Performance - Noise Parameters Freq (GHz ) 0.90 1.90 [7] VDS (V) 3 5 3 5 IDS (mA) 20 40 20 40 NFMIN [7] (dB) 0.25 0.36 0.50 0.58 ΓOPT Mag ∠ Ang 0.70 ∠ 12.1 0.66 ∠ 12.6 0.46 ∠ 26.4 0.38 ∠ 28.1 rN 0.14 0.14 0.13 0.13 Gmax (dB) 21.5 23.3 18.3 19.1 ZS=ΓOPT, ZL=ZL*, NFMIN is a noise parameter for which the input matching circuit losses have been de-emebedded. The noise parameters were measured using a Maury Microwave Automated Tuner System. The device was mounted on a 0.010” PCB with platedthru holes close to pins 2 and 4. 303 Technology Court, Broomfield, CO 80021 Phone: (800) SMI-MMIC http://www.sirenza.com EDS-103162 Rev B 2 Caution: ESD sensitive Appropriate precautions in handling, packaging and testing devices must be observed. ESD class rating to be determined. Preliminary SPF-3143 Low Noise pHEMT GaAs FET Pin Description Pin # 1 2 3 4 Part Number Ordering Information Part Number SPF-3143 Reel Siz e 7" Devices/Reel 3000 Function Gate Source Drain NC RF Input / Gate Bias Description Connection to ground. Use via holes to reduce lead inductance. Place vias as close to ground leads as possible. RF Output / Drain Bias No Connection / Recommend grounding pin Part Symbolization The part will be symbolized with the “F31” designator and a dot signifying pin 1 on the top surface of the package. Pin Designation 4 3 Recommended PCB Layout SOT-343 Package 1 2 Plated Thru Holes (0.020" DIA) Ground Plane Use multiple plated-through vias holes located close to the package pins to ensure a good RF ground connection to a continuous groundplane on the backside of the board. D e e Package Dimensions L HE C L F31 C L E SYMBOL E NOM 1.25 2.05 2.10 1.05 0.90 0.05 0.25 0.65 0.375 0.675 0.14 0.20 Q1 b1 C D HE A A2 A1 b NOTE: 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. DIMENSIONS ARE INCLUSIVE OF PLATING. 3. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH & METAL BURR. 4. ALL SPECIFICATIONS COMPLY TO EIAJ SC70. 5. DIE IS FACING UP FOR MOLD AND FACING DOWN FOR TRIM/FORM. ie :REVERSE TRIM/FORM. 6. PACKAGE SURFACE TO BE MIRROR FINISH. Q1 e b b1 c L A2 A1 A 303 Technology Court, Broomfield, CO 80021 Phone: (800) SMI-MMIC http://www.sirenza.com EDS-103162 Rev B 3