SPF-3143Z

SPF-3143Z Product Description Sirenza Microdevices’ SPF-3143Z is a high performance 0.5μm pHEMT Gallium Arsenide FET. This 600μm device is ideally biased at 3V, 20mA for lowest noise performance and battery powered requirements. At 5V, 40mA the device can deliver OIP3 of 32.5 dBm. It provides ideal performance as a driver stage in many commercial and industrial LNA applications. The matte tin finish on Sirenza’s lead-free package utilizes a post annealing process to mitigate tin whisker formation and is RoHS compliant per EU Directive 2002/95. This package is also manufactured with green molding compounds that contain no antimony trioxide nor halogenated fire retardants. Typical Gain Performance Pb RoHS Compliant & Green Package Low Noise pHEMT GaAs FET Product Features • Available in Lead free, RoHS compliant, & Green packaging • DC-3.5 GHz Operation • 0.58 dB NFMIN @ 2 GHz • 21 dB GMAX @ 2 GHz • +31 dBm OIP3 (5V,40mA) • +17.7 dBm P1dB (5V,40mA) • Low Current, Low Cost • Apps circuits available for key bands 40 35 30 25 20 15 10 5 0 0 5V 40mA Gain, Gmax (dB) 3V 20mA Gmax Gain Applications • • • • Analog and Digital Wireless Systems 3G, Cellular, PCS Fixed Wireless, Pager Systems Driver Stage for Low Power Applications 2 4 Frequency (GHz) 6 8 10 Test Conditions Symbol Parameters VDS=5V, IDQ=40mA, 25C (unless otherwise noted) Units Test Frequency (GHz) Min. Typ. Max. GMAX NFMIN S21 NF Gain OIP3 P1dB VP IDSS gm BVGSO BVGDO VDS IDS RTH, j-l Maximum Available Gain Minimum Noise Figure Insertion Gain Noise Figure Gain Output Third Order Intercept Point Output Power at 1dB Compression Pinchoff Voltage Saturated Drain Current Transconductance Gate-Source Breakdown Voltage Gate-Drain Breakdown Voltage Device Operating Voltage Device Operating Current Thermal Resistance (junction - lead) ZS=ZS*, ZL=ZL* ZS=ΓOPT, ZL=ZL* ZS=ZL=50Ω Application Circuit Application Circuit Application Circuit, Tone Spacing = 1MHz, Pout per tone = 0 dBm Application Circuit VDS = 2V, IDS = 0.6mA VDS = 2V, VGS = 0 V VDS = 2V, VGS = 0 V IGS= 300 μA, drain open IGD= 300 μA, source open drain-source drain-source junction to lead dB dB dB dB dB dBm 0.9 1.9 0.9 1.9 0.9 1.9 1.9 1.9 1.9 18.2 14.1 30.5 19.0 -1.4 23.3 19.9 0.36 0.58 19.7 0.8 15.6 32.5 20.5 -1.0 180 210 -10 -12 21.2 1.0 17.1 V mA mS V V V mA °C/W -0.6 -7 -7 5.5 38 40 200 42 The information provided herein is believed to be reliable at press time. Sirenza Microdevices assumes no responsibility for inaccuracies or omissions. Sirenza Microdevices assumes no responsibility for the use of this information, and all such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. Sirenza Microdevices does not authorize or warrant any Sirenza Microdevices product for use in life-support devices and/or systems. Copyright 2006 Sirenza Microdevices, Inc. All worldwide rights reserved. 303 Technology Court, Broomfield, CO 80021 Phone: (800) SMI-MMIC http://www.sirenza.com EDS-103162 Rev C 1 SPF-3143Z Low Noise pHEMT GaAs FET Junction Temperature Calculation MTTF is inversely proportional to the device junction temperature. For junction temperature and MTTF considerations the device operating conditions should also satisfy the following expression: PDC < (TJ - TL) / RTH where: PDC = IDS * VDS (W) TJ = Junction Temperature (C) TL = Lead Temperature (pin 2) (C) RTH = Thermal Resistance (C/W) Absolute Maximum Ratings Parameter Drain Current Forward Gate Current Reverse Gate Current Drain-to-Source Voltage Gate-to-Source Voltage RF Input Power Storage Temperature Range Power Dissipation Junction Temperature Symbol IDSS IGSF IGSR V DS VGS PIN Tstor PDISS TJ Value 180 600 600 7 0 15 -40 TO +150 325 +150 Unit mA μA μA V V dB m C mW C Biasing Details The SPF-3143Z is a depletion mode FET and requires a negative gate voltage to achieve pinchoff. As such, power supply sequencing circuitry is strongly recommended to prevent damaging bias transients during turn-on. Active bias circuitry is also recommended to maintain a constant drain current from part-to-part. Operation of this device beyond any one of these limits may cause permanent damage. For reliable continuous operation, the device voltage and current must not exceed the maximum operating values specified in the table on page 1. Peak RF Performance Under Optimum Matching Conditions Freq (GHz ) 0.90 1.90 [1] VDS (V) 3 5 3 5 IDQ (mA) 20 40 20 40 NFMIN [1] (dB) 0.25 0.36 0.50 0.58 Gmax (dB) 21.5 23.3 18.3 19.1 P1dB [2] (dBm) 15 18 15 18 OIP3 [3] (dBm) 29 31 29 31 ZSOPT S G D Z LOPT ZS=ΓOPT, ZL=ZL*, The input matching circuit losses have been de-emebedded. [2] ZS=ZSOPT, ZL=ZLOPT, where ZSOPT and ZLOPT have been tuned for max P1dB [3] ZS=ZSOPT, ZL=ZLOPT, where ZSOPT and ZLOPT have been tuned for max OIP3 Note: Optimum NF, P1dB, and OIP3 performance cannot be achieved simultaneously. Typical Performance - Noise Parameters Freq (GHz ) 0.90 1.90 VDS (V) 3 5 3 5 IDS (mA) 20 40 20 40 NFMIN [4] (dB) 0.25 0.36 0.50 0.58 Γ OPT Mag ∠ Ang 0.70 ∠ 12.1 0.66 ∠ 12.6 0.46 ∠ 26.4 0.38 ∠ 28.1 rN 0.14 0.14 0.13 0.13 Gmax (dB) 21.5 23.3 18.3 19.1 [4] ZS=ΓOPT, ZL=ZL*, NFMIN is a noise parameter for which the input matching circuit losses have been de-emebedded. The device was mounted on a 0.010” PCB with plated-thru holes close to pins 2 and 4. Caution: ESD sensitive Appropriate precautions in handling, packaging and testing devices must be observed. ESD class rating 1B. MSL (Moisture Sensitivity Level) Rating: Level 1 303 Technology Court, Broomfield, CO 80021 Phone: (800) SMI-MMIC http://www.sirenza.com EDS-103162 Rev C 2 SPF-3143Z Low Noise pHEMT GaAs FET Pin Description Pin # 1 2 3 4 Part Number Ordering Information Part Number SPF-3143Z Reel Siz e 7" Devices/Reel 3000 Function Gate Source Drain Source RF Input / Gate Bias Description Connection to ground. Use via holes to reduce lead inductance. Place vias as close to ground leads as possible. RF Output / Drain Bias No Connection / Recommend grounding pin Part Symbolization The part will be symbolized with the “F31Z” designator and a dot signifying pin 1 on the top surface of the package. Pin Designation 4 3 Recommended PCB Layout SOT-343 Package 1 2 Plated Thru Holes (0.020" DIA) Ground Plane Use multiple plated-through vias holes located close to the package pins to ensure a good RF ground connection to a continuous groundplane on the backside of the board. D e e Package Dimensions L HE C L F31Z C L E SYMBOL E NOM 1.25 2.05 2.10 1.05 0.90 0.05 0.25 0.65 0.375 0.675 0.14 0.20 Q1 b1 C D HE A A2 A1 b NOTE: 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. DIMENSIONS ARE INCLUSIVE OF PLATING. 3. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH & METAL BURR. 4. ALL SPECIFICATIONS COMPLY TO EIAJ SC70. 5. DIE IS FACING UP FOR MOLD AND FACING DOWN FOR TRIM/FORM. ie :REVERSE TRIM/FORM. 6. PACKAGE SURFACE TO BE MIRROR FINISH. Q1 e b b1 c L A2 A1 A 303 Technology Court, Broomfield, CO 80021 Phone: (800) SMI-MMIC http://www.sirenza.com EDS-103162 Rev C 3