514CBA001557BAG

Ultra Series™ Crystal Oscillator Si540 Data Sheet Ultra Low Jitter Any-Frequency XO (125 fs), 0.2 to 1500 MHz KEY FEATURES The Si540 Ultra Series™ oscillator utilizes Silicon Laboratories’ advanced 4th generation DSPLL® technology to provide an ultra-low jitter, low phase noise clock at any output frequency. The device is factory-programmed to any frequency from 0.2 to 1500 MHz with 6 digits Notes: 1. Contact Silicon Labs for non-standard configurations. 2. Total stability includes temp stability, initial accuracy, load pulling, VDD variation, and 20 year aging at 70 °C. 3. For example: 156.25 MHz = 156M250; 25 MHz = 25M0000. Create custom part numbers at www.silabs.com/oscillators. 1.1 Technical Support Frequently Asked Questions (FAQ) www.silabs.com/Si540-FAQ Oscillator Phase Noise Lookup Utility www.silabs.com/oscillator-phase-noise-lookup Quality and Reliability www.silabs.com/quality Development Kits www.silabs.com/oscillator-tools silabs.com | Building a more connected world. Rev. 1.0 | 2 Si540 Data Sheet Electrical Specifications 2. Electrical Specifications Table 2.1. Electrical Specifications VDD = 1.8 V, 2.5 or 3.3 V ± 5%, TA = –40 to 85 ºC Parameter Symbol Temperature Range Min Typ Max Unit –40 — 85 ºC LVPECL, LVDS, CML 0.2 — 1500 MHz HCSL 0.2 — 400 MHz CMOS, Dual CMOS 0.2 — 250 MHz 3.3 V 3.135 3.3 3.465 V 2.5 V 2.375 2.5 2.625 V 1.8 V 1.71 1.8 1.89 V LVPECL (output enabled) — 100 132 mA LVDS/CML (output enabled) — 75 111 mA HCSL (output enabled) — 80 125 mA CMOS (output enabled) — 74 108 mA Dual CMOS (output enabled) — 80 125 mA Tristate Hi-Z (output disabled) — 64 100 mA Frequency stability Grade A –20 — 20 ppm Frequency stability Grade B –10 — 10 ppm Frequency stability Grade C –7 — 7 ppm Frequency stability Grade A –50 — 50 ppm Frequency stability Grade B –25 — 25 ppm Frequency stability Grade C –20 — 20 ppm LVPECL/LVDS/CML — — 350 ps CMOS / Dual CMOS (CL = 5 pF) — 0.5 1.5 ns HCSL, FCLK >50 MHz — — 550 ps All formats 45 — 55 % TA Frequency Range FCLK Supply Voltage VDD Supply Current IDD Temperature Stability Total Stability1 Test Condition/Comment FSTAB Rise/Fall Time (20% to 80% VPP) TR/TF Duty Cycle DC Output Enable (OE)2 VIH 0.7 × VDD — — V VIL — — 0.3 × VDD V TD Output Disable Time, FCLK >10 MHz — — 3 µs TE Output Enable Time, FCLK >10 MHz — — 20 µs Powerup Time tOSC Time from 0.9 × VDD until output frequency (FCLK) within spec — — 10 ms LVPECL Output Option3 VOC Mid-level VDD – 1.42 — VDD – 1.25 V VO Swing (diff) 1.1 — 1.9 VPP silabs.com | Building a more connected world. Rev. 1.0 | 3 Si540 Data Sheet Electrical Specifications Parameter Symbol Test Condition/Comment Min Typ Max Unit VOC Mid-level (2.5 V, 3.3 V VDD) 1.125 1.20 1.275 V Mid-level (1.8 V VDD) 0.8 0.9 1.0 V VO Swing (diff) 0.5 0.7 0.9 VPP VOH Output voltage high 660 750 850 mV VOL Output voltage low –150 0 150 mV VC Crossing voltage 250 350 550 mV CML Output Option (AC-Coupled) VO Swing (diff) 0.6 0.8 1.0 VPP CMOS Output Option VOH IOH = 8/6/4 mA for 3.3/2.5/1.8V VDD 0.85 × VDD — — V VOL IOL = 8/6/4 mA for 3.3/2.5/1.8V VDD — 0.15 × VDD V LVDS Output Option4 HCSL Output Option5 — Notes: 1. Total Stability includes temperature stability, initial accuracy, load pulling, VDD variation, and aging for 20 yrs at 70 ºC. 2. OE includes a 50 kΩ pull-up to VDD for OE active high. Includes a 50 kΩ pull-down to GND for OE active low. NC (No Connect) pins include a 50 kΩ pull-down to GND. 3. 50 Ω to VDD – 2.0 V. 4. Rterm = 100 Ω (differential). 5. 50 Ω to GND. Table 2.2. Clock Output Phase Jitter and PSRR VDD = 1.8 V, 2.5 or 3.3 V ± 5%, TA = –40 to 85 ºC Parameter Phase Jitter (RMS, 12kHz - 20MHz)1 3.2 x 5 mm, FCLK ≥ 100 MHz Symbol Test Condition/Comment Min Typ Max Unit ϕJ Differential Formats — 125 200 fs CMOS, Dual CMOS — 200 — fs Differential Formats — 150 200 fs CMOS, Dual CMOS — 200 — fs 100 kHz sine wave — -83 — 200 kHz sine wave — -83 — 500 kHz sine wave — -82 — 1 MHz sine wave — -85 — Phase Jitter (RMS, 12kHz - 20MHz)1 5 x 7 mm, FCLK ≥ 100 MHz Spurs Induced by External Power Supply Noise, 50 mVpp Ripple. LVDS 156.25 MHz Output PSRR dBc Note: 1. Guaranteed by characterization. Jitter inclusive of any spurs. silabs.com | Building a more connected world. Rev. 1.0 | 4 Si540 Data Sheet Electrical Specifications Table 2.3. 3.2 x 5 mm Clock Output Phase Noise (Typical) Offset Frequency (f) 156.25 MHz LVDS 200 MHz LVDS 644.53125 MHz LVDS 100 Hz –110 –107 –99 1 kHz –121 –120 –109 10 kHz –132 –130 –121 100 kHz –139 –137 –127 1 MHz –151 –149 –138 10 MHz –160 –161 –155 20 MHz –161 –162 –157 Offset Frequency (f) 156.25 MHz LVPECL 200 MHz LVPECL 644.53125 MHz LVPECL 100 Hz –113 –110 –100 1 kHz –123 –120 –110 10 kHz –133 –130 –119 100 kHz –139 –137 –127 1 MHz –151 –149 –138 10 MHz –162 –166 –156 20 MHz –163 –167 –157 Unit dBc/Hz Unit dBc/Hz Phase jitter measured with Agilent E5052 using a differential-to-single ended converter (balun or buffer). Measurements collected for >700 commonly used frequencies. Phase noise plots for specific frequencies are available using our free, online Oscillator Phase Noise Lookup Tool at www.silabs.com/oscillators. Figure 2.1. Phase Jitter vs. Output Frequency silabs.com | Building a more connected world. Rev. 1.0 | 5 Si540 Data Sheet Electrical Specifications Table 2.4. Environmental Compliance and Package Information Parameter Test Condition Mechanical Shock MIL-STD-883, Method 2002 Mechanical Vibration MIL-STD-883, Method 2007 Solderability MIL-STD-883, Method 2003 Gross and Fine Leak MIL-STD-883, Method 1014 Resistance to Solder Heat MIL-STD-883, Method 2036 Moisture Sensitivity Level (MSL) 1 Contact Pads Gold over Nickel Note: 1. For additional product information not listed in the data sheet (e.g. RoHS Certifications, MDDS data, qualification data, REACH Declarations, ECCN codes, etc.), refer to our "Corporate Request For Information" portal found here: www.silabs.com/support/ quality/Pages/RoHSInformation.aspx. Table 2.5. Thermal Conditions Package 3.2 × 5 mm 6-pin CLCC 5 × 7 mm 6-pin CLCC Parameter Symbol Test Condition Value Unit Thermal Resistance Junction to Ambient ΘJA Still Air, 85 ºC 80.3 ºC/W Thermal Resistance Junction to Board ΘJB Still Air, 85 ºC 50.8 ºC/W Max Junction Temperature TJ Still Air, 85 ºC 125 ºC Thermal Resistance Junction to Ambient ΘJA Still Air, 85 ºC 68.4 ºC/W Thermal Resistance Junction to Board ΘJB Still Air, 85 ºC 52.9 ºC/W Max Junction Temperature TJ Still Air, 85 ºC 125 ºC Table 2.6. Absolute Maximum Ratings1 Parameter Symbol Rating Unit TAMAX 95 ºC TS –55 to 125 ºC Supply Voltage VDD –0.5 to 3.8 ºC Input Voltage VIN –0.5 to VDD + 0.3 V ESD HBM (JESD22-A114) HBM 2.0 kV Solder Temperature2 TPEAK 260 ºC TP 20–40 sec Maximum Operating Temp. Storage Temperature Solder Time at TPEAK2 Notes: 1. Stresses beyond those listed in this table may cause permanent damage to the device. Functional operation specification compliance is not implied at these conditions. Exposure to maximum rating conditions for extended periods may affect device reliability. 2. The device is compliant with JEDEC J-STD-020. silabs.com | Building a more connected world. Rev. 1.0 | 6 Si540 Data Sheet Dual CMOS Buffer 3. Dual CMOS Buffer Dual CMOS output format ordering options support either complementary or in-phase signals for two identical frequency outputs. This feature enables replacement of multiple XOs with a single Si540 device. ~ Complementary Outputs ~ In-Phase Outputs Figure 3.1. Integrated 1:2 CMOS Buffer Supports Complementary or In-Phase Outputs silabs.com | Building a more connected world. Rev. 1.0 | 7 Si540 Data Sheet Recommended Output Terminations 4. Recommended Output Terminations The output drivers support both AC-coupled and DC-coupled terminations as shown in figures below. VDD VDD VDD (3.3V, 2.5V) CLK+ Rp R1 R1 CLK+ 50 Ω CLK- Si54x VDD (3.3V, 2.5V) Rp R2 R2 LVPECL Receiver VDD (3.3V, 2.5V) CLK+ VDD Si54x Rp Rp 50 Ω R2 VDD (3.3V, 2.5V) R1 VTT CLK+ 50 Ω LVPECL Receiver 50 Ω VDD CLK- 50 Ω R2 R2 DC-Coupled LVPECL – Thevenin Termination 50 Ω CLK- 50 Ω Si54x AC-Coupled LVPECL – Thevenin Termination R1 50 Ω CLK- 50 Ω R1 LVPECL Receiver AC-Coupled LVPECL - 50 Ω w/VTT Bias 50 Ω Si54x R1 VTT R2 50 Ω 50 Ω LVPECL Receiver DC-Coupled LVPECL - 50 Ω w/VTT Bias Figure 4.1. LVPECL Output Terminations AC Coupled LVPECL Termination Resistor Values DC Coupled LVPECL Termination Resistor Values VDD R1 R2 Rp VDD R1 R2 3.3 V 127 Ω 82.5 Ω 130 Ω 3.3 V 127 Ω 82.5 Ω 2.5 V 250 Ω 62.5 Ω 90 Ω 2.5 V 250 Ω 62.5 Ω silabs.com | Building a more connected world. Rev. 1.0 | 8 Si540 Data Sheet Recommended Output Terminations (3.3V, 2.5V, 1.8V) VDD CLK+ (3.3V, 2.5V, 1.8V) VDD 50 Ω CLK+ 33 Ω 100 Ω CLK50 Ω Si54x LVDS Receiver CLK+ 50 Ω HCSL Receiver Source Terminated HCSL (3.3V, 2.5V, 1.8V) VDD 50 Ω CLK+ 100 Ω CLK50 Ω Si54x 50 Ω 50 Ω Si54x DC-Coupled LVDS (3.3V, 2.5V, 1.8V) VDD 50 Ω CLK- 33 Ω 50 Ω CLK- LVDS Receiver 50 Ω 50 Ω Si54x AC-Coupled LVDS 50 Ω HCSL Receiver Destination Terminated HCSL Figure 4.2. LVDS and HCSL Output Terminations (3.3V, 2.5V, 1.8V) VDD CLK+ VDD (3.3V, 2.5V, 1.8V) 50 Ω CLK 10 Ω 100 Ω CLK- NC 50 Ω Si54x CML Receiver CLK+ Single CMOS Termination VDD (3.3V, 2.5V, 1.8V) 50 Ω 50 Ω CLK+ 50 Ω CLK- VCM CLK- Si54x CMOS Receiver Si54x CML Termination without VCM (3.3V, 2.5V, 1.8V) VDD 50 Ω 50 Ω CML Receiver CML Termination with VCM 10 Ω 10 Ω Si54x 50 Ω 50 Ω CMOS Receivers Dual CMOS Termination Figure 4.3. CML and CMOS Output Terminations silabs.com | Building a more connected world. Rev. 1.0 | 9 Si540 Data Sheet Package Outline 5. Package Outline 5.1 Package Outline (5×7 mm) The figure below illustrates the package details for the 5×7 mm Si540. The table below lists the values for the dimensions shown in the illustration. Figure 5.1. Si540 (5×7 mm) Outline Diagram Table 5.1. Package Diagram Dimensions (mm) Dimension Min Nom Max Dimension Min Nom Max A 1.13 1.28 1.43 L 1.17 1.27 1.37 A2 0.50 0.55 0.60 L1 0.05 0.10 0.15 A3 0.50 0.55 0.60 p 1.70 — 1.90 b 1.30 1.40 1.50 R 0.70 REF c 0.50 0.60 0.70 aaa 0.15 bbb 0.15 ccc 0.08 D D1 5.00 BSC 4.30 4.40 4.50 e 2.54 BSC ddd 0.10 E 7.00 BSC eee 0.05 E1 6.10 6.20 6.30 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. silabs.com | Building a more connected world. Rev. 1.0 | 10 Si540 Data Sheet Package Outline 5.2 Package Outline (3.2×5 mm) The figure below illustrates the package details for the 3.2×5 mm Si540. The table below lists the values for the dimensions shown in the illustration. Figure 5.2. Si540 (3.2×5 mm) Outline Diagram Table 5.2. Package Diagram Dimensions (mm) Dimension Min Nom Max A 1.06 1.17 1.33 b 0.54 0.64 0.74 c 0.35 0.45 0.55 D D1 3.20 BSC 2.55 2.60 e 1.27 BSC E 5.00 BSC 2.65 E1 4.35 4.40 4.45 H 0.45 0.55 0.65 L 0.80 0.90 1.00 L1 0.05 0.10 0.15 p 1.36 1.46 1.56 R 0.32 REF aaa 0.15 bbb 0.15 ccc 0.08 ddd 0.10 eee 0.05 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. silabs.com | Building a more connected world. Rev. 1.0 | 11 Si540 Data Sheet PCB Land Pattern 6. PCB Land Pattern 6.1 PCB Land Pattern (5×7 mm) The figure below illustrates the 5×7 mm PCB land pattern for the Si540. The table below lists the values for the dimensions shown in the illustration. Figure 6.1. Si540 (5×7 mm) PCB Land Pattern Table 6.1. PCB Land Pattern Dimensions (mm) Dimension (mm) C1 4.20 E 2.54 X1 1.55 Y1 1.95 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification. 3. This Land Pattern Design is based on the IPC-7351 guidelines. 4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm. Solder Mask Design 1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad. Stencil Design 1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. The stencil thickness should be 0.125 mm (5 mils). 3. The ratio of stencil aperture to land pad size should be 1:1. Card Assembly 1. A No-Clean, Type-3 solder paste is recommended. 2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components. silabs.com | Building a more connected world. Rev. 1.0 | 12 Si540 Data Sheet PCB Land Pattern 6.2 PCB Land Pattern (3.2×5 mm) The figure below illustrates the 3.2×5.0 mm PCB land pattern for the Si540. The table below lists the values for the dimensions shown in the illustration. Figure 6.2. Si540 (3.2×5 mm) PCB Land Pattern Table 6.2. PCB Land Pattern Dimensions (mm) Dimension (mm) C1 2.60 E 1.27 X1 0.80 Y1 1.70 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification. 3. This Land Pattern Design is based on the IPC-7351 guidelines. 4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm. Solder Mask Design 1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad. Stencil Design 1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. The stencil thickness should be 0.125 mm (5 mils). 3. The ratio of stencil aperture to land pad size should be 1:1. Card Assembly 1. A No-Clean, Type-3 solder paste is recommended. 2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components. silabs.com | Building a more connected world. Rev. 1.0 | 13 Si540 Data Sheet Top Marking 7. Top Marking The figure below illustrates the mark specification for the Si540. The table below lists the line information. Figure 7.1. Mark Specification Table 7.1. Si540 Top Mark Description Line Position Description 1 1–8 "Si540", xxx = Ordering Option 1, Option 2, Option 3 (e.g. Si540AAA) 2 1–7 Frequency Code (e.g. 100M000 or 6-digit custom code as described in the Ordering Guide) 3 Trace Code Position 1 Pin 1 orientation mark (dot) Position 2 Product Revision (B) Position 3–5 Tiny Trace Code (3 alphanumeric characters per assembly release instructions) Position 6–7 Year (last two digits of the year), to be assigned by assembly site (ex: 2017 = 17) Position 8–9 Calendar Work Week number (1–53), to be assigned by assembly site silabs.com | Building a more connected world. Rev. 1.0 | 14 Si540 Data Sheet Revision History 8. Revision History Revision 1.0 July 2018 • Added 20 ppm total stability option. Revision 0.75 March, 2018 • Added 25 ppm total stability option. Revision 0.71 December 11, 2017 • Added 5x7 package and land pattern. Revision 0.7 June 27, 2017 • Initial release. silabs.com | Building a more connected world. Rev. 1.0 | 15 ClockBuilder Pro One-click access to Timing tools, documentation, software, source code libraries & more. Available for Windows and iOS (CBGo only). www.silabs.com/CBPro Timing Portfolio www.silabs.com/timing SW/HW www.silabs.com/CBPro Quality www.silabs.com/quality Support and Community community.silabs.com Disclaimer Silicon Labs intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. 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