Si 5 15
VO L TAG E - C ONTR OLLED C RYSTAL O S C I L L A T O R (VCXO)
100 k H Z T O 250 MH Z
Features
Supports any frequency from
100 kHz to 250 MHz
Low-jitter operation
Short lead times: 6 digit resolution
Figure 2. Part Number Convention
Example ordering part number: 515BBB212M500BAGR.
The series prefix, 515, indicates the device is a single frequency VCXO.
The 1st option code B specifies the output format is LVDS and powered from a 3.3 V supply. The stability and APR
code B indicates a temperature stability of ±20 ppm with a tuning slope of ±120 ppm/V. The 3rd option code B
specifies the OE pin is active low.
The frequency code is 212M500. Per this convention, and as indicated by the part number lookup utility at
www.silabs.com/VCXOpartnumber, the output frequency is 212.5 MHz. The package code B refers to the
3.2 x 5 mm footprint with six pins. The last A refers to the product revision, G indicates the temperature range (–40
to +85 °C), and R specifies the device ships in tape and reel format.
Note: CMOS and Dual CMOS maximum frequency is 212.5 MHz.
14
Rev. 1.2
Si515
5. Package Outline Diagram: 5 x 7 mm, 6-pin
Figure 3 illustrates the package details for the Si515. Table 14 lists the values for the dimensions shown in the
illustration.
Figure 3. Si515 Outline Diagram
Table 14. Package Diagram Dimensions (mm)
Dimension
Min
Nom
Max
A
1.50
1.65
1.80
b
1.30
1.40
1.50
c
0.50
0.60
0.70
D
D1
5.00 BSC.
4.30
4.40
e
2.54 BSC.
E
7.00 BSC.
4.50
E1
6.10
6.20
6.30
H
0.55
0.65
0.75
L
1.17
1.27
1.37
L1
0.05
0.10
0.15
p
1.80
—
2.60
R
0.7 REF.
aaa
0.15
bbb
0.15
ccc
0.10
ddd
0.10
eee
0.05
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
Rev. 1.2
15
Si5 15
6. PCB Land Pattern: 5 x 7 mm, 6-pin
Figure 4 illustrates the 5 x 7 mm PCB land pattern for the Si515. Table 15 lists the values for the dimensions shown
in the illustration.
Figure 4. Si515 PCB Land Pattern
Table 15. PCB Land Pattern Dimensions (mm)
Dimension
(mm)
C1
4.20
E
5.08
X1
1.55
Y1
1.95
Notes:
General
1.
2.
3.
4.
All dimensions shown are in millimeters (mm) unless otherwise noted.
Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
This Land Pattern Design is based on the IPC-7351 guidelines.
All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition
(LMC) is calculated based on a Fabrication Allowance of 0.05 mm.
Solder Mask Design
5. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder
mask and the metal pad is to be 60 µm minimum, all the way around the pad.
Stencil Design
6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used
to assure good solder paste release.
7. The stencil thickness should be 0.125 mm (5 mils).
8. The ratio of stencil aperture to land pad size should be 1:1.
Card Assembly
9. A No-Clean, Type-3 solder paste is recommended.
10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for
Small Body Components.
16
Rev. 1.2
Si515
7. Package Outline Diagram: 3.2 x 5.0 mm, 6-pin
Figure 5 illustrates the package details for the 3.2 x 5 mm Si515. Table 16 lists the values for the dimensions
shown in the illustration.
Figure 5. Si515 Outline Diagram
Table 16. Package Diagram Dimensions (mm)
Dimension
A
b
c
D
D1
e
E
E1
H
L
L1
p
R
aaa
bbb
ccc
ddd
eee
Min
1.06
0.54
0.35
2.55
4.35
0.45
0.80
0.05
1.17
Nom
1.17
0.64
0.45
3.20 BSC
2.60
1.27 BSC
5.00 BSC
4.40
0.55
0.90
0.10
1.27
0.32 REF
0.15
0.15
0.10
0.10
0.05
Max
1.33
0.74
0.55
2.65
4.45
0.65
1.00
0.15
1.37
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
Rev. 1.2
17
Si5 15
8. PCB Land Pattern: 3.2 x 5.0 mm, 6-pin
Figure 6 illustrates the recommended 3.2 x 5 mm PCB land pattern for the Si515. Table 17 lists the values for the
dimensions shown in the illustration.
Figure 6. Si515 PCB Land Pattern
Table 17. PCB Land Pattern Dimensions (mm)
Dimension
(mm)
C1
2.60
E
1.27
X1
0.80
Y1
1.70
Notes:
General
1.
2.
3.
4.
All dimensions shown are in millimeters (mm) unless otherwise noted.
Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
This Land Pattern Design is based on the IPC-7351 guidelines.
All dimensions shown are at Maximum Material Condition (MMC). Least Material
Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm.
Solder Mask Design
5. All metal pads are to be non-solder mask defined (NSMD). Clearance between the
solder mask and the metal pad is to be 60 µm minimum, all the way around the pad.
Stencil Design
6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be
used to assure good solder paste release.
7. The stencil thickness should be 0.125 mm (5 mils).
8. The ratio of stencil aperture to land pad size should be 1:1.
Card Assembly
9. A No-Clean, Type-3 solder paste is recommended.
10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification
for Small Body Components.
18
Rev. 1.2
Si515
9. Package Outline Diagram: 2.5 x 3.2 mm, 6-pin
Figure 7 illustrates the package details for the 2.5 x 3.2 mm Si515. Table 18 lists the values for the dimensions
shown in the illustration.
Figure 7. Si515 Outline Diagram
Rev. 1.2
19
Si5 15
Table 18. Package Diagram Dimensions (mm)
Dimension
A
A1
A2
W
D
e
E
M
L
D1
E1
SE
aaa
bbb
ddd
Min
—
Nom
—
0.26 REF
0.7 REF
Max
1.1
0.65
0.7
0.75
0.45
3.20 BSC
1.25 BSC
2.50 BSC
0.30 BSC
0.5
2.5 BSC
1.65 BSC
0.825 BSC
0.1
0.2
0.08
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
20
Rev. 1.2
0.55
Si515
10. PCB Land Pattern: 2.5 x 3.2 mm, 6-pin
Figure 8 illustrates the 2.5 x 3.2 mm PCB land pattern for the Si515. Table 19 lists the values for the dimensions
shown in the illustration.
Figure 8. Si515 Recommended PCB Land Pattern
Table 19. PCB Land Pattern Dimensions (mm)
Dimension
C1
(mm)
1.9
E
2.50
X1
0.70
Y1
1.05
Notes:
General
3. All dimensions shown are at Maximum Material Condition (MMC). Least Material
Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm.
4. This Land Pattern Design is based on the IPC-7351 guidelines.
Solder Mask Design
5. All metal pads are to be non-solder mask defined (NSMD). Clearance between the
solder mask and the metal pad is to be 60 µm minimum, all the way around the pad.
Stencil Design
6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be
used to assure good solder paste release.
7. The stencil thickness should be 0.125 mm (5 mils).
8. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pins.
Card Assembly
9. A No-Clean, Type-3 solder paste is recommended.
10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification
for Small Body Components.
Rev. 1.2
21
Si5 15
11. Top Marking
Use the part number configuration utility located at: www.silabs.com/VCXOPartNumber to cross-reference the
mark code to a specific device configuration.
11.1. Si515 Top Marking
5 C CC CC
T TTT TT
Y Y WW
11.2. Top Marking Explanation
Mark Method:
Laser
Line 1 Marking:
5 = Si515
CCCCC = Mark Code
5CCCCC
Line 2 Marking:
TTTTTT = Assembly Manufacturing Code
TTTTTT
Line 3 Marking:
Pin 1 indicator.
Circle with 0.5 mm diameter;
left-justified
YY = Year.
WW = Work week.
Characters correspond to the year and
work week of package assembly.
YYWW
22
Rev. 1.2
Si515
REVISION HISTORY
Revision 1.2
June, 2018
Changed “Trays” to “Coil Tape” in Ordering Guide.
Revision 1.1
December, 2017
Added 2.5 x 3.2 mm package.
Revision 1.0
Updated Table 1 on page 3.
Updates
to supply current typical and maximum values for CMOS, LVDS, LVPECL and HCSL.
frequency test condition corrected to 100 MHz.
Updates to OE VIH minimum and VIL maximum values.
CMOS
Updated Table 3 on page 4.
Dual
CMOS nominal frequency maximum added.
time maximum values updated.
Enable time parameter added.
Disable
Updated Table 4 on page 5.
CMOS
output rise / fall time typical and maximum values updated.
output rise / fall time maximum value updated.
LVPECL output swing maximum value updated.
LVDS output common mode typical and maximum values updated.
HCSL output swing maximum value updated.
Duty cycle minimum and maximum values tightened to 48/52%.
LVPECL/HCSL
Updated Table 5 on page 6.
Phase
jitter test condition, typical and maximum value updated.
noise typical values updated.
Additive RMS jitter due to external power supply noise typical values updated.
Phase
Added Tables 6, 7, 8 for LVDS, HCSL, CMOS and Dual CMOS operations.
Added note to Figure 2 clarifying CMOS and Dual CMOS maximum frequency.
Updated Figure 5 outline diagram to correct pinout.
Updated “11. Top Marking” section and moved to page 22.
Rev. 1.2
23
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