Ultra Series™ Crystal Oscillator
Si540 Data Sheet
Ultra Low Jitter Any-Frequency XO (125 fs), 0.2 to 1500 MHz
KEY FEATURES
The Si540 Ultra Series™ oscillator utilizes Skyworks Solutions’ advanced 4th
generation DSPLL® technology to provide an ultra-low jitter, low phase noise
clock at any output frequency. The device is factory-programmed to any frequency
from 0.2 to 1500 MHz with 6 digits
Notes:
1. Contact Skyworks for non-standard configurations.
2. Total stability includes temp stability, initial accuracy, load pulling, VDD variation, and 20 year aging at 70 °C.
3. For example: 156.25 MHz = 156M250; 25 MHz = 25M0000. Create custom part numbers at https://www.skyworksinc.com/Products/Timing-Oscillators.
1.1 Technical Support
Frequently Asked Questions (FAQ)
https://www.skyworksinc.com/products/timing/ultra-series-crystal-oscillators-xo/
si540
Oscillator Phase Noise Lookup Utility
https://www.skyworksinc.com/tools/oscillator-phase-noise
Quality and Reliability
https://www.skyworksinc.com/Quality
Development Kits
https://www.skyworksinc.com/Products/Timing-Oscillators
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Si540 Data Sheet • Electrical Specifications
2. Electrical Specifications
Table 2.1. Electrical Specifications
VDD = 1.8 V, 2.5 or 3.3 V ± 5%, TA = –40 to 85 ºC
Parameter
Temperature Range
Frequency Range
Supply Voltage
Supply Current
Symbol
Rise/Fall Time
(20% to 80% VPP)
Min
Typ
Max
Unit
–40
—
85
ºC
LVPECL, LVDS, CML
0.2
—
1500
MHz
HCSL
0.2
—
400
MHz
CMOS, Dual CMOS
0.2
—
250
MHz
3.3 V
3.135
3.3
3.465
V
2.5 V
2.375
2.5
2.625
V
1.8 V
1.71
1.8
1.89
V
LVPECL (output enabled)
—
100
145
mA
LVDS/CML (output enabled)
—
75
111
mA
HCSL (output enabled)
—
80
125
mA
HCSL-Fast (output enabled)
—
88
137
mA
CMOS (output enabled)
—
74
108
mA
Dual CMOS (output enabled)
—
80
125
mA
Tristate Hi-Z (output disabled)
—
64
100
mA
Frequency stability Grade A
–20
—
20
ppm
Frequency stability Grade B
–10
—
10
ppm
Frequency stability Grade C
–7
—
7
ppm
Frequency stability Grade A
–50
—
50
ppm
Frequency stability Grade B
–25
—
25
ppm
Frequency stability Grade C
–20
—
20
ppm
LVPECL/LVDS/CML
—
—
350
ps
CMOS / Dual CMOS
(CL = 5 pF)
—
0.5
1.5
ns
HCSL, FCLK >50 MHz
—
—
550
ps
HCSL-Fast, FCLK >50 MHz
—
—
275
ps
All formats
45
—
55
%
TA
FCLK
VDD
IDD
Temperature Stability
Total Stability1
Test Condition/Comment
FSTAB
TR/TF
Duty Cycle
DC
Output Enable (OE)2
VIH
0.7 × VDD
—
—
V
VIL
—
—
0.3 × VDD
V
Powerup Time
3
TD
Output Disable Time,
FCLK >10 MHz
—
—
3
µs
TE
Output Enable Time,
FCLK >10 MHz
—
—
20
µs
tOSC
Time from 0.9 × VDD until output frequency (FCLK) within spec
—
—
10
ms
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Si540 Data Sheet • Electrical Specifications
Parameter
Symbol
Test Condition/Comment
Min
Typ
Max
Unit
VRAMP
Fastest VDD ramp rate allowed on
startup
—
—
100
V/ms
VOC
Mid-level
VDD – 1.42
—
VDD – 1.25
V
VO
Swing (diff)
1.1
—
1.9
VPP
VOC
Mid-level (2.5 V, 3.3 V VDD)
1.125
1.20
1.275
V
Mid-level (1.8 V VDD)
0.8
0.9
1.0
V
Swing (FCLK ≤ 1.4 GHz)
0.6
0.7
0.9
VPP
Swing (FCLK > 1.4 GHz)
0.5
0.7
0.9
VPP
VOH
Output voltage high
660
750
850
mV
VOL
Output voltage low
–150
0
150
mV
VC
Crossing voltage
250
350
550
mV
CML Output Option (AC-Coupled)
VO
Swing (diff)
0.6
0.8
1.0
VPP
CMOS Output Option
VOH
IOH = 8/6/4 mA for 3.3/2.5/1.8V VDD 0.85 × VDD
—
—
V
VOL
IOL = 8/6/4 mA for 3.3/2.5/1.8V VDD
—
0.15 × VDD
V
Powerup VDD Ramp Rate
LVPECL Output Option3
LVDS Output Option4
VO
HCSL Output Option5
HCSL-Fast Output Option5
—
Notes:
1. Total Stability includes temperature stability, initial accuracy, load pulling, VDD variation, and aging for 20 yrs at 70 ºC.
2. OE includes a 50 kΩ pull-up to VDD for OE active high. Includes a 50 kΩ pull-down to GND for OE active low. NC (No Connect)
pins include a 50 kΩ pull-down to GND.
3. 50 Ω to VDD – 2.0 V. Additional DC current from the output driver will flow through the 50Ω resistors, resulting in a shift in common
mode voltage. The measurements in this table have accounted for this.
4. Rterm = 100 Ω (differential).
5. 50 Ω to GND.
Table 2.2. Clock Output Phase Jitter and PSNR
VDD = 1.8 V, 2.5 or 3.3 V ± 5%, TA = –40 to 85 ºC
Parameter
Phase Jitter (RMS, 12kHz - 20MHz)1
2.5 x 3.2 mm, 3.2 x 5 mm, FCLK ≥ 100 MHz
Symbol
Test Condition/Comment
Min
Typ
Max
Unit
ϕJ
Differential Formats
—
125
200
fs
CMOS, Dual CMOS
—
200
—
fs
Differential Formats
—
150
200
fs
CMOS, Dual CMOS
—
200
—
fs
100 kHz sine wave
—
-83
—
200 kHz sine wave
—
-83
—
500 kHz sine wave
—
-82
—
1 MHz sine wave
—
-85
—
Phase Jitter (RMS, 12kHz - 20MHz)1
5 x 7 mm, FCLK ≥ 100 MHz
Spurs Induced by External Power Supply
Noise, 50 mVpp Ripple. LVDS 156.25 MHz
Output
PSNR
dBc
Note:
1. Guaranteed by characterization. Jitter inclusive of any spurs.
4
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Si540 Data Sheet • Electrical Specifications
Table 2.3. 3.2 x 5 mm Clock Output Phase Noise (Typical, 50ppm Total Stability Option)
Offset Frequency (f)
156.25 MHz LVDS
200 MHz LVDS
644.53125 MHz LVDS
100 Hz
–110
–107
–99
1 kHz
–121
–120
–109
10 kHz
–132
–130
–121
100 kHz
–139
–137
–127
1 MHz
–151
–149
–138
10 MHz
–160
–161
–155
20 MHz
–161
–162
–157
Offset Frequency (f)
156.25 MHz
LVPECL
200 MHz
LVPECL
644.53125 MHz
LVPECL
100 Hz
–113
–110
–100
1 kHz
–123
–120
–110
10 kHz
–133
–130
–119
100 kHz
–139
–137
–127
1 MHz
–151
–149
–138
10 MHz
–162
–166
–156
20 MHz
–163
–167
–157
Unit
dBc/Hz
Unit
dBc/Hz
Phase jitter measured with Agilent E5052 using a differential-to-single ended converter (balun or buffer). Measurements collected for
>700 commonly used frequencies. Phase noise plots for specific frequencies are available using our onlineOscillator Phase Noise
Lookup Tool.
Figure 2.1. Phase Jitter vs. Output Frequency
5
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Si540 Data Sheet • Electrical Specifications
Table 2.4. Environmental Compliance and Package Information
Parameter
Test Condition
Mechanical Shock
MIL-STD-883, Method 2002
Mechanical Vibration
MIL-STD-883, Method 2007
Solderability
MIL-STD-883, Method 2003
Gross and Fine Leak
MIL-STD-883, Method 1014
Resistance to Solder Heat
MIL-STD-883, Method 2036
Moisture Sensitivity Level (MSL): 3.2 x 5, 5 x 7 packages
1
Moisture Sensitivity Level (MSL): 2.5 x 3.2 package
2
Contact Pads: 3.2x5, 5x7 packages
Au/Ni (0.3 - 1.0 µm / 1.27 - 8.89 µm)
Contact Pads: 2.5x3.2 packages
Au/Pd/Ni (0.03 - 0.12 µm / 0.1 - 0.2 µm / 3.0 - 8.0 µm)
Note:
1. For additional product information not listed in the data sheet (e.g. RoHS Certifications, MDDS data, qualification data, REACH
Declarations, ECCN codes, etc.), refer to our "Corporate Request For Information" portal found here: www.skyworksinc.com/quality.
Table 2.5. Thermal Conditions
Max Junction Temperature = 125° C
Package
2.5 x 3.2 mm
6-pin DFN
3.2 × 5 mm
6-pin CLCC
5 × 7 mm
6-pin CLCC
Parameter
Symbol
Test Condition
Value
Unit
Thermal Resistance Junction to Ambient
ΘJA
Still Air, 85 °C
80
ºC/W
Thermal Parameter Junction to Board
ΨJB
Still Air, 85 °C
39
ºC/W
Thermal Parameter Junction to Top Center
ΨJT
Still Air, 85 °C
17
ºC/W
Thermal Resistance Junction to Ambient
ΘJA
Still Air, 85 °C
55
ºC/W
Thermal Parameter Junction to Board
ΨJB
Still Air, 85 °C
20
ºC/W
Thermal Parameter Junction to Top Center
ΨJT
Still Air, 85 °C
20
ºC/W
Thermal Resistance Junction to Ambient
ΘJA
Still Air, 85 °C
53
ºC/W
Thermal Parameter Junction to Board
ΨJB
Still Air, 85 °C
26
ºC/W
Thermal Parameter Junction to Top Center
ΨJT
Still Air, 85 °C
26
ºC/W
Note:
1. Based on PCB Dimensions: 4.5" x 7", PCB Thickness: 1.6 mm, Number of Cu Layers: 4.
6
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Si540 Data Sheet • Electrical Specifications
Table 2.6. Absolute Maximum Ratings1
Parameter
Symbol
Rating
Unit
TAMAX
95
ºC
TS
–55 to 125
ºC
Supply Voltage
VDD
–0.5 to 3.8
ºC
Input Voltage
VIN
–0.5 to VDD + 0.3
V
ESD HBM (JESD22-A114)
HBM
2.0
kV
Solder Temperature2
TPEAK
260
ºC
TP
20–40
sec
Maximum Operating Temp.
Storage Temperature
Solder Time at TPEAK2
Notes:
1. Stresses beyond those listed in this table may cause permanent damage to the device. Functional operation specification
compliance is not implied at these conditions. Exposure to maximum rating conditions for extended periods may affect device
reliability.
2. The device is compliant with JEDEC J-STD-020.
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Si540 Data Sheet • Dual CMOS Buffer
3. Dual CMOS Buffer
Dual CMOS output format ordering options support either complementary or in-phase signals for two identical frequency outputs. This
feature enables replacement of multiple XOs with a single Si540 device.
~
~
Complementary
Outputs
In-Phase
Outputs
Figure 3.1. Integrated 1:2 CMOS Buffer Supports Complementary or In-Phase Outputs
8
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Si540 Data Sheet • Recommended Output Terminations
4. Recommended Output Terminations
The output drivers support both AC-coupled and DC-coupled terminations as shown in figures below.
VDD
VDD (3.3V, 2.5V)
CLK+
Rp
R1
R1
CLK+
50 Ω
CLK-
Si54x
VDD
VDD (3.3V, 2.5V)
Rp
R2
R2
LVPECL
Receiver
VDD (3.3V, 2.5V)
CLK+
VDD
Si54x
Rp
Rp
50 Ω
R2
VDD (3.3V, 2.5V)
R1
VTT
CLK+
50 Ω
LVPECL
Receiver
LVPECL
Receiver
AC-Coupled LVPECL - 50 Ω w/VTT Bias
50 Ω
VDD – 2.0V
CLK-
50 Ω
R2
R2
DC-Coupled LVPECL – Thevenin Termination
50 Ω
CLK-
50 Ω
Si54x
AC-Coupled LVPECL – Thevenin Termination
R1
50 Ω
CLK-
50 Ω
R1
50 Ω
50 Ω
50 Ω
Si54x
LVPECL
Receiver
DC-Coupled LVPECL - 50 Ω w/VTT Bias
Figure 4.1. LVPECL Output Terminations
AC Coupled LVPECL
Termination Resistor Values
9
DC Coupled LVPECL
Termination Resistor Values
VDD
R1
R2
Rp
VDD
R1
R2
3.3 V
82.5 Ω
127 Ω
130 Ω
3.3 V
127 Ω
82.5 Ω
2.5 V
62.5 Ω
250 Ω
90 Ω
2.5 V
250 Ω
62.5 Ω
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Si540 Data Sheet • Recommended Output Terminations
(3.3V, 2.5V, 1.8V)
VDD
CLK+
(3.3V, 2.5V, 1.8V)
VDD
50 Ω
CLK+ 33 Ω
100 Ω
CLK50 Ω
Si54x
LVDS
Receiver
CLK+
50 Ω
HCSL
Receiver
Source Terminated HCSL
(3.3V, 2.5V, 1.8V)
VDD
50 Ω
CLK+
100 Ω
CLK50 Ω
Si54x
50 Ω
50 Ω
Si54x
DC-Coupled LVDS
(3.3V, 2.5V, 1.8V)
VDD
50 Ω
CLK- 33 Ω
50 Ω
CLK-
LVDS
Receiver
50 Ω
50 Ω
Si54x
AC-Coupled LVDS
50 Ω
HCSL
Receiver
Destination Terminated HCSL
Figure 4.2. LVDS and HCSL Output Terminations
(3.3V, 2.5V, 1.8V)
VDD
CLK+
VDD (3.3V, 2.5V, 1.8V)
50 Ω
CLK
10 Ω
100 Ω
CLK-
NC
50 Ω
Si54x
CML
Receiver
CLK+
Si54x
Single CMOS Termination
VDD (3.3V, 2.5V, 1.8V)
50 Ω
50 Ω
CLK+
50 Ω
CLK-
VCM
CLK-
CMOS
Receiver
Si54x
CML Termination without VCM
(3.3V, 2.5V, 1.8V)
VDD
50 Ω
50 Ω
CML
Receiver
CML Termination with VCM
10 Ω
10 Ω
Si54x
50 Ω
50 Ω
CMOS
Receivers
Dual CMOS Termination
Figure 4.3. CML and CMOS Output Terminations
10
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Si540 Data Sheet • Package Outline
5. Package Outline
5.1 Package Outline (5×7 mm)
The figure below illustrates the package details for the 5×7 mm Si540. The table below lists the values for the dimensions shown in the
illustration.
Figure 5.1. Si540 (5×7 mm) Outline Diagram
Table 5.1. Package Diagram Dimensions (mm)
Dimension
Min
Nom
Max
Dimension
Min
Nom
Max
A
1.13
1.28
1.43
L
1.17
1.27
1.37
A2
0.50
0.55
0.60
L1
0.05
0.10
0.15
A3
0.50
0.55
0.60
p
1.70
—
1.90
b
1.30
1.40
1.50
R
0.70 REF
c
0.50
0.60
0.70
aaa
0.15
bbb
0.15
ccc
0.08
D
D1
5.00 BSC
4.30
4.40
4.50
e
2.54 BSC
ddd
0.10
E
7.00 BSC
eee
0.05
E1
6.10
6.20
6.30
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
11
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Si540 Data Sheet • Package Outline
5.2 Package Outline (3.2×5 mm)
The figure below illustrates the package details for the 3.2×5 mm Si540. The table below lists the values for the dimensions shown in
the illustration.
Figure 5.2. Si540 (3.2×5 mm) Outline Diagram
Table 5.2. Package Diagram Dimensions (mm)
Dimension
Min
Nom
Max
A
1.06
1.17
1.33
b
0.54
0.64
0.74
c
0.35
0.45
0.55
D
D1
3.20 BSC
2.55
2.60
e
1.27 BSC
E
5.00 BSC
2.65
E1
4.35
4.40
4.45
H
0.45
0.55
0.65
L
0.80
0.90
1.00
L1
0.05
0.10
0.15
p
1.36
1.46
1.56
R
0.32 REF
aaa
0.15
bbb
0.15
ccc
0.08
ddd
0.10
eee
0.05
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
12
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Si540 Data Sheet • Package Outline
5.3 Package Outline (2.5x3.2 mm)
The figure below illustrates the package details for the 2.5x3.2 mm Si540. The table below lists the values for the dimensions shown in
the illustration.
Figure 5.3. Si540 (2.5×3.2 mm) Outline Diagram
Table 5.3. Package Diagram Dimensions (mm)
Dimension
Min
Nom
Max
A
0.85
0.90
1.00
A1
0.36 REF
A2
0.53 REF
W
0.55
0.60
D
3.2 BSC
E
2.5 BSC
e
1.10 BSC
L
0.65
0.70
n
5
D1
2.2 BSC
E1
1.589 BSC
aaa
0.10
bbb
0.10
ddd
0.08
0.65
0.75
Notes:
1. The dimensions in parentheses are reference.
2. All dimensions in millimeters (mm).
3. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
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Si540 Data Sheet • PCB Land Pattern
6. PCB Land Pattern
6.1 PCB Land Pattern (5×7 mm)
The figure below illustrates the 5×7 mm PCB land pattern for the Si540. The table below lists the values for the dimensions shown in
the illustration.
Figure 6.1. Si540 (5×7 mm) PCB Land Pattern
Table 6.1. PCB Land Pattern Dimensions (mm)
Dimension
(mm)
C1
4.20
E
2.54
X1
1.55
Y1
1.95
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on the IPC-7351 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a
Fabrication Allowance of 0.05 mm.
Solder Mask Design
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm
minimum, all the way around the pad.
Stencil Design
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1.
Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
14
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Si540 Data Sheet • PCB Land Pattern
6.2 PCB Land Pattern (3.2×5 mm)
The figure below illustrates the 3.2×5.0 mm PCB land pattern for the Si540. The table below lists the values for the dimensions shown
in the illustration.
Figure 6.2. Si540 (3.2×5 mm) PCB Land Pattern
Table 6.2. PCB Land Pattern Dimensions (mm)
Dimension
(mm)
C1
2.60
E
1.27
X1
0.80
Y1
1.70
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on the IPC-7351 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a
Fabrication Allowance of 0.05 mm.
Solder Mask Design
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm
minimum, all the way around the pad.
Stencil Design
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1.
Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
15
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Si540 Data Sheet • PCB Land Pattern
6.3 PCB Land Pattern (2.5×3.2 mm)
The figure below illustrates the 2.5×3.2 mm PCB land pattern for the Si540. The table below lists the values for the dimensions shown
in the illustration.
Figure 6.3. Si540 (2.5×3.2 mm) PCB Land Pattern
Table 6.3. PCB Land Pattern Dimensions (mm)
Dimension
Description
Value (mm)
X1
Width - leads on long sides
0.85
Y1
Height - leads on long sides
0.7
D1
Pitch in X directions of XLY1 leads
1.639
E1
Lead pitch XLY1 leads
1.10
Notes: The following notes and stencil design are shared as recommendations only. A customer or user may find it necessary to use
different parameters and fine-tune their SMT process as required for their application and tooling.
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on the IPC-7351 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a
Fabrication Allowance of 0.05 mm.
Solder Mask Design
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm
minimum, all the way around the pad.
Stencil Design
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 0.8:1 for the pads.
Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
16
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Si540 Data Sheet • Top Marking (5x7 and 3.2x5 Packages)
7. Top Marking (5x7 and 3.2x5 Packages)
The figure below illustrates the mark specification for the Si540 5x7 and 3.2x5 package sizes. The table below lists the line information.
Figure 7.1. Mark Specification
Table 7.1. Si540 Top Mark Description
Line
Position
Description
1
1–8
"Si540", xxx = Ordering Option 1, Option 2, Option 3 (e.g. Si540AAA)
2
1–7
Frequency Code
(e.g. 100M000 or 6-digit custom code as described in the Ordering Guide)
3
17
Trace Code
Position 1
Pin 1 orientation mark (dot)
Position 2
Product Revision (C)
Position 3–5
Tiny Trace Code (3 alphanumeric characters per assembly release instructions)
Position 6–7
Year (last two digits of the year), to be assigned by assembly site (ex: 2017 = 17)
Position 8–9
Calendar Work Week number (1–53), to be assigned by assembly site
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17
Si540 Data Sheet • Top Marking (2.5x3.2 Package)
8. Top Marking (2.5x3.2 Package)
The figure below illustrates the mark specification for the Si540 2.5x3.2 package sizes. The table below lists the line information.
A C CC CC
T TTT TT
Y Y WW
Figure 8.1. Mark Specification
Table 8.1. Si540 Top Mark Description
Line
Position
1
1–6
2
18
A = Si540, CCCCC = Custom Mark Code
Trace Code
1–6
3
Description
Position 1
Six-digit trace code per assembly release instructions
Pin 1 orientation mark (dot)
Position 2–3
Year (last two digits of the year), to be assigned by assembly site (exp: 2017 = 17)
Position 4–5
Calendar Work Week number (1–53), to be assigned by assembly site
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Si540 Data Sheet • Revision History
9. Revision History
Revision 206609A
May, 2023
• Updated Min and Nom package diagram dimensions specs in 5.3 Package Outline (2.5x3.2 mm).
Revision 1.3
June, 2021
• Updated Ordering Guide and Topmark for Rev. C silicon
• Added HCSL-Fast (faster tR/tF) ordering option
• Updated Table 2.1, Powerup VDD Ramp Rate
Revision 1.2
September, 2020
• Updated Table 2.1, Powerup VDD Ramp Rate and LVDS Swing
Revision 1.1
November, 2019
• Added 2.5x3.2 mm package option
Revision 1.0
July, 2018
• Added 20 ppm total stability option.
Revision 0.75
March, 2018
• Added 25 ppm total stability option.
Revision 0.71
December, 2017
• Added 5x7 package and land pattern.
Revision 0.7
June, 2017
• Initial release.
19
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