569ABCA002177ABG

Ultra Series™ Crystal Oscillator (VCXO) Si569 Data Sheet Ultra Low Jitter I2C Programmable VCXO (100 fs), 0.2 to 3000 MHz KEY FEATURES • I2C programmable to any frequency from 0.2 to 3000 MHz with < 1 ppb resolution The Si569 Ultra Series™ voltage-controlled crystal oscillator utilizes Skyworks Solutions’ advanced 4th generation DSPLL® technology to provide an ultra-low jitter, low phase noise clock at any output frequency. The device is user-programmed via simple I2C commands to provide any frequency from 0.2 to 3000 MHz with 50 MHz — — 450 ps HCSL-Fast, FCLK >50 MHz — — 275 ps All formats 45 — 55 % TA FCLK VDD IDD Temperature Stability1 Rise/Fall Time (20% to 80% VPP) Test Condition/Comment TR/TF Duty Cycle DC Output Enable (OE) Frequency Select (FS)2 VIH 0.7 × VDD — — V VIL — — 0.3 × VDD V Powerup Time Powerup VDD Ramp Rate LVPECL Output Option3 3 TD Output Disable Time, FCLK >10 MHz — — 3 µs TE Output Enable Time, FCLK >10 MHz — — 20 µs TFS Settling Time after FS Change — — 10 ms tOSC Time from 0.9 × VDD until output frequency (FCLK) within spec — — 10 ms VRAMP Fastest VDD ramp rate allowed on startup — — 100 V/ms VOC Mid-level VDD – 1.42 — VDD – 1.25 V VO Swing (diff, FCLK < 1.5 GHz) 1.1 — 1.9 VPP Swing (diff, FCLK > 1.5 GHz)6 0.55 — 1.7 VPP Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com 206626A • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • May 30, 2023 3 Si569 Data Sheet • Electrical Specifications Parameter LVDS Output Option4 Symbol Test Condition/Comment Min Typ Max Unit VOC Mid-level (2.5 V, 3.3 V VDD) 1.125 1.20 1.275 V Mid-level (1.8 V VDD) 0.8 0.9 1.0 V Swing (diff, FCLK < 1.4 GHz) 0.6 0.7 0.9 VPP Swing (diff, FCLK > 1.4 GHz) 6 0.25 0.5 0.8 VPP Swing (diff, FCLK < 1.6 GHz) 7 0.6 0.8 1.0 VPP VOH Output voltage high 660 800 850 mV VOL Output voltage low –150 0 150 mV VC Crossing voltage 250 410 550 mV VO Swing (diff, FCLK < 1.5 GHz) 0.6 0.8 1.0 VPP Swing (diff, FCLK > 1.5 GHz)6 0.3 0.55 0.9 VPP VOH IOH = 8/6/4 mA for 3.3/2.5/1.8V VDD 0.85 × VDD — — V VOL IOL = 8/6/4 mA for 3.3/2.5/1.8V VDD — — 0.15 × VDD V VO HCSL Output Option5 HCSL-Fast Output Option5 CML Output Option (AC-Coupled) CMOS Output Option Notes: 1. Min APR includes ±20 ppm temperature stability, initial accuracy, load pulling, VDD variation, and aging for 20 yrs at 70 ºC. 2. OE includes a 50 kΩ pull-up to VDD for OE active high, or includes a 50 kΩ pull-down to GND for OE active low. FS pin includes a 50 kΩ pull-up to VDD. 3. Rterm = 50 Ω to VDD – 2.0 V (see Figure 4.1). Additional DC current from the output driver will flow through the 50 Ω resistors, resulting in a shift in common mode voltage. The measurements in this table have accounted for this. 4. Rterm = 100 Ω (differential) (see Figure 4.2). 5. Rterm = 50 Ω to GND (see Figure 4.2). 6. Refer to the figure below for Typical Clock Output Swing Amplitudes vs Frequency. 7. High drive LVDS swing is supported when following the method shown in section 5.8 Configuring High Drive LVDS Swing. Figure 2.1. Typical Clock Output Swing Amplitudes vs. Frequency 4 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com 206626A • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • May 30, 2023 4 Si569 Data Sheet • Electrical Specifications Table 2.2. I2C Characteristics VDD = 1.8, 2.5, or 3.3 V ± 5%, TA = –40 to 85 ºC Parameter Symbol Test Condition/Comment Min Typ Max Unit SDA, SCL Input Voltage High VIH 0.70 x VDD — — V SDA, SCL Input Voltage Low VIL — — 0.30 x VDD V MRES — 0.026 — ppb From center frequency -950 — +950 ppm Settling Time for Small Frequency Change < ±950 ppm from center frequency — — 100 μs Settling Time for Large Frequency Change (Output Squelched during Frequency Transition). Includes 30 ms for internal VCO calibration to new frequency (FCAL). See Table 5.7. > ±950 ppm from center frequency — — 40 ms Frequency Reprogramming Resolution Frequency Range for Small Frequency Change (Continuous Glitchless Output) Note: For best performance, place the Si569 on a dedicated I2C bus, or isolate it via an I2C bus multiplexer to minimize noise. Table 2.3. VC Control Voltage Input VDD = 1.8, 2.5 or 3.3 V ± 5%, TA = –40 to 85 ºC Parameter Symbol Control Voltage Range VC Control Voltage Tuning Slope (Vc = 10% VDD to 90% VDD) Kv Kv Variation Test Condition Positive slope, ordering option Kv_var Typ Max Unit 0.1 x VDD VDD/2 0.9 x VDD V 60, 75, 105, 150, 180, 225 ppm/V — — ±10 % –1.5 ±0.5 +1.5 % Control Voltage Linearity LVC Modulation Bandwidth BW — 10 — kHz Vc Input Impedance ZVC 500 — — kΩ 5 Best Straight Line fit Min Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com 206626A • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • May 30, 2023 5 Si569 Data Sheet • Electrical Specifications Table 2.4. Clock Output Phase Jitter and PSNR VDD = 1.8 V, 2.5 or 3.3 V ± 5%, TA = –40 to 85 ºC Parameter Phase Jitter (RMS, 12 kHz - 20 MHz)1 All Differential Formats, FCLK ≥ 200 MHz Phase Jitter (RMS, 12 kHz - 20 MHz) 1 All Diff Formats, 100 MHz ≤ FCLK < 200 MHz Phase Jitter (RMS, 12 kHz - 20 MHz)1 LVDS, FCLK = 156.25 MHz Phase Jitter (RMS, 12 kHz - 20 MHz)1 CMOS / Dual CMOS Formats Spurs Induced by External Power Supply Noise, 50 mVpp Ripple. LVDS 156.25 MHz Output Symbol Test Condition/Comment Min Typ Max Unit ϕJ Kv = 60 ppm/V — 100 150 fs Kv = 75 ppm/V — 103 — fs Kv = 105 ppm/V — 110 — fs Kv = 150 ppm/V — 123 — fs Kv = 180 ppm/V — 132 — fs Kv = 225 ppm/V — 150 — fs Kv = 60 ppm/V — 115 180 fs Kv = 75 ppm/V — 118 — fs Kv = 105 ppm/V — 125 — fs Kv = 150 ppm/V — 138 — fs Kv = 180 ppm/V — 147 — fs Kv = 225 ppm/V — 165 — fs Kv = 60 ppm/V — 110 130 fs Kv = 75 ppm/V — 113 — fs Kv = 105 ppm/V — 120 — fs Kv = 150 ppm/V — 133 — fs Kv = 180 ppm/V — 142 — fs Kv = 225 ppm/V — 160 — fs 10 MHz ≤ FCLK < 250 MHz — 200 — fs ϕJ ϕJ ϕJ PSNR 100 kHz sine wave -83 200 kHz sine wave -83 500 kHz sine wave -82 1 MHz sine wave -85 dBc Note: 1. Guaranteed by characterization. Jitter inclusive of any spurs, I2C lines not active. 6 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com 206626A • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • May 30, 2023 6 Si569 Data Sheet • Electrical Specifications Table 2.5. 3.2 x 5 mm Clock Output Phase Noise (Typical) Offset Frequency (f) 156.25 MHz LVDS 200 MHz LVDS 644.53125 MHz LVDS 100 Hz –73 –71 –60 1 kHz –102 –102 –93 10 kHz –130 –128 –118 100 kHz –141 –139 –129 1 MHz –150 –148 –138 10 MHz –159 –160 –153 20 MHz –160 –162 –154 Offset Frequency (f) 156.25 MHz LVPECL 200 MHz LVPECL 644.53125 MHz LVPECL 100 Hz –72 –71 –60 1 kHz –103 –101 –92 10 kHz –130 –127 –117 100 kHz –142 –139 –129 1 MHz –150 –148 –138 10 MHz –160 –162 –154 20 MHz –161 –162 –156 Unit dBc/Hz Unit dBc/Hz Figure 2.2. Phase Jitter vs. Output Frequency Phase jitter measured with Agilent E5052 using a differential-to-single ended converter (balun or buffer). Measurements collected for >700 commonly used frequencies. Phase noise plots for specific frequencies are available using our free, online Oscillator Phase Noise Lookup Tool at https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/user-guides/ug298-si5xxuc-evb-ug.pdf. 7 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com 206626A • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • May 30, 2023 7 Si569 Data Sheet • Electrical Specifications Table 2.6. Environmental Compliance and Package Information Parameter Test Condition Mechanical Shock MIL-STD-883, Method 2002 Mechanical Vibration MIL-STD-883, Method 2007 Solderability MIL-STD-883, Method 2003 Gross and Fine Leak MIL-STD-883, Method 1014 Resistance to Solder Heat MIL-STD-883, Method 2036 Moisture Sensitivity Level (MSL): 3.2 x 5, 5 x 7 packages 1 Moisture Sensitivity Level (MSL): 2.5 x 3.2 package 2 Contact Pads: 3.2x5, 5x7 packages Au/Ni (0.3 - 1.0 µm / 1.27 - 8.89 µm) Contact Pads: 2.5x3.2 packages Au/Pd/Ni (0.03 - 0.12 µm / 0.1 - 0.2 µm / 3.0 - 8.0 µm) Note: 1. For additional product information not listed in the data sheet (e.g. RoHS Certifications, MDDS data, qualification data, REACH Declarations, ECCN codes, etc.), refer to our "Corporate Request For Information" portal found here: www.skyworksinc.com/quality. Table 2.7. Thermal Conditions1 Max Junction Temperature = 125° C Package 2.5 x 3.2 mm 8-pin DFN2 3.2 × 5 mm 8-pin CLCC 5 × 7 mm 8-pin CLCC Parameter Symbol Test Condition Value Unit Thermal Resistance Junction to Ambient ΘJA Still Air, 85 °C 72 ºC/W Thermal Parameter Junction to Board ΨJB Still Air, 85 °C 38 ºC/W Thermal Parameter Junction to Top Center ΨJT Still Air, 85 °C 15 ºC/W Thermal Resistance Junction to Ambient ΘJA Still Air, 85 °C 55 ºC/W Thermal Parameter Junction to Board ΨJB Still Air, 85 °C 20 ºC/W Thermal Parameter Junction to Top Center ΨJT Still Air, 85 °C 20 ºC/W Thermal Resistance Junction to Ambient ΘJA Still Air, 85 °C 53 ºC/W Thermal Parameter Junction to Board ΨJB Still Air, 85 °C 26 ºC/W Thermal Parameter Junction to Top Center ΨJT Still Air, 85 °C 26 ºC/W Note: 1. Based on PCB Dimensions: 4.5" x 7", PCB Thickness: 1.6 mm, Number of Cu Layers: 4. 2. For best 2.5x3.2mm thermal performance, use 2 GND vias as shown in the Si5xxUC-EVB eval board layout 8 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com 206626A • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • May 30, 2023 8 Si569 Data Sheet • Electrical Specifications Table 2.8. Absolute Maximum Ratings1 Parameter Symbol Rating Unit TAMAX 95 ºC TS –55 to 125 ºC Supply Voltage VDD –0.5 to 3.8 ºC Input Voltage VIN –0.5 to VDD + 0.3 V ESD HBM (JESD22-A114) HBM 2.0 kV Solder Temperature2 TPEAK 260 ºC TP 20–40 sec Maximum Operating Temp. Storage Temperature Solder Time at TPEAK2 Notes: 1. Stresses beyond those listed in this table may cause permanent damage to the device. Functional operation specification compliance is not implied at these conditions. Exposure to maximum rating conditions for extended periods may affect device reliability. 2. The device is compliant with JEDEC J-STD-020. 9 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com 206626A • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • May 30, 2023 9 Si569 Data Sheet • Dual CMOS Buffer 3. Dual CMOS Buffer Dual CMOS output format ordering options support either complementary or in-phase signals for two identical frequency outputs. This feature enables replacement of multiple VCXOs with a single Si569 device. ~ ~ Complementary Outputs In-Phase Outputs Figure 3.1. Integrated 1:2 CMOS Buffer Supports Complementary or In-Phase Outputs 10 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com 206626A • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • May 30, 2023 10 Si569 Data Sheet • Recommended Output Terminations 4. Recommended Output Terminations The output drivers support both AC-coupled and DC-coupled terminations as shown in figures below. VDD VDD (3.3V, 2.5V) CLK+ Rp R1 R1 CLK+ 50 Ω CLK- Si56x VDD VDD (3.3V, 2.5V) Rp R2 R2 LVPECL Receiver VDD (3.3V, 2.5V) CLK+ CLK- Si56x Rp 50 Ω Rp R2 VDD (3.3V, 2.5V) R1 CLK+ 50 Ω VTT LVPECL Receiver LVPECL Receiver AC-Coupled LVPECL - 50 Ω w/VTT Bias 50 Ω VDD – 2.0V CLK- 50 Ω R2 R2 DC-Coupled LVPECL – Thevenin Termination 50 Ω VDD 50 Ω Si56x AC-Coupled LVPECL – Thevenin Termination R1 50 Ω CLK- 50 Ω R1 50 Ω 50 Ω 50 Ω Si56x LVPECL Receiver DC-Coupled LVPECL - 50 Ω w/VTT Bias Figure 4.1. LVPECL Output Terminations AC-Coupled LVPECL Termination Resistor Values 11 DC-Coupled LVPECL Termination Resistor Values VDD R1 R2 Rp VDD R1 R2 3.3 V 82.5 Ω 127 Ω 130 Ω 3.3 V 127 Ω 82.5 Ω 2.5 V 62.5 Ω 250 Ω 90 Ω 2.5 V 250 Ω 62.5 Ω Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com 206626A • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • May 30, 2023 11 Si569 Data Sheet • Recommended Output Terminations (3.3V, 2.5V, 1.8V) VDD CLK+ (3.3V, 2.5V, 1.8V) VDD 50 Ω CLK+ 33 Ω 100 Ω CLK50 Ω Si56x LVDS Receiver CLK+ 50 Ω HCSL Receiver Source Terminated HCSL (3.3V, 2.5V, 1.8V) VDD 50 Ω CLK+ 100 Ω CLK50 Ω Si56x 50 Ω 50 Ω Si56x DC-Coupled LVDS (3.3V, 2.5V, 1.8V) VDD 50 Ω CLK- 33 Ω 50 Ω CLK- LVDS Receiver 50 Ω 50 Ω Si56x AC-Coupled LVDS 50 Ω HCSL Receiver Destination Terminated HCSL Figure 4.2. LVDS and HCSL Output Terminations (3.3V, 2.5V, 1.8V) VDD CLK+ VDD (3.3V, 2.5V, 1.8V) 50 Ω CLK 10 Ω 100 Ω CLK- NC 50 Ω Si56x CML Receiver CLK+ Si56x Single CMOS Termination VDD (3.3V, 2.5V, 1.8V) 50 Ω 50 Ω CLK+ 50 Ω CLK- VCM CLK- CMOS Receiver Si56x CML Termination without VCM (3.3V, 2.5V, 1.8V) VDD 50 Ω 50 Ω CML Receiver CML Termination with VCM 10 Ω 10 Ω 50 Ω 50 Ω Si56x CMOS Receivers Dual CMOS Termination Figure 4.3. CML and CMOS Output Terminations 12 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com 206626A • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • May 30, 2023 12 Si569 Data Sheet • Configuring Si569 via I2C 5. Configuring Si569 via I2C The Si569 VCXO device contains a fixed frequency crystal and frequency synthesis IC using Skyworks patented DSPLLTM technology, all enclosed in a standard hermetically sealed voltage controlled crystal oscillator (VCXO) package. The internal crystal provides the reference frequency used by the DSPLL frequency synthesis IC. The center output frequency of the Si569 voltage controlled oscillator is set via I2C register settings in the DSPLL frequency synthesis IC. The output frequency is then pulled higher or lower by applying a voltage above or below VDD/2 to the VC pin. The amount of output frequency change per volt is based on a programmed ppm/V (Kv) register setting. DSPLL technology provides unmatched frequency flexibility with superior output jitter/phase noise performance and part per trillion frequency accuracy. This section describes how to calculate the required Si569 register values used to set device output frequency and Kv gain, and how to load these values into the Si569 device. Fvco Fosc VC ADC OE Control Logic and NVM Digital Phase Detector Phase Error Cancellation Digital Loop Filter Digital VCO HSDIV LSDIV Driver OSC Out+ Out- Fout Δf Phase Error I2C / FS FBDIV Δf Power Supply Processing VDD GND Figure 5.1. Si569 Block Diagram The figure above is a simplified high-level block diagram of the Si569 VCXO device. The output frequency is set by a combination of three divider blocks highlighted in the above block diagram. 1. FBDIV - DSPLLTM Feedback Divider used to set Digital VCO frequency 2. HSDIV - High-Speed Output Divider 3. LSDIV - Low-Speed Output Divider The final device output frequency (Fout) is based on the digital VCO frequency (Fvco) divided by the product of the HSDIV and LSDIV divider values. The digital VCO frequency is based on the crystal reference frequency (OSC) multiplied by the feedback divider setting (FBDIV). The FBDIV value is set via I2C registers and is modulated depending on the voltage on the Vc pin. The amount of digital VCO frequency variation for a given Vc voltage in ppm/V depends on the Kv register setting. The limits of each of these internal blocks (digital VCO and dividers) determines the valid operating frequency range of the device. The FBDIV divider is a fractional fixed-point divider with a total length of 43 bits consisting of an 11-bit integer field (FBINT) and a 32 bit fractional field (FBFRAC) where total FBDIV = [FBINT].[FBFRAC] with an implied decimal point as shown. This bit format is known as an 11.32 fixed point format where the integer portion is 11 bits and fractional portion is 32 bits, for a total of 43 bits. The HSDIV divider is an integer divider, 11 bits in length, containing a binary divider value. One noteworthy feature of the HSDIV divider is a special duty cycle correction circuit that allows odd divide ratios of lower divider values (4-33 only) with 50% duty cycle output. This feature is useful when LSDIV divide ratio is set to 1. The LSDIV divider performs power-of-2 divides ranging from divide by 1 (20) to divide by 32 (25). The register controlling the LSDIV divider is 3 bits in length, holding the power-of-2 divide ratio (divider exponent). For example, if the LSDIV register = 3 the LSDIV divide ratio is 2^3 = 8. Note that LSDIV has a maximum value of 32 and therefore LSDIV register settings of 5, 6 or 7 will all result in the maximum divide-by-32 LSDIV operation. The tables below summarize the divider limits for LSDIV, HSDIV, FBDIV. These limits and restrictions must be observed when deriving divider register values as will be explained in later sections. 13 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com 206626A • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • May 30, 2023 13 Si569 Data Sheet • Configuring Si569 via I2C Table 5.1. Si569 Divider Range Limits Divider Upper Limit Lower Limit HSDIV[10:0] (unsigned) 2046 4 LSDIV[2:0]1 (unsigned) 32 (2^5) 1 (2^0) FBDIV[42:0] hex (unsigned) 7FDFFFFFFFF 03C00000000 FBDIV[42:0] int.frac (unsigned) 2045.99999999976 60.0 Note: 1. LSDIV is power of 2 divider. See LSDIV table below for actual divide ratio based on LSDIV register value. Table 5.2. Additional LSDIV and HSDIV Divider Restrictions LSDIV Divide Ratio HSDIV Value Restrictions Register Value 0 1 1 2 2 4 3 8 5-33 even or odd values 1 , 4 16 34-2046 even values only 5 32 6 32 7 32 Note: 1. HSDIV can implement low value (5-33) odd divide ratios while providing a 50% duty cycle output due to special duty cycle correction circuit. Note that all divider values (FBDIV, HSDIV, LSDIV) are unsigned and contain only positive values. The Si569 high-performance VCXO family has four different speed grade offerings, each covering a specific frequency range. The table below outlines the output frequency range coverage by each speed grade, the corresponding min and max VCO frequency for that speed grade, and the nominal crystal frequency. The information in the table below is needed when calculating divider settings for a given device, speed grade, and output frequency. Table 5.3. Si569 Speed Grades, Crystal Frequency, and VCO Range Limits 14 Device Speed Grade Xtal freq (MHz) Min Output Freq (MHz) Max Output Freq (MHz) Min Fvco (GHz) Max Fvco (GHz) Si569 A 152.6 0.2 3000 10.8 13.122222022 B 152.6 0.2 1500 10.8 12.511886114 C 152.6 0.2 800 10.8 12.206718160 D 152.6 0.2 325 10.8 12.206718160 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com 206626A • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • May 30, 2023 14 Si569 Data Sheet • Configuring Si569 via I2C 5.1 Output Frequency and Kv Gain Calibration Equations The basic equations used to derive the output frequency are given below and can be inferred from the device block diagram in Figure 5.2 Si569 Frequency Definition Block Diagram on page 15. Equation 1 is the relationship between the output frequency (Fout), and the VCO frequency (Fvco) and total output divider ratio (HSDIV * LSDIV). Equation 2 is the relationship between the VCO frequency (Fvco), the fixed crystal oscillator frequency (Fosc), and the feedback divider (FBDIV). Equation 2 also includes frequency adjustment (Δf) using the input control voltage (Vc) and the ppm/V control voltage gain (Kv). Fout = Fvco / (HSDIV x LSDIV) Equation 1 Fvco = (Fosc x FBDIV) x (1 + Δf) (offset freq in ppm) Equation 2a Fvco = (Fosc x FBDIV) x (1 + [(Vc - VDD/2) * Kv]) Equation 2b Fvco Fosc VC ADC OE Control Logic and NVM Digital Phase Detector Phase Error Cancellation Digital Loop Filter Digital VCO HSDIV Driver OSC LSDIV Out+ Out- Fout Δf Phase Error I2C / FS Power Supply Processing FBDIV Δf VDD GND Figure 5.2. Si569 Frequency Definition Block Diagram Equation 3a is a rearranged Equation 1 to solve for the total output divider (HSDIV *LSDIV) given Fout and Fvco. Equation 3b is rearranged again solving for Fvco given Fout and (HSDIV * LSDIV). (HSDIV x LSDIV) = Fvco / Fout Equation 3a Fvco = Fout x (HSDIV x LSDIV) Equation 3b Equation 4a is a rearranged Equation 2b to now solve for FBDIV given Fvco, Vc, VDD, Kv, and Fosc. Equation 4b simplifies Equation 4a to determine the FBDIV value for the center output frequency when Vc = VDD/2. FBDIV = (Fvco / Fosc) / [1 + (Vc - VDD/2) * Kv] Equation 4a FBDIV = Fvco / Fosc for Vc = VDD/2 (center frequency) Equation 4b Equations 3a, 3b, 4a, and 4b will be used in the process of deriving the required divider values to provide a desired center output frequency (Fout). The basic process is outlined in the next section. Whenever the Fvco frequency is modified from the factory default, it is necessary to re-calibrate Kv gain. This is because the Vc ADC input sampling rate is tied to Fvco and is factory calibrated to 80 MHz based on the factory Fvco setting. Whenever Fvco is modified to change the output center frequency, the Vc ADC sampling rate is also changed so the full-scale Kv gain must be re-calculated. 15 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com 206626A • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • May 30, 2023 15 Si569 Data Sheet • Configuring Si569 via I2C CADC_FSGAIN = round (128 * nominal Vc ADC sampling rate / new Vc ADC sampling rate) Equation 5a CADC_FSGAIN = round (128 * 80e6 / (Fvco / NFXDIV / 8)) Equation 5b Equations 5a and 5b are used along with the table below to re-calculate the Kv full scale gain. This process is also outlined in the next section. Table 5.4. Si569 NFXDIV Values for Different FBDIV Integer Values FBDIV Min FBDIV Max NFXDIV Value — 71.999999… 16 72.000000… 78.999999… 18 79.000000… 85.999999… 20 86.000000… — 22 5.2 General Process Steps for Divider Calculations and Kv Gain Calibration 1. Estimate a theoretical total output divider value (HSDIV * LSDIV) based on desired Fout while targeting the minimum valid Fvco frequency using Equation 3a and Table 5.3 Si569 Speed Grades, Crystal Frequency, and VCO Range Limits on page 14. Use floating point calculations for this step. • Result: Floating point value of total output divider (HSDIV * LSDIV) for Fvco minimum. 2. Derive a valid LSDIV divider value based on LSDIV and HSDIV divider limitations. Use the lowest possible integer value for LSDIV. For example, if the floating point output divider (HSDIV * LSDIV) for Fvco minimum = 8.22, use LSDIV = 1 and HSDIV = 8.22 versus LSDIV = 2 and HSDIV = 4.11. • Result: Valid integer LSDIV value. 3. Using the LSDIV value from #2 above, find the nearest valid integer HSDIV divider value resulting in Fvco being equal to or greater than Fvco min, observing all HSDIV limitations. Use Equations 3a/3b as necessary. • Result: Valid integer HSDIV value. 4. With valid integer HSDIV and LSDIV values, calculate the target Fvco center frequency with Equation. 3b. (Fvco must remain in the valid range per Table 5.3 Si569 Speed Grades, Crystal Frequency, and VCO Range Limits on page 14.) • Result: Valid Fvco frequency. 5. With the derived valid Fvco frequency, use Equation 4b to calculate the required FBDIV based on the device specific Fosc frequency from Table 5.3 Si569 Speed Grades, Crystal Frequency, and VCO Range Limits on page 14. Assume Vc = VDD/2 to calculate an FBDIV value for the center Fout frequency. • Result: Valid fractional FBDIV value 6. At this point all FBDIV, HSDIV and LSDIV values required to generate the desired center output frequency have been calculated. These three divider values must be now be appropriately formatted to fit the register format expected by the device. This is described in a later section. • Result: Valid register values for FBDIV, HSDIV, LSDIV 7. To re-calibrate Kv gain, first determine the integer portion of the new FBDIV value in step #5 above using truncation (not rounding) and then use that value to select the correct NFXDIV value using Table 5.4 Si569 NFXDIV Values for Different FBDIV Integer Values on page 16. • Result: Valid NFXDIV value 8. To complete Kv gain calibration, calculate the new Kv gain calibration value (CADC_FSGAIN) using Equation 5b. This Kv gain calibration value must be appropriately formatted to fit the register format expected by the device. This is described in a later section. • Result: Valid CADC_FSGAIN value 16 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com 206626A • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • May 30, 2023 16 Si569 Data Sheet • Configuring Si569 via I2C 5.3 Example: Deriving Si569 Divider Settings for 156.75 MHz Output The general process of deriving divider values for a specific output frequency is outlined in the previous section and now will be used in this example. To reiterate, all calculations must be done while observing divider limits and valid VCO frequency range limits for your device. In this example, the device is Si569 and with a desired output frequency of 156.75 MHz, the speed grade required will be “D” or better. (One important note: All divider and register settings derived for any speed grade will work without modification for all faster speed grades on the same base part number device.) Example VB code that implements the following divider calculation process is given in 5.10 Si569 Frequency Planner VB Code and can be used for implementing any supported output frequency. Step 1: Find the valid theoretical lower limit of the total output divider (HSDIV*LSDIV) based on the desired output frequency and lowest valid VCO frequency. This will bias the divider solution to the lowest possible VCO frequency since this will provide the best performance solution. Given the valid Si569 VCO range is 10.8000 GHz to 13.1222 GHz, the minimum theoretical values for (HSDIV * LSDIV) for the example 156.75 MHz output frequency are given in Equation 3: Minimum (HSDIV*LSDIV) = (10.8000 GHz / 156.75 MHz) = 68.89952… Step 2: Find valid LSDIV divisor value given minimum (HSDIV*LSDIV) from step 1. For best performance, preference should be given to implementation of the total output divider (HSDIV*LSDIV) using HSDIV with LSDIV divide ratio = 1, if possible. Use LSDIV divide ratios > 1 only if HSDIV alone cannot implement the required output divider. Since the total (HSDIV*LSDIV) value of 68.8995… is less than the HSDIV maximum divider value of 2046, the LSDIV divide ratio value will be 1, which corresponds to a LSDIV register setting of 0, since the LSDIV divider can only be a power of 2 value (see Table 5.2 Additional LSDIV and HSDIV Divider Restrictions on page 14 for valid LSDIV settings). LSDIV divide ratio = 1, therefore LSDIV register value = 0 Step 3: Find HSDIV divisor value. Given LSDIV = 1, HSDIV must implement 68.8995… or greater. Since HSDIV is an integer divider, the next greatest integer is 69. But, checking valid HSDIV values when LSDIV divide ratio = 1, we see 69 is NOT valid since it is greater than 33 and an odd value. This means the next greater integer value must be used, which is 70 (now even value). Note that 68 would not be valid since 68 is less than 68.8995… and would result in a VCO frequency below the lower VCO frequency limit. HSDIV divide ratio = 70, which gives HSDIV register value = 70 decimal (or hex value = 0x46) Step 4: Calculate a valid VCO frequency and corresponding floating point FBDIV value. Given the calculated output divider value (HSDIV*LSDIV) = 70, the VCO frequency must be set to (156.75 MHz * 70) = 10.9725 GHz. Note that 10.9725 GHz is indeed within the valid VCO frequency range per Table 5.3 Si569 Speed Grades, Crystal Frequency, and VCO Range Limits on page 14. Fvco = 10.9725 GHz Step 5: Calculate the FBDIV value necessary to provide a 10.9725 GHz Fvco using a 152.6 MHz crystal as reference (Si569 device). The floating point FBDIV value required to attain 10.9725 GHz with a 152.6 MHz crystal reference can be calculated as follows: FBDIV (float) = 10.9725 GHz / 152.6 MHz = 71.9036697247707 Step 6: Format each divider value into the required register format. LSDIV and HSDIV are simply binary values and can be directly used. FBDIV must first be put into 11.32 fixed point format. Converting the floating point FBDIV value into the 11.32 fixed point hex value required by the Si569 is done as follows: Integer value = 71 decimal. Convert 71 to 11 bit hex = 0x047. This is FBINT. Fractional value = 0.9036697247707. Multiply fractional value by 2^32 = 3881231914.2752. Now extract only the integer part of the result which is 3881231914. Convert 3881231914 to 32 bit hex = 0xE756E62A. This is FBFRAC. The resulting 11.32 fixed point hex number is therefore: FBDIV = FBINT.FBFRAC = 0x047E756E62A 17 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com 206626A • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • May 30, 2023 17 Si569 Data Sheet • Configuring Si569 via I2C At this point we have calculated all the required divider values. The table below summarizes the resulting divider values for implementing a 156.75 MHz output clock on the Si569. Table 5.5. Divider Register Values for Si569 Configured for 156.75 MHz Output Clock Divider Register Decimal Value Hex Value Reg Length (bits) LSDIV 0 0x0 3 HSDIV 70 0x046 11 FBDIV 71.9036697247707 0x047E756E62A 43 (11+32) 5.4 Example: Deriving Si569 Kv Gain Settings for 156.75 MHz Output Whenever the Fvco frequency is modified from the factory default it is necessary to re-calibrate Kv gain. Step 1: Find the Fvco and FBDIV values from the new configuration to be used for Equation 5b. Fvco = 10.9725 GHz FBDIV (float) = 10.9725 GHz / 152.6 MHz = 71.9036697247707 Step 2: Use the integer portion of FBDIV to find the correct value for NFXDIV using Table 5.4 Si569 NFXDIV Values for Different FBDIV Integer Values on page 16. Do not round up the integer portion of FBDIV, instead truncate FBDIV down via the floor function. FBDIV (int) = floor (10.9725 GHz / 152.6 MHz) = floor (71.9036697247707) = 71 Excerpt from Table 5.4 Si569 NFXDIV Values for Different FBDIV Integer Values on page 16: FBDIV Min FBDIV Max NFXDIV Value — 71.999999… 16 72.000000… 78.999999… 18 Step 3: Calculate the new CADC_FSGAIN calibration value using Fvco, FBDIV (int) and NFXDIV. CADC_FSGAIN = round (128 * 80e6 / (Fvco / NFXDIV / 8)) CADC_FSGAIN = round (128 * 80e6 / (10.9725e9 / 16 / 8)) CADC_FSGAIN = round (119.455) = 119 = 0x77 18 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com 206626A • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • May 30, 2023 18 Si569 Data Sheet • Configuring Si569 via I2C 5.5 Mapping Divider Settings into Register Values For the previous 156.75 MHz example, the divider value to register mapping is shown in the table below. Note that Register 24 is a packed register and contains bits from both LSDIV and HSDIV registers as follows: LSDIV[2:0] maps into Reg24[6:4] and HSDIV[10:8] maps into Reg24[2:0]. Note that bits Reg24[7] and Reg24[3] are not used and indicated with ‘x’ in the RegName field below. See also the Register Map Reference section for specific bit positioning within registers. Table 5.6. Si569 Divider Register Values for 156.75 MHz Output Clock Configuration 19 Register (Decimal) Hex Value Reg Name 23 46 HSDIV[7:0] 24 00 x:LSDIV[2:0]:x:HSDIV[10:8] 26 2A FBDIV[7:0] 27 E6 FBDIV[15:8] 28 56 FBDIV[23:16] 29 E7 FBDIV[31:24] 30 47 FBDIV[39:32] 31 00 FBDIV[42:40] 35 77 CADC_FSGAIN[7:0] Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com 206626A • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • May 30, 2023 19 Si569 Data Sheet • Configuring Si569 via I2C 5.6 I2C Register Write Procedure to Set Output Frequency After the frequency setting registers (Reg 23-Reg31) are calculated, there is a procedure that must be followed involving other specific control registers for the device to properly use the new frequency setting registers. Simply writing Reg23-Reg31 is not enough. The following procedure must be performed as shown to properly configure the Si569 for the desired output frequency. In other words, all the following register writes must be done, and in the exact sequence shown. This programming sequence consists of three distinct phases. 1. Writing to specific registers to get the device ready to be updated. 2. Writing the calculated frequency (divider) settings for the desired output frequency. 3. Writing to specific registers necessary to start-up the device after divider registers have been updated. The new output frequency will appear on output. The divider values shown in the table below are for the previously described Si569 example for an output frequency of 156.75 MHz (for other frequencies, replace the divider values in registers 23-31 with values specific to your frequency requirements). Table 5.7. Si569 Register Write Sequence to Set Output Frequency 20 Register (decimal) Write Data (hex) Description Purpose 255 0x00 Set page register to point to page 0 Get Device Ready for Update 69 0x00 Disable FCAL override (to allow FCAL for this Freq Update) 17 0x00 Synchronously disable output 23 0x46 HSDIV[7:0] 24 0x00 LSDIV[2:0]:HSDIV[10:8] 26 0x2A FBDIV[7:0] 27 0xE6 FBDIV[15:8] 28 0x56 FBDIV[23:16] 29 0xE7 FBDIV[31:24] 30 0x47 FBDIV[39:32] 31 0x00 FBDIV[42:40] 35 0x77 CADC_FSGAIN[7:0] Update Kv Gain 7 0x08 Start FCAL using new divider values Startup Device — — Internal FCAL VCO calibration (30 ms delay) 17 0x01 Synchronously enable output Update Dividers Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com 206626A • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • May 30, 2023 20 Si569 Data Sheet • Configuring Si569 via I2C 5.7 Digitally Controlled Oscillator – ADPLL: Small, Fast Frequency Changes The Si569 can make small, fast frequency adjustments over a range of +/- 950 ppm (parts-per-million) around the device output frequency (set as described in previous sections). This mode is typically used in applications requiring a digitally controlled oscillator (DCO) for digital PLL or other types of frequency control loops. We refer to this type of application as an all-digital PLL or ADPLL. For ADPLL applications and superior ADPLL performance, Skyworks recommends the Si548 I2C oscillator. The Si548 is a 6-pin device that features lower jitter than the Si569 while I2C lines are active, due to the different physical location of the SDA/SCL pins on the package. The ADPLL mode uses a single 24 bit register, ADPLL_DELTA_M[23:0], to add an offset to the VCO frequency to affect the small frequency change. This offset is added in a synchronous fashion to prevent frequency discontinuities and can be updated as fast as the max I2C bus speed of 1 MHz will allow. The frequency offset can be positive or negative over a range of -950 ppm to +950 ppm with 0.0001164 ppm resolution. The equation for this frequency change is simply, ADPLL_DELTA_M[23:0] = ∆ FoutPPM / 0.0001164 Where ∆ FoutPPM is the desired ppm change in output frequency, ADPLL_DELTA_M[23:0] is a two’s complement 24 bit value, and 0.0001164 is a constant per-bit ppm value. The 24 bit ADPLL_DELTA_M[23:0] value is written into three sequential 8 bit registers in LSByte to MSByte order via I2C. Upon writing the MSByte, the frequency change takes effect. Below is an example VB to implement this feature. (Note that writing ADPLL_DELTA_M[23:0] = 0x000 will result in no frequency offset and return to the nominal output frequency.) VB Code example for ADPLL (small frequency change) calculation and operation: nAddr = Device I2C address PPM_Delta = desired PPM frequency shift Function Set_ADPLL(ByVal nAddr As UInteger, ByVal PPM_Delta As Double) As Integer Dim ADPLL_PPM_StepSize As Double = 0.0001164 Dim ADPLL_Delta_M As Integer Dim Reg231 As UInteger = 0 Dim Reg232 As UInteger = 0 Dim Reg233 As UInteger = 0 Dim ReturnCode As Integer = 0 '1=OK, -1 PPM requested is out of bounds If (PPM_Delta = -950) Then ADPLL_Delta_M = (PPM_Delta / ADPLL_PPM_StepSize) Reg231 = (ADPLL_Delta_M And &HFF) Reg232 = (ADPLL_Delta_M >> 8) And &HFF Reg233 = (ADPLL_Delta_M >> 16) And &HFF I2C_Write(nAddr, 0, 231, Reg231) 'write “Reg231” value to register 231 at nAddr, page 0 (LSByte) I2C_Write(nAddr, 0, 232, Reg232) 'write “Reg232” value to register 232 at nAddr, page 0 I2C_Write(nAddr, 0, 233, Reg233) 'write “Reg233” value to register 233 at nAddr, page 0 (MSByte) ReturnCode = 1 Else ReturnCode = -1 End If Return (ReturnCode) End Function 5.8 Configuring High Drive LVDS Swing The Si569 LVDS clock output swing can be increased 100 mV via I2C to have the same swing as AC-coupled CML. This is done by programming the three registers as shown in the table below. Table 5.8. LVDS and CML Output Drive Settings 21 Register Address (dec) Output Drive LVDS (dec) High Drive LVDS / CML (dec) 16 [5:0] OD_DRV_TRIM_V3P3[5:0] 17 20 125 [5:0] OD_DRV_TRIM_V2P5[5:0] 20 23 126 [5:0] OD_DRV_TRIM_V1P8[5:0] 22 25 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com 206626A • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • May 30, 2023 21 Si569 Data Sheet • Configuring Si569 via I2C 5.9 Register Map Reference Table 5.9. Register Map Reference Summary Register (decimal) Register Bit 7 6 5 4 0 7 2 1 RESET = 3'b000 MS_ICAL 2 = 3'b000 23 ODC_OE HSDIV[7:0] LSDIV[2:0] Reset Value R 0x45 R/W 0x00 R/W 0x01 R/W 0x54 R/W 0x00 0 DEVICE_TYPE[7:0] 17 24 3 Type HSDIV[10:8] 26 FBDIV[7:0] R/W 0x00 27 FBDIV[15:8] R/W 0x00 28 FBDIV[23:16] R/W 0x00 29 FBDIV[31:24] R/W 0x00 30 FBDIV[39:32] R/W 0x64 R/W 0x00 R/W 0x06 R/W 0x80 R/W 0x01 31 32 35 69 FBDIV[42:40] KV_VCXO[4:0] CADC_FSGAIN[7:0] FCAL_OVR = 7'b0000001 231 ADPLL_DELTA_M[7:0] R/W 0x00 232 ADPLL_DELTA_M[15:8] R/W 0x00 233 ADPLL_DELTA_M[23:16] R/W 0x00 R/W 0x00 255 = 6'b000000 PAGE[1:0] Table 5.10. Register Bit Field Summary Register Bit Field Name Bit Field (#bits) Register Description DEVICE_TYPE[7:0] 8 0 Read only value of 69 (dec) which represents the device type (Si569) RESET 1 7 Set to 1 to reset device. Self clearing. MS_ICAL2 1 7 Set to 1 to initiate FCAL. Self clearing. ODC_OE 1 17 Set to 0 to disable the output clock, and remove output enable/disable control from the external OE or OEB pin. Set to 1 to return enable/disable control back to the OE or OEB pin. HSDIV[10:0] 22 11 23-24 HSDIV is High-speed output divider value in unsigned 11-bit binary format. Valid divide values are from 5 to 2046, with values of 5-33 even or odd, and values 34-2046 restricted to even values only. Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com 206626A • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • May 30, 2023 22 Si569 Data Sheet • Configuring Si569 via I2C 23 Register Bit Field Name Bit Field (#bits) Register Description LSDIV[2:0] 3 24 LSDIV sets a power-of-2 output divider. Values of 0,1,2,3,4,5,6,7 result in divide ratio of 1,2,4,8,16,32,32,32 respectively. Note that a value of 0 (divide-by-1) essentially bypasses this divider. FBDIV[42:0] 43 26-31 The main DSPLL system feedback divide (FBDIV) value for Si56x. This 43 bit value is composed of an unsigned 11-bit integer value (FBDIV[42:32]) concatenated with a 32-bit fractional value (FBDIV[31:0]), for an 11.32 fixed point binary format. The valid range of the 11-bit integer part is from 60 to 2045. KV_VCXO[4:0] 5 32 Sets Vc voltage control gain Kv (ppm/V). Multiply the register value in decimal by 7.5 to get the actual Kv in ppm/V. CADC_FSGAIN[7:0] 8 35 Full-scale Kv gain parameter. Used to set the (ppm/V) full-scale of the Vc input depending on the programmed VCO frequency. FCAL_OVR 1 69 FCAL Override: If set to 1, FCAL is bypassed. Clear to 0 to allow FCAL. ADPLL_DELTA_M[23:0] 24 231-233 Digital word to effect small frequency shifts to base frequency. Value is 24 bit 2's complement causing a 0.0001164 ppm per bit shift in frequency. Positive values = positive freq shift, negative values = negative freq shift. Valid range is -8161513 to +8161512, representing a max PPM shift range of -950 ppm to +950 ppm, with 0 value representing 0 PPM shift. Writing a new ADPLL_DELTA_M value will take effect upon writing to the MSByte (Register 233). Therefore, value updates should follow the sequence of writing in register order Reg 231...Reg 232...Reg 233. PAGE[1:0] 2 255 Sets which page of registers the I2C port is reading/writing. The size of a page is 256 bytes which is the addressable range of an I2C "set address" command. The value of PAGE is multiplied by 256 and added to what "set address" has set. Physically, the 2 PAGE bits become bits [9:8] of the device's internal register map address. This mechanism allows for more than 256 registers to be addressed within the 8 bit I2C "set address" limitation. Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com 206626A • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • May 30, 2023 23 Si569 Data Sheet • Configuring Si569 via I2C 5.10 Si569 Frequency Planner VB Code -------------------------------------------------------------------------------------------------Module Main ' ' Si56x Frequency Planner Code ' ' 'Set Target device type, Speed grade, and desired output frequency ' Public Device As Integer = 569 ' Public SpeedGrade As String = "D" 'Can only be "A" or "B" or "C" or “D” Public Output_Freq As Double = 312500000.0 'Output frequency in Hz (initially set to 312.5 MHz) 'Set in 'SetLimits" function... Public Fvco_max As Double 'Fvco Max per Table 5.3 Public Fvco_min As Double 'Fvco Min per Table 5.3 Public Xtal_freq As Double 'Xtal_Freq per Table 5.3 Public Fout_min As Double 'Minimum output frequency Public Fout_max As Double 'Maximum output frequency Sub Main() ' ' Device divider limits (see Tables 5.1 & 5.2) ' Dim HSDIV_UpperLimit As Integer = 2046 Dim HSDIV_LowerLimit As Integer = 4 Dim HSDIV_LowerLimit_Odd As Integer = 5 'min count for odd HSDIV divisor Dim HSDIV_UpperLimit_Odd As Integer = 33 'max count for odd HSDIV divisor Dim LSDIV_UpperLimit As Integer = 5 Dim LSDIV_LowerLimit As Integer = 0 Dim FBDIV_UpperLimit As Double = 2045 + ((2 ^ 32 - 1) / (2 ^ 32)) Dim FBDIV_LowerLimit As Double = 60.0 ' ' Working variables ' Dim Min_HSLS_Div As Double Dim LSDIV_Div As Double ' actual LSDIV divide ratio Dim LSDIV_Reg As Integer ' LSDIV as encoded in power of 2 for device register use Dim HSDIV As Double Dim FBDIV As Double Dim Fvco As Double Dim FBDIV_Int As UInteger Dim FBDIV_Frac As UInteger Dim Reg23 As UInteger = 0 'HSDIV[7:0] Dim Reg24 As UInteger = 0 'OD_LSDIV[2:0],HSDIV[10:8] (*2^4,/2^8) Dim Reg26 As UInteger = 0 'FBDIV[7:0] Dim Reg27 As UInteger = 0 'FBDIV[15:8] (/2^8) Dim Reg28 As UInteger = 0 'FBDIV[23:16] (/2^16) Dim Reg29 As UInteger = 0 'FBDIV[31:24] (/2^24) Dim Reg30 As UInteger = 0 'FBDIV[39:32] (/2^32) Dim Reg31 As UInteger = 0 'FBDIV[42:40] (/2^40) ' ' Set device limits based on device type and speed grade. ' (Checks if desired output frequency is valid based on device and speed grade) ' If SetLimits(Device, SpeedGrade, Output_Freq) = 0 Then ' ' If limits are set and output frequency is valid, calculate frequency plan... '*********************************************************************************************** ' Step 1: Find theoretical HSDIV *LSDIV value based on lowest valid VCO frequency... ' (Assumes "Output_Freq" has been tested and is in valid range for the device grade according to Table 5.3) ' Min_HSLS_Div = Fvco_min / Output_Freq ' Floating point HS*LS div value. Remember to first bounds check Output_Freq! 'Step 2: Find LSDIV divisor value given Min_HSLS_Div value ' LSDIV_Div = Math.Ceiling(Min_HSLS_Div / HSDIV_UpperLimit) 24 ' Divisor value of LSDIV, NOT yet Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com 206626A • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • May 30, 2023 24 Si569 Data Sheet • Configuring Si569 via I2C encoded as power of 2 If (LSDIV_Div > 32) Then LSDIV_Div = 32 ' clip at 32 (max LSDIV divisor) ' 'Encode LSDIV divisor value into next nearest 'power of 2' value if not already. This will be LSDIV_Reg ' LSDIV_Reg = Math.Ceiling(Math.Log(LSDIV_Div, 2)) ' LSDIV_Reg now encoded as proper power of 2. Will range from 0 to 5. ' Adjust LSDIV_Div (holder of divisor) based on rounded power of 2 value in LSDIV_Reg LSDIV_Div = 2 ^ LSDIV_Reg 'LSDIV_Div divisor now synchronized to actual LSDIV_Reg. ' 'Step 3: Find HSDIV divisor value using known LSDIV divisor ' HSDIV = Math.Ceiling(Min_HSLS_Div / LSDIV_Div) If ((HSDIV >= HSDIV_LowerLimit_Odd) And (HSDIV Fout_max)) Then ReturnCode = -1 End If ElseIf SpeedGrade = "B" Then 25 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com 206626A • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • May 30, 2023 25 Si569 Data Sheet • Configuring Si569 via I2C Fvco_min = 10800000000.0 Fvco_max = 12511886114.0 Fout_min = 200000.0 Fout_max = 1500000000.0 If ((Output_Freq < Fout_min) Or (Output_Freq > Fout_max)) Then ReturnCode = -1 End If ElseIf SpeedGrade = "C" Then Fvco_min = 10800000000.0 Fvco_max = 12206718160.0 Fout_min = 200000.0 Fout_max = 800000000.0 If ((Output_Freq < Fout_min) Or (Output_Freq > Fout_max)) Then ReturnCode = -1 End If ElseIf SpeedGrade = "D" Then Fvco_min = 10800000000.0 Fvco_max = 12206718160.0 Fout_min = 200000.0 Fout_max = 325000000.0 If ((Output_Freq < Fout_min) Or (Output_Freq > Fout_max)) Then ReturnCode = -1 End If Else ReturnCode = -1 'Speed Grade not found End If Else ReturnCode = -1 'Device type not found End If Return (ReturnCode) End Function End Module -------------------------------------------------------------------------- 26 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com 206626A • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • May 30, 2023 26 Si569 Data Sheet • Configuring Si569 via I2C 5.11 Table of Common Frequencies for Si569 (152.6 MHz xtal) Fout (MHz) LSDIV HSDIV FBDIV Fvco (GHz) Reg 23 Reg 24 Reg 26 Reg 27 Reg 28 Reg 29 Reg 30 Reg 31 70.656 0 154 71.30422018 10.881024 9Ah 00h BAh 5Fh E1h 4Dh 47h 00h 100 0 108 70.77326343 10.8 6Ch 00h A7h 97h F4h C5h 46h 00h 122.88 0 88 70.86133683 10.81344 58h 00h 04h 92h 80h DCh 46h 00h 125 0 88 72.08387942 11 58h 00h 34h 1Fh 79h 15h 48h 00h 148.351648 0 74 71.93985552 10.97802195 4Ah 00h 07h 5Fh 9Ah F0h 47h 00h 148.5 0 74 72.01179554 10.989 4Ah 00h 63h 08h 05h 03h 48h 00h 148.945454 0 74 72.22780862 11.0219636 4Ah 00h 7Dh AAh 51h 3Ah 48h 00h 150 0 72 70.77326343 10.8 48h 00h A7h 97h F4h C5h 46h 00h 153.6 0 72 72.47182176 11.0592 48h 00h 84h 4Fh C9h 78h 48h 00h 155.52 0 70 71.33944954 10.8864 46h 00h 46h 2Ah E6h 56h 47h 00h 156.25 0 70 71.67431193 10.9375 46h 00h D8h B4h 9Fh ACh 47h 00h 168.04 0 66 72.67785059 11.09064 42h 00h C2h 9Dh 87h ADh 48h 00h 168.75 0 64 70.77326343 10.8 40h 00h A7h 97h F4h C5h 46h 00h 200 0 54 70.77326343 10.8 36h 00h A7h 97h F4h C5h 46h 00h 212.5 0 52 72.41153342 11.05 34h 00h 17h 41h 5Ah 69h 48h 00h 245.76 0 44 70.86133683 10.81344 2Ch 00h 04h 92h 80h DCh 46h 00h 250 0 44 72.08387942 11 2Ch 00h 34h 1Fh 79h 15h 48h 00h 270 0 40 70.77326343 10.8 28h 00h A7h 97h F4h C5h 46h 00h 311.04 0 36 73.37771953 11.19744 24h 00h 1Ch 3Ah B2h 60h 49h 00h 312.5 0 36 73.72214941 11.25 24h 00h A3h C8h DEh B8h 49h 00h 322.265625 0 34 71.80230177 10.95703125 22h 00h 14h A6h 63h CDh 47h 00h 400 0 27 70.77326343 10.8 1Bh 00h A7h 97h F4h C5h 46h 00h 425 0 26 72.41153342 11.05 1Ah 00h 17h 41h 5Ah 69h 48h 00h 491.52 0 22 70.86133683 10.81344 16h 00h 04h 92h 80h DCh 46h 00h 500 0 22 72.08387942 11 16h 00h 34h 1Fh 79h 15h 48h 00h 614.4 0 18 72.47182176 11.0592 12h 00h 84h 4Fh C9h 78h 48h 00h 622.08 0 18 73.37771953 11.19744 12h 00h 1Ch 3Ah B2h 60h 49h 00h 644.53125 0 17 71.80230177 10.95703125 11h 00h 14h A6h 63h CDh 47h 00h 750 0 15 73.72214941 11.25 0Fh 00h A3h C8h DEh B8h 49h 00h 800 0 14 73.39449541 11.2 0Eh 00h C0h A6h FDh 64h 49h 00h 27 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com 206626A • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • May 30, 2023 27 Si569 Data Sheet • Configuring Si569 via I2C 5.12 I2C Interface Configuration and operation of the Si569 is controlled by reading and writing to the RAM space using the I2C interface. The device operates in slave mode with 7-bit addressing and can operate in Standard-Mode (100 kbps), Fast-Mode (400 kbps), or Fast-Mode Plus (1 Mbps). Burst data transfer with auto address increments are also supported. The I2C bus consists of a bidirectional serial data line (SDA) and a serial clock input (SCL). Both the SDA and SCL pins must be connected to the VDD supply via an external pull-up as recommended by the I2C specification. The Si569 7-bit I2C slave address is user-customized during the part number configuration process. Data is transferred MSB first in 8-bit words as specified by the I2C specification. A write command consists of a 7-bit device (slave) address + a write bit, an 8-bit register address, and 8 bits of data as shown in the figure below. A write burst operation is also shown where every additional data word is written using an auto-incremented address. Write Operation – Single Byte S Slv Addr [6:0] 0 A Reg Addr [7:0] A Data [7:0] A P A Data [7:0] Write Operation - Burst (Auto Address Increment) S Slv Addr [6:0] 0 A Reg Addr [7:0] A Data [7:0] A P Reg Addr +1 1 – Read 0 – Write A – Acknowledge (SDA LOW) N – Not Acknowledge (SDA HIGH) S – START condition P – STOP condition From slave to master From master to slave Figure 5.3. I2C Write Operation A read operation is performed in two stages. A data write is used to set the register address, then a data read is performed to retrieve the data from the set address. A read burst operation is also supported. This is shown in the figure below. Read Operation – Single Byte S Slv Addr [6:0] 0 A Reg Addr [7:0] A S Slv Addr [6:0] 1 A Data [7:0] P N P Read Operation - Burst (Auto Address Increment) S Slv Addr [6:0] 0 A Reg Addr [7:0] A S Slv Addr [6:0] 1 A Data [7:0] A P Data [7:0] N P Reg Addr +1 From slave to master From master to slave 1 – Read 0 – Write A – Acknowledge (SDA LOW) N – Not Acknowledge (SDA HIGH) S – START condition P – STOP condition Figure 5.4. I2C Read Operation The timing specifications and timing diagram for the I2C bus is compatible with the I2C-Bus standard. SDA timeout is supported for compatibility with SMBus interfaces. The I2C bus can be operated at a bus voltage of 1.71 to 3.63 V and should be the same voltage as the Si569 VDD. 28 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com 206626A • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • May 30, 2023 28 Si569 Data Sheet • Package Outline 6. Package Outline 6.1 Package Outline (5x7 mm) The figure below illustrates the package details for the 5x7 mm Si569. The table below lists the values for the dimensions shown in the illustration. Figure 6.1. Si569 (5x7 mm) Outline Diagram Table 6.1. Package Diagram Dimensions (mm) Dimension Min Nom Max Dimension Min Nom Max A 1.07 1.18 1.33 L 1.07 1.17 1.27 A2 0.40 0.50 0.60 L1 1.00 1.10 1.20 A3 0.45 0.55 0.65 L2 0.05 0.10 0.15 b 1.30 1.40 1.50 L3 0.15 0.20 0.25 b1 0.50 0.60 0.70 p 1.70 -- 1.90 c 0.50 0.60 0.70 R 0.70 REF aaa 0.15 bbb 0.15 D D1 5.00 BSC 4.30 4.40 4.50 e 2.54 BSC ccc 0.08 E 7.00 BSC ddd 0.10 eee 0.05 E1 6.10 6.20 6.30 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 29 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com 206626A • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • May 30, 2023 29 Si569 Data Sheet • Package Outline 6.2 Package Outline (3.2x5 mm) The figure below illustrates the package details for the 3.2x5 mm Si569. The table below lists the values for the dimensions shown in the illustration. Figure 6.2. Si569 (3.2x5 mm) Outline Diagram Table 6.2. Package Diagram Dimensions (mm) Dimension MIN NOM MAX Dimension MIN NOM MAX A 1.02 1.17 1.33 E1 A2 0.50 0.55 0.60 L 0.8 0.9 1.0 A3 0.45 0.50 0.55 L1 0.45 0.55 0.65 b 0.54 0.64 0.74 L2 0.05 0.10 0.15 b1 0.54 0.64 0.75 L3 0.15 0.20 0.25 2.85 BSC D 5.00 BSC aaa 0.15 D1 4.65 BSC bbb 0.15 e 1.27 BSC ccc 0.08 e1 1.625 TYP ddd 0.10 E 3.20 BSC eee 0.05 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 30 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com 206626A • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • May 30, 2023 30 Si569 Data Sheet • Package Outline 6.3 Package Outline (2.5x3.2 mm) The figure below illustrates the package details for the 2.5x3.2 mm Si569. The table below lists the values for the dimensions shown in the illustration. Figure 6.3. Si569 (2.5x3.2 mm) Outline Diagram Table 6.3. Package Diagram Dimensions (mm) Dimension MIN NOM MAX Dimension MIN NOM MAX A 0.85 0.90 1.00 L1 0.35 0.4 0.45 A1 0.36 REF e 1.1 BSC A2 0.53 REF n 5 D 3.2 BSC n1 2 E 2.5 BSC D1 2.2 BSC W 0.55 0.6 0.65 aaa 0.10 L 0.5 0.55 0.6 bbb 0.10 W1 0.35 0.4 0.45 ddd 0.08 Notes: 1. The dimensions in parentheses are reference. 2. All dimensions shown are in millimeters (mm) unless otherwise noted. 3. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 31 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com 206626A • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • May 30, 2023 31 Si569 Data Sheet • PCB Land Pattern 7. PCB Land Pattern 7.1 PCB Land Pattern (5x7 mm) The figure below illustrates the 5x7 mm PCB land pattern for the Si569. The table below lists the values for the dimensions shown in the illustration. Figure 7.1. Si569 (5x7 mm) PCB Land Pattern Table 7.1. PCB Land Pattern Dimensions (mm) Dimension (mm) Dimension (mm) C1 4.20 Y1 1.95 C2 6.05 X2 1.80 E 2.54 Y2 0.75 X1 1.55 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification. 3. This Land Pattern Design is based on the IPC-7351 guidelines. 4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm. Solder Mask Design 1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad. Stencil Design 1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. The stencil thickness should be 0.125 mm (5 mils). 3. The ratio of stencil aperture to land pad size should be 1:1. Card Assembly 1. A No-Clean, Type-3 solder paste is recommended. 2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 32 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com 206626A • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • May 30, 2023 32 Si569 Data Sheet • PCB Land Pattern 7.2 PCB Land Pattern (3.2x5 mm) The figure below illustrates the 3.2x5.0 mm PCB land pattern for the Si569. The table below lists the values for the dimensions shown in the illustration. Figure 7.2. Si569 (3.2x5 mm) PCB Land Pattern Table 7.2. PCB Land Pattern Dimensions (mm) Dimension (mm) Dimension (mm) C1 2.70 X2 0.90 E 1.27 Y1 1.60 E1 4.30 Y2 0.70 X1 0.74 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification. 3. This Land Pattern Design is based on the IPC-7351 guidelines. 4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm. Solder Mask Design 1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad. Stencil Design 1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. The stencil thickness should be 0.125 mm (5 mils). 3. The ratio of stencil aperture to land pad size should be 1:1. Card Assembly 1. A No-Clean, Type-3 solder paste is recommended. 2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 33 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com 206626A • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • May 30, 2023 33 Si569 Data Sheet • PCB Land Pattern 7.3 PCB Land Pattern (2.5x3.2 mm) The figure below illustrates the 2.5x3.2 mm PCB land pattern for the Si569. The table below lists the values for the dimensions shown in the illustration. Figure 7.3. Si569 (2.5x3.2 mm) PCB Land Pattern Table 7.3. PCB Land Pattern Dimensions (mm) 34 Dimension Description Value (mm) X1 Width - leads on long sides 0.7 Y1 Height - leads on long sides 0.7 X2 Width - single leads on short sides 0.5 Y2 Height - single leads on short sides 0.55 D1 Pitch in X directions of XL, Y1 leads 1.80 E1 Lead pitch X1, Y1 leads 1.10 E2 Lead pitch X2,Y2 leads 2.65 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com 206626A • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • May 30, 2023 34 Si569 Data Sheet • PCB Land Pattern Dimension Description Value (mm) Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification. 3. This Land Pattern Design is based on the IPC-7351 guidelines. 4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm. Solder Mask Design 1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad. Stencil Design 1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. The stencil thickness should be 0.125 mm (5 mils). 3. The ratio of stencil aperture to land pad size should be 0.8:1 for the pads. Card Assembly 1. A No-Clean, Type-3 solder paste is recommended. 2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 35 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com 206626A • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • May 30, 2023 35 Si569 Data Sheet • Top Markings 8. Top Markings 8.1 Top Marking (5x7 and 3.2x5 Packages) The figure below illustrates the mark specification for the Si569 5x7 and 3.2x5 package sizes. The table below lists the line information. Figure 8.1. Mark Specification Table 8.1. Si569 Top Mark Description Line Position Description 1 1–8 2 1 x = Frequency Range Supported as described in the 1. Ordering Guide 2–7 6-digit custom Frequency Code as described in the 1. Ordering Guide "Si569", xxx = Ordering Option 1, Option 2, Option 3 (e.g. Si569AAA) 3 36 Trace Code Position 1 Pin 1 orientation mark (dot) Position 2 Product Revision (C) Position 3–5 Tiny Trace Code (3 alphanumeric characters per assembly release instructions) Position 6–7 Year (last two digits of the year), to be assigned by assembly site (ex: 2017 = 17) Position 8–9 Calendar Work Week number (1–53), to be assigned by assembly site Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com 206626A • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • May 30, 2023 36 Si569 Data Sheet • Top Markings 8.2 Top Marking (2.5x3.2 Package) The figure below illustrates the mark specification for the Si569 2.5x3.2 package sizes. The table below lists the line information. SC CC CC T TTT TT Y Y WW Figure 8.2. Mark Specification Table 8.2. Si569 Top Mark Description Line Position 1 1–6 2 37 S = Si569, CCCCC = Custom Mark Code Trace Code 1–6 3 Description Position 1 Six-digit trace code per assembly release instructions Pin 1 orientation mark (dot) Position 2–3 Year (last two digits of the year), to be assigned by assembly site (exp: 2017 = 17) Position 4–5 Calendar Work Week number (1–53), to be assigned by assembly site Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com 206626A • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • May 30, 2023 37 Si569 Data Sheet • Revision History 9. Revision History Revision 206626A May, 2023 • Updated Min and Nom package diagram dimensions specs in 6.3 Package Outline (2.5x3.2 mm). Revision 1.3 June, 2021 • Updated Ordering Guide and Top Mark for Rev C silicon. • Added HCSL-Fast (faster tR/tF) ordering option. • Updated Table 2.1, Powerup VDD Ramp Rate. • Updated Table 2.2, Settling Time for Large Frequency Change. Revision 1.2 September, 2020 • Added 2.5x3.2 mm package option • Updated Table 2.1, Powerup VDD Ramp Rate and LVDS Swing. Revision 1.1 September, 2018 • Updated Electrical Specifications table to include high drive LVDS swing. • Added section 5.8 Configuring High Drive LVDS Swing. Revision 1.0 June, 2018 • Initial release. 38 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com 206626A • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • May 30, 2023 38 ClockBuilder Pro One-click access to Timing tools, documentation, software, source code libraries & more. Available for Windows and iOS (CBGo only). skyworksinc.com/CBPro Portfolio SW/HW Quality Support & Resources skyworksinc.com skyworksinc.com/CBPro skyworksinc.com/quality skyworksinc.com/support Copyright © 2022 Skyworks Solutions, Inc. All Rights Reserved. Information in this document is provided in connection with Skyworks Solutions, Inc. (“Skyworks”) products or services. These materials, including the information contained herein, are provided by Skyworks as a service to its customers and may be used for informational purposes only by the customer. Skyworks assumes no responsibility for errors or omissions in these materials or the information contained herein. Skyworks may change its documentation, products, services, specifications or product descriptions at any time, without notice. Skyworks makes no commitment to update the materials or information and shall have no responsibility whatsoever for conflicts, incompatibilities, or other difficulties arising from any future changes. No license, whether express, implied, by estoppel or otherwise, is granted to any intellectual property rights by this document. Skyworks assumes no liability for any materials, products or information provided hereunder, including the sale, distribution, reproduction or use of Skyworks products, information or materials, except as may be provided in Skyworks’ Terms and Conditions of Sale. THE MATERIALS, PRODUCTS AND INFORMATION ARE PROVIDED “AS IS” WITHOUT WARRANTY OF ANY KIND, WHETHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, INCLUDING FITNESS FOR A PARTICULAR PURPOSE OR USE, MERCHANTABILITY, PERFORMANCE, QUALITY OR NONINFRINGEMENT OF ANY INTELLECTUAL PROPERTY RIGHT; ALL SUCH WARRANTIES ARE HEREBY EXPRESSLY DISCLAIMED. SKYWORKS DOES NOT WARRANT THE ACCURACY OR COMPLETENESS OF THE INFORMATION, TEXT, GRAPHICS OR OTHER ITEMS CONTAINED WITHIN THESE MATERIALS. SKYWORKS SHALL NOT BE LIABLE FOR ANY DAMAGES, INCLUDING BUT NOT LIMITED TO ANY SPECIAL, INDIRECT, INCIDENTAL, STATUTORY, OR CONSEQUENTIAL DAMAGES, INCLUDING WITHOUT LIMITATION, LOST REVENUES OR LOST PROFITS THAT MAY RESULT FROM THE USE OF THE MATERIALS OR INFORMATION, WHETHER OR NOT THE RECIPIENT OF MATERIALS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE Skyworks products are not intended for use in medical, lifesaving or life-sustaining applications, or other equipment in which the failure of the Skyworks products could lead to personal injury, death, physical or environmental damage. Skyworks customers using or selling Skyworks products for use in such applications do so at their own risk and agree to fully indemnify Skyworks for any damages resulting from such improper use or sale. Customers are responsible for their products and applications using Skyworks products, which may deviate from published specifications as a result of design defects, errors, or operation of products outside of published parameters or design specifications. Customers should include design and operating safeguards to minimize these and other risks. Skyworks assumes no liability for applications assistance, customer product design, or damage to any equipment resulting from the use of Skyworks products outside of Skyworks’ published specifications or parameters. Skyworks, the Skyworks symbol, Sky5®, SkyOne®, SkyBlue™, Skyworks Green™, ClockBuilder®, DSPLL®, ISOmodem®, ProSLIC®, and SiPHY® are trademarks or registered trademarks of Skyworks Solutions, Inc. or its subsidiaries in the United States and other countries. Third-party brands and names are for identification purposes only and are the property of their respective owners. Additional information, including relevant terms and conditions, posted at www.skyworksinc.com, are incorporated by reference. Skyworks Solutions, Inc. | Nasdaq: SWKS | sales@skyworksinc.com | www.skyworksinc.com USA: 781-376-3000 | Asia: 886-2-2735 0399 | Europe: 33 (0)1 43548540