DATA SHEET
AAT3215
150mA CMOS High Performance LDO
General Description
Features
The AAT3215 MicroPower™ low dropout (LDO) linear
regulator is ideally suited for portable applications where
low noise, extended battery life, and small size are critical. The AAT3215 has been specifically designed for very
low output noise performance, fast transient response,
and high power supply rejection ratio (PSRR), making it
ideal for powering sensitive RF circuits.
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•
•
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Other features include low quiescent current, typically
95μA, and low dropout voltage which is typically less
than 140mV at full output current. The device is output
short-circuit protected and has a thermal shutdown circuit for additional protection under extreme conditions.
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•
•
•
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Low Dropout: 140mV at 150mA
Guaranteed 150mA Output
High Accuracy ±1.5%
95μA Quiescent Current
High Power Supply Ripple Rejection
▪ 70dB at 1kHz
▪ 50dB at 10kHz
Very Low Self Noise: 45μVrms
Fast Line and Load Transient Response
Short-Circuit Protection
Over-Temperature Protection
Uses Low Equivalent Series Resistance (ESR) Ceramic
Capacitors
Noise Reduction Bypass Capacitor
Shutdown Mode for Longer Battery Life
Low Temperature Coefficient
Six Factory-Programmed Output Voltages
SOT23 5-Pin Package
The AAT3215 also features a low-power shutdown mode
for extended battery life. A reference bypass pin has
been provided to improve PSRR performance and output
noise by connecting an external capacitor from the
AAT3215’s reference output to ground.
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•
•
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•
The AAT3215 is available in a Pb-free, space-saving
5-pin SOT23 package in six factory-programmed voltages: 2.6V, 2.85V, 3.0V, 3.1V, 3.3V, or 3.6V.
Applications
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•
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Bluetooth™ Headsets
Cellular Phones
Digital Cameras
Notebook Computers
Personal Portable Electronics
Portable Communication Devices
Typical Application
VOUT
VIN
IN
OUT
AAT3215
ON/OFF
BYP
EN
GND
1μF
GND
10nF
2.2μF
GND
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DATA SHEET
AAT3215
150mA CMOS High Performance LDO
Pin Descriptions
Pin Number
Symbol
1
2
IN
GND
3
EN
4
BYP
5
OUT
Function
Input voltage pin; should be decoupled with 1μF or greater capacitor.
Ground connection pin.
Enable pin. When pulled low, the PMOS pass transistor turns off and all internal
circuitry enters low-power mode, consuming less than 1μA. This pin should not
be left floating.
Bypass capacitor connection. To improve AC ripple rejection, connect a 10nF
capacitor to GND. This will also provide a soft-start function.
Output pin; should be decoupled with 2.2μF capacitor.
Pin Configuration
SOT23-5
(Top View)
2
IN
1
GND
2
EN
3
5
OUT
4
BYP
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DATA SHEET
AAT3215
150mA CMOS High Performance LDO
Absolute Maximum Ratings1
TA = 25°C, unless otherwise noted.
Symbol
VIN
VENIN(MAX)
IOUT
TJ
Description
Input Voltage
Maximum EN to Input Voltage
DC Output Current
Operating Junction Temperature Range
Value
Units
6
0.3
PD/(VIN-VO)
-40 to 150
mA
°C
Rating
Units
190
526
°C/W
mW
Rating
Units
(VOUT + 0.3) to 5.5
-40 to +85
V
°C
V
Thermal Information2
Symbol
Description
Maximum Thermal Resistance
Maximum Power Dissipation
θJA
PD
Recommended Operating Conditions
Symbol
VIN
T
Description
Input Voltage
Ambient Temperature Range
1. Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. Functional operation at conditions other than the operating conditions
specified is not implied.
2. Mounted on a demo board.
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DATA SHEET
AAT3215
150mA CMOS High Performance LDO
Electrical Characteristics
VIN = VOUT(NOM) + 1V, IOUT = 1mA, COUT = 2.2μF, CIN = 1μF, CBYP = 10nF, TA = -40°C to +85°C, unless otherwise noted.
Typical values are TA = 25°C.
Symbol
VOUT
IOUT
VDO
ISC
IQ
ISD
VOUT/
VOUT*VIN
Description
Conditions
Output Voltage Tolerance
IOUT = 1mA to 150mA
Output Current
Dropout Voltage1
Short-Circuit Current
Ground Current
Shutdown Current
VOUT > 1.2V
IOUT = 150mA
VOUT < 0.4V
VIN = 5V, No Load, EN = VIN
VIN = 5V, EN = 0V
Line Regulation
VIN = VOUT + 1 to 5.5V
VOUT(line)
Dynamic Line Regulation
VOUT(load)
VEN(L)
VEN(H)
IEN
Dynamic Load Regulation
Enable Threshold Low
Enable Threshold High
Leakage Current on Enable Pin
PSRR
TSD
THYS
eN
TC
Power Supply Rejection Ratio
Over-Temperature Shutdown
Threshold
Over-Temperature Shutdown
Hysteresis
Output Noise
Output Voltage Temperature
Min
TA = 25°C
TA = -40 to 85°C
Typ
-1.5
-2.5
150
140
600
95
VIN = VOUT + 1V to VOUT + 2V, IOUT = 150mA,
TR/TF = 2μs
IOUT = 1mA to 150mA, TR < 5μs
Max
Units
1.5
2.5
%
250
mA
mV
mA
150
1
μA
0.07
%/V
1
mV
30
0.6
1.5
VEN = 5V
IOUT = 10mA, CBYP = 10nF
1
1kHz
10kHz
1MHz
70
50
47
μA
dB
150
°C
10
45
22
1. VDO is defined as VIN - VOUT when VOUT is 98% of nominal.
4
V
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μVrms
ppm/°C
DATA SHEET
AAT3215
150mA CMOS High Performance LDO
Typical Characteristics
Unless otherwise noted, VIN = 5V, TA = 25°C.
Dropout Characteristics
Dropout Voltage vs. Temperature
3.1
180
Output Voltage (V)
Dropout Voltage (mV)
200
IL = 150mA
160
140
IL = 100mA
120
100
80
IL = 50mA
60
40
3.0
IOUT = 10mA
IOUT = 0mA
IOUT = 150mA
2.9
IOUT = 100mA
2.8
IOUT = 50mA
20
2.7
0
-40
-20
0
20
40
60
80
100
2.9
120
3.0
3.1
3.2
3.3
Input Voltage (V)
Temperature (°°C)
Ground Current vs. Input Voltage
Dropout Voltage vs. Output Current
120
Ground Current (μ
μA)
Dropout Voltage (mV)
200
180
160
140
120
100
80
60
40
VOUT = 3.0V
100
80
IOUT = 5mA
IOUT = 0
60
IOUT = 150mA
40
20
0
20
2
0
0
50
100
3
150
4
5
Input Voltage (V)
Output Current (mA)
Ground Current vs. Temperature
Output Voltage vs. Temperature
105
3.014
100
3.013
Output Voltage (V)
Ground Current (μA)
(VOUT = 3.0V)
95
90
85
80
-50
0
50
Temperature (°C)
100
150
3.012
3.011
3.01
3.009
3.008
3.007
-50
0
50
100
150
Temperature (°°C)
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DATA SHEET
AAT3215
150mA CMOS High Performance LDO
Typical Characteristics
Unless otherwise noted, VIN = 5V, TA = 25°C.
On/Off Transient Response
On/Off Transient Response
(No CBYP Capacitor)
(CBYP = 10nF)
EN (2V/div)
EN (2V/div)
VOUT (1V/div)
VOUT (1V/div)
10mA
10mA
150mA
150mA
Time (5ms/div)
Time (100μs/div)
Load Transient Response
3.10
500
3.03
5
3.05
400
3.02
4
3.00
300
3.01
3
2.95
200
3.00
2
2.90
100
2.99
1
2.85
0
2.98
0
2.80
-100
Output Voltage (V)
6
Time (100μs/div)
Time (5μs/div)
1.2
1
90
80
0.8
70
60
0.6
0.4
Time (10ms/div)
IOUT = 150mA
4.7μF
COUT = 10μF
2.2μF
50
40
30
20
10
0
10
0.2
0
6
Power Supply Rejection Ratio vs.
Frequency
PSRR (dB)
Short-Circuit Current (A)
Short-Circuit Current
1.0μF
100
1k
10k
100k
Frequency (Hz)
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1m
10m
Output Current (mA)
3.04
Input Voltage (V)
Output Voltage (V)
Line Transient Response
DATA SHEET
AAT3215
150mA CMOS High Performance LDO
Typical Characteristics
Unless otherwise noted, VIN = 5V, TA = 25°C.
Noise Amplitude in nVrms/√Hz
(50nVrms/√Hz per div)
Output Self Noise
500
0
10
100
1k
10k
100k
1m
10m
Frequency (Hz)
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DATA SHEET
AAT3215
150mA CMOS High Performance LDO
Functional Block Diagram
IN
OUT
Over-Current
Protection
Over-Temperature
Protection
Error
Amplifier
EN
BYP
Voltage
Reference
GND
Functional Description
The AAT3215 is intended for LDO regulator applications
where output current load requirements range from no
load to 150mA.
The advanced circuit design of the AAT3215 provides
excellent input-to-output isolation, which allows for good
power supply ripple rejection characteristics. To optimize
for very low output self noise performance, a bypass
capacitor pin has been provided to decrease noise generated by the internal voltage reference. This bypass
capacitor will also enhance PSRR behavior. The two combined characteristics of low noise and high PSRR make
the AAT3215 a truly high performance LDO regulator
especially well suited for circuit applications which are
sensitive to their power source.
8
The LDO regulator output has been specifically optimized
to function with low-cost, low-ESR ceramic capacitors.
However, the design will allow for operation over a wide
range of capacitor types.
The device enable circuit is provided to shut down the
LDO regulator for power conservation in portable products. The enable circuit has an additional output capacitor discharge circuit to assure sharp application circuit
turn-off upon device shutdown.
This LDO regulator has complete short-circuit and thermal protection. The integral combination of these two
internal protection circuits gives the AAT3215 a comprehensive safety system during extreme adverse operating
conditions. Device power dissipation is limited to the
package type and thermal dissipation properties. Refer
to the Thermal Considerations section of this datasheet
for details on device operation at maximum output current loads.
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DATA SHEET
AAT3215
150mA CMOS High Performance LDO
Applications Information
To assure the maximum possible performance is obtained
from the AAT3215, please refer to the following application recommendations.
Input Capacitor
Typically, a 1μF or larger capacitor is recommended for
CIN in most applications. A CIN capacitor is not required
for basic LDO regulator operation. However, if the
AAT3215 is physically located more than three centimeters from an input power source, a CIN capacitor will be
needed for stable operation. CIN should be located as
closely to the device VIN pin as practically possible. CIN
values greater than 1μF will offer superior input line
transient response and will assist in maximizing the
highest possible power supply ripple rejection.
Bypass Capacitor and
Low Noise Applications
A bypass capacitor pin is provided to enhance the very
low noise characteristics of the AAT3215 LDO regulator.
The bypass capacitor is not necessary for operation of
the AAT3215. However, for best device performance, a
small ceramic capacitor should be placed between the
bypass pin (BYP) and the device ground pin (GND). The
value of CBYP may range from 470pF to 10nF. For lowest
noise and best possible power supply ripple rejection
performance, a 10nF capacitor should be used. To practically realize the highest power supply ripple rejection
and lowest output noise performance, it is critical that
the capacitor connection between the BYP pin and GND
pin be direct and PCB traces should be as short as possible. Refer to the PCB Layout Recommendations section
of this document for examples.
Ceramic, tantalum, or aluminum electrolytic capacitors
may be selected for CIN. There is no specific capacitor
ESR requirement for CIN. However, for 150mA LDO regulator output operation, ceramic capacitors are recommended for CIN due to their inherent capability over
tantalum capacitors to withstand input current surges
from low impedance sources such as batteries in portable devices.
There is a relationship between the bypass capacitor
value and the LDO regulator turn-on time. In applications where fast device turn-on time is desired, the
value of CBYP should be reduced.
Output Capacitor
DC leakage on this pin can affect the LDO regulator output noise and voltage regulation performance. For this
reason, the use of a low leakage, high quality ceramic
(NPO or C0G type) or film capacitor is highly recommended.
For proper load voltage regulation and operational stability, a capacitor is required between pins VOUT and GND.
The COUT capacitor connection to the LDO regulator
ground pin should be made as direct as practically possible for maximum device performance.
The AAT3215 has been specifically designed to function
with very low ESR ceramic capacitors. Although the
device is intended to operate with these low ESR capacitors, it is stable over a very wide range of capacitor
ESR, thus it will also work with higher ESR tantalum or
aluminum electrolytic capacitors. However, for best performance, ceramic capacitors are recommended.
Typical output capacitor values for maximum output current conditions range from 1μF to 10μF. Applications
utilizing the exceptionally low output noise and optimum
power supply ripple rejection characteristics of the
AAT3215 should use 2.2μF or greater for COUT. If desired,
COUT may be increased without limit.
In low output current applications where output load is
less than 10mA, the minimum value for COUT can be as
low as 0.47μF.
In applications where low noise performance and/ or
ripple rejection are less of a concern, the bypass capacitor may be omitted. The fastest device turn-on time will
be realized when no bypass capacitor is used.
Capacitor Characteristics
Ceramic composition capacitors are highly recommended over all other types of capacitors for use with the
AAT3215. Ceramic capacitors offer many advantages
over their tantalum and aluminum electrolytic counterparts. A ceramic capacitor typically has very low ESR, is
lower cost, has a smaller PCB footprint, and is nonpolarized. Line and load transient response of the LDO
regulator is improved by using low ESR ceramic capacitors. Since ceramic capacitors are non-polarized, they
are not prone to incorrect connection damage.
Equivalent Series Resistance: ESR is a very important characteristic to consider when selecting a capacitor. ESR is the internal series resistance associated with
a capacitor that includes lead resistance, internal connections, size and area, material composition, and ambi-
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DATA SHEET
AAT3215
150mA CMOS High Performance LDO
ent temperature. Typically, capacitor ESR is measured in
milliohms for ceramic capacitors and can range to more
than several ohms for tantalum or aluminum electrolytic
capacitors.
Ceramic Capacitor Materials: Ceramic capacitors less
than 0.1μF are typically made from NPO or C0G materials. NPO and C0G materials generally have tight tolerance and are very stable over temperature. Larger
capacitor values are usually composed of X7R, X5R, Z5U,
or Y5V dielectric materials. Large ceramic capacitors (i.e.,
greater than 2.2μF) are often available in low-cost Y5V
and Z5U dielectrics. These two material types are not
recommended for use with LDO regulators since the
capacitor tolerance can vary more than ±50% over the
operating temperature range of the device. A 2.2μF Y5V
capacitor could be reduced to 1μF over temperature; this
could cause problems for circuit operation. X7R and X5R
dielectrics are much more desirable. The temperature
tolerance of X7R dielectric is better than ±15%.
Capacitor area is another contributor to ESR. Capacitors
that are physically large in size will have a lower ESR
when compared to a smaller sized capacitor of an equivalent material and capacitance value. These larger devices can improve circuit transient response when compared
to an equal value capacitor in a smaller package size.
Consult capacitor vendor datasheets carefully when
selecting capacitors for LDO regulators.
Enable Function
The AAT3215 features an LDO regulator enable/disable
function. This pin (EN) is active high and is compatible
with CMOS logic. To assure the LDO regulator will switch
on, the EN turn-on control level must be greater than
2.0V. The LDO regulator will go into the disable shutdown mode when the voltage on the EN pin falls below
0.6 volts. If the enable function is not needed in a specific application, it may be tied to VIN to keep the LDO
regulator in a continuously on state.
When the LDO regulator is in shutdown mode, an internal 1.5k resistor is connected between VOUT and GND.
This is intended to discharge COUT when the LDO regulator is disabled. The internal 1.5k has no adverse effect
on device turn-on time.
Short-Circuit Protection
The AAT3215 contains an internal short-circuit protection
circuit that will trigger when the output load current
10
exceeds the internal threshold limit. Under short-circuit
conditions, the output of the LDO regulator will be current limited until the short-circuit condition is removed
from the output or LDO regulator package power dissipation exceeds the device thermal limit.
Thermal Protection
The AAT3215 has an internal thermal protection circuit
which will turn on when the device die temperature
exceeds 150°C. The internal thermal protection circuit
will actively turn off the LDO regulator output pass
device to prevent the possibility of over-temperature
damage. The LDO regulator output will remain in a shutdown state until the internal die temperature falls back
below the 150°C trip point.
The combination and interaction between the short-circuit and thermal protection systems allows the LDO
regulator to withstand indefinite short-circuit conditions
without sustaining permanent damage.
No-Load Stability
The AAT3215 is designed to maintain output voltage
regulation and stability under operational no-load conditions. This is an important characteristic for applications
where the output current may drop to zero.
Reverse Output-to-Input
Voltage Conditions and Protection
Under normal operating conditions, a parasitic diode
exists between the output and input of the LDO regulator. The input voltage should always remain greater than
the output load voltage, maintaining a reverse bias on
the internal parasitic diode. Conditions where VOUT might
exceed VIN should be avoided since this would forward
bias the internal parasitic diode and allow excessive current flow into the VOUT pin, possibly damaging the LDO
regulator.
In applications where there is a possibility of VOUT
exceeding VIN for brief amounts of time during normal
operation, the use of a larger value CIN capacitor is
highly recommended. A larger value of CIN with respect
to COUT will effect a slower CIN decay rate during shutdown, thus preventing VOUT from exceeding VIN. In applications where there is a greater danger of VOUT exceeding
VIN for extended periods of time, it is recommended to
place a Schottky diode across VIN to VOUT (connecting the
cathode to VIN and anode to VOUT). The Schottky diode
forward voltage should be less than 0.45V.
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DATA SHEET
AAT3215
150mA CMOS High Performance LDO
Thermal Considerations and
High Output Current Applications
The AAT3215 is designed to deliver a continuous output
load current of 150mA under normal operating conditions.
The limiting characteristic for the maximum output load
current safe operating area is essentially package power
dissipation and the internal preset thermal limit of the
device. In order to obtain high operating currents, careful device layout and circuit operating conditions need to
be taken into account.
The following discussions will assume the LDO regulator
is mounted on a printed circuit board utilizing the minimum recommended footprint as stated in the Layout
Considerations section of this datasheet.
At any given ambient temperature (TA), the maximum
package power dissipation can be determined by the following equation:
TJ(MAX) - TA
PD(MAX) =
θJA
Constants for the AAT3215 are TJ(MAX), the maximum
junction temperature for the device which is 125°C, and
JA = 190°C/W, the package thermal resistance. Typically,
maximum conditions are calculated at the maximum
operating temperature where TA = 85°C, under normal
ambient conditions TA = 25°C. Given TA = 85°C, the
maximum package power dissipation is 211mW. At TA =
25°C, the maximum package power dissipation is
526mW.
The maximum continuous output current for the AAT3215
is a function of the package power dissipation and the
input-to-output voltage drop across the LDO regulator.
Refer to the following simple equation:
IOUT(MAX) <
PD(MAX)
VIN - VOUT
For example, if VIN = 5V, VOUT = 3V, and TA = 25°C,
IOUT(MAX) < 264mA. If the output load current were to
exceed 264mA or if the ambient temperature were to
increase, the internal die temperature would increase. If
the condition remained constant, the LDO regulator
thermal protection circuit would activate.
To determine the maximum input voltage for a given
load current, refer to the following equation. This calculation accounts for the total power dissipation of the LDO
regulator, including that caused by ground current.
PD(MAX) = (VIN - VOUT) · IOUT + VIN · IGND
This formula can be solved for VIN to determine the
maximum input voltage.
VIN(MAX) =
PD(MAX) + VOUT · IOUT
IOUT + IGND
The following is an example for an AAT3215 set for a 2.6
volt output:
VOUT = 2.6V
IOUT = 150mA
IGND = 150μA
VIN(MAX) =
526mW + 2.6V · 150mA
150mA + 150μA
VIN(MAX) = 6.1V
From the discussion above, PD(MAX) was determined to
equal 526mW at TA = 25°C.
Thus, the AAT3215 can sustain a constant 2.6V output
at a 150mA load current as long as VIN is ≤ 6.1V at an
ambient temperature of 25°C. 6.1V is the absolute
maximum voltage where an AAT3215 would never be
operated, thus at 25°C, the device would not have any
thermal concerns or operational VIN(MAX) limits.
This situation can be different at 85°C. The following is an
example for an AAT3215 set for a 2.6V output at 85°C:
VOUT = 2.6V
IOUT = 150mA
IGND = 150μA
VIN(MAX) =
211mW + 2.6V · 150mA
150mA + 150μA
VIN(MAX) = 4V
From the discussion above, PD(MAX) was determined to
equal 211mW at TA = 85°C.
Higher input-to-output voltage differentials can be
obtained with the AAT3215, while maintaining device
functions within the thermal safe operating area. To
accomplish this, the device thermal resistance must be
reduced by increasing the heat sink area or by operating
the LDO regulator in a duty-cycled mode.
For example, an application requires VIN = 4.2V while VOUT
= 2.6V at a 150mA load and TA = 85°C. VIN is greater than
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11
DATA SHEET
AAT3215
150mA CMOS High Performance LDO
4V, which is the maximum safe continuous input level for
VOUT = 2.6V at 150mA for TA = 85°C. To maintain this high
input voltage and output current level, the LDO regulator
must be operated in a duty-cycled mode. Refer to the following calculation for duty-cycle operation:
IGND = 150μA
IOUT = 150mA
VIN = 4.2V
PD(MAX) = (VIN - VOUT)IOUT + (VIN · IGND)
PD(100mA) = (4.2V - 2.6V)100mA + (4.2V · 150μA)
PD(100mA) = 160.6mW
PD(91.8%D/C) = %DC · PD(100mA)
PD(91.8%D/C) = 0.918 · 160.6mW
PD(91.8%D/C) = 147.4mW
The power dissipation for 100mA load occurring for
91.8% of the duty cycle will be 147.4mW. Now the power
dissipation for the remaining 8.2% of the duty cycle at
the 150mA load can be calculated:
VOUT = 2.6V
%DC =
PD(MAX)
(VIN - VOUT) ∙ IOUT + VIN · IGND
%DC =
211mW
(4.2V - 2.6V) ∙ 150mA + 4.2V · 150μA
%DC = 87.68%
PD(MAX) was assumed to be 211mW.
For a 150mA output current and a 2.8V drop across the
AAT3215 at an ambient temperature of 85°C, the maximum on-time duty cycle for the device would be 87.68%.
High Peak Output Current Applications
Some applications require the LDO regulator to operate
at continuous nominal level with short duration, highcurrent peaks. The duty cycles for both output current
levels must be taken into account. To do so, first calculate the power dissipation at the nominal continuous
level, then factor in the additional power dissipation due
to the short duration, high-current peaks.
For example, a 2.6V system using a AAT3215IGV-2.6-T1
operates at a continuous 100mA load current level and
has short 150mA current peaks. The current peak occurs
for 378μs out of a 4.61ms period. It will be assumed the
input voltage is 4.2V.
First, the current duty cycle in percent must be calculated:
% Peak Duty Cycle: X/100 = 378μs/4.61ms
% Peak Duty Cycle = 8.2%
The LDO regulator will be under the 100mA load for
91.8% of the 4.61ms period and have 150mA peaks
occurring for 8.2% of the time. Next, the continuous
nominal power dissipation for the 100mA load should be
determined then multiplied by the duty cycle to conclude
the actual power dissipation over time.
PD(MAX) = (VIN - VOUT)IOUT + (VIN · IGND)
PD(150mA) = (4.2V - 2.6V)150mA + (4.2V · 150mA)
PD(150mA) = 240.6mW
PD(8.2%D/C) = %DC · PD(150mA)
PD(8.2%D/C) = 0.082 · 240.6mW
PD(8.2%D/C) = 19.7mW
The power dissipation for 150mA load occurring for 8.2%
of the duty cycle will be 19.7mW. Finally, the two power
dissipation levels can summed to determine the total
true power dissipation under the varied load.
PD(total) = PD(100mA) + PD(150mA)
PD(total) = 147.4mW + 19.7mW
PD(total) = 167.1mW
The maximum power dissipation for the AAT3215 operating at an ambient temperature of 85°C is 211mW. The
device in this example will have a total power dissipation
of 167.1mW. This is well within the thermal limits for
safe operation of the device.
Printed Circuit Board
Layout Recommendations
In order to obtain the maximum performance from the
AAT3215 LDO regulator, careful consideration should be
given to the printed circuit board (PCB) layout. If grounding connections are not properly made, power supply
ripple rejection, low output self noise, and transient
response can be compromised.
Figure 1 shows a common LDO regulator layout scheme.
The LDO regulator, external capacitors (CIN, COUT, and
CBYP), and the load circuit are all connected to a common
ground plane. This type of layout will work in simple
applications where good power supply ripple rejection
and low self noise are not a design concern. For high
performance applications, this method is not recommended.
The problem with the layout in Figure 1 is the bypass
12
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DATA SHEET
AAT3215
150mA CMOS High Performance LDO
capacitor and output capacitor share the same ground
path to the LDO regulator ground pin, along with the
high current return path from the load back to the power
supply. The bypass capacitor node is connected directly
to the LDO regulator internal reference, making this
node very sensitive to noise or ripple. The internal reference output is fed into the error amplifier, thus any noise
or ripple from the bypass capacitor will be subsequently
amplified by the gain of the error amplifier. This effect
can increase noise seen on the LDO regulator output, as
well as reduce the maximum possible power supply ripple rejection. There is PCB trace impedance between the
bypass capacitor connection to ground and the LDO
regulator ground connection. When the high load current
returns through this path, a small ripple voltage is created, feeding into the CBYP loop.
VIN
LDO
Regulator
EN
DC INPUT
Evaluation Board Layout
The AAT3215 evaluation layout follows the recommend
printed circuit board layout procedures and can be used
as an example for good application layouts (see Figures
3, 4, and 5).
Note: Board layout shown is not to scale.
ILOAD
IIN
VIN
Figure 2 shows the preferred method for the bypass and
output capacitor connections. For low output noise and
highest possible power supply ripple rejection performance, it is critical to connect the bypass and output
capacitor directly to the LDO regulator ground pin. This
method will eliminate any load noise or ripple current
feedback through the LDO regulator.
VOUT
BYP
GND
CIN
CBYP
IGND
IRIPPLE
IBYP + noise
COUT
RLOAD
CBYP
GND
LOOP
GND
RTRACE
RTRACE
RTRACE
RTRACE
ILOAD return + noise and ripple
Figure 1: Common LDO Regulator Layout with CBYP Ripple Feedback Loop.
ILOAD
IIN
VIN
VIN
LDO
Regulator
EN
VOUT
BYP
GND
DC INPUT
CIN
IGND
CBYP
COUT
RLOAD
IBYP only
IRIPPLE
GND
RTRACE
RTRACE
RTRACE
RTRACE
ILOAD return + noise and ripple
Figure 2: Recommended LDO Regulator Layout.
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13
DATA SHEET
AAT3215
150mA CMOS High Performance LDO
Figure 3: Evaluation Board
Figure 4: Evaluation Board
Component Side Layout.
Solder Side Layout.
Figure 5: Evaluation Board
Top Side Silk Screen Layout /
Assembly Drawing.
14
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DATA SHEET
AAT3215
150mA CMOS High Performance LDO
Ordering Information
Output Voltage
Package
Marking1
Part Number (Tape and Reel)2
SOT23-5
GKXYY
CIXYY
BTXYY
GJXYY
BUXYY
DYXYY
AAT3215IGV-2.6-T1
AAT3215IGV-2.85-T1
AAT3215IGV-3.0-T1
AAT3215IGV-3.1-T1
AAT3215IGV-3.3-T1
AAT3215IGV-3.6-T1
2.6V
2.85V
3.0V
3.1V
3.3V
3.6V
Skyworks Green™ products are compliant with
all applicable legislation and are halogen-free.
For additional information, refer to Skyworks
Definition of Green™, document number
SQ04-0074.
Package Information
SOT23-5
2.85 ± 0.15
1.90 BSC
0.075 ± 0.075
10°° ± 5°°
0.40 ± 0.10
0.15 ± 0.07
GAUGE PLANE
4°° ± 4°°
1.10 ± 0.20
0.60 REF
1.20 ± 0.25
2.80 ± 0.20
1.575 ± 0.125
0.95
BSC
0.60 REF
0.45 ± 0.15
0.10 BSC
All dimensions in millimeters.
1. XYY = assembly and date code.
2. Sample stock is generally held on part numbers listed in BOLD.
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
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15
DATA SHEET
AAT3215
150mA CMOS High Performance LDO
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