S i 3 0 5 0 + S i 3 0 11 / 1 8 / 1 9
P R O G R A M M A B L E VO I C E D A A S O L U T I O N S
Features
PCM highway data interface
µ-law/A-law companding
SPI control interface
GCI interface
80 dB dynamic range TX/RX
Line voltage monitor
Loop current monitor
+6 dBm or +3.2 dBm TX/RX level
mode
Parallel handset detection
3 µA on-hook line monitor current
Overload detection
Programmable line interface
AC termination
DC termination
Ring detect threshold
Ringer impedance
TIP/RING polarity detection
Integrated codec and 2- to 4-wire
analog hybrid
Programmable digital hybrid for
near-end echo reduction
Polarity reversal detection
Programmable digital gain in 0.1 dB
increments
Integrated ring detector
Type I and II caller ID support
Pulse dialing support
3.3 V power supply
Daisy-chaining for up to 16 devices
Greater than 5000 V isolation
Patented isolation technology
Ground start and loop start support
Available in Pb-free RoHS-compliant
packages
Ordering Information
See page 106.
Applications
Voice mail systems
DECT base stations
Package Options
FSYNC
RGDT
RG
TGD
TGDE
RESET
AOUT/INT
Rev. 1.5 10/11
Ring Detect
Control
Logic
Off-Hook
RNG1
RNG2
QB
QE
QE2
NC
SDITHR
SCLK
19
16
VA
DTX
4
15
C1A
DRX
5
14
C2A
RGDT
6
13
RESET
Si3050
Top View
11
TGD
12
10
NC
TGDE
9
NC
8
GND
IB
3
C1B
4
C2B
5
NC
2
IGND
1
RX
DCT2
NC
QE
Si3011/18/19
20
19
18
17
16
15 DCT3
14 QB
IGND
PAD
13 QE2
12 SC
6
7
8
9
10
VREG2
Line
Data
Interface
Isolation
Interface
20
3
RNG2
DTX
DRX
Isolation
Interface
IB
SC
DCT
VREG
VREG2
DCT2
DCT3
NC
VDD
PCKLK
IGND
PCLK
Hybrid, AC
and DC
Terminations
21
GND
17
RNG1
SDI
SDO
SDI THRU
RX
Control
Data
Interface
SDO
18
2
VREG
CS
SCLK
Si3018/19
22
1
Functional Block Diagram
Si3050
SDI
CS
FSYNC
7
The Si3050+Si3011/18/19 Voice DAA chipset provides a highly-programmable
and globally-compliant foreign exchange office (FXO) analog interface. The
solution implements Silicon Laboratories' patented isolation capacitor technology,
which eliminates the need for costly isolation transformers, relays, or
opto-isolators, while providing superior surge immunity for robust field
performance. The Voice DAA is available as a chipset, a system-side device
(Si3050) paired with a line-side device (Si3011/18/19). The Si3050 is available in
a 20-pin TSSOP or a 24-pin QFN. The Si3011/18/19 is available in a 16-pin
TSSOP, a 16-pin SOIC, or a 20-pin QFN and requires minimal external
components. The Si3050 interfaces directly to standard telephony PCM
interfaces.
23
Description
24
Si3050
RG
AOUT/INT
DSL IADs
VoIP gateways
PBX and IP-PBX systems
DCT
11 NC
US Patent# 5,870,046
US Patent# 6,061,009
Copyright © 2011 by Silicon Laboratories
Si3050 + Si3011/18/19
Si3050 + Si3011/18/19
2
Rev. 1.5
Si3050 + Si3011/18/19
TABLE O F C ONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
2. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3. Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4. AOUT PWM Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.1. Line-Side Device Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.2. Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.3. Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
5.4. Isolation Barrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.5. Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.6. Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.7. In-Circuit Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
5.8. Exception Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.9. Revision Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.10. Transmit/Receive Full-Scale Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.11. Parallel Handset Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.12. Line Voltage/Loop Current Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.13. Off-Hook . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.14. Ground Start Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.15. Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.16. DC Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.17. AC Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.18. Ring Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.19. Ring Validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
5.20. Ringer Impedance and Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.21. Pulse Dialing and Spark Quenching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.22. Receive Overload Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
5.23. Billing Tone Filter (Optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.24. On-Hook Line Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.25. Caller ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.26. Overload Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
5.27. Gain Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
5.28. Transhybrid Balance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.29. Filter Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
5.30. Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.31. Communication Interface Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
5.32. PCM Highway . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.33. Companding in PCM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.34. 16 kHz Sampling Operation in PCM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.35. SPI Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
5.36. GCI Highway . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Rev. 1.5
3
Si3050 + Si3011/18/19
5.37. Companding in GCI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5.38. 16 kHz Sampling Operation in GCI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5.39. Monitor Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5.40. Summary of Monitor Channel Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
5.41. Device Address Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
5.42. Command Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
5.43. Register Address Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
5.44. SC Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
5.45. Receive SC Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
5.46. Transmit SC Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
6. Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
7. Pin Descriptions: Si3011/18/19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
8. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
9. Product Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
10. Package Outline: 20-Pin TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
10.1. PCB Land Pattern: Si3050 TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
11. Package Outline: 24-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
12. PCB Land Pattern: Si3050 QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
13. Package Outline: 16-Pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
13.1. PCB Land Pattern: Si3011/18/19 SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
14. Package Outline: 16-Pin TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
14.1. PCB Land Pattern: Si3011/18/19 TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
15. Package Outline: 20-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
16. PCB Land Pattern: Si3011/18/19 QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Silicon Labs Si3050 Support Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
4
Rev. 1.5
Si3050 + Si3011/18/19
1. Electrical Specifications
Table 1. Recommended Operating Conditions and Thermal Information
Parameter1
Symbol
Ambient Temperature
TA
Si3050 Supply Voltage, Digital
VD
JA
Thermal Resistance (Si3011/18/19)3
Thermal Resistance (Si3050)3
JA
Test Condition
Min2
Typ
Max2
F-Grade
0
25
70
G-Grade
–40
25
85
3.0
3.3
3.6
SOIC-16
—
77
—
TSSOP-16
—
89
—
QFN-20
—
120
—
TSSOP-20
—
84
—
QFN-24
—
67
—
Unit
°C
V
°C/W
°C/W
Notes:
1. The Si3050 specifications are guaranteed when the typical application circuit (including component tolerance) and any
Si3050 and any Si3011/18/19 are used. See "2. Typical Application Schematic" on page 17 for the typical application
circuit.
2. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise stated.
3. Operation above 125 °C junction temperature may degrade device reliability.
Rev. 1.5
5
Si3050 + Si3011/18/19
Table 2. Loop Characteristics
(VD = 3.0 to 3.6 V, TA = 0 to 70 °C, see Figure 1 on page 6)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
DC Termination Voltage
VTR
IL =20 mA, ILIM =0
DCV = 00, MINI = 11, DCR = 0
—
—
6.0
V
DC Termination Voltage
VTR
IL = 120 mA, ILIM = 0
DCV = 00, MINI = 11, DCR = 0
9
—
—
V
DC Termination Voltage
VTR
IL =20 mA, ILIM =0
DCV = 11, MINI = 00, DCR = 0
—
—
7.5
V
DC Termination Voltage
VTR
IL = 120 mA, ILIM = 0
DCV = 11, MINI = 00, DCR = 0
9
—
—
V
DC Termination Voltage
VTR
IL =20 mA, ILIM =1
DCV = 11, MINI = 00, DCR = 0
—
—
7.5
V
DC Termination Voltage
VTR
IL =60 mA, ILIM =1
DCV = 11, MINI = 00, DCR = 0
40
—
—
V
DC Termination Voltage
VTR
IL =50 mA, ILIM =1
DCV = 11, MINI = 00, DCR = 0
—
—
40
V
On-Hook Leakage Current
ILK
VTR = –48 V
—
—
5
µA
MINI = 00, ILIM = 0
10
—
120
mA
Operating Loop Current
ILP
Operating Loop Current
ILP
MINI = 00, ILIM = 1
10
—
60
mA
dc current flowing through ring
detection circuitry
—
1.5
3
µA
VRD
RT2 = 0, RT = 0
13.5
15
16.5
RT2 = 0, RT = 1
19.35
21.5
23.65
Vrms
VRD
RT2 = 1, RT = 1
40.5
45
49.5
DC Ring Current
Ring Detect Voltage*
Ring Detect Voltage
Ring Detect Voltage
*
VRD
*
Ring Frequency
Ringer Equivalence Number
FR
REN
13
—
68
—
—
0.2
Vrms
Vrms
Hz
*Note: The ring signal is guaranteed to not be detected below the minimum. The ring signal is guaranteed to be detected
above the maximum.
TIP
+
600
IL
Si3011/18/19 VTR
10F
RING
–
Figure 1. Test Circuit for Loop Characteristics
6
Rev. 1.5
Si3050 + Si3011/18/19
Table 3. DC Characteristics, VD = 3.0 to 3.6 V
(VD = 3.0 to 3.6 V, TA = 0 to 70 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
High Level Input Voltage1
VIH
2.0
—
—
V
1
Low Level Input Voltage
VIL
—
—
0.8
V
High Level Output Voltage
VOH
=
IO –2 mA
2.4
—
—
V
Low Level Output Voltage
VOL
IO = 2 mA
—
—
0.35
V
AOUT High Level Voltage
VAH
IO = 10 mA
2.4
—
—
V
AOUT Low Level Voltage
VAL
IO = 10 mA
—
—
0.35
V
–10
—
10
µA
Input Leakage Current
Power Supply Current, Digital
IL
2
Total Supply Current, Sleep Mode2
Total Supply Current, Deep Sleep
2,3
ID
VD pin
—
8.5
10
mA
ID
PDN = 1, PDL = 0
—
5.0
6.0
mA
ID
PDN = 1, PDL = 1
—
1.3
1.5
mA
Notes:
1. VIH/VIL do not apply to C1A/C2A.
2. All inputs at 0.4 or VD – 0.4 (CMOS levels). All inputs are held static except clock and all outputs unloaded
(Static IOUT = 0 mA).
3. RGDT is not functional in this state.
Rev. 1.5
7
Si3050 + Si3011/18/19
Table 4. AC Characteristics
(VD = 3.0 to 3.6 V, TA = 0 to 70 °C, Fs = 8000 Hz, see "2. Typical Application Schematic" on page 17)
Parameter
Symbol
Sample Rate
PCLK Input Frequency
Test Condition
Min
Typ
Max
Unit
Fs
8
—
16
kHz
PCLK
256
—
8192
kHz
Receive Frequency Response
Low –3 dBFS Corner, FILT = 0
—
5
—
Hz
Receive Frequency Response
Low –3 dBFS Corner, FILT = 1
—
200
—
Hz
FULL = 0 (0 dBm)
—
1.1
—
VPEAK
FULL = 1 (+3.2 dBm)2
—
1.58
—
VPEAK
dBm)2
—
2.16
—
VPEAK
VFS
Transmit Full-Scale Level1
FULL2 = 1 (+6.0
VFS
Receive Full-Scale
Level1,3
FULL = 0 (0 dBm)
—
1.1
—
VPEAK
dBm)2
—
1.58
—
VPEAK
FULL2 = 1 (+6.0 dBm)2
—
2.16
—
VPEAK
FULL = 1 (+3.2
Dynamic Range4,5,6
DR
ILIM = 0, DCV = 11, MINI=00
DCR = 0, IL = 100 mA
—
80
—
dB
Dynamic Range4,5,6
DR
ILIM = 0, DCV = 00, MINI=11
DCR = 0, IL = 20 mA
—
80
—
dB
Dynamic Range4,5,6
DR
ILIM = 1, DCV = 11, MINI=00
DCR = 0, IL = 50 mA
—
80
—
dB
Transmit Total Harmonic
Distortion6,7
THD
ILIM = 0, DCV = 11, MINI=00
DCR = 0, IL = 100 mA
—
–72
—
dB
Transmit Total Harmonic
Distortion6,7
THD
ILIM = 0, DCV = 00, MINI=11
DCR = 0, IL = 20 mA
—
–78
—
dB
Receive Total Harmonic
Distortion6,7
THD
ILIM = 0, DCV = 00, MINI=11
DCR = 0, IL = 20 mA
—
–78
—
dB
Receive Total Harmonic
Distortion6,7
THD
ILIM = 1,DCV = 11, MINI=00
DCR = 0, IL = 50 mA
—
–78
—
dB
Notes:
1. Measured at TIP and RING with 600 termination at 1 kHz, as shown in Figure 1 on page 6.
2. With FULL = 1, the transmit and receive full-scale level of +3.2 dBm can be achieved with a 600 ac termination.
While the transmit and receive level in dBm varies with reference impedance, the DAA will transmit and receive 1 dBV
into all reference impedances. With FULL2 = 1, the transmit and receive full-scale level of +6.0 dBm can be achieved
with a 600 termination. In this mode, the DAA will transmit and receive +1.5 dBV into all reference impedances.
3. Receive full-scale level produces –0.9 dBFS at DTX.
4. DR = 20 x log (RMS VFS/RMS Vin) + 20 x log (RMS Vin/RMS noise). The RMS noise measurement excludes
harmonics. Here, VFS is the 0 dBm full-scale level per Note 1 above.
5. Measurement is 300 to 3400 Hz. Applies to both transmit and receive paths.
6. Vin =1 kHz, –3 dBFS.
7. THD = 20 x log (RMS distortion/RMS signal).
8. DRCID = 20 x log (RMS VCID/RMS VIN) + 20 x log (RMS VIN/RMS noise). VCID is the 1.5 V full-scale level with the
enhanced caller ID circuit. With the typical CID circuit, the VCID full-scale level is 6 V peak, and the DRCID decreases to
50 dB.
9. Refer to Tables 10–11 for relative gain accuracy characteristics (passband ripple).
10. Analog hybrid only. ZACIM controlled by ACIM in Register 30.
8
Rev. 1.5
Si3050 + Si3011/18/19
Table 4. AC Characteristics (Continued)
(VD = 3.0 to 3.6 V, TA = 0 to 70 °C, Fs = 8000 Hz, see "2. Typical Application Schematic" on page 17)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
DRCID
VIN =1 kHz, –13 dBFS
—
62
—
dB
—
1.5
—
VPEAK
2-W to DTX,
TXG2, RXG2, TXG3,
and RXG3 = 0000
–0.5
0
0.5
dB
300–3.4 kHz, ZACIM = ZLINE
20
—
—
dB
1 kHz, ZACIM = ZLINE
—
30
—
dB
Two-Wire Return Loss
300–3.4 kHz, all ac
terminations
25
—
—
dB
Two-Wire Return Loss
1 kHz, all ac terminations
—
32
—
dB
Dynamic Range (Caller ID mode)
8
Caller ID Full-Scale Level
8
VCID
Gain Accuracy6,9
Transhybrid Balance10
Transhybrid Balance
10
Notes:
1. Measured at TIP and RING with 600 termination at 1 kHz, as shown in Figure 1 on page 6.
2. With FULL = 1, the transmit and receive full-scale level of +3.2 dBm can be achieved with a 600 ac termination.
While the transmit and receive level in dBm varies with reference impedance, the DAA will transmit and receive 1 dBV
into all reference impedances. With FULL2 = 1, the transmit and receive full-scale level of +6.0 dBm can be achieved
with a 600 termination. In this mode, the DAA will transmit and receive +1.5 dBV into all reference impedances.
3. Receive full-scale level produces –0.9 dBFS at DTX.
4. DR = 20 x log (RMS VFS/RMS Vin) + 20 x log (RMS Vin/RMS noise). The RMS noise measurement excludes
harmonics. Here, VFS is the 0 dBm full-scale level per Note 1 above.
5. Measurement is 300 to 3400 Hz. Applies to both transmit and receive paths.
6. Vin =1 kHz, –3 dBFS.
7. THD = 20 x log (RMS distortion/RMS signal).
8. DRCID = 20 x log (RMS VCID/RMS VIN) + 20 x log (RMS VIN/RMS noise). VCID is the 1.5 V full-scale level with the
enhanced caller ID circuit. With the typical CID circuit, the VCID full-scale level is 6 V peak, and the DRCID decreases to
50 dB.
9. Refer to Tables 10–11 for relative gain accuracy characteristics (passband ripple).
10. Analog hybrid only. ZACIM controlled by ACIM in Register 30.
Table 5. Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
DC Supply Voltage
VD
–0.5 to 3.6
V
Input Current, Si3050 Digital Input Pins
IIN
±10
mA
VIND
–0.3 to (VD + 0.3)
V
TA
–40 to 100
°C
TSTG
–65 to 150
°C
Digital Input Voltage
Ambient Operating Temperature Range
Storage Temperature Range
Note: Permanent device damage can occur if the above Absolute Maximum Ratings are exceeded. Functional operation
should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute
maximum rating conditions for extended periods might affect device reliability.
Rev. 1.5
9
Si3050 + Si3011/18/19
Table 6. Switching Characteristics—General Inputs
(VD = 3.0 to 3.6 V, TA = 0 to 70 °C, CL = 20 pF)
Parameter1
Symbol
Min
Typ
Max
Unit
Cycle Time, PCLK
tp
0.12207
—
3.90625
s
PCLK Duty Cycle
tdty
40
50
60
%
PCLK Jitter Tolerance
tjitter
—
—
2
ns
tr
—
—
25
ns
tf
—
—
25
ns
tmr
10
—
—
cycles
trl
250
—
—
ns
tmxr
20
—
—
ns
tr
—
—
25
ns
Rise Time, PCLK
Fall Time, PCLK
2
PCLK Before RESET
RESET Pulse Width3
CS, SCLK Before RESET
Rise Time, Reset
Notes:
1. All timing (except Rise and Fall time) is referenced to the 50% level of the waveform. Input test levels are
VIH = VD – 0.4 V, VIL = 0.4 V. Rise and Fall times are referenced to the 20% and 80% levels of the waveform.
2. FSYNC/PCLK relationship must be fixed after RESET
3. The minimum RESET pulse width is the greater of 250 ns or 10 PCLK cycle times.
tr
tp
PC LK
V IH
V IL
tm r
RESET
t rl
C S, SC LK
tm xr
Figure 2. General Inputs Timing Diagram
10
tf
Rev. 1.5
Si3050 + Si3011/18/19
Table 7. Switching Characteristics—Serial Peripheral Interface
(VIO = 3.0 to 3.6 V, TA = 0 to 70 °C, CL = 20 pF)
Parameter*
Symbol
Test
Conditions
Min
Typ
Max
Unit
Cycle Time SCLK
tc
61.03
—
—
ns
Rise Time, SCLK
tr
—
—
25
ns
Fall Time, SCLK
tf
—
—
25
ns
Delay Time, SCLK Fall to SDO Active
td1
—
—
20
ns
Delay Time, SCLK Fall to SDO
Transition
td2
—
—
20
ns
Delay Time, CS Rise to SDO Tri-state
td3
—
—
20
ns
Setup Time, CS to SCLK Fall
tsu1
25
—
—
ns
Hold Time, SCLK to CS Rise
th1
20
—
—
ns
Setup Time, SDI to SCLK Rise
tsu2
25
—
—
ns
Hold Time, SCLK Rise to SDI Transition
th2
20
—
—
ns
Delay time between chip selects
tcs
220
—
—
ns
—
6
—
ns
Propagation Delay, SDI to SDITHRU
*Note: All timing (except Rise and Fall time) is referenced to the 50% level of the waveform. Input test levels are
VIH = VD – 0.4 V, VIL = 0.4 V. Rise and Fall times are referenced to the 20% and 80% levels of the waveform.
tr
SCLK
tf
tc
tsu1
CS
tsu2
th2
th1
tcs
SDI
SDO
td1
td2
td3
Figure 3. SPI Timing Diagram
Rev. 1.5
11
Si3050 + Si3011/18/19
Table 8. Switching Characteristics—PCM Highway Serial Interface
(VD = 3.0 to 3.6 V, TA = 0 to 70 °C, CL = 20 pF)
Parameter1
Test
Conditions
Symbol
Min
Typ
Max
Units
122
—
3906
ns
—
—
—
—
—
—
—
—
256
512
768
1.024
1.536
2.048
4.096
8.192
—
—
—
—
—
—
—
—
kHz
kHz
kHz
MHz
MHz
MHz
MHz
MHz
tfp
—
125
—
s
PCLK Duty Cycle
tdty
40
50
60
%
PCLK Jitter-Tolerance
tjitter
—
—
2
ns
FSYNC Jitter Tolerance
tjitter
—
—
±120
ns
tr
—
—
25
ns
Cycle Time PCLK
tp
Valid PCLK Inputs
FSYNC Period2
Rise Time, PCLK
tf
—
—
25
ns
td1
—
—
20
ns
td2
—
—
20
ns
Delay Time, PCLK Rise to DTX Tri-State
td3
—
—
20
ns
Fall Time, PCLK
Delay Time, PCLK Rise to DTX Active
Delay Time, PCLK Rise to DTX Transition
3
Setup Time, FSYNC Rise to PCLK Fall
tsu1
25
—
—
ns
Hold Time, PCLK Fall to FSYNC Fall
th1
20
—
—
ns
Setup Time, DRX Transition to PCLK Fall
tsu2
25
—
—
ns
Hold Time, PCLK Falling to DRX Transition
th2
20
—
—
ns
Notes:
1. All timing is referenced to the 50% level of the waveform. Input test levels are VIH = VO – 0.4 V, VIL = 0.4 V, rise and fall
times are referenced to the 20% and 80% levels of the waveform.
2. FSYNC must be 8 kHz under all operating conditions.
3. Specification applies to PCLK fall to DTX tri-state when that mode is selected.
tp
PCLK
th1
tsu1
t fp
FSYNC
tsu2
th2
DRX
td1
td2
td3
DTX
Figure 4. PCM Highway Interface Timing Diagram (RXS = TXS = 1)
12
Rev. 1.5
Si3050 + Si3011/18/19
Table 9. Switching Characteristics—GCI Highway Serial Interface
(VD = 3.0 to 3.6 V, TA = 0 to 70 °C, CL = 20 pF)
Parameter1
Symbol
Test
Conditions
Min
Typ
Max
Units
Cycle Time PCLK (Single Clocking Mode)
tp
—
488
—
ns
Cycle Time PCLK (Double Clocking Mode)
tp
—
244
—
ns
—
—
2.048
4.096
—
—
MHz
MHz
Valid PCLK Inputs
FSYNC Period2
tfp
—
125
—
µs
PCLK Duty Cycle
tdty
40
50
60
%
PCLK Jitter Tolerance
tjitter
—
—
2
ns
FSYNC Jitter Tolerance
tjitter
—
—
±120
ns
Rise Time, PCLK
tr
—
—
25
ns
Fall Time, PCLK
tf
—
—
25
ns
td1
—
—
20
ns
td2
—
—
20
ns
td3
—
—
20
ns
Setup Time, FSYNC Rise to PCLK Fall
tsu1
25
—
—
ns
Hold Time, PCLK Fall to FSYNC Fall
th1
20
—
—
ns
Setup Time, DRX Transition to PCLK Fall
tsu2
25
—
—
ns
Hold Time, PCLK Falling to DRX Transition
th2
20
—
—
ns
Delay Time, PCLK Rise to DTX Active
Delay Time, PCLK Rise to DTX Transition
Delay Time, PCLK Rise to DTX Tri-State
3
Notes:
1. All timing is referenced to the 50% level of the waveform. Input test levels are VIH = VO – 0.4 V, VIL = 0.4 V, rise and fall
times are referenced to the 20% and 80% levels of the waveform.
2. FSYNC must be 8 kHz under all operating conditions.
3. Specification applies to PCLK fall to DTX tri-state when that mode is selected.
tr
tp
tf
PCLK
th1
t su1
tfp
FSYNC
t su2
t
h2
DRX
t d1
t d2
t d3
DTX
Figure 5. GCI Highway Interface Timing Diagram (1x PCLK Mode)
Rev. 1.5
13
Si3050 + Si3011/18/19
tr
tf
PCLK
tfp
th1
tsu2
FSYNC
tsu2
th2
DRX
td2
td1
td3
DTX
Figure 6. GCI Highway Interface Timing Diagram (2x PCLK Mode)
Table 10. Digital FIR Filter Characteristics—Transmit and Receive
(VD = 3.0 to 3.6 V, Sample Rate = 8 kHz, TA = 0 to 70 °C)
Parameter
Symbol
Min
Typ
Max
Unit
Passband (0.1 dB)
F(0.1 dB)
0
—
3.3
kHz
F(3 dB)
0
—
3.6
kHz
–0.1
—
0.1
dB
—
4.4
—
kHz
–74
—
—
dB
—
12/Fs
—
s
Passband (3 dB)
Passband Ripple Peak-to-Peak
Stopband
Stopband Attenuation
Group Delay
tgd
Note: Typical FIR filter characteristics for Fs = 8000 Hz are shown in Figures 7, 8, 9, and 10.
Table 11. Digital IIR Filter Characteristics—Transmit and Receive
(VD = 3.0 to 3.6 V, Sample Rate = 8 kHz, TA = 0 to 70 °C)
Parameter
Passband (3 dB)
Symbol
Min
Typ
Max
Unit
F(3 dB)
0
—
3.6
kHz
–0.2
—
0.2
dB
—
4.4
—
kHz
–40
—
—
dB
—
1.6/Fs
—
s
Passband Ripple Peak-to-Peak
Stopband
Stopband Attenuation
Group Delay
tgd
Note: Typical IIR filter characteristics for Fs = 8000 Hz are shown in Figures 11, 12, 13, and 14. Figures 15 and 16 show
group delay versus input frequency.
14
Rev. 1.5
Si3050 + Si3011/18/19
Figure 7. FIR Receive Filter Response
Figure 9. FIR Transmit Filter Response
Figure 8. FIR Receive Filter Passband Ripple
Figure 10. FIR Transmit Filter Passband Ripple
For Figures 7–10, all filter plots apply to a sample rate of
Fs = 8 kHz.
For Figures 11–14, all filter plots apply to a sample rate of
Fs = 8 kHz.
Rev. 1.5
15
Si3050 + Si3011/18/19
Figure 11. IIR Receive Filter Response
Figure 14. IIR Transmit Filter Passband Ripple
Figure 12. IIR Receive Filter Passband Ripple
Figure 15. IIR Receive Group Delay
Figure 13. IIR Transmit Filter Response
Figure 16. IIR Transmit Group Delay
16
Rev. 1.5
Ground Start
PCM Highway
SPI Control
Rev. 1.5
R53
1
2
3
4
5
6
7
8
9
10
U1
C50
Si3050
SDO
SDI_THRU
SDI
SCLK
CS
GND
FSYNC
VDD
PCLK
VA
DTX
C1A
DRX
C2A
RGDT
RST
AOUT/INT
TGDE
RG
TGD
R302
20
19
18
17
16
15
14
13
12
11
C51
R13
R12
C2
C1
R9
C4
C5
+
R1
ISOLATION Barrier
1
2
3
4
5
6
7
8
Si3019
QE
DCT2
DCT
IGND
RX
DCT3
IB
QB
C1B
QE2
C2B
SC
VREG VREG2
RNG1 RNG2
U2
16
15
14
13
12
11
10
9
R32
IGND
C31
R11
R31
R7
R30
C30
Optional CID Population
R8
C6
R2
R33
R3
R10
Q5
-
Q4
C3
R4
D1
+
C7
R5
No Ground Plane In DAA Section
FB1
FB2
Z1
Q1
C9
Q3
Q2
C8
R6
C10
Figure 17. Typical Application Circuit for the Si3050 (TSSOP) and Si3011/18/19 (SOIC/TSSOP)
(Refer to “AN67: Si3050/52/54/56 Layout Guidelines” for Recommended Layout Guidelines)
/RG
/TGD
/TGDE
/RGDT
/INT
/RESET
FSYNC
PCLK
DTX
DRX
SDO
SDI
/CS
SCLK
SDITHRU
R52
VDD
FB204
FB203
RV1
TIP
RING
Si3050 + Si3011/18/19
2. Typical Application Schematic
17
Ground Start
PCM Highway
SPI Control
/RG
/TGD
/TGDE
/RGDT
/INT
/RESET
FSYNC
PCLK
DTX
DRX
SDO
SDI
/CS
SCLK
SDITHRU
NI
Rev. 1.5
22
23
24
1
2
3
4
5
6
7
8
9
U203
Si3050FM
21
20
19
18
17
16
15
14
13
12
11
10
C50
0.1uF
NC
NC
SDO
SDI_THRU
SDI
SCLK
CS
GND
FSYNC
VDD
PCLK
VA
DTX
C1A
DRX
C2A
RGDT
RST
AOUT/INT
TGDE
RG
TGD
NC
NC
0
2A
C51
0.1uF
16V
R13
R12
56.2
1/16W
56.2
1/16W
C2
C1
33pF
Y2
33pF
Y2
C5
1M
1/16W
0.1uF
16V
1/2W
50V
R9
1.07K
R1
C4
1uF
ISOLATION Barrier
19
20
1
2
3
4
5
6
7
8
47K
U2
Si3019FM
18
17
16
15
14
13
12
11
10
9
R32
NI
120pF
C31
20M
R8
1/4W
250V
15M
150V
IGND
MMBTA06LT1
1/16W
536
5.1M
150V
R31
NI
250V
150V
15M
R30
120pF
C30
20M
R7
Optional CID Population
5.1M
150V
R33
0.1uF
16V
C6
150
R2
1/2W
3.65K
R3
R10
No Ground Plane In DAA Area
QE
DCT2
DCT
IGND
NC
NC
RX
DCT3
IB
QB
C1B
QE2
C2B
SC
VREG
NC
RNG1 VREG2
IGND RNG2
EPAD
47K
Q5
1/2W
73.2
R11
D1
HD04
400V
-
Q4
C3
R4
+
3.9nF
250V
2.49K
1/2W
MMBTA06LT1
1/16W
100K
680pF
Y2
680pF
Y2
600 Ohm
FB204
600 Ohm
FB203
Q3
MMBTA42LT1
R6
0.01uF
MMBTA92LT1
C10
C8
43V
Z1
Q2
MMBTA42LT1
C9
600 Ohm
FB1
600 Ohm
FB2
2.7nF
50V
C7
1/16W
100K
R5
Q1
Figure 18. Typical Application Circuit for the Si3050 (QFN) and Si3011/18/19 (QFN)
(Refer to “AN67: Si3050/52/54/56 Layout Guidelines” for Recommended Layout Guidelines)
R52
NI
R53
R302
EPAD
EPAD
18
IGND
VDD
RV1
TIP
P3100SB
RING
Si3050 + Si3011/18/19
Si3050 + Si3011/18/19
3. Bill of Materials
Component
Value
Supplier(s)
C1, C2
33 pF, Y2, X7R, ±20%
Panasonic, Murata, Vishay
3.9 nF, 250 V, X7R, ±20%
Venkel, SMEC
C4
1.0 µF, 50 V, Elec/Tant, ±20%
Panasonic
C5, C6, C50, C51
0.1 µF, 16 V, X7R, ±20%
Venkel, SMEC
C7
2.7 nF, 50 V, X7R, ±20%
Venkel, SMEC
C8, C9
680 pF, Y2, X7R, ±10%
Panasonic, Murata, Vishay
0.01 µF, 16 V, X7R, ±20%
Venkel, SMEC
120 pF, 250 V, X7R, ±10%
Venkel, SMEC
Dual Diode, 225 mA, 300 V, (MMBD3004S)
Diodes Inc.
FB1, FB2, FB203, FB204
Ferrite Bead, BLM18AG601SN1
Murata
Q1, Q3
NPN, 300 V, MMBTA42
OnSemi, Fairchild, Diodes Inc.
Q2
PNP, 300 V, MMBTA92
OnSemi, Fairchild, Diodes Inc.
Q4, Q5
NPN, 80 V, 330 mW, MMBTA06
Central OnSemi, Fairchild
RV1
Sidactor, 275 V, 100 A
Teccor, Diodes Inc., Shindengen
R1
1.07 k, 1/2 W, 1%
Venkel, SMEC, Panasonic
R2
150 , 1/16 W, 5%
Venkel, SMEC, Panasonic
R3
3.65 k, 1/2 W, 1%
Venkel, SMEC, Panasonic
R4
2.49 k, 1/2 W, 1%
Venkel, SMEC, Panasonic
R5, R6
100 k, 1/16 W, 5%
Venkel, SMEC, Panasonic
Not Installed, 20 M, 1/8 W, 5%
Venkel, SMEC, Panasonic
R9
1 M, 1/16 W, 1%
Venkel, SMEC, Panasonic
R10
536 , 1/4 W, 1%
Venkel, SMEC, Panasonic
R11
73.2 , 1/2 W, 1%
Venkel, SMEC, Panasonic
C3
1
C10
1
C30, C31
D1,
R7,
D22
R81
R12, R13
56.2 , 1/16 W, 1%
Venkel, SMEC, Panasonic
1
15 M, 1/8 W, 5%
Venkel, SMEC, Panasonic
R331
5.1 M, 1/8 W, 5%
Venkel, SMEC, Panasonic
R52, R53
4.7 k, 1/16 W, 5%
Venkel, SMEC, Panasonic
U1
Si3050
Silicon Labs
U2
Si3011/8/19
Silicon Labs
Z1
Zener Diode, 43 V, 1/2 W
General Semi, On Semi, Diodes Inc.
R30, R32
R31,
Notes:
1. R7–R8 may be substituted for R30–R33 and C30–C31 for lower cost, but reduced CID performance.
2. Several diode bridge configurations are acceptable. Parts, such as a single HD04, a DF-04S, or four 1N4004 diodes,
may be used (suppliers include General Semiconductor, Diodes Inc., etc.).
Rev. 1.5
19
Si3050 + Si3011/18/19
4. AOUT PWM Output
Table 12. Component Values—AOUT PWM
Figure 19 illustrates an optional circuit to support the
pulse width modulation (PWM) output capability of the
Si3050 for call progress monitoring purposes. To enable
this mode, the INTE bit (Register 2) should be set to 0,
the PWME bit (Register 1) set to 1, and the PWMM bits
(Register 2) set to 00.
Component
Value
Supplier
LS1
Speaker BRT1209PF-06
Intervox
Q6
NPN KSP13
Fairchild
C41
R41
+5VA
LS1
R41
150 1/10 W, ±5%
Venkel, SMEC,
Panasonic
Registers 20 and 21 allow the receive and transmit
paths to be attenuated linearly. When these registers
are set to all 0s, the transmit and receive paths are
muted. These registers affect the call progress output
only and do not affect transmit and receive operations
on the telephone line.
Q6
AOUT
C41
Figure 19. AOUT PWM Circuit for Call Progress
20
0.1 µF, 16 V, X7R, ±20% Venkel, SMEC
The PWMM[1:0] bits (Register 1, bits 5:4) select one of
three different PWM output modes for the AOUT signal,
including a delta-sigma data stream, a 32 kHz return to
0 PWM output, and a balanced 32 kHz PWM output.
Rev. 1.5
Si3050 + Si3011/18/19
5. Functional Description
Si3050
CS
SCLK
SDI
SDO
SDI THRU
PCLK
DTX
DRX
Si3018/19
RX
Control
Data
Interface
Line
Data
Interface
Hybrid, AC
and DC
Terminations
Isolation
Interface
Isolation
Interface
FSYNC
RGDT
RG
TGD
TGDE
RESET
AOUT/INT
Ring Detect
Off-Hook
Control
Logic
IB
SC
DCT
VREG
VREG2
DCT2
DCT3
RNG1
RNG2
QB
QE
QE2
Figure 20. Si3050 + Si3011/18/19 Functional Block Diagram
The Si3050 is an integrated direct access arrangement
(DAA) providing a programmable line interface that
meets global telephone line requirements. The Si3050
implements Silicon Laboratories’ patented isolation
capacitor technology, which offers the highest level of
integration by replacing an analog front end (AFE), an
isolation transformer, relays, opto-isolators, and a 2- to
4-wire hybrid with two highly-integrated ICs.
The Si3050 DAA is fully software programmable to meet
global requirements and is compliant with FCC, TBR21,
JATE, and other country-specific PTT specifications as
shown in Table 13. In addition, the Si3050 meets the
most stringent global requirements for out-of-band
energy, emissions, immunity, high-voltage surges, and
safety, including FCC Parts 15 and 68, EN55022,
EN55024, and many other standards.
5.1. Line-Side Device Support
5.1.1. Si3011
TBR-21 and FCC-compliant line-side device.
Selectable
dc terminations.
selectable ac terminations to increase return loss
and trans-hybrid loss performance.
+6 dBm TX/RX level mode (600 )
Two
5.1.2. Si3018
Globally-compliant line-side device—targets global
DAA requirements for voice applications. This
line-side device supports both FCC-compliant
countries and non-FCC-compliant countries.
Selectable
dc terminations.
selectable ac terminations to increase return loss
and trans-hybrid loss performance.
+6 dBm TX/RX level mode (600 )
Four
5.1.3. Si3019
Three different line-side devices are available for use
with the Si3050 system-side device. The Si3011
line-side device only supports DC terminations
compliant with TBR21 and FCC-compliant countries.
The Si3018 and Si3019 line-side devices are globally
compliant, have a selectable 5 Hz or 200 Hz RX
high-pass filter pole, and offer a –16.5 to 13.5 dB digital
gain/attenuation adjustment in 0.1dB increments for the
transmit and receive paths.
Rev. 1.5
Globally-compliant, enhanced features line-side
device—targets global DAA requirements for voice
applications.
Selectable
dc terminations
selectable ac terminations to further increase
return loss and trans-hybrid loss performance.
Line voltage monitoring in on- and off-hook modes to
enable line in-use/parallel handset detection.
Programmable line current / voltage threshold interrupt.
Polarity reversal interrupt.
+3.2 dBm TX/RX level mode (600 )
+6 dBm TX/RX level mode (600 )
Higher resolution (1.1 mA/bit) loop current
measurement.
Sixteen
21
Si3050 + Si3011/18/19
Table 13. Country-specific Register Settings
Register
16
31
16
16
26
26
26
Country
OHS
OHS2
RZ
RT
ILIM
Argentina
0
0
0
0
0
11
00
0000
Australia1
1
0
0
0
0
01
01
0011
Austria
0
1
0
0
1
11
00
0010
Bahrain
0
1
0
0
1
11
00
0010
Belgium
0
1
0
0
1
11
00
0010
Brazil
0
0
0
0
0
11
00
0001
Bulgaria
0
1
0
0
1
11
00
0011
Canada
0
0
0
0
0
11
00
0000
Chile
0
0
0
0
0
11
00
0000
China
0
0
0
0
0
11
00
1010
Colombia
0
0
0
0
0
11
00
0000
Croatia
0
1
0
0
1
11
00
0010
Cyprus
0
1
0
0
1
11
00
0010
Czech Republic
0
1
0
0
1
11
00
0010
Denmark
0
1
0
0
1
11
00
0010
Ecuador
0
0
0
0
0
11
00
0000
Egypt
0
1
0
0
1
11
00
0010
El Salvador
0
0
0
0
0
11
00
0000
Finland
0
1
0
0
1
11
00
0010
France
0
1
0
0
1
11
00
0010
Germany
0
1
0
0
1
11
00
0010
Greece
0
1
0
0
1
11
00
0010
Guam
0
0
0
0
0
11
00
0000
Hong Kong
0
0
0
0
0
11
00
0000
Hungary
0
1
0
0
1
11
00
0010
Iceland
0
1
0
0
1
11
00
0010
India
0
0
0
0
0
11
00
0000
Indonesia
0
0
0
0
0
11
00
0000
DCV[1:0] MINI[1:0]
30
ACIM[3:0]
Note:
1. See "5.16. DC Termination" on page 31 for DCV and MINI settings.
2. Supported for loop current 20 mA.
3. TBR21 includes the following countries: Austria, Belgium, Denmark, Finland, France, Germany, Greece,
Iceland, Ireland, Italy, Luxembourg, Netherlands, Norway, Portugal, Spain, Sweden, Switzerland, and the
United Kingdom.
22
Rev. 1.5
Si3050 + Si3011/18/19
Table 13. Country-specific Register Settings (Continued)
Register
16
31
16
16
26
Country
OHS
OHS2
RZ
RT
ILIM
Ireland
0
1
0
0
1
11
00
0010
Israel
0
1
0
0
1
11
00
0010
Italy
0
1
0
0
1
11
00
0010
Japan
0
0
0
0
0
10
01
0000
Jordan
0
0
0
0
0
01
01
0000
Kazakhstan
0
0
0
0
0
11
00
0000
Kuwait
0
0
0
0
0
11
00
0000
Latvia
0
1
0
0
1
11
00
0010
Lebanon
0
1
0
0
1
11
00
0010
Luxembourg
0
1
0
0
1
11
00
0010
Macao
0
0
0
0
0
11
00
0000
0
0
0
0
0
01
01
0000
Malta
0
1
0
0
1
11
00
0010
Mexico
0
0
0
0
0
11
00
0000
Morocco
0
1
0
0
1
11
00
0010
Netherlands
0
1
0
0
1
11
00
0010
New Zealand
0
0
0
0
0
11
00
0100
Nigeria
0
1
0
0
1
11
00
0010
Norway
0
1
0
0
1
11
00
0010
Oman
0
0
0
0
0
01
01
0000
Pakistan
0
0
0
0
0
01
01
0000
Peru
0
0
0
0
0
11
00
0000
Philippines
0
0
0
0
0
01
01
0000
Poland
0
1
0
0
1
11
00
0010
Portugal
0
1
0
0
1
11
00
0010
Romania
0
1
0
0
1
11
00
0010
Russia
0
0
0
0
0
11
00
0000
Saudi Arabia
0
0
0
0
0
11
00
0000
Singapore
0
0
0
0
0
11
00
0000
Malaysia
2
26
26
DCV[1:0] MINI[1:0]
30
ACIM[3:0]
Note:
1. See "5.16. DC Termination" on page 31 for DCV and MINI settings.
2. Supported for loop current 20 mA.
3. TBR21 includes the following countries: Austria, Belgium, Denmark, Finland, France, Germany, Greece,
Iceland, Ireland, Italy, Luxembourg, Netherlands, Norway, Portugal, Spain, Sweden, Switzerland, and the
United Kingdom.
Rev. 1.5
23
Si3050 + Si3011/18/19
Table 13. Country-specific Register Settings (Continued)
Register
16
31
16
16
26
26
26
Country
OHS
OHS2
RZ
RT
ILIM
Slovakia
0
1
0
0
1
11
00
0010
Slovenia
0
1
0
0
1
11
00
0010
South Africa
0
0
1
0
0
11
00
0011
South Korea
0
0
1
0
0
11
00
0000
Spain
0
1
0
0
1
11
00
0010
Sweden
0
1
0
0
1
11
00
0010
Switzerland
0
1
0
0
1
11
00
0010
Taiwan
0
0
0
0
0
11
00
0000
TBR213
0
0
0
0
1
11
00
0010
Thailand
0
0
0
0
0
01
01
0000
UAE
0
0
0
0
0
11
00
0000
United Kingdom
0
1
0
0
1
11
00
0101
USA
0
0
0
0
0
11
00
0000
Yemen
0
0
0
0
0
11
00
0000
DCV[1:0] MINI[1:0]
30
ACIM[3:0]
Note:
1. See "5.16. DC Termination" on page 31 for DCV and MINI settings.
2. Supported for loop current 20 mA.
3. TBR21 includes the following countries: Austria, Belgium, Denmark, Finland, France, Germany, Greece,
Iceland, Ireland, Italy, Luxembourg, Netherlands, Norway, Portugal, Spain, Sweden, Switzerland, and the
United Kingdom.
24
Rev. 1.5
Si3050 + Si3011/18/19
5.2. Power Supplies
The Si3050 operates from a 3.3 V power supply. The
Si3050 input pins require 3.3 V CMOS signal levels. If
support of 5 V signal levels is necessary, a level shifter
is required. The Si3011/18/19 derives its power from
two sources: the Si3050 and the telephone line. The
Si3050 supplies power over the patented isolation
capacitor link between the two devices, allowing the
line-side device to communicate with the Si3050 while
on-hook, and perform other on-hook functions such as
line voltage monitoring. When off-hook, the line-side
device also derives power from the line current supplied
from the telephone line. This feature is exclusive to
DAAs from Silicon Labs and allows the most
cost-effective implementation for a DAA while still
maintaining robust performance over all line conditions.
5.3. Initialization
Each time the Si3050 is powered up, assert the RESET
pin. When the RESET pin is deasserted, the registers
have default values to guarantee the line-side device
(Si3011/18/19) is powered down without the possibility
of loading the line (i.e., off-hook). An example
initialization procedure follows:
1. Power up and de-assert RESET.
2. Wait until the PLL is locked. This time is less than
1 ms from the application of PCLK.
3. Enable PCM (Register 33) or GCI (Register 42)
mode.
4. Set the desired line interface parameters (i.e.,
DCV[1:0], MINI[1:0], ILIM, DCR, ACIM[3:0], OHS,
RT, RZ, TGA2, and TXG2[3:0]) shown in Table 13 on
page 22.
5. Set the FULL (or FULL2) + IIRE bits as required.
6. Write a 0x00 into Register 6 to power up the
line-side device (Si3011/18/19).
The communications link is disabled by default. To
enable it, the PDL bit (Register 6, bit 4) must be
cleared. No communication between the Si3050 and
Si3018/19 can occur until this bit is cleared. Allow the
PLL to lock to the PCLK and FSYNC input signals
before clearing the PDL bit.
5.5. Power Management
The Si3050 supports four basic power management
operation modes. The modes are normal operation,
reset operation, sleep mode, and full powerdown mode.
The power management modes are controlled by the
PDN and PDL bits (Register 6).
On powerup, or following a reset, the Si3050 is in reset
operation. The PDL bit is set, and the PDN bit is
cleared. The Si3050 is operational, except for the
communications link. No communication between the
Si3050 and line-side device (Si3011/18/19) can occur
during reset operation. Bits associated with the line-side
device are invalid in this mode.
In typical applications, the DAA will predominantly be
operated in normal mode. In normal mode, the PDL and
PDN bits are cleared. The DAA is operational and the
communications link passes information between the
Si3050 and the Si3011/18/19.
The Si3050 supports a low-power sleep mode that
supports ring validation and wake-up-on-ring features.
To enable the sleep mode, the PDN bit must be set.
When the Si3050 is in sleep mode, the PCLK signal
must remain active. In low-power sleep mode, the
Si3050 is non-functional except for the communications
link and the RGDT signal. To take the Si3050 out of
sleep mode, pulse the reset pin (RESET) low.
In summary, the powerdown/up sequence for sleep
mode is as follows:
1. Ensure the PDL bit (Register 6, bit 4) is cleared.
When this procedure is complete, the Si3011/18/19 is
ready for ring detection and off-hook operation.
5.4. Isolation Barrier
The Si3050 achieves an isolation barrier through
low-cost, high-voltage capacitors in conjunction with
Silicon Laboratories’ patented signal processing
techniques. Differential capacitive communication
eliminates
signal
degradation
from
capacitor
mismatches, common mode interference, or noise
coupling. As shown in the "2. Typical Application
Schematic" on page 17, the C1, C2, C8, and C9
capacitors isolate the Si3050 (system-side) from the
Si3011/18/19 (line-side). Transmit, receive, control, ring
detect, and caller ID data are passed across this barrier.
2. Set the PDN bit (Register 6, bit 3).
3. The device is now in sleep mode. PCLK must remain
active.
4. To exit sleep mode, reset the Si3050 by pulsing the
RESET pin.
5. Program registers to desired settings.
The Si3050 also supports an additional Powerdown
mode. When both the PDN (Register 6, bit 3) and PDL
(Register 6, bit 4) bits are set, the chipset enters a
complete powerdown mode and draws negligible
current (deep sleep mode). In this mode, the Si3050 is
non-functional. The RGDT pin does not function and the
Si3050 will not detect a ring. Normal operation can be
restored using the same process for taking the Si3050
out of sleep mode.
Rev. 1.5
25
Si3050 + Si3011/18/19
5.6. Calibration
The Si3050 initiates two auto-calibrations by default
when the device goes off-hook or experiences a loss of
line power. A 17 ms resistor calibration is performed to
allow circuitry internal to the DAA to adjust to the exact
line conditions present at the time of going off-hook.
This resistor calibration can be disabled by setting the
RCALD bit (Register 25, bit 5). A 256 ms ADC
calibration is also performed to remove offsets that
might be present in the on-chip A/D converter, which
could affect the A/D dynamic range. The ADC
auto-calibration is initiated after the DAA dc termination
stabilizes and the resistor calibration completes. Due to
the large variation in line conditions and line card
behavior presented to the DAA, it might be beneficial to
use manual ADC calibration instead of auto-calibration.
Manual ADC calibration should be executed as close as
possible to 256 ms before valid transmit/receive data is
expected.
The following steps should be taken to implement
manual ADC calibration:
1. The CALD bit (auto-calibration disable—Register 17)
must be set to 1.
2. The MCAL bit (manual calibration) must be toggled
to one and then 0 to begin and complete the
calibration.
3. The calibration is completed in 256 ms.
5.7. In-Circuit Testing
The Si3050’s advanced design provides the designer
with an increased ability to determine system
functionality during production line tests and support for
end-user diagnostics. Six loopback modes allow
increased coverage of system components. For four of
the test modes, a line-side power source is needed.
While a standard phone line can be used, the test circuit
in Figure 1 on page 6 is adequate. In addition, an
off-hook sequence must be performed to connect the
power source to the line-side device.
For the start-up loopback test mode, no line-side power
is necessary, and no off-hook sequence is required. The
start-up test mode is enabled by default. When the PDL
bit (Register 6, bit 4) is set (the default case), the line
side is in a powerdown mode, and the system-side is in
a digital loopback mode. In this mode, data received on
DRX passes through the internal filters and is
transmitted on DTX. This path introduces approximately
0.9 dB of attenuation on the DRX signal received. The
group delay of both transmit and receive filters exists
between DRX and DTX. Clearing the PDL bit disables
this mode, and the DTX data switches to the receive
data from the line side. When the PDL bit is cleared, the
26
FDT bit (Register 12, bit 6) becomes active to indicate
that successful communication between the line side
and system side is established. This provides
verification that the communications link is operational.
The digital data loop-back mode offers a way to input
data on the DRX pin and have the identical data output
on the DTX pin through bypassing the transmit and
receive filters. Setting the DDL bit (Register 10, bit 0)
enables this mode, which provides an easy way to verify
communication between the host processor/DSP and
the DAA. No line-side power or off-hook sequence is
required for this mode.
The remaining test modes require an off-hook sequence
to operate. The following sequence lists the off-hook
requirements:
1. Powerup or reset.
2. Allow the internal PLL to lock on PCLK and FSYNC.
3. Enable line-side by clearing PDL bit.
4. Issue an off-hook command.
5. Delay 402.75 ms for calibration to occur.
6. Set desired test mode.
The communications link digital loopback mode allows
the host processor to provide a digital input test pattern
on DRX and receive that digital test pattern back on
DTX. To enable this mode, set the IDL bit (Register 1,
bit 1). The communications link is tested in this mode.
The digital stream is delivered across the isolation
capacitors, C1 and C2, of the "2. Typical Application
Schematic" on page 17, to the line-side device and
returned across the same path. In this digital loopback
mode, the 0.9 dB attenuation and filter group delays
also exist.
The PCM analog loopback mode extends the signal
path of the analog loopback mode. In this mode, an
analog signal is driven from the line into the line-side
device. This analog signal is converted to digital data
and then passed across the communications link to the
system-side device. The data passes through the
receive filter, through the transmit filter, and is then
passed across the communications link and sent back
out onto the line as an analog signal. Set the PCML bit
(Register 33, bit 7) to enable this mode.
With the final testing mode, internal analog loopback,
the system can test the operation of the transmit and
receive paths on the line-side device and the external
components in the "2. Typical Application Schematic"
on page 17. The host provides a digital test waveform
on DRX. Data passes across the isolation barrier, is
transmitted to and received from the line, passes back
across the isolation barrier, and is presented to the host
on DTX. Clear the HBE bit (Register 2, bit 1) to enable
this mode.
Rev. 1.5
Si3050 + Si3011/18/19
When the HBE bit is cleared, it produces a dc offset that
affects the signal swing of the transmit signal. Silicon
Laboratories recommends that the transmit signal be
12 dB lower than normal transmit levels. A lower level
eliminates clipping from the dc offset that results from
disabling the hybrid. It is assumed in this test that the
line ac impedance is nominally 600
Note: All test modes are mutually exclusive. If more than one
test mode is enabled concurrently, the results are
unpredictable.
mode (or 2x full scale) is enabled by setting the FULL2
bit in Register 30. With FULL2 = 1, the full-scale signal
level increases to +6.0 dBm into a 600 load or
1.5 dBV into all reference impedances. The full-scale
and enhanced full-scale modes provide the ability to
trade off TX power and TX distortion for a peak signal.
By using the programmable digital gain registers in
conjunction with the enhanced full-scale signal level
mode, a specific power level (+3.2 dBm for example)
can be achieved across all ACT settings.
5.8. Exception Handling
5.11. Parallel Handset Detection
The Si3050 can determine if an error occurs during
operation. Through the secondary frames of the serial
link, the controlling DSP can read several status bits.
The bit of highest importance is the frame detect bit
(FDT, Register 12, bit 6) which indicates that the
system-side (Si3050) and line-side (Si3011, 3018 or
Si3019) devices are communicating. During normal
operation, the FDT bit can be checked before reading
the bits that indicate information about the line side. If
FDT is not set, the following bits related to the line side
are invalid—RDT, RDTN, RDTP, LCS[4:0], LSID[1:0],
REVB[3:0], LVS[7:0], LCS2[7:0], ROV, BTD, DOD, and
OVL; the RGDT operation is also non-functional.
The Si3050 can detect a parallel handset going
off-hook. When the Si3050 is off-hook, the loop current
can be monitored with the LCS or LCS2 bits. A
significant drop in loop current signals a parallel handset
going off-hook. If a parallel handset going off-hook
causes the loop current to drop to 0, the LCS and LCS2
bits will read all 0s. Additionally, the Drop-Out Detect
(DOD) bit will fire (and generate an interrupt if the
DODM bit is set) indicating that the line-derived power
supply has collapsed.
Following powerup and reset, the FDT bit is not set
because the PDL bit (Register 6 bit 4) defaults to 1. In
this state, the ISOcap is not operating and no
information about the line side can be determined. The
user must provide a valid PCLK and FSYNC to the
system and clear the PDL bit to activate the ISOcap
link. Communication with the line-side device takes less
than 10 ms to establish.
5.9. Revision Identification
The Si3050 provides information to determine the
revision of the Si3050 and/or the Si3011/18/19. The
REVA[3:0] bits (Register 11) identify the revision of the
Si3050, where 0101b denotes revision E. The
REVB[3:0] bits (Register 13) identify the revision of the
line-side device, where 0110b denotes revision F.
5.10. Transmit/Receive Full-Scale Level
The Si3050 supports programmable maximum transmit
and receive levels. The default signal level supported by
the Si3050 is 0 dBm into a 600 load. Two additional
modes of operation offer increased transmit and receive
level capability to enable use of the DAA in applications
that require higher signal levels. The full-scale mode is
enabled by setting the FULL bit in Register 31. With
FULL = 1 (Si3019 only), the full-scale signal level
increases to +3.2 dBm into a 600 load or 1 dBV into
all reference impedances. The enhanced full-scale
With the Si3019 line side, the LVS bits also can be read
when on- or off-hook to determine the line voltage.
Significant drops in line voltage can signal a parallel
handset. For the Si3050 to operate in parallel with
another handset, the parallel handset must have a
sufficiently high dc termination to support two off-hook
DAAs on the same line. Improved parallel handset
operation can be achieved by changing the dc
impedance from 50 to 800 and reducing the DCT
pin voltage with the DCV[1:0] bits.
5.12. Line Voltage/Loop Current Sensing
The Si3050 can measure loop current with either the
Si3011, Si3018 or the Si3019 line-side device. The 5-bit
LCS[4:0] register reports loop current measurements
when off-hook. The Si3011 and Si3019 offer an
additional register to report loop current to a finer
resolution (LCS2[7:0]). The Si3050 can only measure
line voltage when used with the Si3011 and Si3019
line-side devices. The LVS[7:0] register is available with
the Si3011 or Si3019, and monitors voltage both on and
off-hook. These registers can be used to help determine
the following line conditions:
When on-hook, detect if a line is connected.
When on-hook, detect if a parallel phone is off-hook.
When off-hook, detect if a parallel phone goes on or
off-hook.
Detect if enough loop current is available to operate.
When used in conjunction with the OPD bit, detect if
an overload condition exists. (See "5.26. Overload
Detection" on page 37.)
Rev. 1.5
27
Si3050 + Si3011/18/19
5.12.1. Line Voltage Measurement
(Si3011 and Si3019 Line Side Devices Only)
The Si3050 reports line voltage with the LVS[7:0] bits
(Register 29) in both on- and off-hook states with a
resolution of 1 V per bit. The accuracy of these bits is
approximately ±10%. Bits 0 through 7 of this 8-bit
signed number indicate the value of the line voltage in
2s complement format. Bit 7 indicates the polarity of the
TIP/RING voltage.
If the INTE bit (Register 2, bit 7) and the POLM bit
(Register 3, bit 0) are set, a hardware interrupt is
generated on the AOUT/INT pin when Bit 7 of the LVS
register changes state. The edge-triggered interrupt is
cleared by writing 0 to the POLI bit (Register 4, bit 0).
The POLI bit is set each time bit 7 of the LVS register
changes state, and must be written to 0 to clear it. The
default state of the LVS register forces the LVS[7:0] bits
to 0 when the line voltage is 3 V or less. The LVFD bit
(Register 31, bit 0) disables this force-to-zero function
and allows the LVS register to display non-zero values
of 3 V and below. This register may display
unpredictable values at line voltages between 0 to 2 V.
At 0 V, the LVS register displays all 0s.
Possible Overload
30
25
20
LCS
BITS
15
10
5
0
0
3.3
6.6
9.9 13.2 16.5 19.8 23.1 26.4 29.7
33
36.3 39.6 42.9 46.2 49.5 52.8 56.1 59.1 62.7 66
Loop Current (mA)
69.3 72.6 75.9 79.2 82.5 85.8 89.1 92.4 95.7 99 102.3
Figure 21. Typical Loop Current LCS Transfer Function (ILIM = 0)
28
Rev. 1.5
127
Si3050 + Si3011/18/19
5.12.2. Loop Current Measurement
When the Si3050 is off-hook, the LCS[4:0] bits measure
loop current in 3.3 mA/bit resolution. With the LCS[4:0]
bits, a user can detect another phone going off-hook by
monitoring the dc loop current. The line current sense
transfer function is shown in Figure 21 and is detailed in
Table 14. The LCS and LCS2 bits report loop current
down to the minimum operating loop current for the
DAA. Below this threshold, the reported value of loop
current is unpredictable. The minimum operating loop
current of the DAA is set by the MINI[1:0] bits in
Register 26.
When the LCS bits reach max value, the Loop Current
Sense Overload Interrupt bit (Register 4) fires. LCSOI
firing however, does not necessarily imply that an
overcurrent situation has occurred. An overcurrent
situation in the DAA is determined by the status of the
OPD bit (Register 19). After the LCSOI interrupt fires,
the OPD bit should be checked to determine if an
overcurrent situation exists. The OPD bit indicates an
overcurrent situation when loop current exceeds either
160 mA (ILIM = 0) or 60 mA (ILIM = 1), depending on
the setting of the ILIM bit (Register 26).
Table 14. Loop Current Transfer Function
LCS[4:0]
Condition
00000
Insufficient line current for normal operation.
Use the DOD bit (Register 19, bit 1) to
determine if a line is still connected.
00100
Minimum line current for normal operation.
(MINI[1:0] = 01)
11111
Loop current may be excessive. Use the
OPD bit to determine if an overload condition exists.
The LCS2 register also reports loop current in the
off-hook state. This register has a resolution of 1.1 mA
per bit.
5.13. Off-Hook
The communication system generates an off-hook
command by setting the OH bit (Register 5, bit 0). This
off-hook state seizes the line for incoming/outgoing
calls. It also can be used for pulse dialing.
With the OH bit at logic 0, negligible dc current flows
through the hookswitch. When a logic 1 is written to the
OH bit, the hookswitch transistor pair, Q1 and Q2, turn
on. A termination impedance across TIP and RING is
applied and causes dc loop current to flow. The
termination impedance has both an ac and a dc
component.
Several events occur in the DAA when the OH bit is set.
There is a 250 µs latency for the off-hook command to
be communicated to the line-side device. When the
line-side device goes off-hook, an off-hook counter
forces a delay to allow line transients to settle before
transmission or reception can occur. The off-hook
counter time is controlled by the FOH[1:0] bits
(Register 31, bits 6:5). The default setting for the
off-hook counter time is 128 ms, but can be adjusted up
to 512 ms or down to 64 or 8 ms.
After the off-hook counter expires, a resistor calibration
is performed for 17 ms to allow the DAA internal
circuitry to adjust to the exact conditions present at the
time of going off-hook. This resistor calibration can be
disabled by setting the RCALD bit (Register 25, bit 5).
After the resistor calibration is performed, an ADC
calibration is performed for 256 ms. This calibration
helps to remove offset in the A/D sampling the
telephone line. ADC calibration can be disabled by
setting the CALD bit (Register 17, bit 5). See "5.6.
Calibration" on page 26 for more information on
automatic and manual calibration.
Silicon Laboratories recommends that the resistor and
the ADC calibrations not be disabled except when a fast
response is needed after going off-hook, such as when
responding to a Type II Caller-ID signal. See "5.25.
Caller ID" on page 36 for detailed information.
To calculate the total time required to go off-hook and
start transmission or reception, include the digital filter
delay (typically 1.5 ms with the FIR filter) in the
calculation.
5.14. Ground Start Support
The Si3050 DAA supports loop-start applications by
default. It can also support ground-start applications
with the RG, TGD, and TGDE pins and the schematic
shown in Figure 22. The component values are listed in
Table 15.
Rev. 1.5
29
Si3050 + Si3011/18/19
on RING and grounds TIP. This sets the TGD bit
(Register 32, bit 2). The DAA may then be taken
off-hook and the relay in series with RING opened (clear
the RG bit). The call continues as in loop-start mode.
VD
R106
TGDb
5.14.3. CO Requests Line Seizure
-24V
R105
In a normal on-hook state, the relay in series with TIP
should be closed, connecting the –24 V isolated supply.
The CO grounds TIP to request line seizure, causing
current to flow. The opto-isolator U3 (see Figure 22 on
page 30) detects this current and sets the TGD bit
(Register 32, bit 2). This bit remains high as long as
current is detected. The TGDI bit (Register 4, bit 1) is a
sticky bit, and remains high until cleared. A hardware
interrupt on the AOUT/INT can be made to occur when
TIP current begins to flow by enabling the TGDM bit
(Register 3, bit 1). Clear the interrupt by writing 0 to the
TGDI bit (Register 4 bit 1). The DAA may then be taken
off-hook and the call continued as in loop-start mode.
U3
1
1
4
4
2
2
3
3
Opto-Isolator
VD
R104
R102
R103
RL1
TGDEb
RGb
1
1
8
8
2
2
7
7
TIP
3
3
6
6
RING
4
4
5
5
Opto-Relay
R101
5.15. Interrupts
Figure 22. Typical Application Circuit for
Ground Start Support on the SI3050
Table 15. Component Values for the Ground
Start Support Schematic
Symbol
Value
Supplier(s)
R101
200 , 2 W, ±5%
Venkel, SMEC,
Panasonic
R102, R103,
R106
1 k, 1/10 W, ±5%
Venkel, SMEC,
Panasonic
R104
1.5 k, 1/10 W, ±5% Venkel, SMEC,
Panasonic
R105
10 k, 1/2 W, ±5%
Venkel, SMEC,
Panasonic
RL1
AQW210S
Aromat, NEC
U3
PS2501L-1
NEC, Fairchild
5.14.1. Ground Start Idle
Ensure the relay in series with TIP is closed by clearing
the TGOE bit (Register 32, bit 1). This enables the DAA
to sense if the CO grounds TIP. Set RG to 1
(Register 32, bit 0) so that no current flows through the
relay connecting RING to ground.
5.14.2. DAA Requests Line Seizure
With TGOE set to zero, seize the line by closing the
relay in series with RING (clear the RG bit,
Register 32, bit 0). The CO detects this current flowing
30
The AOUT/INT pin can be used as a hardware interrupt
pin by setting the INTE bit (Register 2, bit 7). When this
bit is set, the analog output used for call progress
monitoring is not available. The default state of this
interrupt output pin is active low, but active high
operation can be enabled by setting the INTP bit
(Register 2, bit 6). This pin is an open-drain output
when the INTE bit is set and requires a 4.7 k pullup or
pulldown for correct operation. If multiple INT pins are
connected to a single input, the combined pullup or
pulldown resistance should equal 4.7 k Bits 7–0 in
Register 3 and bit 1 in Register 44 can be set to enable
hardware interrupt sources (bit 0 is available with the
Si3011 and Si3019 line-side devices only). When one or
more of these bits is set, the AOUT/INT pin goes into an
active state and stays active until the interrupts are
serviced. If more than one hardware interrupt is enabled
in Register 3, use software polling to determine the
cause of the interrupts. Register 4 and bit 3 of
Register 44 contain sticky interrupt flag bits. Clear these
bits after servicing the interrupt.
Registers 43 and 44 contain the line current/voltage
threshold interrupt. These line current/voltage registers
and interrupt are only available with the Si3011 and
Si3019 line-side devices. This interrupt is triggered
when the measured line voltage or current in the LVS or
LCS2 registers, as selected by the CVS bit
(Register 44, bit 2), crosses the threshold programmed
into the CVT[7:0] bits. With the CVP bit, the interrupt
can be programmed to occur when the measured value
rises above or falls below the threshold. Only the
magnitude of the measured value is used for
comparison to the threshold programmed into the
Rev. 1.5
Si3050 + Si3011/18/19
CVT[7:0] bits. Therefore, only positive numbers should
be used as a threshold.
5.16. DC Termination
The DAA has programmable settings for the dc
impedance, current limiting, minimum operational loop
current and TIP/RING voltage. The dc impedance of the
DAA is normally represented with a 50 slope as
shown in Figure 23, but can be changed to an 800
slope by setting the DCR bit. This higher dc termination
presents a higher resistance to the line as loop current
increases.
Voltage Across DAA (V)
12
Finally, Australia has separate dc termination
requirements for line seizure versus line hold. Japan
mode (only available with the Si3018 or Si3019) may be
used to satisfy both requirements. However, if a higher
transmit level for modem operation is desired, switch to
FCC mode 500 ms after the initial off-hook. This
satisfies the Australian dc termination requirements.
FCC DCT Mode
11
10
9
5.17. AC Termination
8
7
6
.01 .02 .03 .04 .05 .06 .07 .08 .09 .1 .11
Loop Current (A)
Figure 23. FCC Mode I/V Characteristics,
DCV[1:0] = 11, MINI[1:0] = 00, ILIM = 0
For applications requiring current limiting per the TBR21
standard, the ILIM bit may be set to select this mode. In
this mode, the dc I/V curve is changed to a 2000
slope above 40 mA, as shown in Figure 24. This allows
the DAA to operate with a 50 V, 230 feed, which is the
maximum linefeed specified in the TBR21 standard.
Voltage Across DAA (V)
45
The MINI[1:0] bits select the minimum operational loop
current for the DAA, and the DCV[1:0] bits adjust the
DCT pin voltage, which affects the TIP/RING voltage of
the DAA. These bits allow important trade-offs to be
made between signal headroom and minimum
operational loop current. Increasing TIP/RING voltage
increases signal headroom, whereas decreasing the
TIP/RING voltage allows compliance to PTT standards
in low-voltage countries, such as Japan. Increasing the
minimum operational loop current above 10 mA also
increases signal headroom and prevents degradation of
the signal level in low-voltage countries.
TBR21 DCT Mode
40
35
30
The Si3050 + Si3011 chipset provides two ac
termination impedances. The Si3050 + Si3018 chipset
provides four ac termination impedances. The
ACIM[3:0] bits in Register 30 are used to select the ac
impedance setting. The two available settings for the
Si3050 + Si3011 chipset are listed in Table 16. The four
available settings for the Si3018 are listed in Table 17. If
an ACIM[3:0] setting other than the four listed in
Table 16 or Table 17 is selected, the ac termination is
forced to 600 (ACIM[3:0] = 0000). The programmable
digital hybrid can be used to further reduce near-end
echo for each of the four listed ac termination settings.
See "5.28. Transhybrid Balance" on page 38 for details.
Table 16. AC Termination Settings for the
Si3011 Line-Side Device
ACIM[3:0]
AC Termination
0000
600
0001
210 + (750 || 150 nF) and 275 +
(780 || 150 nF)
25
20
15
10
5
.015 .02 .025 .03 .035 .04 .045 .05 .055 .06
Loop Current (A)
Figure 24. TBR21 Mode I/V Characteristics,
DCV[1:0] = 11, MINI[1:0] = 00, ILIM = 1
Rev. 1.5
31
Si3050 + Si3011/18/19
Table 17. AC Termination Settings for the
Si3018 Line-Side Device
Table 18. AC Termination Settings for the
Si3019 Line-Side Device
ACIM[3:0]
AC Termination
0000
600
0011
220 + (820 || 120 nF) and 220 +
(820 || 115 nF)
0100
370 + (620 || 310 nF)
1111
Global complex impedance
ACIM[3:0]
The Si3019 provides sixteen ac termination
impedances when used with the Si3050. The ACIM[3:0]
bits in Register 30 are used to select the ac impedance
setting on the Si3019. The sixteen available settings for
the Si3019 are listed in Table 18.
The most widely used ac terminations are available as
register options to satisfy various global PTT
requirements. The real 600 impedance satisfies the
requirements of FCC Part 68, JATE, and other country
requirements. The 270 + (750 || 150 nF) satisfies
the requirements of TBR21.
There are two selections useful for satisfying
non-standard ac termination requirements. The
350 + (1000 || 210 nF) impedance selection in
Register 30 is the ANSI/EIA/TIA 464 compromise
impedance network for trunks. The last ac termination
selection, ACIM[3:0] = 1111, is designed to satisfy
minimum return loss requirements for every country that
requires a complex termination. By selecting this
setting, the system is ensured to meet minimum PTT
requirements.
For each of the sixteen ac termination settings, the
programmable digital hybrid can be used to further
reduce near-end echo. See "5.28. Transhybrid Balance"
on page 38 for details.
32
Rev. 1.5
AC Termination
0000
600
0001
900
0010
270 + (750 || 150 nF) and
275 + (780 || 150 nF)
0011
220 + (820 || 120 nF) and 220
+ (820 || 115 nF)
0100
370 + (620 || 310 nF)
0101
320 + (1050 || 230 nF)
0110
370 + (820 || 110 nF)
0111
275 + (780 || 115 nF)
1000
120 + (820 || 110 nF)
1001
350 + (1000 || 210 nF)
1010
200 + (680 || 100 nF)
1011
600 + 2.16 µF
1100
900 + 1 µF
1101
900 + 2.16 µF
1110
600 + 1 µF
1111
Global complex impedance
Si3050 + Si3011/18/19
5.18. Ring Detection
The ring signal is resistively coupled from TIP and RING
to the RNG1 and RNG2 pins. The Si3050 supports
either full- or half-wave ring detection. With full-wave
ring detection, the designer can detect a polarity
reversal of the ring signal. See “5.25.Caller ID” on
page 36. The ring detection threshold is programmable
with the RT bit (Register 16, bit 0) and RT2 bit
(Register 17, bit 4). The ring detector output can be
monitored in three ways. The first method uses the
RGDT pin. The second method uses the register bits,
RDTP, RDTN, and RDT (Register 5). The final method
uses the DTX output.
The ring detector mode is controlled by the RFWE bit
(Register 18, bit 1). When the RFWE bit is 0 (default
mode), the ring detector operates in half-wave rectifier
mode. In this mode, only positive ring signals are
detected. A positive ring signal is defined as a voltage
greater than the ring threshold across RNG1-RNG2.
Conversely, a negative ring signal is defined as a
voltage less than the negative ring threshold across
RNG1-RNG2. When the RFWE bit is 1, the ring detector
operates in full-wave rectifier mode. In this mode, both
positive and negative ring signals are detected.
The first method to monitor ring detection output uses
the RGDT pin. When the RGDT pin is used, it defaults
to active low, but can be changed to active high by
setting the RPOL bit (Register 14, bit 1). This pin is an
open-drain output, and requires a 4.7 k pullup or
pulldown for correct operation. If multiple RGDT pins
are connected to a single input, the combined pullup or
pulldown resistance should equal 4.7 k
When the RFWE bit is 0, the RGDT pin is asserted
when the ring signal is positive, which results in an
output signal frequency equal to the actual ring
frequency. When the RFWE bit is 1, the RGDT pin is
asserted when the ring signal is positive or negative.
The output then appears to be twice the frequency of
the ring waveform.
The second method to monitor ring detection uses the
ring detect bits (RDTP, RDTN, and RDT). The RDTP
and RDTN behavior is based on the RNG1-RNG2
voltage. When the signal on RNG1-RNG2 is above the
positive ring threshold, the RDTP bit is set. When the
signal on RNG1-RNG2 is below the negative ring
threshold, the RDTN bit is set. When the signal on
RNG1-RNG2 is between these thresholds, neither bit is
set.
The RDT behavior is also based on the RNG1-RNG2
voltage. When the RFWE bit is 0, a positive ring signal
sets the RDT bit for a period of time. When the RFWE
bit is 1, a positive or negative ring signal sets the RDT
bit.
The RDT bit acts like a one shot. When a new ring
signal is detected, the one shot is reset. If no new ring
signals are detected prior to the one shot counter
reaching 0, then the RDT bit clears. The length of this
count is approximately 5 seconds. The RDT bit is reset
to 0 by an off-hook event. If the RDTM bit
(Register 3, bit 7) is set, a hardware interrupt occurs on
the AOUT/INT pin when RDT is triggered. This interrupt
can be cleared by writing to the RDTI bit
(Register 4, bit 7). When the RDI bit (Register 2, bit 2) is
set, an interrupt occurs on both the beginning and end
of the ring pulse as defined by the RTO bits
(Register 23, bits 6:3). Ring validation may be enabled
when using the RDI bit.
The third method to monitor detection uses the DTX
data samples to transmit ring data. If the ISOcap is
active (PDL= 0) and the device is not off-hook or in
on-hook line monitor mode, the ring data is presented
on DTX. The waveform on DTX depends on the state of
the RFWE bit.
When RFWE is 0, DTX is –32768 (0x8000) while the
RNG1-RNG2 voltage is between the thresholds. When
a ring is detected, DTX transitions to +32767 when the
ring signal is positive, then goes back to –32768 when
the ring is near 0 and negative. Thus a near square
wave is presented on DTX that swings from –32768 to
+32767 in cadence with the ring signal.
When RFWE is 1, DTX sits at approximately +1228
while the RNG1-RNG2 voltage is between the
thresholds. When the ring becomes positive, DTX
transitions to +32767. When the ring signal goes near 0,
DTX remains near 1228. As the ring becomes negative,
the DTX transitions to –32768. This repeats in cadence
with the ring signal.
To observe the ring signal on DTX, watch the MSB of
the data. The MSB toggles at the same frequency as
the ring signal independent of the ring detector mode.
This method is adequate for determining the ring
frequency.
Rev. 1.5
33
Si3050 + Si3011/18/19
5.19. Ring Validation
Ring validation prevents false triggering of a ring
detection by validating the ring parameters. Invalid
signals, such as a line-voltage change when a parallel
handset goes off-hook, pulse dialing, or a high-voltage
line test are ignored. Ring validation can be enabled
during normal operation and in low-power sleep mode
when a valid external PCLK signal is supplied.
The ring validation circuit operates by calculating the
time between alternating crossings of positive and
negative ring thresholds to validate that the ring
frequency is within tolerance. High and low frequency
tolerances are programmable in the RAS[5:0] and
RMX[5:0] fields. The RCC[2:0] bits define how long the
ring signal must be within tolerance.
Once the duration of the ring frequency is validated by
the RCC bits, the circuitry stops checking for frequency
tolerance and begins checking for the end of the ring
signal, which is defined by a lack of additional threshold
crossings for a period of time configured by the
RTO[3:0] bits. When the ring frequency is first validated,
a timer defined by the RDLY[2:0] bits is started. If the
RDLY[2:0] timer expires before the ring timeout, then
the ring is validated and a valid ring is indicated. If the
ring timeout expires before the RDLY[2:0] timer, a valid
ring is not indicated.
Ring validation requires the following five parameters:
Timeout parameter to place a lower limit on the
frequency of the ring signal (the RAS[5:0] bits in
Register 24). The frequency is measured by
calculating the time between crossings of positive
and negative ring thresholds.
Minimum count to place an upper limit on the
frequency (the RMX[5:0] bits in Register 22).
Time interval over which the ring signal must be the
correct frequency (the RCC[2:0] bits in Register 23).
Timeout period that defines when the ring pulse has
ended based on the most recent ring threshold
crossing.
Delay period between when the ring signal is
validated and when a valid ring signal is indicated to
accommodate distinctive ringing.
The RNGV bit (Register 24, bit 7) enables or disables
the ring validation feature in both normal operating
mode and low-power sleep mode.
Ring validation affects the behavior of the RDT status
bit, the RDTI interrupt, the INT pin, and the RGDT pin.
1. When ring validation is enabled, the status bit seen
in the RDT read-only bit (r5.2), represents the
detected envelope of the ring. The ring validation
parameters are configurable so that this envelope
34
may remain high throughout a distinctive-ring
sequence.
2. The RDTI interrupt fires when a validated ring
occurs. If RDI is zero (default), the interrupt occurs
on the rising edge of RDT. If RDI is set, the interrupt
occurs on both rising and falling edges of RDT.
3. The INT pin follows the RDTI bit with configurable
polarity.
4. The RGDT pin can be configured to follow the
ringing signal envelope detected by the ring
validation circuit by setting RFWE to 0. If RFWE is
set to 1, the RGDT pin follows an unqualified ring
detect one-shot signal initiated by a ring-threshold
crossing and terminated by a fixed counter timeout
of approximately 5 seconds. (This information is
shown in Register 18).
5.20. Ringer Impedance and Threshold
The ring detector in a typical DAA is ac coupled to the
line with a large 1 F, 250 V decoupling capacitor. The
ring detector on the Si3011/18/19 is resistively coupled
to the line. This coupling produces a high ringer
impedance to the line of approximately 20 M to meet
the majority of country PTT specifications including FCC
and TBR21.
Several countries including Poland, South Africa, and
Slovenia require a maximum ringer impedance that can
be met with an internally-synthesized impedance by
setting the RZ bit (Register 16). Certain countries also
specify ringer thresholds differently. The RT and RT2
bits (Register 16 and Register 17, respectively) select
between three different ringer thresholds: 15 V ±10%,
21 V ±10%, and 45 V ±10%. These three settings
enable satisfaction of global ringer threshold
requirements. Thresholds are set so that a ring signal is
guaranteed to not be detected below the minimum, and
a ring signal is guaranteed to be detected above the
maximum.
5.21. Pulse Dialing and Spark Quenching
Pulse dialing is accomplished by going off- and on-hook
to generate make and break pulses. The nominal rate is
10 pulses per second. Some countries have strict
specifications for pulse fidelity including make and
break times, make resistance, and rise and fall times. In
a traditional, solid-state dc holding circuit, there are a
number of issues in meeting these requirements.
The Si3050 dc holding circuit has active control of the
on- and off-hook transients to maintain pulse dialing
fidelity.
Spark quenching requirements in countries, such as
Italy, the Netherlands, South Africa, and Australia, deal
Rev. 1.5
Si3050 + Si3011/18/19
with the on-hook transition during pulse dialing. These
tests provide an inductive dc feed resulting in a large
voltage spike. This spike is caused by the line
inductance and the sudden decrease in current through
the loop when going on-hook. The traditional way of
dealing with this problem is to put a parallel RC shunt
across the hookswitch relay. The capacitor is large
(~1 µF, 250 V) and relatively expensive. In the Si3050,
loop current can be controlled to achieve three distinct
on-hook speeds to pass spark quenching tests without
additional BOM components. Through the settings of
four bits in three registers, OHS (Register 16), OHS2
(Register 31), SQ0, and SQ1 (Register 59), a slow ramp
down of loop current can be achieved which induces a
delay between the time the OH bit is cleared and the
time the DAA actually goes on-hook.
To ensure proper operation of the DAA during pulse
dialing, disable the automatic resistor calibration that is
performed each time the DAA enters the off-hook state
by setting the RCALD bit (Register 25, bit 5).
bits will be set. An external interrupt can optionally be
triggered by the DODI bit by setting the DODM and
INTE bits.
5.23. Billing Tone Filter (Optional)
Optionally, a billing tone filter may be inserted between
the line and the voice DAA to minimize disruptions
caused by large billing tones. The notch filter design
requires two notches, one at 12 kHz and one at 16 kHz.
Because these components are expensive and few
countries utilize billing tones, this filter is typically placed
in an external dongle or added as a population option.
Figure 25 shows a billing tone filter example. Table 19
gives the component values.
L1 must carry the entire loop current. The series
resistance of the inductors is important to achieve a
narrow and deep notch. This design has more than
25 dB of attenuation at both 12 kHz and 16 kHz.
C1
5.22. Receive Overload Detection
C2
The Voice DAA chipset is capable of monitoring and
reporting receive overload conditions on the line. Billing
tones, parallel phone off-hook events, polarity reversals
and other disturbances on the line may trigger multiple
levels of overload detection as described below.
Transient events less than 1.1 VPK on the line are
filtered out by the low-pass digital filter on the Si3050 +
Si3011 and Si3050+Si3019. The ROV and ROVI bits
are set when the received signal is greater than 1.1
VPK. Both bits will continue to indicate an overload
condition until a zero is written to clear. The OVL mirrors
the function of the ROV and ROVI bits but it
automatically clears after the overload condition has
been removed. When the OVL bit returns to 0, the DAA
initiates an auto-calibration sequence that must
complete before data can be transmitted. An external
interrupt can optionally be triggered by the ROVI bit by
setting the ROVM and INTE bits.
Certain events such as billing tones can be sufficiently
large to disrupt the line-derived power supply of the
Voice DAA line side device (Si3011, Si3018 or Si3019.)
To ensure that the device maintains the off-hook line
state during these events, the BTE bit should be set. If
such an event occurs while the BTE bit is set, the BTD
and BTDI bits will be asserted. A zero must be written to
the BTE bit to clear the BTD and BTDI bits. An external
interrupt can optionally be triggered by the BTDI bit by
setting the BTDM and INTE bits.
In the event that a line disturbance causes the loop
current to collapse below the minimum required
operating current of the Voice DAA, the DOD and DODI
L1
TIP
From Line
L2
C3
To
DAA
RING
Figure 25. Billing Tone Filter
Table 19. Component Values—Optional Billing
Tone Filters
Component
Value
C1,C2
0.027 µF, 50 V, ±10%
C3
0.01 µF, 250 V, ±10%
L1
3.3 mH, >120 mA, 40 mA, 127 mA, and an overload condition may exist.
Read returns zero.
Frame Detect.
0 = Indicates ISOcap link has not established frame lock.
1 = Indicates ISOcap link frame lock is established.
Rev. 1.5
71
Si3050 + Si3011/18/19
Register 13. Line-Side Device Revision
Bit
D7
D6
D5
D4
D3
Name
1
REVB[3:0]
Type
R
R
D2
D1
D0
D2
D1
D0
Reset settings = xxxx_xxxx
Bit
Name
Function
7
Reserved
Read returns zero.
6
Reserved
This bit always reads a one.
5:2
REVB[3:0] Line-Side Device Revision.
Four-bit value indicating the revision of the line-side device.
1:0
Reserved
Read returns zero.
Register 14. DAA Control 4
Bit
D7
D6
D5
D4
D3
Name
RPOL
Type
R/W
Reset settings = 0000_0000
Bit
Name
7:2
Reserved
1
RPOL
Function
Read returns zero.
Ring Detect Polarity.
0 = The RGDT pin is active low.
1 = The RGDT pin is active high.
0
72
Reserved
Read returns zero.
Rev. 1.5
Si3050 + Si3011/18/19
Register 15. TX/RX Gain Control 1
Bit
D7
D6
D5
D4
D3
Name
TXM
RXM
Type
R/W
R/W
D2
D1
D0
Reset settings = 0000_0000
Bit
Name
7
TXM
6:4
Reserved
3
RXM
2:0
Reserved
Function
Transmit Mute.
0 = Transmit signal is not muted.
1 = Mutes the transmit signal.
Read returns zero.
Receive Mute.
0 = Receive signal is not muted.
1 = Mutes the receive signal.
Read returns zero.
Rev. 1.5
73
Si3050 + Si3011/18/19
Register 16. International Control 1
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
OHS
IIRE
RZ
RT
Type
R/W
R/W
R/W
R/W
Reset settings = 0000_0000
Bit
7
6
5
Name
Function
Reserved These bits may be written to a zero or one.
OHS
On-Hook Speed. Si3018 and Si3019 line-side only.
This bit, in combination with the OHS2 bit (Register 31) and the SQ[1:0] bits (Register 59), sets
the amount of time for the line-side device to go on-hook. The on-hook speeds specified are
measured from the time the OH bit is cleared until loop current equals zero.
OHS
OHS2
SQ[1:0]
Mean On-Hook Speed
0
0
00
Less than 0.5 ms
0
1
00
3 ms ±10% (meets ETSI standard)
1
X
11
26 ms ±10% (meets Australia spark quenching spec)
For Si3011 line-side device, this bit may be written to a zero or one.
Reserved These bits may be written to a zero or one.
IIR Filter Enable.
0 = FIR filter enabled for transmit and receive filters. (See Figures 7–10 on page 15.)
1 = IIR filter enabled for transmit and receive filters. (See Figures 11–16 on page 16.)
4
IIRE
3:2
Reserved
1
RZ
Ringer Impedance. Si3018 and Si3019 line-side only.
0 = Maximum (high) ringer impedance.
1 = Synthesized ringer impedance used to satisfy a maximum ringer impedance specification
in countries, such as Poland, South Africa, and Slovenia.
For Si3011 line-side device, this bit may be written to a zero or one.
0
RT
Ringer Threshold Select. Si3018 and Si3019 line-side only.
This bit, in combination with the RT2 bit, is used to satisfy country requirements on ring detection. Signals below the lower level do not generate a ring detection; signals above the upper
level are guaranteed to generate a ring detection.
RT
RT2
RT Lower level
RT Upper level
0
0
13.5 Vrms
16.5 Vrms
0
1
Reserved, do not use this setting.
23.65 VRMS
1
0
19.35 Vrms
1
1
40.5 Vrms
49.5 VRMS
For Si3011 line-side device, this bit may be written to a zero or one.
74
Read returns zero.
Rev. 1.5
Si3050 + Si3011/18/19
Register 17. International Control 2
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
CALZ
MCAL
CALD
RT2
OPE
BTE
ROV
BTD
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Reset settings = 0000_0000
Bit
7
Name
CALZ
6
MCAL
5
CALD
4
RT2
3
OPE
2
BTE
Function
Clear ADC Calibration.
0 = Normal operation.
1 = Clears the existing ADC calibration data. This bit must be written back to 0 after being set.
Manual ADC Calibration.
0 = No calibration.
1 = Initiate manual ADC calibration.
Auto-Calibration Disable.
0 = Enable auto-calibration.
1 = Disable auto-calibration.
Ringer Threshold Select 2. Si3018 and Si3019 line-side only.
This bit, in combination with the RT bit, is used to satisfy country requirements on ring detection. Signals below the lower level do not generate a ring detection; signals above the upper
level are guaranteed to generate a ring detection.
RT
RT2
RT Lower level
RT Upper level
0
0
13.5 Vrms
16.5 Vrms
0
1
Reserved, do not use this setting.
23.65 VRMS
1
0
19.35 Vrms
1
1
40.5 Vrms
49.5 VRMS
For Si3011 line-side device, always write this bit to zero.
Overload Protect Enable.
0 = Disabled.
1 = Enabled.
The OPE bit should always be cleared before going off-hook.
Billing Tone Detect Enable.
The DAA can detect events, such as billing tones, that can cause a disruption in the line-side
power supply. When this bit is set, the device will maintain off-hook during such events. If a
billing tone is detected, the BTD bit (Register 17, bit 0) is set to indicate the event. Writing this
bit to zero clears the BTD bit.
0 = Billing tone detection disabled. The BTD bit is not functional.
1 = Billing tone detection enabled. The BTD bit is not functional.
Rev. 1.5
75
Si3050 + Si3011/18/19
Bit
1
Name
ROV
0
BTD
Function
Receive Overload.
This bit is set when the receive input has an excessive input level (i.e., receive pin goes below
ground). Writing a 0 to this location clears this bit and the ROVI bit (Register 4, bit 6).
0 = Normal receive input level.
1 = Excessive receive input level.
Billing Tone Detected.
This bit is set if an event, such as a billing tone, causes a disruption in the line-side power
supply. Writing a zero to BTE clears this bit.
0 = No billing tone detected.
1 = Billing tone detected.
Register 18. International Control 3
Bit
D7
D6
D5
D4
D3
D2
D1
Name
RFWE
Type
R/W
D0
Reset settings = 0000_0000
Bit
7:3
2
1
0
76
Name
Function
Reserved Read returns zero.
Reserved This bit may be written to a zero or one.
RFWE
Ring Detector Full-Wave Rectifier Enable.
When RNGV (Register 24) is disabled, this bit controls the ring detector mode and the assertion of the RGDT pin. When RNGV is enabled, this bit configures the RGDT pin to either follow
the ringing signal detected by the ring validation circuit, or to follow an unqualified ring detect
one-shot signal initiated by a ring-threshold crossing and terminated by a fixed counter timeout
of approximately 5 seconds.
RNGV
RFWE
RGDT
0
0
Half-Wave
0
1
Full-Wave
1
0
Validated Ring Envelope
1
1
Ring Threshold Crossing One-Shot
Reserved Read returns zero.
Rev. 1.5
Si3050 + Si3011/18/19
Register 19. International Control 4
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
OVL
DOD
OPD
Type
R
R
R
Reset settings = 0000_0000
Bit
Name
Function
7:3
Reserved
2
OVL
Receive Overload Detect.
This bit has the same function as ROV (Register 17), but clears itself after the overload is
removed. See “5.22.Receive Overload Detection” on page 35. This bit is only masked by the
off-hook counter and is not affected by the BTE bit.
0 = Normal receive input level.
1 = Excessive receive input level.
1
DOD
Recal/Dropout Detect.
When the line-side device is off-hook, it is powered from the line itself. This bit will read 1
when loop current is not flowing. For example, if this line-derived power supply collapses,
such as when the line is disconnected, this bit is set to 1. Additionally, when on-hook, and the
line-side device is enabled, this bit is set to 1.
0 = Normal operation.
1 = Line supply dropout detected when off-hook.
0
OPD
Overload Protect Detect.
This bit is used to indicate that the DAA has detected a loop current overload. The detector firing threshold depends on the setting of the ILIM bit (Register 26).
OPD
ILIM
Overcurrent Threshold
Overcurrent Status
0
0
160 mA
No overcurrent condition exists
0
1
60 mA
No overcurrent condition exists
1
0
160 mA
Overcurrent condition has been detected
1
1
60 mA
Overcurrent condition has been detected
Read returns zero.
Rev. 1.5
77
Si3050 + Si3011/18/19
Register 20. Call Progress RX Attenuation
Bit
D7
D6
D5
D4
D3
Name
ARM[7:0]
Type
R/W
D2
D1
D0
Reset settings = 0000_0000
Bit
Name
Function
7:0
ARM[7:0]
AOUT Receive Path Attenuation.
When decremented from the default setting, these bits linearly attenuate the AOUT
receive path signal used for call progress monitoring. Setting the bits to all 0s mutes the
AOUT receive path.
Attenuation = 20 log(ARM[7:0]/64)
1111_1111 = +12 dB (gain)
0111_1111 = +6 dB (gain)
0100_0000 = 0 dB
0010_0000 = –6 dB (attenuation)
0001_0000 = –12 dB
...
0000_0000 = Mute
Register 21. Call Progress TX Attenuation
Bit
D7
D6
D5
D4
D3
Name
ATM[7:0]
Type
R/W
D2
D1
D0
Reset settings = 0000_0000
Bit
Name
7:0
ATM[7:0]
Function
AOUT Transmit Path Attenuation.
When decremented from the default settings, these bits linearly attenuate the AOUT transmit path signal used for call progress monitoring. Setting the bits to all 0s mutes the AOUT
transmit path.
Attenuation = 20 log(ATM[7:0]/64)
1111_1111 = +12 dB (gain)
0111_1111 = +6 dB (gain)
0100_0000 = 0 dB
0010_0000 = –6 dB (attenuation)
0001_0000 = –12 dB
...
0000_0000 = Mute
78
Rev. 1.5
Si3050 + Si3011/18/19
Register 22. Ring Validation Control 1
Bit
D7
D6
D5
D4
D3
D2
Name
RDLY[1:0]
RMX[5:0]
Type
R/W
R/W
D1
D0
Reset settings = 1001_0110
Bit
Name
Function
7:6
RDLY[1:0]
Ring Delay Bits 1 and 0.
These bits, in combination with the RDLY[2] bit (Register 23), set the amount of time
between when a ring signal is validated and when a valid ring signal is indicated.
RDLY[2]
RDLY[1:0]
Delay
0
00
0 ms
0
01
256 ms
0
10
512 ms
...
1
11
1792 ms
5:0
RMX[5:0]
Ring Assertion Maximum Count.
These bits set the maximum ring frequency for a valid ring signal within a 10% margin of
error. During ring qualification, a timer is loaded with the RAS[5:0] field upon a TIP/RING
event and decrements at a regular rate. When a subsequent TIP/RING event occurs, the
timer value is compared to the RMX[5:0] field and if it exceeds the value in RMX[5:0] then
the frequency of the ring is too high and the ring is invalidated. The difference between
RAS[5:0] and RMX[5:0] identifies the minimum duration between TIP/RING events to qualify as a ring, in binary-coded increments of 2.0 ms (nominal). A TIP/RING event typically
occurs twice per ring tone period. At 20 Hz, TIP/RING events would occur every 1/
(2 x 20 Hz) = 25 ms. To calculate the correct RMX[5:0] value for a frequency range [f_min,
f_max], the following equation should be used:
1
RMX 5:0 RAS 5:0 – --------------------------------------------- RMX RAS
2 f_max 2 ms
To compensate for error margin and ensure a sufficient ring detection window, it is recommended that the calculated value of RMX[5:0] be incremented by 1.
Rev. 1.5
79
Si3050 + Si3011/18/19
Register 23. Ring Validation Control 2
Bit
D7
D6
D5
D4
D3
D2
D1
Name
RDLY[2]
RTO[3:0]
RCC[2:0]
Type
R/W
R/W
R/W
D0
Reset settings = 0010_1101
Bit
Name
7
RDLY[2]
Ring Delay Bit 2.
This bit, in combination with the RDLY[1:0] bits (Register 22), sets the amount of time
between when a ring signal is validated and when a valid ring signal is indicated.
RDLY[2]
RDLY[1:0]
Delay
0
00
0 ms
0
01
256 ms
0
10
512 ms
...
1
11
1792 ms
6:3
RTO[3:0]
Ring Timeout.
These bits set when a ring signal is determined to be over after the most recent ring
threshold crossing.
RTO[3:0]
Ring Timeout
0000
DO NOT USE THIS SETTING
0001
128 ms
0010
256 ms
...
1111
1920 ms
2:0
RCC[2:0]
Ring Confirmation Count.
These bits set the amount of time that the ring frequency must be within the tolerances set
by the RAS[5:0] bits and the RMX[5:0] bits to be classified as a valid ring signal.
RCC[2:0]
Ring Confirmation Count Time
000
100 ms
001
150 ms
010
200 ms
011
256 ms
100
384 ms
101
512 ms
110
640 ms
111
1024 ms
80
Function
Rev. 1.5
Si3050 + Si3011/18/19
Register 24. Ring Validation Control 3
Bit
D7
D6
D5
D4
D3
D2
Name
RNGV
RAS[5:0]
Type
R/W
R/W
D1
D0
Reset settings = 0001_1001
Bit
Name
7
RNGV
Function
Ring Validation Enable.
0 = Ring validation feature is disabled.
1 = Ring validation feature is enabled in both normal operating mode and low-power
mode.
6
Reserved
This bit must always be written to 0.
5:0
RAS[5:0]
Ring Assertion Time.
These bits set the minimum ring frequency for a valid ring signal. During ring qualification,
a timer is loaded with the RAS[5:0] field upon a TIP/RING event and decrements at a regular rate. If a second or subsequent TIP/RING event occurs after the timer has timed out
then the frequency of the ring is too low and the ring is invalidated. The difference between
RAS[5:0] and RMX[5:0] identifies the minimum duration between TIP/RING events to qualify as a ring, in binary-coded increments of 2.0 ms (nominal). A TIP/RING event typically
occurs twice per ring tone period. At 20 Hz, TIP/RING events would occur every
1/(2 x 20 Hz) = 25 ms. To calculate the correct RAS[5:0] value for a frequency range
[f_min, f_max], the following equation should be used:
1
RAS 5:0 ------------------------------------------2 f_min 2 ms
Register 25. Resistor Calibration
Bit
D7
D6
D5
Name
RCALS
RCALM
RCALD
Type
R
R/W
R/W
D4
D3
D2
D1
D0
RCAL[3:0]
R/W
Reset settings = xx0x_xxxx
Bit
Name
7
RCALS
Resistor Auto Calibration.
0 = Resistor calibration is not in progress.
1 = Resistor calibration is in progress.
6
RCALM
Manual Resistor Calibration.
0 = No calibration.
1 = Initiate manual resistor calibration. (After a manual calibration has been initiated, this bit
must be cleared within 1 ms.)
5
RCALD
Resistor Calibration Disable.
0 = Internal resistor calibration enabled.
1 = Internal resistor calibration disabled.
4
Reserved
3:0
Function
This bit can be written to a 0 or 1.
RCAL[3:0] Always write back the value read. Result of resistor calibration. Do not modify this value.
Rev. 1.5
81
Si3050 + Si3011/18/19
Register 26. DC Termination Control
Bit
D7
D6
D5
D4
Name
DCV[1:0]
MINI[1:0]
Type
R/W
R/W
D3
D2
D1
D0
0
0
ILIM
DCR
R/W
R/W
Reset settings = 0000_0000
Bit
Name
Function
7:6
DCV[1:0]
TIP/RING Voltage Adjust. Si3018 and Si3019 line-side only.
These bits adjust the voltage on the DCT pin of the line-side device, which affects the TIP/
RING voltage on the line. Low-voltage countries should use a lower TIP/RING voltage. Raising the TIP/RING voltage can improve signal headroom.
DCV[1:0] DCT Pin Voltage
00
3.1 V
01
3.2 V
10
3.35 V
11
3.5 V
For Si3011 line-side device, the only valid setting for DCV[1:0] is 10.
5:4
MINI[1:0]
Minimum Operational Loop Current. Si3018 and Si3019 line-side only.
Adjusts the minimum loop current at which the DAA can operate. Increasing the minimum
operational loop current can improve signal headroom at a lower TIP/RING voltage.
MINI[1:0] Min Loop Current
00
10 mA
01
12 mA
10
14 mA
11
16 mA
For Si3011 line-side device, the only valid setting for MINI[1:0] is 00.
3:2
Reserved
These bits must always be written to 0.
1
ILIM
Current Limiting Enable.
0 = Current limiting mode disabled.
1 = Current limiting mode enabled. This mode limits loop current to a maximum of 60 mA per
the TBR21 standard.
0
DCR
DC Impedance Selection.
0 = 50 dc termination is selected. This mode should be used for all standard applications.
1 = 800 dc termination is selected.
82
Rev. 1.5
Si3050 + Si3011/18/19
Register 27. Reserved
Bit
D7
D6
D5
D4
D3
D2
D1
D0
D2
D1
D0
Name
Type
Reset settings = xxxx_xxxx
Bit
Name
7:0
Reserved
Function
Do not write to these register bits.
Register 28. Loop Current Status
Bit
D7
D6
D5
D4
D3
Name
LCS2[7:0]
Type
R
Reset settings = 0000_0000
Bit
7:0
Name
Function
LCS2[7:0] Loop Current Status.
Eight-bit value returning the loop current. Each bit represents 1.1 mA of loop current.
0000_0000 = Loop current is less than required for normal operation.
Register 29. Line Voltage Status
Bit
D7
D6
D5
D4
D3
Name
LVS[7:0]
Type
R
D2
D1
D0
Reset settings = 0000_0000
Bit
Name
7:0
LVS[7:0]
Function
Line Voltage Status.
Eight-bit value returning the loop voltage. Each bit represents 1 V of loop voltage. This register operates in on- and off-hook modes. Bit seven of this register indicates the polarity of the
TIP/RING voltage. When this bit changes state, it indicates that a polarity reversal has
occurred. The value returned is represented in 2s complement format.
0000_0000 = No line is connected.
Rev. 1.5
83
Si3050 + Si3011/18/19
Register 30. AC Termination Control
Bit
D7
D6
D5
D4
D3
D2
D1
Name
FULL2
ACIM[3:0]
Type
R/W
R/W
D0
Reset settings = 0000_0000
Bit
Name
7:6
Reserved
Read returns zero.
5
Reserved
This bit may be written to a zero or one.
4
FULL2
3:0
Function
Enhanced Full Scale (2x) Transmit and Receive Mode.
0 = Default
1 = Transmit/Receive 2x Full Scale
This bit changes the full scale of the ADC and DAC from 0 min to +6 dBm into 600 load (or
1.5 dBV into all reference impedances). When this bit is set, the DCV[1:0] bits (Register 26)
should be set to all 1s to avoid distortion at low loop currents.
ACIM[3:0] AC Impedance Selection.
The off-hook ac termination is selected from the following:
0000 = 600
0001 = 900
0010 = 270 + (750 || 150 nF) and 275 + (780 || 150 nF)
0011 = 220 + (820 || 120 nF) and 220 + (820 || 115 nF)
0100 = 370 + (620 || 310 nF)
0101 = 320 + (1050 || 230 nF)
0110 = 370 + (820 || 110 nF)
0111 = 275 + (780 || 115 nF)
1000 = 120 + (820 || 110 nF)
1001 = 350 + (1000 || 210 nF)
1010 = 200 + (680 || 100 nF)
1011 = 600 + 2.16 µF
1100 = 900 + 1 µF
1101 = 900 + 2.16 µF
1110 = 600 + 1 µF
1111 = Global impedance
For si3011 line-side device, always write bits 3:2 and bit 0 to zero.
84
Rev. 1.5
Si3050 + Si3011/18/19
Register 31. DAA Control 5
Bit
D7
D6
D5
Name
FULL
FOH[1:0]
Type
R/W
RW
D4
D3
D2
D1
D0
0
OHS2
0
FILT
LVFD
R/W
R/W
R/W
Reset settings = 0010_0000
Bit
Name
Function
7
FULL
Full Scale Transmit and Receive Mode. Si3018 and Si3019 line-side only.
0 = Default.
1 = Transmit/receive full scale.
This bit changes the full scale of the ADC and DAC from 0 dBm min to +3.2 dBm into a 600
load (or 1 dBV into all reference impedances). When this bit is set, the DCV[1:0] bits
(Register 26) should be set to all 1s. The MINI[1:0] bits also should be set to all 0s. This ensures
correct operation of the full scale mode.
For Si3011 line-side device, always write this bit to zero.
6:5
4
3
2
FOH[1:0] Fast Off-Hook Selection.
These bits determine the length of the off-hook counter. The default setting is 128 ms.
00 = 512 ms
01 = 128 ms
10 = 64 ms
11 = 8 ms
Reserved Always write these bits to zero.
OHS2
On-Hook Speed 2.
This bit, in combination with the OHS bit (Register 16) and the SQ[1:0] bits on-hook speeds
specified are measured from the time the OH bit is cleared until loop current equals zero.
OHS
OHS2
SQ[1:0]
Mean On-Hook Speed
0
0
00
Less than 0.5 ms
0
1
00
3 ms ±10% (meets ETSI standard)
1
X
11
26 ms ±10% (meets Australia spark quenching spec)
Reserved Always write these bits to zero.
1
FILT
Filter Pole Selection.
0 = The receive path has a low –3 dBFS corner at 5 Hz.
1 = The receive path has a low –3 dBFS corner at 200 Hz.
0
LVFD
Line Voltage Force Disable (Si3011 and Si3019 line-side only).
0 = Normal operation.
1 = The circuitry that forces the LVS register (Register 29) to all 0s at 3 V or less is disabled. The
LVS register may display unpredictable values at voltages between 0 to 2 V. All 0s are displayed
if the line voltage is 0 V.
Rev. 1.5
85
Si3050 + Si3011/18/19
Register 32. Ground Start Control
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
TGD
TGDE
RG
Type
R
W
W
Reset settings = 0000_0x11
Bit
Name
Function
7:3
Reserved
Read returns zero.
2
TGD
TIP Ground Detect.
0 = The CO has grounded TIP, causing current to flow. When current ceases to flow, this bit
returns to a one.
1 = The CO has not grounded TIP causing current to flow.
1
TGDE
TIP Ground Detect Enable.
0 = The external relay connecting TIP to an isolated supply is closed, enabling current to flow
in TIP if the CO grounds TIP.
1 = The external relay connecting TIP to an isolated supply is open. In this state, the DAA is
unable to determine if the CO has grounded TIP.
0
RG
Ring Ground.
0 = The external relay connecting RING to ground is closed, causing current to flow in RING.
1 = The external relay connecting RING to ground is open, not allowing current to flow in
RING.
86
Rev. 1.5
Si3050 + Si3011/18/19
Register 33. PCM/SPI Mode Select
Bit
D7
Name
PCML
Type
R/W
D6
R/W
D5
D4
D3
D2
D1
D0
PCME
PCMF[1:0]
0
PHCF
TRI
R/W
R/W
R/W
R/W
R/W
Reset settings = 0000_0000
Bit
Name
Function
7
PCML
PCM Analog Loopback.
0 = Normal operation.
1 = Enables analog data to be received from the line, converted to digital data and transmitted across the ISOcap link. The data passes through the RX filter and is looped back
through the TX filter and is transmitted back out to the line.
5
PCME
PCM Enable (Registers 34–37 should be set before PCM transfers are enabled).
0 = Disable PCM transfers.
1 = Enable PCM transfers.
4:3
PCMF[1:0]
PCM Data Format.
00 = A-Law. Signed magnitude data format (refer to Table 23 on page 46).
01 = µ-Law. Signed magnitude data format (refer to Table 22 on page 45).
10 = 8-bit linear. The top 8-bits of the 16-bit linear signal are transferred, and the bottom
8-bits are discarded (2s complement data format).
11 = 16-bit linear (2s complement data format).
2
Reserved
Always write this bit to zero.
1
PHCF
0
TRI
PCM Highway Clock Format.
0 = 1 PCLK per data bit.
1 = 2 PCLKs per data bit.
Tri-state Bit 0.
0 = Tri-state bit 0 on positive edge of PCLK.
1 = Tri-state bit 0 on negative edge of PCLK.
Rev. 1.5
87
Si3050 + Si3011/18/19
Register 34. PCM Transmit Start Count—Low Byte
Bit
D7
D6
D5
D4
D3
Name
TXS[7:0]
Type
R/W
D2
D1
D0
Reset settings = 0000_0000
Bit
Name
Function
7:0
TXS[7:0]
PCM Transmit Start Count.
PCM Transmit Start Count equals the number of PCLKs following FSYNC before data
transmission begins.
Register 35. PCM Transmit Start Count—High Byte
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
TXS[1:0]
Type
R/W
Reset settings = 0000_0000
Bit
Name
Function
7:2
Reserved
Read returns zero.
1:0
TXS[1:0]
PCM Transmit Start Count.
PCM Transmit Start Count equals the number of PCLKs following FSYNC before data
transmission begins.
Register 36. PCM Receive Start Count—Low Byte
Bit
D7
D6
D5
D4
D3
Name
RXS[7:0]
Type
R/W
D2
D1
D0
Reset settings = 0000_0000
Bit
Name
7:0
RXS[7:0]
88
Function
PCM Receive Start Count.
PCM Receive Start Count equals the number of PCLKs following FSYNC before data
reception begins.
Rev. 1.5
Si3050 + Si3011/18/19
Register 37. PCM Receive Start Count—High Byte
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
RXS[1:0]
Type
R/W
Reset settings = 0000_0000
Bit
Name
Function
7:2
Reserved
Read returns zero.
1:0
RXS[1:0]
PCM Receive Start Count.
PCM Receive Start Count equals the number of PCLKs following FSYNC before data
reception begins.
Register 38. TX Gain Control 2
Bit
D7
D6
D5
D4
D3
D2
D1
Name
TGA2
TXG2[3:0]
Type
R/W
R/W
D0
Reset settings = 0000_0000
Bit
Name
7:5
Reserved
4
TGA2
3:0
Function
Read returns zero.
Transmit Gain or Attenuation 2.
0 = Incrementing the TXG2[3:0] bits results in gaining up the transmit path.
1 = Incrementing the TXG2[3:0] bits results in attenuating the transmit path.
TXG2[3:0] Transmit Gain 2.
Each bit increment represents 1 dB of gain or attenuation, up to a maximum of +12 dB and
–15 dB respectively.
For example:
TGA2
TXG2[3:0]
Result
X
0000
0 dB gain or attenuation is applied to the transmit path.
0
0001
1 dB gain is applied to the transmit path.
0
:
0
11xx
12 dB gain is applied to the transmit path.
1
0001
1 dB attenuation is applied to the transmit path.
1
:
1
1111
15 dB attenuation is applied to the transmit path.
Rev. 1.5
89
Si3050 + Si3011/18/19
Register 39. RX Gain Control 2
Bit
D7
D6
D5
D4
D3
D2
D1
Name
RGA2
RXG2[3:0]
Type
R/W
R/W
D0
Reset settings = 0000_0000
Bit
Name
7:5
Reserved
4
RGA2
3:0
90
Function
Read returns zero.
Receive Gain or Attenuation 2.
0 = Incrementing the RXG2[3:0] bits results in gaining up the receive path.
1 = Incrementing the RXG2[3:0] bits results in attenuating the receive path.
RXG2[3:0] Receive Gain 2.
Each bit increment represents 1 dB of gain or attenuation, up to a maximum of +12 dB and
–15 dB respectively.
For example:
RGA2
RXG2[3:0]
Result
X
0000
0 dB gain or attenuation is applied to the receive path.
0
0001
1 dB gain is applied to the receive path.
0
:
0
11xx
12 dB gain is applied to the receive path.
1
0001
1 dB attenuation is applied to the receive path.
1
:
1
1111
15 dB attenuation is applied to the receive path.
Rev. 1.5
Si3050 + Si3011/18/19
Register 40. TX Gain Control 3
Bit
D7
D6
D5
D4
D3
D2
D1
Name
TGA3
TXG3[3:0]
Type
R/W
R/W
D0
Reset settings = 0000_0000
Bit
Name
7:5
Reserved
4
TGA3
3:0
Function
Read returns zero.
Transmit Gain or Attenuation 3.
0 = Incrementing the TGA3[3:0] bits results in gaining up the transmit path.
1 = Incrementing the TGA3[3:0] bits results in attenuating the transmit path.
TXG3[3:0] Transmit Gain 3.
Each bit increment represents 0.1 dB of gain or attenuation, up to a maximum of 1.5 dB.
For example:
TGA3
TXG3[3:0]
Result
X
0000
0 dB gain or attenuation is applied to the transmit path.
0
0001
0.1 dB gain is applied to the transmit path.
0
:
0
1111
1.5 dB gain is applied to the transmit path.
1
0001
0.1 dB attenuation is applied to the transmit path.
1
:
1
1111
1.5 dB attenuation is applied to the transmit path.
Rev. 1.5
91
Si3050 + Si3011/18/19
Register 41. RX Gain Control 3
Bit
D7
D6
D5
D4
D3
D2
D1
Name
RGA3
RXG3[3:0]
Type
R/W
R/W
D0
Reset settings = 0000_0000
Bit
Name
7:5
Reserved
4
RGA3
3:0
92
Function
Read returns zero.
Receive Gain or Attenuation 2.
0 = Incrementing the RXG3[3:0] bits results in gaining up the receive path.
1 = Incrementing the RXG3[3:0] bits results in attenuating the receive path.
RXG3[3:0] Receive Gain 3.
Each bit increment represents 0.1 dB of gain or attenuation, up to a maximum of 1.5 dB.
For example:
RGA3
RXG3[3:0]
Result
X
0000
0 dB gain or attenuation is applied to the receive path.
0
0001
0.1 dB gain is applied to the receive path.
0
:
0
1111
1.5 dB gain is applied to the receive path.
1
0001
0.1 dB attenuation is applied to the receive path.
1
:
1
1111
1.5 dB attenuation is applied to the receive path.
Rev. 1.5
Si3050 + Si3011/18/19
Register 42. GCI Control
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
GCIF[1:0]
B2D
B1D
Type
R/W
R/W
R/W
Reset settings = 0000_0000
Bit
Name
Function
7:4
Reserved
Read returns zero.
3:2
GCIF[1:0]
GCI Data Format.
00 = A-Law.
01 = µ-Law.
10 = 8-bit linear. The top 8-bits of the 16-bit linear signal are transferred, and the bottom 8-bits
are discarded.
11 = 16-bit linear. B1 and B2 channels are used for the 16-bits of data. Regardless of whether
the DAA is set to transmit and receive in the B1 or B2 channel, both channels are used to
send and receive the 16-bit linear data.
1
B2D
Channel B2 Enable.
0 = Channel B2 transfers are disabled.
1 = Channel B2 transfers are enabled. If 16-bit linear data format is chosen, disabling the B2
channel results in only the top 8 bits of line data being sent and received in the B1 channel.
0
B1D
Channel B1 Enable.
0 = Channel B1 transfers are disabled.
1 = Channel B1 transfers are enabled. If 16-bit linear data format is chosen, disabling the B1
channel results in only the bottom 8 bits of line data being sent and received in the B2 channel.
Rev. 1.5
93
Si3050 + Si3011/18/19
Register 43. Line Current/Voltage Threshold Interrupt (Si3011 and Si3019 line-side only)
Bit
D7
D6
D5
D4
D3
Name
CVT[7:0]
Type
R/W
D2
D1
D0
Reset settings = 0000_0000
Bit
Name
7:0
CVT[7:0]
Function
Current/Voltage Threshold.
These bits determine the threshold at which an interrupt is generated from either the LCS or
LVS register. This interrupt can be generated to occur when the line current or line voltage
rises above or drops below the value in the CVT[7:0] register.
Register 44. Line Current/Voltage Threshold Interrupt Control (Si3011 and Si3019 line-side only)
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
CVI
CVS
CVM
CVP
Type
R/W
R/W
R/W
R/W
Reset settings = 0000_0000
Bit
Name
7:4
Reserved
3
CVI
Function
Read returns zero.
Current/Voltage Interrupt.
0 = The current/voltage threshold has not been crossed.
1 = The current/voltage threshold is crossed. If the CVM and INTE bits are set, a hardware
interrupt occurs on the AOUT/INT pin. Once set, this bit must be written to 0 to be cleared.
2
CVS
Current/Voltage Select.
0 = The line current shown in the LCS2 register is used to generate an interrupt.
1 = The line voltage shown in the LVS register is used to generate an interrupt.
1
CVM
Current/Voltage Interrupt Mask.
0 = The current/voltage threshold being triggered does not cause a hardware interrupt on the
AOUT/INT pin.
1 = The current/voltage threshold being triggered causes a hardware interrupt on the
AOUT/INT pin.
0
CVP
Current/Voltage Interrupt Polarity.
0 = The current/voltage threshold is triggered by the absolute value of the number in either
the LCS2 or LVS register falling below the value in the CVT[7:0] register.
1 = The current/voltage threshold is triggered by the absolute value of the number in either
the LCS2 or LVS register rising above the value in the CVT[7:0] register.
94
Rev. 1.5
Si3050 + Si3011/18/19
Register 45. Programmable Hybrid Register 1
Bit
D7
D6
D5
D4
D3
Name
HYB1[7:0]
Type
R/W
D2
D1
D0
Reset settings = 0000_0000
Bit
7:0
Name
Function
HYB1[7:0] Programmable Hybrid Register 1.
These bits can be programmed with a coefficient value to adjust the hybrid response to
reduce near-end echo. This register represents the first tap in the eight-tap filter. When this
register is set to all 0s, this filter stage does not have an effect on the hybrid response. See
the section entitled "5.28. Transhybrid Balance" on page 38 for more information on selecting
coefficients for the programmable hybrid.
Register 46. Programmable Hybrid Register 2
Bit
D7
D6
D5
D4
D3
Name
HYB2[7:0]
Type
R/W
D2
D1
D0
Reset settings = 0000_0000
Bit
7:0
Name
Function
HYB2[7:0] Programmable Hybrid Register 2.
These bits can be programmed with a coefficient value to adjust the hybrid response to
reduce near-end echo. This register represents the second tap in the eight-tap filter. When
this register is set to all 0s, this filter stage does not have an effect on the hybrid response.
See the section entitled "5.28. Transhybrid Balance" on page 38 for more information on
selecting coefficients for the programmable hybrid.
Rev. 1.5
95
Si3050 + Si3011/18/19
Register 47. Programmable Hybrid Register 3
Bit
D7
D6
D5
D4
D3
Name
HYB3[7:0]
Type
R/W
D2
D1
D0
Reset settings = 0000_0000
Bit
7:0
Name
Function
HYB3[7:0] Programmable Hybrid Register 3.
These bits can be programmed with a coefficient value to adjust the hybrid response to
reduce near-end echo. This register represents the third tap in the eight-tap filter. When this
register is set to all 0s, this filter stage does not have an effect on the hybrid response. See
the section entitled "5.28. Transhybrid Balance" on page 38 for more information on selecting
coefficients for the programmable hybrid.
Register 48. Programmable Hybrid Register 4
Bit
D7
D6
D5
D4
D3
Name
HYB4[7:0]
Type
R/W
D2
D1
D0
Reset settings = 0000_0000
Bit
7:0
Name
Function
HYB4[7:0] Programmable Hybrid Register 4.
These bits can be programmed with a coefficient value to adjust the hybrid response to
reduce near-end echo. This register represents the fourth tap in the eight-tap filter. When this
register is set to all 0s, this filter stage does not have an effect on the hybrid response. See
the section entitled "5.28. Transhybrid Balance" on page 38 for more information on selecting
coefficients for the programmable hybrid.
96
Rev. 1.5
Si3050 + Si3011/18/19
Register 49. Programmable Hybrid Register 5
Bit
D7
D6
D5
D4
D3
Name
HYB5[7:0]
Type
R/W
D2
D1
D0
Reset settings = 0000_0000
Bit
7:0
Name
Function
HYB5[7:0] Programmable Hybrid Register 5.
These bits can be programmed with a coefficient value to adjust the hybrid response to
reduce near-end echo. This register represents the fifth tap in the eight-tap filter. When this
register is set to all 0s, this filter stage does not have an effect on the hybrid response. See
the section entitled "5.28. Transhybrid Balance" on page 38 for more information on selecting
coefficients for the programmable hybrid.
Register 50. Programmable Hybrid Register 6
Bit
D7
D6
D5
D4
D3
Name
HYB6[7:0]
Type
R/W
D2
D1
D0
Reset settings = 0000_0000
Bit
7:0
Name
Function
HYB6[7:0] Programmable Hybrid Register 6.
These bits can be programmed with a coefficient value to adjust the hybrid response to
reduce near-end echo. This register represents the sixth tap in the eight-tap filter. When this
register is set to all 0s, this filter stage does not have an effect on the hybrid response. See
the section entitled "5.28. Transhybrid Balance" on page 38 for more information on selecting
coefficients for the programmable hybrid.
Rev. 1.5
97
Si3050 + Si3011/18/19
Register 51. Programmable Hybrid Register 7
Bit
D7
D6
D5
D4
D3
Name
HYB7[7:0]
Type
R/W
D2
D1
D0
Reset settings = 0000_0000
Bit
Name
Function
HYB7[7:0] Programmable Hybrid Register 7.
7:0
These bits can be programmed with a coefficient value to adjust the hybrid response to
reduce near-end echo. This register represents the seventh tap in the eight-tap filter. When
this register is set to all 0s, this filter stage does not have an effect on the hybrid response.
See the section entitled "5.28. Transhybrid Balance" on page 38 for more information on
selecting coefficients for the programmable hybrid.
Register 52. Programmable Hybrid Register 8
Bit
D7
D6
D5
D4
D3
Name
HYB8[7:0]
Type
R/W
D2
D1
D0
Reset settings = 0000_0000
Bit
Name
Function
HYB8[7:0] Programmable Hybrid Register 8.
7:0
These bits can be programmed with a coefficient value to adjust the hybrid response to
reduce near-end echo. This register represents the eighth tap in the eight-tap filter. When this
register is set to all 0s, this filter stage does not have an effect on the hybrid response. See
the section entitled "5.28. Transhybrid Balance" on page 38 for more information on selecting
coefficients for the programmable hybrid.
Register 53-58. Reserved
Bit
D7
D6
D5
D4
D3
Name
Type
Reset settings = xxxx_xxxx
Bit
7:0
98
Name
Function
Reserved Do not write to these register bits.
Rev. 1.5
D2
D1
D0
Si3050 + Si3011/18/19
Register 59. Spark Quenching Control
Bit
D7
D6
D5
D4
D3
D2
D1
Name
SQ1
SQ0
RG1
GCE
Type
R/W
R/W
R/W
R/W
D0
Reset settings = xxxx_xxxx
Bit
7
6
Name
Function
Reserved Always write this bit to zero.
SQ1
Spark Quenching. Si3018 and Si3019 line-side only.
This bit, in combination with the OHS bit (Register 16), and the OHS2 bit (Register 31), sets
the amount of time for the line-side device to go on-hook. The on-hook speeds specified are
measured from the time the OH bit is cleared until loop current equals zero.
OHS
OHS2
SQ[1:0]
Mean On-Hook Speed
0
0
00
Less than 0.5 ms
0
1
00
3 ms±10% (meets ETSI standard)
1
X
11
26 ms ±10% (meets Australia spark quenching spec)
For Si3011 line-side device, always write this bit to zero.
5
4
3
Reserved Always write this bit to zero.
SQ0
Spark Quenching. Si3018 and Si3019 line-side only.
This bit, in combination with the OHS bit (Register 16), and the OHS2 bit (Register 31), sets
the amount of time for the line-side device to go on-hook. The on-hook speeds specified are
measured from the time the OH bit is cleared until loop current equals zero.
OHS
OHS2
SQ[1:0]
Mean On-Hook Speed
0
0
00
Less than 0.5 ms
0
1
00
3 ms±10% (meets ETSI standard)
1
X
11
26 ms ±10% (meets Australia spark quenching spec)
For Si3011 line-side device, always write this bit to zero.
Reserved Always write this bit to zero.
2
RG1
Receive Gain 1 (Line-side Revision E or later).
This bit enables receive path gain adjustment.
0 = No gain applied to hybrid, full scale RX on line = 0 dBm.
1 = 1 dB of gain applied to hybrid, full scale RX on line = –1 dBm.
1
GCE
Guarded Clear Enable (Line-side Revision E or later).
This bit (in conjunction with the R2 bit set to 1) enables the Si3050 to meet BT’s Guarded
Clear Spec (B5 6450, Part 1: 1993, Section 15.4.3.3). With these bits set, the DAA will draw
approximately 2.5 mA of current from the line while on-hook.
0 = Default, DAA does not draw loop current.
1 = Guarded Clear enabled, DAA draws 2.5 mA while on-hook to meet Guarded Clear
requirement.
0
Reserved Always write this bit to zero.
Rev. 1.5
99
SDI
SDO
NC
NC
SDITHRU
SCLK
24
23
22
21
20
19
Si3050 + Si3011/18/19
CS
1
18
GND
FSYNC
2
17
VDD
PCKLK
3
16
VA
DTX
4
15
C1A
DRX
5
14
C2A
RGDT
6
13
RESET
Si3050
Top View
12
TGDE
10
NC
11
9
NC
TGD
8
RG
AOUT/INT
7
GND
Figure 50. Si3050 QFN
SDO
SDI
CS
FSYNC
PCLK
DTX
DRX
RGDT
AOUT/INT
RG
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
13
12
11
10
SDITHRU
SCLK
GND
VDD
VA
C1A
C2A
RESET
TGDE
TGD
Figure 51. Si3050 TSSOP
100
Rev. 1.5
Si3050 + Si3011/18/19
Table 26. Si3050 Pin Descriptions
QFN
Pin #
TSSOP
Pin #
Pin Name
23
1
SDO
Serial Port Data Output.
Serial port control data output.
24
2
SDI
Serial Port Data Input.
Serial port control data input.
1
3
CS
Chip Select Input.
An active low input control signal that enables the SPI Serial port. When
inactive, SCLK and SDI are ignored and SDO is high impedance.
2
4
FSYNC
3
5
PCLK
4
6
DTX
Transmit PCM or GCI Highway Data Output.
Outputs data from either the PCM or GCI highway bus.
5
7
DRX
Receive PCM or GCI Highway Data Input.
Receives data from either the PCM or GCI highway bus.
6
8
RGDT
Ring Detect Output.
Produces an active low rectified version of the ring signal.
7
9
AOUT/INT
Analog Speaker Output/Interrupt Output.
Provides an analog output signal for driving a call progress speaker in AOUT
mode. Alternatively, this pin can be set to provide a hardware interrupt signal.
8
10
RG
Ring Ground Output.
Control signal for ring ground relay. Used to support ground start applications.
9
NC
No connect.
10
NC
No connect.
Description
Frame Sync Input.
Data framing signal that is used to indicate the start and stop of a
communication/data frame.
Master Clock Input.
Master clock input.
11
11
TGD
TIP Ground Detect Input.
Used to detect current flowing in TIP for supporting ground start applications.
12
12
TGDE
TIP Ground Detect Enable Output.
Control signal for the ground detect relay. Used to support ground start applications.
13
13
RESET
Reset Input.
An active low input that is used to reset all control registers to a defined,
initialized state. Also used to bring the Si3050 out of sleep mode.
Rev. 1.5
101
Si3050 + Si3011/18/19
Table 26. Si3050 Pin Descriptions (Continued)
QFN
Pin #
TSSOP
Pin #
Pin Name
Description
14
14
C2A
Isolation Capacitor 2A.
Connects to one side of the isolation capacitor C2. Used to communicate with
the line-side device.
15
15
C1A
Isolation Capacitor 1A.
Connects to one side of the isolation capacitor C1. Used to communicate with
the line-side device.
16
16
VA
Regulator Voltage Reference.
This pin connects to an external capacitor and serves as the reference for the
internal voltage regulator.
17
17
VDD
Digital Supply Voltage.
Provides the 3.3 V digital supply voltage to the Si3050.
18
18
GND
Ground.
Connects to the system digital ground.
19
19
SCLK
Serial Port Bit Clock Input.
Controls the serial data on SDO and latches the data on SDI.
20
20
SDITHRU
SDI Passthrough Output.
Cascaded SDI output signal to daisy-chain the SPI interface with additional
devices.
21
NC
No connect.
22
NC
No connect.
102
Rev. 1.5
Si3050 + Si3011/18/19
C2B
5
NC
4
IGND
C1B
18
17
16
15 DCT3
14 QB
IGND
PAD
13 QE2
12 SC
VREG
6
7
8
9
10
11 NC
VREG2
3
DCT2
IB
19
RNG2
2
QE
RX
20
IGND
1
RNG1
NC
DCT
7. Pin Descriptions: Si3011/18/19
Figure 52. Si3011/18/19 QFN
QE
DCT
RX
IB
C1B
C2B
VREG
RNG1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
DCT2
IGND
DCT3
QB
QE2
SC
VREG2
RNG2
Figure 53. Si3011/18/19 SOIC/TSSOP
Rev. 1.5
103
Si3050 + Si3011/18/19
Table 27. Si3011/18/19 Pin Descriptions
QFN
Pin #
SOIC/
TSSOP Pin Name
Pin #
1
NC
No connect.
Transistor Emitter.
Connects to the emitter of Q3.
19
1
QE
20
2
DCT
2
3
RX
Receive Input.
Serves as the receive side input from the telephone network.
3
4
IB
Internal Bias.
Provides a bias voltage to the device.
4
5
C1B
Isolation Capacitor 1B.
Connects to one side of isolation capacitor C1. Used to communicate with the
system-side device.
5
6
C2B
Isolation Capacitor 2B.
Connects to one side of isolation capacitor C2. Used to communicate with the
system-side device.
6
7
VREG
Voltage Regulator.
Connects to an external capacitor to provide bypassing for an internal power supply.
7
8
RNG1
Ring 1.
Connects through a resistor to the TIP lead of the telephone line. Provides the ring
and caller ID signals to the DAA.
IGND
Isolated Ground. Connects to ground on the line-side interface.
8
DC Termination.
Provides dc termination to the telephone network.
9
9
RNG2
Ring 2.
Connects through a resistor to the RING lead of the telephone line. Provides the
ring and caller ID signals to the DAA.
10
10
VREG2
Voltage Regulator 2.
Connects to an external capacitor to provide bypassing for an internal power supply.
11
104
Description
NC
No connect.
SC Connection.
Enables external transistor network. Should be tied through a 0 resistor to IGND.
12
11
SC
13
12
QE2
14
13
QB
15
14
DCT3
Transistor Emitter 2.
Connects to the emitter of Q4.
Transistor Base.
Connects to the base of transistor Q4.
DC Termination 3.
Provides dc termination to the telephone network.
Rev. 1.5
Si3050 + Si3011/18/19
Table 27. Si3011/18/19 Pin Descriptions (Continued)
QFN
Pin #
SOIC/
TSSOP Pin Name
Pin #
16
NC
Description
No Connect.
17
15
IGND
Isolated Ground.
Connects to ground on the line-side interface.
18
16
DCT2
DC Termination 2.
Provides dc termination to the telephone network.
Rev. 1.5
105
Si3050 + Si3011/18/19
8. Ordering Guide
Part Number1
Description
AC
Terminations
Package2
Temperature
Range
Si3050-E1-FT
System-side Voice DAA
2, 4, 16
TSSOP-20
0 to +70 °C
Si3050-E1-GT
System-side Voice DAA
2, 4, 16
TSSOP-20
–40 to +85 °C
Si3050-E1-FM
System-side Voice DAA
2, 4, 16
QFN-24
0 to +70 °C
Si3050-E1-GM
System-side Voice DAA
2, 4, 16
QFN-24
–40 to +85 °C
Si3011-F-FS
Line-side Voice DAA-FCC/TBR21 only
2
SOIC-16
0 to +70 °C
Si3011-F-GS
Line-side Voice DAA-FCC/TBR21 only
2
SOIC-16
–40 to +85 °C
Si3011-F-FT
Line-side Voice DAA-FCC/TBR21 only
2
TSSOP-16
0 to +70 °C
Si3011-F-GT
Line-side Voice DAA-FCC/TBR21 only
2
TSSOP-16
–40 to +85 °C
Si3011-F-FM
Line-side Voice DAA-FCC/TBR21 only
2
QFN-20
0 to +70 °C
Si3011-F-GM
Line-side Voice DAA-FCC/TBR21 only
2
QFN-20
–40 to +85 °C
Si3018-F-FS
Line-side Voice DAA-Global
4
SOIC-16
0 to +70 °C
Si3018-F-GS
Line-side Voice DAA-Global
4
SOIC-16
–40 to +85 °C
Si3018-F-FT
Line-side Voice DAA-Global
4
TSSOP-16
0 to +70 °C
Si3018-F-GT
Line-side Voice DAA-Global
4
TSSOP-16
–40 to +85 °C
Si3018-F-FM
Line-side Voice DAA-Global
4
QFN-20
0 to +70 °C
Si3018-F-GM
Line-side Voice DAA-Global
4
QFN-20
–40 to +85 °C
Si3019-F-FS
Line-side Voice DAA-Enhanced Global
16
SOIC-16
0 to +70 °C
Si3019-F-GS
Line-side Voice DAA-Enhanced Global
16
SOIC-16
–40 to +85 °C
Si3019-F-FT
Line-side Voice DAA-Enhanced Global
16
TSSOP-16
0 to +70 °C
Si3019-F-GT
Line-side Voice DAA-Enhanced Global
16
TSSOP-16
–40 to +85 °C
Si3019-F-FM
Line-side Voice DAA-Enhanced Global
16
QFN-20
0 to +70 °C
Si3019-F-GM
Line-side Voice DAA-Enhanced Global
16
QFN-20
–40 to +85 °C
Notes:
1. Adding the suffix “R” to the end of the part number (e.g., Si3050-E1-FTR) denotes tape-and-reel packaging.
2. All packages are RoHS-compliant.
106
Rev. 1.5
Si3050 + Si3011/18/19
9. Product Identification
The product identification number is a finished goods part number or is specified by a finished goods part number,
such as a special customer part number.
Example:
Si3050-E1-FSR
Product Designator
Product Revision
Shipping Option
Blank = Tubes
R = Tape and Reel
Package Type
S = SOIC
T = TSSOP
M = QFN
Part Type/Lead Finish
F = Commercial/Lead-Free
G = Industrial Temp/Lead-Free
Rev. 1.5
107
Si3050 + Si3011/18/19
10. Package Outline: 20-Pin TSSOP
Figure 54 illustrates the package details for the Si3050. Table 28 lists the values for the dimensions shown in the
illustration.
Figure 54. 20-Pin Thin Shrink Small Outline Package (TSSOP)
108
Rev. 1.5
Si3050 + Si3011/18/19
‘
Table 28. 20-Pin TSSOP Package Diagram Dimensions
Dimension
Min
Nom
Max
A
—
—
1.20
A1
0.05
—
0.15
A2
0.80
1.00
1.05
b
0.19
—
0.30
c
0.09
—
0.20
D
6.40
6.50
6.60
E
E1
6.40 BSC
4.40
4.40
e
L
0.65 BSC
0.45
0.60
L2
θ
4.50
0.75
0.25 BSC
0°
—
aaa
0.10
bbb
0.10
ccc
0.20
8°
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-153, Variation AC.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C
specification for Small Body Components.
Rev. 1.5
109
Si3050 + Si3011/18/19
10.1. PCB Land Pattern: Si3050 TSSOP
Figure 55. 20-Pin Thin Shrink Small Outline Package (TSSOP) PCB Land Pattern
Table 29. 20-Pin Thin Shrink Small Outline Package (TSSOP) PCB Land Pattern Dimensions
Dimension
C1
Feature
(mm)
Pad Column Spacing
5.80
E
Pad Row Pitch
0.65
X1
Pad Width
0.45
Y1
Pad Length
1.40
Notes:
1. This Land Pattern Design is based on IPC-7351
specifications for Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition
(MMC) and a card fabrication tolerance of 0.05 mm is
assumed.
110
Rev. 1.5
Si3050 + Si3011/18/19
11. Package Outline: 24-Pin QFN
Figure 56 illustrates the package details for the Si3050. Table 30 lists the values for the dimensions shown in the
illustration.
Figure 56. 24-Pin QFN Package
Rev. 1.5
111
Si3050 + Si3011/18/19
Table 30. 24-Pin QFN Package Dimensions
Dimension
MIN
NOM
MAX
A
0.80
—
—
A1
0.00
—
—
b
0.18
—
—
D
D2
112
4.00 BSC
2.05
2.20
e
0.50 BSC
E
4.00 BSC
2.35
E2
2.35
2.50
2.65
L
0.30
0.40
0.50
aaa
0.10
bbb
0.10
ccc
0.08
ddd
0.10
eee
0.05
Rev. 1.5
Si3050 + Si3011/18/19
12. PCB Land Pattern: Si3050 QFN
Figure 57. 24-Pin Quad Flat No-Lead (QFN) PCB Land Pattern
Rev. 1.5
113
Si3050 + Si3011/18/19
Table 31. 24-Pin Quad Flat No-Lead (QFN) PCB Land Pattern Dimensions
Symbol
MIN
NOM
MAX
P1
2.10
2.20
2.30
P2
2.10
2.20
2.30
X1
0.20
0.25
0.30
Y1
0.75
0.80
0.85
C1
3.90
C2
3.90
E
0.50
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on the IPC-7351 guidelines.
Solder mask design
1. All metal pads are to be non-solder mask defined (NSMD). Clearance
between the solder mask and the metal pad is to be 60 mm minimum, all the
way around the pad.
Stencil Design
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls
should be used to assure good solder paste release.
2. The stencil thickness should be 0.125mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter
pins.
4. A 2 x 2 array of 0.90 mm square openings on 1.20 mm pitch should be used
for the center ground pad.
Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020
specification for Small Body Components.
114
Rev. 1.5
Si3050 + Si3011/18/19
13. Package Outline: 16-Pin SOIC
Figure 58 illustrates the package details for the Si3011/18/19. Table 32 lists the values for the dimensions shown in
the illustration.
Figure 58. 16-Pin Small Outline Integrated Circuit (SOIC) Package
Rev. 1.5
115
Si3050 + Si3011/18/19
Table 32. 16-Pin SOIC Package Diagram Dimensions
Dimension
Min
Max
A
—
1.75
A1
0.10
0.25
A2
1.25
—
b
0.31
0.51
c
0.17
0.25
D
9.90 BSC
E
6.00 BSC
E1
3.90 BSC
e
1.27 BSC
L
0.40
L2
1.27
0.25 BSC
h
0.25
0.50
θ
0°
8°
aaa
0.10
bbb
0.20
ccc
0.10
ddd
0.25
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MS-012, Variation AC.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020
specification for Small Body Components.
116
Rev. 1.5
Si3050 + Si3011/18/19
13.1. PCB Land Pattern: Si3011/18/19 SOIC
Figure 59. 16-Pin Small Outline Integrated Circuit (SOIC) PCB Land Pattern
Table 33. 16-Pin Small Outline Integrated Circuit (SOIC) PCB Land Pattern Dimensions
Dimension
Feature
(mm)
Pad Column Spacing
5.40
E
Pad Row Pitch
1.27
X1
Pad Width
0.60
Y1
Pad Length
1.55
C1
Notes:
1. This Land Pattern Design is based on IPC-7351 pattern
SOIC127P600X165-16N for Density Level B (Median Land
Protrusion).
2. All feature sizes shown are at Maximum Material Condition
(MMC) and a card fabrication tolerance of 0.05 mm is
assumed.
Rev. 1.5
117
Si3050 + Si3011/18/19
14. Package Outline: 16-Pin TSSOP
Figure 60 illustrates the package details for the Si3011/18/19. Table 34 lists the values for the dimensions shown in
the illustration.
Figure 60. 16-Pin Thin Shrink Small Outline Package (TSSOP)
118
Rev. 1.5
Si3050 + Si3011/18/19
Table 34. 16-Pin TSSOP Package Diagram Dimensions
Dimension
Min
Nom
Max
A
—
—
1.20
A1
0.05
—
0.15
A2
0.80
1.00
1.05
b
0.19
—
0.30
c
0.09
—
0.20
D
4.90
5.00
5.10
E
E1
6.40 BSC
4.40
4.40
e
L
0.65 BSC
0.45
0.60
L2
θ
4.50
0.75
0.25 BSC
0°
—
aaa
0.10
bbb
0.10
ccc
0.20
8°
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-153, Variation AB.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification
for Small Body Components.
Rev. 1.5
119
Si3050 + Si3011/18/19
14.1. PCB Land Pattern: Si3011/18/19 TSSOP
Figure 61. 16-Pin Thin Shrink Small Outline Package (TSSOP) PCB Land Pattern
Table 35. 16-Pin Thin Shrink Small Outline Package (TSSOP) PCB Land Patten Dimensions
Dimension
C1
Feature
(mm)
Pad Column Spacing
5.80
E
Pad Row Pitch
0.65
X1
Pad Width
0.45
Y1
Pad Length
1.40
Notes:
1. This Land Pattern Design is based on IPC-7351
specifications for Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition
(MMC) and a card fabrication tolerance of 0.05 mm is
assumed.
120
Rev. 1.5
Si3050 + Si3011/18/19
15. Package Outline: 20-Pin QFN
Figure 62 illustrates the package details for the Si3011/18/19. Table 36 lists the values for the dimensions shown in
the illustration.
Figure 62. 20-Pin Quad Flat No-Lead (QFN) Package
Rev. 1.5
121
Si3050 + Si3011/18/19
Table 36. 20-Pin QFN Package Diagram Dimensions
Dimension
MIN
NOM
MAX
A
0.80
0.85
—
A1
0.00
0.02
—
b
0.20
0.25
—
c
0.27
0.32
—
D
D2
3.00 BSC
1.65
1.70
e
.50 BSC
E
3.00 BSC
E2
1.65
f
1.70
1.75
2.53 BSC
L
0.35
0.40
0.45
L1
0.00
—
0.10
aaa
—
—
0.05
bbb
—
—
0.05
ccc
—
—
0.08
ddd
—
—
0.10
eee
—
—
0.10
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
122
1.75
Rev. 1.5
Si3050 + Si3011/18/19
16. PCB Land Pattern: Si3011/18/19 QFN
Figure 63. 20-Pin Quad Flat No-Lead (QFN) PCB Land Pattern
Rev. 1.5
123
Si3050 + Si3011/18/19
Table 37. 20-Pin Quad Flat No-Lead (QFN) PCB Land Pattern Dimensions
Dimension
MIN
MAX
D
D2
2.71 REF
1.60
1.80
e
0.50 BSC
E
2.71 REF
E2
1.60
1.80
f
2.53 BSC
GD
2.10
—
GE
2.10
—
W
—
0.34
X
—
0.28
Y
0.61 REF
ZE
—
3.31
ZD
—
3.31
Notes:
General
1. All dimensions shown are in milllimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on IPC-SM-782 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material
Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm.
Solder Mask Design
1. All pads are to be non-solder mask defined (NSMD). Clearance between the solder
mask and the metal pad is to be 60 m minimum, all the way around the pad.
Stencil Design
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be
used to assure good solder paste release.
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads.
4. A 1.45 x 1.45 mm square aperture should be used for the center pad. This provides
approximately 70% solder paste coverage on the pad, which is optimum to assure
correct component stand-off.
Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification
for Small Body Components.
124
Rev. 1.5
Si3050 + Si3011/18/19
SILICON LABS Si3050 SUPPORT DOCUMENTATION
AN30: Ground Start Implementation with Silicon Laboratories’ DAAs
AN67: Layout Guidelines
AN72: Ring Detection/Validation with the Si305x DAAs
AN84: Digital Hybrid with the Si305x DAAs
Si3050PPT-EVB Data Sheet
Note: Refer to www.silabs.com for a current list of support documents for this chipset.
Rev. 1.5
125
Si3050 + Si3011/18/19
DOCUMENT CHANGE LIST
Revision 1.2 to Revision 1.3
Revision 1.01 to Revision 1.1
Added package thermal information in Table 1,
“Recommended Operating Conditions and Thermal
Information,” on page 5.
Added Note 10 to the transhybrid balance parameter
in Table 4 on page 8.
Updated Table 7, “Switching Characteristics—Serial
Peripheral Interface,” on page 11.
Removed R54 and R55 from " " on page 18.
Changed recommended DCV setting for Japan from
01 to 10 in Table 13 on page 22.
Updated initialization procedure in "5.3. Initialization"
on page 25.
Removed incorrect description of FDT bit in "5.8.
Exception Handling" on page 27.
Updated Billing Tone and Receive Overload section.
Changed to "5.22. Receive Overload Detection" on
page 35.
Updated text and added description of hybrid
coefficient format in "5.28. Transhybrid Balance" on
page 38.
Removed references to line-side revisions C and E.
Updated "8. Ordering Guide" on page 106.
Updated package information for 20-Pin TSSOP and
16-Pin SOIC on pages 103 and 104.
Added “14.Package Outline: 16-Pin TSSOP”.
Revision 1.1 to Revision 1.31
Si3050 part numbers to reflect the latest
product revision level.
delay time between chip selects.
Step 6 with standard hexadecimal notation.
Updated Figure 27, “Si3011/18/19 Signal Flow
Diagram,” on page 38.
Corrected
ACIM settings for Brazil.
Updated "5.3. Initialization" on page 25.
Revised
HPF pole.
Updated "8. Ordering Guide" on page 106.
126
Updated "3. Bill of Materials" on page 19.
Updated "8. Ordering Guide" on page 106.
Updated
Updated Table 13, “Country-specific Register
Settings,” on page 22.
Corrected
Added Si3011 device specifications
Added Si3050, Si3011, Si3018, and Si3019 QFN
information
Revision 1.4 to Revision 1.5
Updated Table 7, “Switching Characteristics—Serial
Peripheral Interface,” on page 11.
Updated
The internal System-Side Revision value (REVA[3:0]
in Register 11) has been incremented by one for
Si3050 revision E.
Revision 1.31 to Revision 1.4
Revision 1.1 to Revision 1.2
Updated Deep Sleep Total Supply Current from 1.0
to 1.3 mA typical
Updated package pictures
Removed all SPIM references (SPIM bit is never
present in any Si3050 device).
Removed SnPb package options
Minor typo corrections
Rev. 1.5
Corrected Si3011 bit settings for Register 26 [7:6
and 5:4].
Si3050 + Si3011/18/19
NOTES:
Rev. 1.5
127
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using or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific
device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Laboratories
reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy
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