SI3225-KQ

Si3220/Si3225 P R E L I M I N A R Y D A TA S H E E T D U A L P R O SLIC™ P R O G R A M M A B L E C M O S S L I C / C O D E C Features ! ! ! ! ! ! ! Performs all BORSCHT functions ! Ideal for applications up to 18 kft ! Internal balanced ringing to 65 Vrms ! (Si3220) ! External bulk ringer support (Si3225) ! Low standby power consumption: ! 61 mA will disable threshold detection. Ground Key Detection LONGLPF = [(2πf x 4096)/800] Ground Key detection detects an alerting signal from the terminal equipment during the Active linefeed state (forward or reverse polarity). The functional blocks required to implement a Ground Key detector are shown in Figure 21, and the register set for detecting a ground key event is provided in Table 22. The primary input to the system is the Longitudinal Current Sense value provided by the voltage/current/power monitoring circuitry and reported in the ILONG RAM address. The ILONG value is processed in the ISP provided the LFS bits in the Linefeed register indicate the device is in an Active state. The output of the ISP is the input to a programmable digital low-pass filter, which removes unwanted ac signal components before threshold detection. Where f = the desired cutoff frequency of the filter. The low-pass filter coefficient is calculated using the equation below and is entered into the LONGLPF RAM location. ILONG Input Signal Processor Digital LPF The programmable range of the filter is from 0 (blocks all signals) to 4000h (unfiltered). A typical value of 10 Hz (0A10h) is sufficient to filter out any unwanted ac artifacts while allowing the dc information to pass through the filter. The output of the low-pass filter is compared to the programmable threshold, LONGHITH. Hysteresis is enabled by programming a second threshold, LONGLOTH, to detect when the ground key is released. The threshold comparator output feeds a programmable debounce filter. The output of the debounce filter remains in its present state unless the input remains in the opposite state for the entire period of time programmed by the loop closure debounce interval, LONGDBI. If the debounce interval is satisfied, the LONGHI bit is set to indicate that a valid loop closure has occurred. + Debounce Filter LONGHI – LONGLPF LONGDBI LFS Interrupt Logic LONGS Ground Key Threshold LONGE LONGHITH LONGLOTH Figure 21. Ground Key Detection Circuitry Preliminary Rev. 0.91 37 Si3220/Si3225 Table 22. Register and RAM Locations Used for Ground Key Detection Parameter Register/ RAM Mnemonics Register/RAM Bits Programmable Range LSB Size Resolution Ground Key Interrupt Pending IRQVEC2 LONGS Yes/No N/A N/A Ground Key Interrupt Enable IRQEN2 LONGE Yes/No N/A N/A Ground Key Linefeed Shadow LINEFEED LFS[2:0] Monitor only N/A N/A Ground Key Detect Status LCRRTP LONGHI Monitor only N/A N/A Ground Key Detect Debounce Interval LONGDBI LONGDBI[15:0] 0 to 40.96 s 1.25 ms 1.25 ms ILONG ILONG[15:0] Monitor only Ground Key Threshold (enabled) LONGHITH LONGHITH[15:0] 0 to 101.09 mA* 3.097 µA 396.4 µA Ground Key Threshold (released) LONGLOTH LONGLOTH[15:0] 0 to 101.09 mA* 3.097 µA 396.4 µA LONGLPF LONGLPF[15:3] 0 to 4000h N/A N/A Longitudinal Current Sense Ground Key Filter Coefficient See Table 19 *Note: The usable range for LONGHITH and LONGLOTH is limited to 16 mA. Setting a value > 16 mA will disable threshold detection. Automatic Dual Battery Switching The Dual ProSLIC chipsets provide the ability to switch between several user-provided battery supplies to aid thermal management. Two specific scenarios where this method may be required are as follows: ! Ringing to off-hook state transition (Si3220): During the on-hook operating state, the Dual ProSLIC chipset must operate from the ringing battery supply to provide the desired ringing signal when required. Once an off-hook condition is detected, the Dual ProSLIC chipset must transition to the lower battery supply, typically –24 V, to reduce power dissipation during the active state. The low current consumed by the Dual ProSLIC chipset during the on-hook state results in very little power dissipation while being powered from the ringing battery supply, which can have an amplitude as high as –100 V depending on the desired ringing amplitude. ! On-hook to off-hook state, short loop feed (Si3225): When sourcing both long and short loop lengths, the Dual ProSLIC chipset can automatically switch from the typical –48 V off-hook battery supply to a lower off-hook battery supply (e.g., –24 V) to 38 reduce the total off-hook power dissipation. The Dual ProSLIC chipset continuously monitors the TIPRING voltage and selects the lowest battery voltage required to power the loop when transitioning from the on-hook to the off-hook state, thus assuring the lowest power dissipation. The BATSELa and BATSELb pins switch between the two battery voltages based on the operating state and the TIP-RING voltage. Figure 22 illustrates the chip connections required to implement an automatic dual battery switching scheme. When BATSEL is pulled LOW, the desired channel is powered from the VBATL supply. When BATSEL is pulled HIGH, the VBATH source supplies power to the desired channel. The BATSEL pins for both channels are controlled using the BATSEL bit of the RLYCON register and can be programmed to automatically switch to the lower battery supply (VBATL) when the off-hook TIP-RING voltage is low enough to allow proper operation from the lower supply. When using the Si3220, this mode should always be enabled to allow seamless switching between the ringing and off-hook states. The same switching scheme is used with the Si3225 to reduce power by switching to a lower off-hook battery when sourcing a short loop. Preliminary Rev. 0.91 Si3220/Si3225 Two thresholds are provided to enable battery switching with hysteresis. The BATHTH RAM location specifies the threshold at which the Dual ProSLIC device switches from the low battery (VBATL) to the high battery (VBATH) due to an off-hook to on-hook transition. The BATLTH RAM location specifies the threshold at which the Si3220/Si3225 switches from VBATH to VBATL due to a transition from the on-hook or ringing state to the offhook state or because the overhead during active OffHook mode is sufficient to feed the subscriber loop using a lower battery voltage. The low pass filter coefficient is calculated using the equation below and is entered into the BATLPF RAM location. BATLPF = [(2πf x 4096)/800] Where f = the desired cutoff frequency of the filter The programmable range of the filter is from 0 (blocks all signals) to 4000h (unfiltered). A typical value of 10 Hz (0A10h) is sufficient to filter out any unwanted ac artifacts while allowing the dc information to pass through the filter. Table 23 provides the register and RAM locations used for programming the battery switching functions. Table 23. Register and RAM Locations Used for Battery Switching Parameter Register/RAM Mnemonic Register/RAM Bits Programmable Range Resolution (LSB Size) Battery Select Switch RLYCON BATSEL Toggle N/A High Battery Detect Threshold BATHTH BATHTH[14:7] 0 to 160.173 V* 628 mV (4.907 mV) Low Battery Detect Threshold BATLTH BATLTH[14:7] 0 to 160.173 V* 628 mV (4.907 mV) Ringing Battery Switch (Si3220 only) RLYCON GPO Toggle N/A Battery Select Indicator RLYCON BSEL Toggle N/A Battery Switching LPF BATLPF BATLPF[15:3] 0 to 4000h N/A *Note: Usable range for BATHTH and BATLTH is limited to VBATH. Si3220 Si3225 SVBAT Battery Control Logic Battery Sense Circuit BATSEL 40.2 kΩ 806 kΩ Si3200 Linefeed Circuitry VBATL BATSEL Battery Select Control VBATL VBAT VBATH VBATH Figure 22. External Battery Switching Using the Si3220/Si3225 Preliminary Rev. 0.91 39 Si3220/Si3225 When generating a high-voltage ringing amplitude using the Si3220, the power dissipated during the OHT state typically increases due to operating from the ringing battery supply in this mode. To reduce power, the Si3220/Si3200 chipset provides the ability to accommodate up to three separate battery supplies by implementing a secondary battery switch using a few low-cost external components as illustrated in Figure 22. The Si3220’s BATSEL pin is used to switch between the VBATH (typically –48 V) and VBATL (typically –24 V) rails using the switch internal to the Si3200. The Si3220’s GPO pin is used along with the external transistor circuit to switch the VRING rail (the ringing voltage battery rail) onto the Si3200’s VBAT pin when ringing is enabled. The GPO signal is driven automatically by the ringing cadence provided that the RRAIL bit of the RLYCON register is set to 1 (signifying that a third battery rail is present). Table 24. 3-Battery Switching Components Component Value Comments R102 10 kΩ,1/10 W, ± 5% R103 402 kΩ,1/10 W,± 1% Ringing Generation The Si3220-based Dual ProSLIC chipset provides a balanced ringing waveform, with or without dc offset. The ringing frequency, cadence, waveshape, and dc offset are register programmable. Using a balanced ringing scheme, the ringing signal is applied to both the TIP and the RING lines using ringing waveforms that are 180° out of phase with each other. The resulting ringing signal seen across TIP-RING is twice the amplitude of the ringing waveform on either the TIP or the RING line, which allows the ringing circuitry to withstand half the total ringing amplitude seen across TIP-RING. Si3220 806 kΩ VRING GPO BATSEL SVBAT RING 0.1 µF Si3200 R101 VBAT VBAT R9 40.2 kΩ VBATH VBATH R6 40.2 kΩ CXT5401 VBATL BATSEL SLIC Q1 0.1 µF VBATL VOFF R102 TIP 10 kΩ 402 kΩ Q2 IN4003 VTIP R103 D1 CXT5551 Figure 23. 3-Battery Switching with Si3220/ Si3200 GND VCM VTIP V PK Table 24. 3-Battery Switching Components VOFF Component Value Comments D1 200 V, 200 mA 1N4003 or similar Q1 100 V PNP CXT5401 or similar Q2 100 V NPN CXT5551 or similar Figure 24. Balanced Ringing R101 1/10 W, ± 5% 2.4 kΩ for VDD=3.3 V 3.9 kΩ for VDD=5 V An internal ringing scheme provides >40 Vrms into a 5REN load at the terminal equipment using a userprovided ringing battery supply. The specific ringing supply voltage required depends on the ringing voltage desired. The ringing amplitude at the terminal equipment depends on the loop impedance as well and 40 VRING VOV VBATH Preliminary Rev. 0.91 Si3220/Si3225 the load impedance in REN. The following equation can be used to determine the TIP-RING ringing amplitude required for a specific load and loop condition. R LOOP = ( 0.09Ω per foot for 26AWG wire ) R OUT = 320Ω RLOOP + ROUT 7000Ω R LOAD = -----------------#REN RLOAD VRING VTERM – Figure 25. Simplified Loop Circuit During Ringing R LOAD V TERM = V RING × --------------------------------------------------------------------( R LOAD + R LOOP + R OUT ) When ringing longer loop lengths, adding a dc offset voltage is necessary to reliably detect a ring trip condition (off-hook phone). Adding dc offset to the ringing signal decreases the maximum possible ringing amplitude. Adding significant dc offset also increases the power dissipation in the Si3200 and may require additional airflow or modified PCB layout to maintain acceptable operating temperatures in the line feed circuitry. The Dual ProSLIC chipset automatically applies and removes the ringing signal during VOCcrossing periods to reduce noise and crosstalk to adjacent lines. Table 25 provides a list of registers required for internal ringing generation where Table 25. Register and RAM Locations Used for Ringing Generation Parameter Register/ RAM Mnemonic Register/RAM Bits Programmable Range Resolution (LSB Size) Ringing Waveform RINGCON TRAP Sinusoid/Trapezoid N/A Ringing Active Timer Enable RINGCON TAEN Enabled/Disabled N/A Ringing Inactive Timer Enable RINGCON TIEN Enabled/Disabled N/A Ringing Oscillator Enable Monitor RINGCON RINGEN Enabled/Disabled N/A Ringing Oscillator Active Timer RINGTALO/ RINGTAHI RINGTA[15:0] 0 to 8.19 s 125 µs Ringing Oscillator Inactive Timer RINGTILO/ RINGTIHI RINGTI[15:0] 0 to 8.19 s 125 µs Linefeed Control (Initiates Ringing State) LINEFEED LF[2:0] 000 to 111 N/A On-Hook Line Voltage VOC VOC[15:0] 0 to 63.3 V 1.005 V (4.907 mV) Ringing Voltage Offset RINGOF RINGOF[15:0] 0 to 63.3 V 1.005 V (4.907 mV) Ringing Frequency RINGFRHI/ RINGFRLO RINGFRHI[14:3]/ RINGFRLO[14:3] 4 to 100 Hz Ringing Amplitude RINGAMP RINGAMP[15:0] 0 to 160.173 V Preliminary Rev. 0.91 628 mV (4.907 mV) 41 Si3220/Si3225 Table 25. Register and RAM Locations Used for Ringing Generation (Continued) Parameter Register/ RAM Mnemonic Register/RAM Bits Ringing Initial Phase Sinusoidal Trapezoid External Ringing RINGPHAS RINGPHAS[15:0] Ringing Relay Driver Enable (Si3225 only) RELAYCON VOVRING Ringing Overhead Voltage Programmable Range Resolution (LSB Size) N/A 0 to 1.024 s 0 to 662.83 mA N/A 31.25 µs 2.6 mA (20.3 µA) RDOE Enabled/Disabled N/A VOVRING[15:0] 0 to 63.3 V 1.005 V (4.907 mV) Internal Sinusoidal Ringing A sinusoidal ringing waveform is generated by the onchip digital tone generator. The tone generator used to generate ringing tones is a two-pole resonator with a programmable frequency and amplitude. Since ringing frequencies are low compared to the audio band signaling frequencies, the sinusoid is generated at a 1 kHz rate. The ringing generator is programmed via the RINGFREQ, RINGAMP, and RINGPHAS registers. The equations are as follows: 2πf coeff = cos  ---------------------  1000Hz DesiredV PK 1 1 – coeff 15 RINGAMP = --- ----------------------- × ( 2 ) × --------------------------------4 1 + coeff 160.173V allow on/off cadence settings up to 8 s on/8 s off. In addition to controlling ringing cadence, these timers control the transition into and out of the ringing state. To initiate ringing, the user must program the RINGFREQ, RINGAMP, and RINGPHAS RAM addresses as well as the RINGTA and RINGTI registers, and select the ringing waveshape and dc offset. After this is done, TAEN and TIEN bits are set as desired. Ringing state is invoked by a write to the linefeed register. At the expiration of RINGTA, the Dual ProSLIC turns off the ringing waveform and goes to the on-hook transmission state. At the expiration of RINGTI, ringing is initiated again. This process continues as long as the two timers are enabled and the linefeed register remains in the ringing state. Internal Trapezoidal Ringing RINGPHAS = 0 For example, to generate a 60 Vrms (87 VPK), 20 Hz ringing signal, the equations are as follows: 23 RINGFREQ = coeff ( 2 ) 2π20 coeff = cos  --------------------- = 99211 1000Hz RINGPHAS = 4 x Period x 8000 RINGAMP = (Desired V/160.8 V) x (215) 23 RINGFREQ = 99211 × ( 2 ) = 8322461 = 0x7EFD9D 1 00789 85 15 RINGAMP = --- -------------------- × ( 2 ) × --------------------- = 273 = 0x111 4 1.99211 160.173 In addition to the variable frequency and amplitude, a selectable dc offset (VOFF), which can be added to the waveform is included. The dc offset is defined in the RINGOF RAM location. As with the tone generators, the ringing generator has two timers which function as described above. They 42 In addition to the traditional sinusoidal ringing waveform, the Dual ProSLIC can generate a trapezoidal ringing waveform similar to the one illustrated in Figure 26. The RINGFREQ, RINGAMP, and RINGPHAS RAM addresses are used for programming the ringing wave shape as follows: RINGFREQ = (2 x RINGAMP)/(tRISE x 8000) RINGFREQ is a value that is added or subtracted from the waveform to ramp the signal up or down in a linear fashion. This value is a function of rise time, period, and amplitude, where rise time and period are related through the following equation for the crest factor of a trapezoidal waveform. 3 1 t RISE = --- T  1 – ----------2-  4  CF where Preliminary Rev. 0.91 Si3220/Si3225 Ringing DC Offset Voltage 1 T = Period = -------------- CF = desired crest factor f RING So for a 90 VPK, 20 Hz trapezoidal waveform with a crest factor of 1.3, the period is 0.05 s and the rise time requirement is 0.015 s. A dc offset voltage can be added to the Si3220’s ac ringing waveform by programming the RINGOF RAM location to the appropriate setting. The value of RINGOF is calculated as follows: RINGPHAS = 4 x 0.05 x 8000 = 1600 (0x0640) V OFF 15 RINGOF = --------------- × 2 64.32 RINGAMP = 90/160.8 x (215) = 18340 (0x47A5) RINGFREQ = (2 x RINGAMP)/(0.0153 x 8000) = 300 (0x012C) The time registers and interrupts described in the sinusoidal ring description also apply to the trapezoidal ring waveform. Ringing Coefficients The ringing coefficients are calculated in decimal for sinusoidal and trapezoidal waveforms. The RINGPHAS and RINGAMP hex values are decimal to hex conversions in 16-bit, 2’s complement representations for their respective RAM locations. To obtain sinusoidal RINGFREQ RAM values, the RINGFREQ decimal number is converted to a 24-bit 2’s complement value. The lower 12 bits are placed in RINGFRLO bits 14:3. RINGFRLO bits 15 and 2:0 are cleared to 0. The upper 12 bits are set in a similar manner in RINGFRHI, bits 13:3. RINGFRHI bit 14 is the sign bit and RINGFRHI bits 2:0 are cleared to 0. For example, the register RINGFREQ=0x7EFD9D are as follows: values for RINGFRHI = 0x3F78 RINGFRLO = 0x6CE8 To obtain trapezoidal RINGFREQ RAM values, the RINGFREQ decimal number is converted to an 8-bit, 2’s complement value. This value is loaded into RINGFRHI. RINGFRLO is not used. External Unbalanced Ringing The Si3225 supports centralized, battery-backed unbalanced ringing schemes by providing a ringing relay driver as well as inputs from an external ring trip circuit. Using this scheme, line-card designers can use the Dual ProSLIC chipset in existing system architectures with minimal system changes. Linefeed Overhead Voltage Considerations During Ringing The ringing mode output impedance allows ringing operation without overhead voltage modification (VOVR = 0). If an offset of the ringing signal from the ring lead is desired, VOVR can be used for this purpose. Ringing Power Considerations The total power consumption of the Si3220/Si3200 chipset using internal ringing generation is dependent on the VDD supply voltage, the desired ringing amplitude, the total loop impedance, and the AC load impedance (number of REN). The following equations can be used to approximate the total current required for each channel during ringing mode. VDD = 3.3 V: I DD,AVE = 22mA + ( 6mA × REN ) VDD = 5 V: VTIP-RING I DD,AVE = 26mA + ( 6mA × REN ) And v RING,RMS 2.04 I BAT,RMS = ---------------------------------------------------------------- × ----------R LOAD + R LOOP + R OUT π VOFF Where: T = 1/freq REN = number of REN RLOAD = 7000/REN for North America tRISE time RLOOP = loop impedance ROUT = ProSLIC output impedance = 320 Ω Figure 26. Trapezoidal Ringing Waveform Preliminary Rev. 0.91 43 Si3220/Si3225 Ring Trip Detection A ring trip event signals that the terminal equipment has transitioned to an off-hook state after ringing has commenced, ensuring that the ringing signal is removed before normal speech begins. The Dual ProSLIC is designed to implement either an ac- or dc-based internal ring trip detection scheme or a combination of both schemes. The system design is flexible to address varying loop lengths of different applications. An ac ring trip detection scheme cannot reliably detect an off-hook condition when sourcing longer loop lengths, as the 20 Hz ac impedance of an off-hook long loop is indistinguishable from a heavily loaded (5 REN) short loop in the on-hook state. Therefore, a dc ring trip detection scheme is required when sourcing longer loop lengths. The Si3220 can implement either an ac- or dc-based ring trip detection scheme, depending on the application. The Si3225 allows external dc ring trip detection when using a battery-backed external ringing generator by monitoring the ringing feed path through two sensing inputs on each channel. By monitoring this path, the Dual ProSLIC detects a dc current flowing in the loop once the end equipment has gone off-hook. Table 26 provides recommended register and RAM settings for various applications, and Table 27 lists the register and RAM addresses that must be written or monitored to correctly detect a ring trip condition. Figure 27 illustrates the internal functional blocks that correctly detect and process a ring trip event. The primary input to the system is the loop current sense (ILOOP) value provided by the loop monitoring circuitry and reported in the ILOOP RAM location register. The ILOOP RAM location value is processed by the ISP block when the LFS bits in the Linefeed register indicate the device is in the ringing state. The output of the ISP then feeds into a pair of programmable digital low-pass filters; one for the ac ring trip detection path and one for 44 the dc path. The ac path also includes a full wave rectifier block prior to the LPF block. The outputs of each low pass filter block are then passed on to a programmable ring trip threshold (RTACTH for ac detection and RTDCTH for dc detection). Each threshold block output is then fed to a programmable debounce filter to ensure a valid ring trip event. The output of each debounce filter remains constant unless the input remains in the opposite state for the entire period of time set using the ac and dc ring trip debounce interval registers, RTACDB and RTDCDB, respectively. The outputs of both debounce filter blocks are then ORed together. If either the ac or the dc ring trip circuits indicate a valid ring trip event has occurred, the RTP bit is set. Either the ac or dc ring trip detection circuits are disabled by setting the respective ring trip threshold sufficiently high so that it does not trip under any condition. A ring trip interrupt also generates if the RTRIPE bit is enabled. Ringtrip Timeout Counter The Dual ProSLIC incorporates a ringtrip timeout counter (RTCOUNT) that will monitor the status of the ringing control. When exiting ringing, the Dual ProSLIC will allow the ringtrip timeout counter amount of time (RTCOUNT x 1.25 ms/LSB) for the mode to switch to On-hook Transmission or Active. The mode that is being exited to is governed by whether the command to exit ringing is a ringing active timer expiration (on-hook transmission) or ringtrip/manual mode change (Active mode). The ringtrip timeout counter will assure ringing is exited within its time setting (RTCOUNT x 1.25 ms/LSB, typically 200 ms). Ringtrip Debounce Interval The ac and dc ring trip debounce intervals can be calculated based on the following equations: RTACDB = tdebounce (1600/RTPER) RTDCDB = tdebounce (1600/RTPER) Preliminary Rev. 0.91 Si3220/Si3225 RTACTH AC Ring Trip Threshold LFS _ ILOOP Input Signal Processor Full Wave Rectifier Digital LPF + Debounce Filter_AC RTP Interrupt Logic RTACDB RTPER Digital LPF + _ DC Ring Trip Threshold RTRIPS RTRIPE Debounce Filter_DC RTDCDB RTDCTH Figure 27. Ring Trip Detect Processing Circuitry Preliminary Rev. 0.91 45 Si3220/Si3225 Table 26. Recommended Values for Ring Trip Registers and RAM Addresses1 Ringing Method Internal (Si3220) External (Si3225) Ringing Frequency 16–32 Hz 33–60 Hz 16–32 Hz 33–60 Hz DC Offset Added? Yes No Yes No Yes Yes RTPER RTACTH RTDCTH RTACDB/ RTDCDB 800/fRING 800/fRING 2(800/fRING) 2(800/fRING) 800/fRING 2(800/fRING) 221 x RTPER 1.59 x VRING,PK x RTPER 221 x RTPER 1.59 x VRING,PK x RTPER 32767 32767 0.577(RTPER x VOFF) 32767 0.577(RTPER x VOFF) 32767 0.067 x RTPER x VOFF 0.067 x RTPER x VOFF See Note 2 Notes: 1. All calculated values should be rounded to the nearest integer. 2. Refer to Ring Trip Debounce Interval for RTACDB and RTDCDB equations. Table 27. Register and RAM Locations Used for Ring Trip Detection Parameter Register/RAM Mnemonic Register/RAM Bits Programmable Range Resolution Ring Trip Interrupt Pending IRQVEC2 RTRIPS Yes/No N/A Ring Trip Interrupt Enable IRQEN2 RTRIPE Enabled/Disabled N/A AC Ring Trip Threshold RTACTH RTACTH[15:0] See Table 26 DC Ring Trip Threshold RTDCTA RTDCTH[15:0] See Table 26 Ring Trip Sample Period RTPER RTPER[15:0] See Table 26 LINEFEED LFS[2:0] N/A N/A Ring Trip Detect Status (monitor only) LCRRTP RTP N/A N/A AC Ring Trip Detect Debounce Interval RTACDB RTACDB[15:0] 0 to 40.96 s 1.25 ms DC Ring Trip Detect Debounce Interval RTDCDB RTDCDB[15:0] 0 to 40.96 s 1.25 ms ILOOP ILOOP[15:0] 0 to 101.09 mA See Table 19 Linefeed Shadow (monitor only) Loop Current Sense (monitor only) Loop Closure Mask The Dual ProSLIC implements a loop closure mask to ensure mode change between Ringing and Active or On-hook Transmission without causing an erroneous loop closure detection. The loop closure mask register, LCRMASK, should be set such that loop closure detection is ignored for LCRMASK 1.25 ms/LSB amount of time. The programmed time is set to mask detection of transitional currents that occur when exiting the ringing mode while driving a reactive load (i.e., 5 REN). A typical setting is 80 ms (LCRMASK = 0x40). Si3220 Ring Trip Detection The Si3220 provides the ability to process a ring trip event using an ac-based detection scheme. Using this scheme eliminates the need to add dc offset to the 46 ringing signal, which reduces the total power dissipation during the ringing state and maximizes the available ringing amplitude. This scheme is valid for shorter loop lengths only since it cannot reliably detect a ring trip event if the off-hook line impedance overlaps the onhook impedance at 20 Hz. The Si3220 also can add a dc offset component to the ringing signal and detect a ring trip event by monitoring the dc loop current flowing once the terminal equipment transitions to the off-hook state. Although adding dc offset reduces the maximum available ringing amplitude (using the same ringing supply), this method is required to reliably detect a valid ring trip event when sourcing longer loop lengths. The dc offset can be programmed from 0 to 64.32 V in the RINGOF RAM address as Preliminary Rev. 0.91 Si3220/Si3225 required to produce adequate dc loop current in the offhook state. Depending on the loop length and the ring trip method, the ac or dc ring trip detection circuits are disabled by setting their respective ring trip thresholds (RTACTH or RTDCTH) sufficiently high so it does not trip under any condition. VDD VCC Si3220/ Si3225 3 V/5 V Relay (polarized or non-polarized) Si3225 Ring Trip Detection The Si3225 implements an external ring trip detection scheme when using a standard battery-backed, external ringing generator. In this application, the centralized ringing generator produces an unbalanced ringing signal that is distributed to individual TIP/RING pairs. A per-channel ringing relay is required to disconnect the Si3225 from the TIP/RING pair and apply the ringing signal. By monitoring the ringing feed path across a ring feed sense resistor (RRING in Figure 31) in series with the ringing source, the Si3225 can detect the dc current path created when the hook switch inside the terminal equipment closes. The internal ring trip detection circuitry is identical to that illustrated in Figure 27. Figure 31 illustrates the typical external ring trip circuitry required for the Si3225. Because of the long loop nature of these applications, a dc ring trip detection scheme is used typically. The user can disable the ac ring trip detection circuitry by setting the RTACTH threshold sufficiently high so it does not trip under any condition. Relay Driver Considerations The Dual ProSLIC devices include up to three dedicated relay drivers to drive external ringing and/or test relays. Test relay drivers TRD1a, TRD1b, TRD2a, and TRD2b are provided in all product versions, and ringing relay drivers RRDa and RRDb are included for the Si3225 only. In most applications, the relay can be driven directly from the Dual ProSLIC with no external relay drive circuitry required. Figure 28 illustrates the internal relay driver circuitry using a 3 V or 5 V relay. Relay Driver Logic RRDa/b TRD1a/b TRD2a/b GDD Figure 28. Dual ProSLIC Internal Relay Drive Circuitry The internal driver logic and drive circuitry is powered by the same VDD supply as the chip’s main VDD supply (VDD1–VDD4 pins). When operating external relays from a VCC supply equal to the chip’s VDD supply, an internal diode network provides protection against overvoltage conditions from flyback spikes when the relay is opened. Both 3 V or 5 V relays can be used in the configuration shown in Figure 28 and either polarized or non-polarized relays are acceptable if the VCC and VDD supplies are identical. The input impedance (RIN) of the relay driver pins is a constant 11 Ω while sinking less than the maximum rated 85 mA into the pin. If the operating voltage of the relay (VCC) is higher than the Dual ProSLIC’s VDD supply voltage, an external drive circuit is required to eliminate leakage from VCC to VDD through the internal protection diode. In this configuration, a polarized relay will provide optimal overvoltage protection and minimal external components. Figure 29 illustrates the required external drive circuit and Table 28 provides recommended values for RDRV for typical relay characteristics and VCC supplies. The output impedance (ROUT) of the relay driver pins is a constant 63 Ω while sourcing less than the maximum rated 28 mA out of the pin. Preliminary Rev. 0.91 47 Si3220/Si3225 VCC VDD Si3220/ Si3225 Polarized relay RRDa/b TRD1a/b TRD2a/b IDRV Q1 RDRV Figure 29. Driving Relays with VCC > VDD The maximum allowable RDRV value can be calculated with the following equation: ( V DD,MIN – 0.6 V ) ( R RELAY ) ( β Q1,MIN ) MaxR DRV = ------------------------------------------------------------------------------------------------- – R SOURCE V CC,MAX – 0.3 V Where βQ1,MIN ~ 30 for a 2N2222. Table 28. Recommended RDRV Values 48 ProSLIC VDD Relay VCC Relay RCOIL Maximum RDRV Recommended 5% Value 3.3 V ±5% 3.3 V ±5% 64 Ω Not Required — 5 V ±5% 5 V ±5% 178 Ω Not Required — 3.3 V ±5% 5 V ±5% 178 Ω 2718 Ω 2.7 kΩ 3.3 V ±5% 12 V ±10% 1028 Ω 6037 Ω 5.6 kΩ 3.3 V ±5% 24 V ±10% 2880 Ω 8364 Ω 8.2 kΩ 3.3 V ±5% 48 V ±10% 7680 Ω 11092 Ω 11 kΩ 5 V ±5% 12 V ±10% 1028 Ω 9910 Ω 9.1 kΩ 5 V ±5% 24 V ±10% 2880 Ω 13727 Ω 13 kΩ 5 V ±5% 48 V ±10% 7680 Ω 18202 Ω 18 kΩ Preliminary Rev. 0.91 IRINGXSCAL D ZERDELAY COUNTER0 0 1 2 3 4 COUNTER1 5 6 7 8 9 10 11 0 1 2 3 4 5 6 7 8 9 10 11 0 1 2 3 4 5 6 7 8 9 10 11 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 8 9 10 11 0 1 2 3 4 5 6 7 8 9 10 11 0 1 2 3 4 5 6 7 8 9 10 11 0 Preliminary Rev. 0.91 RINGEN RRD On Off On LF Active Ringing LFSDELAY LFS Off Ringing LFSDELAY OHT Ringing 49 Si3220/Si3225 Figure 30. Timing Characteristics for Ringing Relay Control Active Si3220/Si3225 VOFF VRING + 510 Ω _ 806 kΩ RTRP BLkRING 806 kΩ Relay Phone RING Si3200 Si3225 Hook Switch Protection RRD TIP VDD Figure 31. Si3225 External Ring Trip Circuitry Ringing Relay Activation During Zero Crossings The Si3225 is for applications that use a centralized ringing generator and a per-channel ringing relay to connect the ringing signal to the TIP/RING pair. The Si3225 has one relay driver output per channel (RRDa and RRDb) that can drive a mechanical or solid-state DPDT relay. To reduce impulse noise that can couple into adjacent lines, the relay should be closed when there is zero voltage across the relay contacts and opened during periods when there is zero current through the contacts. Closing the Relay at Zero Voltage Internal voltage monitoring circuitry closes the relay at zero voltage with respect to the line voltage. By observing the phase of the ringing signal and constantly monitoring the open-circuit T-R voltage, VOC, the Si3225 can detect the next time when there is zero voltage across the relay contacts. Opening the Relay at Zero Current Opening the ringing relay at zero current also is accomplished using the internal monitoring circuitry and prevents arcing from excess current flow when the relay contacts are opened. The current flowing through the ringing relay is continuously monitored in the IRNGNG RAM address, and two internal counters (COUNTER0 and COUNTER1) detect time elapsed since the last two zero current crossings based on the ringing period and predict when the next zero crossing occurs. The ringing relay current and internal counters are both updated at an 8 kHz rate. To account for the mechanical delay of the relay, a programmable advance firing timer allows the user to initiate relay opening up to 10 ms prior to the zero current crossing event. Figure 30 illustrates the 50 timing sequence for a typical ringing relay control application. During a typical ringing sequence, the Si3225 monitors both the ringing relay current (IRNGNG) and the RINGEN bit of the RINGCON register. The RINGEN bit toggles because of pre-programmed ringing cadence or a change in operating state. COUNTER0 and COUNTER1 are re-started at each alternating zero current crossing event, and the delay period ZERDELAY equal to the ringing frequency period less the desired advance firing time (D) is entered by the user. If either counter reaches the same value as ZERDELAY, the relay control signal is enabled when the RINGEN bit transition has already occurred. During typical ringing bursts, the LFS bits of the Linefeed register toggle between the RINGING and OHT states based on the pre-programmed ringing cadence. The transition from OHT to RINGING is synchronized with the RRD state transitions so the ringing burst starts immediately. The transition from RINGING to OHT is gated by a user-programmed delay period LFSDELAY that ensures the ringing burst has ceased before going to the OHT state or to the ACTIVE state in response to a Linefeed state change. Preliminary Rev. 0.91 Si3220/Si3225 Polarity Reversal The Dual ProSLIC devices support polarity reversal for message waiting functionality and various signaling modes. The ramp rate can be programmed for a smooth transition or an abrupt transition to accommodate different application requirements. A wink function is provided for special equipment that responds to a smooth ramp to VOC = 0 V. Table 29 illustrates the register bits required to program the polarity reversal modes. Setting the Linefeed register to the opposite polarity immediately reverses (hard reversal) the line polarity. For example, to transition from Forward Active mode to Reverse Active mode changes LF[2:0] from 001 to 101. Polarity reversal is accommodated in the OHT and ground start modes. The POLREV bit is a read-only bit that reflects if the device is in Polarity Reversal mode. For smooth polarity reversal, set the PREN bit to 1 and the RAMP bit to 0 or 1 depending on the desired ramp rate (see Table 29). Polarity reversal is then accomplished by toggling the linefeed register from forward to reverse modes as desired. A wink function slowly ramps down the TIP-RING voltage (VOC) to 1 followed by a return to the original VOC value (set in the VOC RAM location). This scheme lights a message-waiting lamp in certain handsets. No change to the linefeed register is necessary to enable this function. Instead, the user sets the VOCZERO bit to 1 so that the TIP-RING voltage collapses to 0 V at the rate programmed by the RAMP bit. Setting the VOCZERO bit back to 0 returns the TIP-RING voltage to its normal setting. With a software timer, the user can automate the cadence of the wink function. Figure 32 illustrates the wink function. Table 29. Register and RAM Locations used for Polarity Reversal Parameter Programmable Range Linefeed See table 15 Polarity Reversal Status Read only Wink Function (Smooth transition to Voc=0V) 1 = Ramp to 0 V 0 = Return to previous VOC Smooth Polarity Reversal Enable Smooth Polarity Reversal Ramp Rate Register/RAM Register/RAM Bits Mnemonic LF[2:0] LINEFEED POLREV POLREV VOCZERO POLREV 0 = Disabled 1 = Enabled PREN POLREV 0 = 1 V/1.25 ms 1 = 2 V/1.25 ms RAMP POLREV Preliminary Rev. 0.91 51 Si3220/Si3225 VTIP/RING (V) VOC = 48 V 50 40 2 V/1.25 ms slope set by RAMP bit 30 20 10 Time (ms) 0 0 10 20 30 40 Set VOCZERO bit to 1 50 60 70 80 Set VOCZERO bit to 0 Figure 32. Wink Function with Programmable Ramp Rate Two-Wire Impedance Synthesis Two-wire impedance synthesis is performed on-chip to optimally match the output impedance of the Dual ProSLIC to the impedance of the subscriber loop to minimize the receive path signal reflected back onto the transmit path. The Dual ProSLIC chipset provides onchip digitally programmable, two-wire impedance synthesis to meet return loss requirements against virtually any global two-wire impedance requirement. Real and complex two-wire impedances are realized by a programmable digital filter block. (See Z block in Figure 11 on page 22.) RP RS CP Figure 33. Two-Wire Impedance Synthesis Configuration Table 30. Two-Wire Impedance Synthesis Limitations Desired Configuration Programmable Limits RS only 100–1000 Ω RS + CP RS x CP > 0.5 ms RS + RP||CP RS/(RS + RP) > 0.1 The two-wire impedance is programmed by loading the desired real or complex impedance value into the Si322X Coefficient Generator software in the format RS + RP||CP, as shown in Figure 33. The software calculates the appropriate hex coefficients and loads them into the appropriate control registers (registers 33–52). The two-wire impedance can be set to any real or complex value within the boundaries set in Table 30. The actual impedance presented to the subscriber loop varies with series impedance from protection devices placed between the Dual ProSLIC chipset outputs and the TIP/RING pair according to the following equation: Z T = 2R PROT + ( R S + R P || C P ) Where: 52 Preliminary Rev. 0.91 ZT is the termination impedance presented to the TIP/RING pair Si3220/Si3225 RPROT is the series resistance caused by protection devices RS is the series portion of the synthesized impedance RP||CP is the parallel portion of the synthesized impedance The user must enter the value of RPROT into the software so the equalizer block can compensate for additional series impedance. (See Figure 11 on page 22.) Figure 34 illustrates the simplified two-wire impedance circuit including external protection resistors, where ZL is the actual line impedance for the specific geographical region. The Dual ProSLIC devices can accomodate up to 50 Ω of series protection impedance per leg. The Dual ProSLIC devices load a 600 Ω default setting into the RS register if the user does not define the impedance setting, which assumes there is no additional series protection resistance. The ac impedance generation scheme is comprised of analog and DSP-based coefficients. To turn off the analog coefficients (RS, ZP, and ZZ bits in the ZRS and ZZ registers), the user can simply set the ZSDIS bit of the ZZ register to 0. To turn off the DSP coefficients (ZA1H1 through ZB3LO registers), each register must be loaded with 0x00. TIP ZT RING Si3200 ZL RPROT Dual ProSLIC Transhybrid Balance Filter The Dual ProSLIC devices provide a transhybrid balance function via a digitally programmable balance filter block. (See “H” block in Figure 11 on page 22.) The Dual ProSLIC devices implement a 8-tap FIR filter and a second order IIR filter, both running at a 16 kHz sample rate. These two filters combine to form a digital replica of the reflected signal (echo) from the transmit path inputs. The user can filter settings on a per-line basis by loading the desired impedance cancellation coefficients into the appropriate registers. The Si322X Coefficient Generator software interface is provided for calculating the appropriate coefficients for the FIR and IIR filter blocks. The transhybrid balance filters can be disabled to implement loopback diagnostic modes. To disable the transhybrid balance filter (zero cancellation), set the HYBDIS bit in the DIGCON register to 1. With the hybrid balance cancellation scheme disabled, the user can accurately measure the full transmit path signal to measure the two-wire return loss. Note: The user must enter values into each register location to ensure correct operation when the hybrid balance block is enabled. Tone Generators Dual ProSLIC devices have two digital tone generators that allow a wide variety of single or dual tone frequency and amplitude combinations that spare the user the effort of generating the required POTS signaling tones on the PCM highway. DTMF, FSK (caller ID), call progress, and other tones can all be generated on-chip. The tones are sent to the receive or transmit paths. (See Figure 11 on page 22.) Tone Generator Architecture RPROT Figure 34. Two-Wire Impedance Simplified Circuit A simplified diagram of the tone generator architecture is shown in Figure 35. The oscillator, active/inactive timers, interrupt block, and signal routing block are connected for flexibility in creating audio signals. Control and status register bits are placed in the figure to indicate their association with the tone generator architecture. The register set for tone generation is summarized in Table 31 on page 55. Preliminary Rev. 0.91 53 Si3220/Si3225 8 kHz Clock 8 kHz Clock ZEROENn Zero Cross ENSYNCn OSCnEN 16-Bit Modulo Counter OSCnTA Expire Zero Cross Logic Two-Pole Resonant Register Oscillator Load Logic OSCnTI Expire to TX Path Enable Signal Routing Load to RX Path OSCnTA OSCnFREQ REL* INT Logic OSCnTAEN OSnTIS OSCnTI ROUTn OSCnAMP OSnTIE OSnTAS INT Logic OSCnTIEN OSCnPHAS OSnTAE *Tone Generator 1 Only n = "1" or "2" for Tone Generator 1 and 2, respectively Figure 35. Tone Generator Diagram Oscillator Frequency and Amplitude Each of the two tone generators contains a two-pole resonant oscillator circuit with a programmable frequency and amplitude, which are programmed via RAM addresses OSC1FREQ, OSC1AMP, OSC1PHAS, OSC2FREQ, OSC2AMP, and OSC2PHAS. The sample rate for the two oscillators is 8000 Hz. The equations are as follows: 1 15 OSC1AMP = --- 0.21556 --------------------- × ( 2 – 1 ) × 0.5 = 1424 4 1.78434 = 0x590 OSC1PHAS = 0 coeff2 = cos (2π 1336 / 8000) = 0.49819 OSC2FREQ = 0.49819 (214) = 8162 = 0x1FE2 coeffn = cos(2π fn/8000 Hz), where fn is the frequency to be generated; 1 15 OSC2AMP = --- 0.50181 --------------------- × ( 2 – 1 ) × 0.5 = 2370 4 1.49819 14 OSCnFREQ = coeffn x (2 ); = 0x942 1 1 – coeff DesiredVrms 15 OSCnAMP = --- ----------------------- × ( 2 – 1 ) × -------------------------------------4 1 + coeff 1.11Vrms where desired Vrms is the amplitude to be generated; OSCnPHAS = 0, n = 1 or 2 for oscillator 1 or oscillator 2, respectively. For example, to generate a DTMF digit of 8, the two required tones are 852 Hz and 1336 Hz. Assuming we want to generate half-scale values (ignoring twist), the following values are calculated: 2π852 coeff 1 = cos  ----------------- = 0.78434 8000 14 OSC1FREQ = 0.78434 ( 2 ) = 12851 = 0x3233 54 OSC2PHAS = 0 The computed values above are written to the corresponding registers to initialize the oscillators. Once the oscillators are initialized, the oscillator control registers can be accessed to enable the oscillators and direct their outputs. Tone Generator Cadence Programming Each of the two tone generators contains two timers, one for setting the active period and one for setting the inactive period. The oscillator signal is generated during the active period and suspended during the inactive period. Both the active and inactive periods can be programmed from 0 to 8 seconds in 125 µs steps. The active period time interval is set using OSC1TA for tone generator 1 and OSC2TA for tone generator 2. Preliminary Rev. 0.91 Si3220/Si3225 To enable automatic cadence for tone generator 1, define the OSC1TA and OSC1TI registers and then set the OSC1TAEN and OSC1TIEN bits. This enables each of the timers to control the state of the Oscillator Enable bit, OSC1EN. The 16-bit counter counts until the active timer expires, when the 16-bit counter resets to zero and begins counting until the inactive timer expires. The cadence continues until the user clears the OSC1TA and OSC1TIEN control bits. Setting the ZEROEN1 bit implements the zero crossing detect feature. This ensures that each oscillator pulse ends without a dc component. The timing diagram in Figure 36 is an example of an output cadence that uses the zero crossing feature. One-shot oscillation is possible with OSC1EN and OSC1TAEN. Direct control over the cadence is achieved by setting the OSC1EN bit directly if OSC1TAEN and OSC1TIEN are disabled. The operation of tone generator 2 is identical to that of tone generator 1 using its respective control registers. Note: Tone Generator 2 should not be enabled simultaneously with the ringing oscillator because of resource sharing within the hardware. Table 31. Register and RAM Locations Used for Tone Generation Tone Generator 1 Parameter Register/RAM Mnemonics Register/RAM Bits Description/Range (LSB Size) Oscillator 1 Frequency Coefficient OSC1FREQ OSC1FREQ[15:3] Sets oscillator frequency Oscillator 1 Amplitude Coefficient OSC1AMP OSC1AMP[15:0] Sets oscillator amplitude Oscillator 1 Initial Phase Coefficient OSC1PHAS OSC1PHAS[15:0] Sets initial phase (default = 0) Oscillator 1 Active Timer O1TALO/O1TAHI OSC1TA[15:0] 0 to 8.19 s (125 µs) Oscillator 1 Inactive Timer O1TILO/O1TIHI OSC1TI[15:0] 0 to 8.19 s (125 µs) Oscillator 1 Control OMODE, OCON FSKSSEN, OSC1FSK, ZEROEN1, ROUT1, ENSYNC1, OSC1TAEN, OSC1TIEN, OSC1EN Enables all Oscillator 1 parameters Oscillator 1 Interrupts IRQVEC1, IRQEN1 OS1TAS, OS1TIS, OS1TAE, OS1TIE Interrupt enable/status Tone Generator 2 Parameter Location Register/RAM Address Description/Range Oscillator 2 Frequency Coefficient OSC2FREQ OSC2FREQ[15:3] Sets oscillator frequency Oscillator 2 Amplitude Coefficient OSC2AMP OSC2AMP[15:0] Sets oscillator amplitude Oscillator 2 Initial Phase Coefficient OSC2PHAS OSC2PHAS[15:0] Sets initial phase (default = 0) Oscillator 2 Active Timer O2TALO/O2TAHI OSC2TA[15:0] 0 to 8.19 s (125 µs) Oscillator 2 Inactive Timer O2TILO/O2TIHI OSC2TI[15:0] 0 to 8.19 s (125 µs) Oscillator 2 Control OMODE, OCON ZEROEN2, ROUT2, ENSYNC2, OSC2TAEN, OSC2TIEN, OSC2EN Enables all Oscillator 2 parameters Oscillator 2 Interrupts IRQVEC1, IRQEN1 OS2TAS, OS2TIS, OS2TAE, OS2TIE Interrupt enable/status Preliminary Rev. 0.91 55 Si3220/Si3225 OSC1EN 0,1 ... ..., OSC1TA 0,1 ... ... ..., OSC1TI 0,1 ... ..., OSC1TA 0,1 ... ... ENSYNC1 Tone Gen. 1 Signal Output Figure 36. Tone Generator Timing Diagram First Ring Burst Message Type Channel Seizure Message Length Parameter 1 Message Header Parameter Type Mark Data Packet Parameter 2 Second Ring Burst Parameter n Message Body Data Length Data Content Figure 37. On-Hook Caller ID Transmission Sequence 56 Preliminary Rev. 0.91 Checksum Si3220/Si3225 Tone Generator Interrupts Both the active and inactive timers can generate an interrupt to signal “on/off” transitions to the software. The timer interrupts for tone generator 1 can be individually enabled by setting the OS1TAE and OS1TIE bits. Timer interrupts for tone generator 2 are OS2TAE and OS2TIE. A pending interrupt for each of the timers is determined by reading the OS1TAS, OS1TIS, OS2TAS, and OS2TIS bits in the IRQVEC1 register. Caller ID Generation The Dual ProSLIC devices generate caller ID signals in compliance with various Bellcore and ITU specifications as described in Table 32 by providing continuous phase binary frequency shift key (FSK) modulation. Oscillator 1 is required because it preserves phase continuity during frequency shifts whereas Oscillator 2 does not. Figure 37 illustrates a typical caller ID transmission sequence in accordance with Bellcore requirements. Table 32. FSK Modulation Requirements Parameter ITU-T V.23 Bellcore GR30-CORE Mark Frequency (logic 1) 1300 Hz 1200 Hz Space Frequency (logic 0) 2100 Hz 2200 Hz Transmission Rate 1200 baud Table 33. Register and RAM Locations used for Caller ID Generation Parameter Register/RAM Mnemonic Register/RAM Bits Description/Range OMODE O1FSK8 Enable/disable O1TALO/O1TAHI OSC1TA[15:0] 0 to 8.19 s/125 µs FSKDAT FSKDAT[7:0] Caller ID data FSK Frequency for Space FSKFREQ0 FSKFREQ0[15:3] Audio range FSK Frequency for Mark FSKFREQ1 FSKFREQ1[15:3] Audio range FSK Amplitude for Space FSKAMP0 FSKAMP0[15:3] FSK Amplitude for Mark FSKAMP1 FSKAMP1[15:3] FSK 0-1 Transition Freq, High FSK01HI FSK01HI[15:3] FSK 0-1 Transition Freq, Low FSK01LO FSK01LO[15:3] FSK 1-0 Transition Freq, High FSK10HI FSK10HI[15:3] FSK 1-0 Transition Freq, Low FSK10LO FSK10LO[15:3] FSK Start & Stop Bit Enable Oscillator 1 Active Timer FSK Data Byte The register and RAM locations for caller ID generation are listed in Table 33. Caller ID data is entered into the 8-bit FSKDAT register. The data byte is double buffered so that the Dual ProSLIC can generate an interrupt indicating the next data byte can be written when processing begins on the current data byte. The caller ID data can be transmitted in one of two modes controlled by the O1FSK8 register bit. When O1FSK8 = 0 (default case), the 8-bit caller ID data is transmitted with a start bit and stop bit to create a 10-bit data sequence. If O1FSK8 = 1, the caller ID data is transmitted as a raw 8-bit sequence with no start or stop bits. The value programmed into the OSC1TA register determines the bit rate, and the interrupt rate is equal to the bit rate divided by the data sequence length (8 or 10 bits). Pulse Metering Generation The Si3220 offers an additional tone generator to generate tones above the audio frequency band. This oscillator generates billing tones which are typically 12 kHz or 16 kHz. The generator follows the same algorithm as described in "Tone Generator Architecture" on page 53 with the exception that the sample rate for computation is 64 kHz instead of 8 kHz. The equation is as follows: Preliminary Rev. 0.91 Coeff = cos (2πf / 64000 Hz) PMFREQ = coeff x (214 – 1) 57 Si3220/Si3225 DesiredV PK 15 1 1 – coeff PMAMPL = --- ----------------------- × ( 2 – 1 ) × -------------------------------------FullScaleV PK 4 1 + coeff where Full Scale VPK = 0.5 V. The pulse metering oscillator has a volume envelope (linear ramp) on the on/off transitions of the oscillator. The ramp is controlled by the value in the PMRAMP RAM address, and the sinusoidal generator output is multiplied by this volume before it is sent to the Pulse Metering DAC. The volume value is incremented by the value in PMRAMP at an 8 kHz rate. The volume will ramp from 0 to 7FFF in increments of PMRAMP to allow the value of PMRAMP to set the slope of the ramp. The clip detector stops the ramp once the signal seen at the transmit path exceeds the amplitude threshold set by PMAMPTH, which provides an automatic gain control (AGC) function to prevent the audio signal from clipping. When the pulse metering signal is turned off, the volume ramps down to 0 by decrementing according to the value of PMRAMP. Figure 38 illustrates the functional blocks involved in pulse metering generation, and Table 34 presents the register and RAM locations required that must be set to generate pulse metering signals. Table 34. Register and RAM Locations Used for Pulse Metering Generation Parameter Register/RAM Mnemonic Register/RAM Bits Description/Range (LSB Size) Pulse Metering Frequency Coefficient PMFREQ PMFREQ[15:3] Sets oscillator frequency Pulse Metering Amplitude Coefficient PMAMPL PMAMPL[15:0] Sets oscillator amplitude Pulse Metering Attack/Decay Ramp Rate PMRAMP PMRAMP[15:0] 0 to PMAMPL (full amplitude) Pulse Metering Active Timer PMTALO/PMTAHI PULSETA[15:0] 0 to 8.19 s (125 µs) Pulse Metering Inactive Timer PMTILO/PMTIHI PULSETI[15:0] 0 to 8.19 s (125 µs) Pulse Metering, Control Interrupt IRQVEC1, IRQEN1 PULSTAE, PULSTIE, PULSTAS, PULSTIS Interrupt Status and control registers Pulse Metering AGC Amplitude Threshold PMAMPTH PMAMPTH[15:0] 0 to 500 mV PM Waveform Present PMCON ENSYNC Indicates signal present PM Active Timer Enable PMCON TAEN Enable/disable PM Inactive Timer Enable PMCON TIEN Enable/disable Pulse Metering Enable PMCON PULSE1 Enable/disable 58 Preliminary Rev. 0.91 Si3220/Si3225 Decimation Filter ADC 12/16 kHz Bandpass Peak Detector PMAMPTH – IBUF ZA ++ + DAC PMRAMP Pulse Metering DAC ±+ x+ Pulse Metering Oscillator Volume Clip Logic 7FFF or 0 8 kHz Figure 38. Pulse Metering Generation Block Diagram DTMF Detection On-chip DTMF detection, also known as Touch Tone, is available in the Si3220 and Si3225. It is an in-band signaling system that replaces the pulsedial signaling standard. In DTMF, two tones generate a DTMF digit. One tone is chosen from the four possible row tones and one tone is chosen from the four possible column tones. The sum of these tones constitute one of 16 possible DTMF digits. The row and column tones and corresponding digits are shown in Table 35. DTMF detection is performed using a modified Goertzel algorithm to compute the DFT for each of the eight DTMF frequencies and their second harmonics. At the end of the DFT computation, the squared magnitudes of the DFT results for the 8 DTMF fundamental tones are computed. The row results are sorted to determine the strongest row frequency, and the column frequencies are sorted as well. At the completion of this process, checks are made to determine if the strongest row and column tones constitute a DTMF digit. overwritten by a new one. There is no buffering of the digit information. Table 35. DTMF Row/Column Tones 697 Hz 1 2 3 A 770 Hz 4 5 6 B 852 Hz 7 8 9 C 941 Hz * 0 # D 1209 Hz 1336 Hz 1477 Hz 1633 Hz Table 36 outlines the hex code corresponding to the detected DTMF digits. The detection process occurs twice within the 45 ms minimum tone time. A digit must be detected on two consecutive tests after a pause to be recognized as a new digit. If all tests pass, an interrupt is generated and the DTMF digit value is loaded into the DTMF register according to the following table. If tones occur at the maximum rate of 100 ms per digit, the interrupt must be serviced within 85 ms so that the current digit is not Preliminary Rev. 0.91 59 Si3220/Si3225 attenuation for signals above 3.4 kHz are part of the combined decimation filter characteristic of the A/D converter. One more digital filter is available in the transmit path, THPF. THPF implements the high-pass attenuation requirements for signals below 65 Hz. An equalizer block then equalizes the transmit signal path to compensate for series protection resistance (RPROT) outside of the ac-sensing inputs. The linear PCM data stream output from the equalizer block is amplified by the transmit-path programmable gain amplifier, TPGA, which can be programmed from –∞ to 6 dB. The DTMF decoder receives the linear PCM data stream and performs the digit extraction if enabled by the user. The final step in the transmit path signal processing is the A-law or µ-law compression which can reduce the data stream word width to 8 bits. Depending on the PCM Mode Select register selection, every 8-bit compressed serial data word occupies one time slot on the PCM highway, or every 16-bit uncompressed serial data word occupies two time slots on the PCM highway. Table 36. DTMF Hex Codes Digit 1 2 3 4 5 6 7 8 9 0 * # A B C D Hex code 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF 0x0 Receive Path Modem Tone Detection The Dual ProSLIC devices are capable of detecting a 2100 Hz modem tone as described in ITU-T Recommendation V.8. The detection scheme can be implemented in both transmit and receive paths, and is enabled by programming the appropriate register bit. The detection scheme should be disabled for power conservation after the modem tone window has passed. Once a valid modem tone is detected, a register bit will be set accordingly and the user can check the results by reading the register value. A programmable debounce interval is provided to eliminate false detection and can be programmed in increments of 67 ms by writing to the appropriate register. Audio Path Processing Unlike traditional SLICs, the Dual ProSLIC devices integrate the codec function into the same IC. The onchip 16-bit codec offers programmable gain/attenuation blocks and multiple loopback modes for self testing. The signal path block diagram is shown in Figure 11 on page 22. Transmit Path In the transmit path, the analog signal fed by the external ac coupling capacitors is passed through an anti-aliasing filter before being processed by the A/D converter. An analog mute function is provided directly prior to the A/D converter input. The output of the A/D converter is an 8 kHz, 16-bit wide, linear PCM data stream. The standard requirements for transmit path 60 In the receive path, the optionally compressed 8-bit data is first expanded to 16-bit words. The PCMF register bit can bypass the expansion process, so that two 8-bit words are assembled into one 16-bit word. RPGA is the receive path programmable gain amplifier which can be programmed from –∞ dB to 6 dB. An 8 kHz, 16-bit signal is then provided to a D/A converter. An analog mute function is provided directly after the D/A converter. When not muted, the resulting analog signal is applied at the input of the transconductance amplifier, Gm, which drives the off-chip current buffer, IBUF. TPGA/RPGA Gain/Attenuation Blocks The TPGA and RPGA blocks are essentially linear multipliers with the structure illustrated in Figure 39. Both blocks can be independently programmed from –∞ to +6 dB (0 to 2 linear scale). The TXGAIN and RXGAIN RAM locations are used to program each block. A setting of 0000h will mute all audio signals; a setting of 4000h will pass the audio signal with no gain or attenuation (0 dB), and a setting of 7FFFh will provide the maximum 6 dB of gain to the incoming audio signal. The DTXMUTE and DRXMUTE bits in the DIGCON register are also available in order to allow muting of the transmit and receive paths without requiring modifications to the TXGAIN or RXGAIN settings. Preliminary Rev. 0.91 Si3220/Si3225 TPGA or RPGA PCM In X PCM Out The group delay distortion in either path is limited to no more than the levels indicated in Figure 9. The reference in Figure 9 is the smallest group delay for a sine wave in the range of 500 Hz to 2500 Hz at 0 dBm0. M where M = {0, 1/16384, 2/16384,...32767/16384} Figure 39. TPGA and RPGA structure Audio Characteristics The dominant source of distortion and noise in both the transmit and receive paths is the quantization noise introduced by the µ-law or the A-law compression process. Figure 5 on page 18 specifies the minimum Signal-to-Noise-and-Distortion Ratio for either path for a sine wave input of 200 Hz to 3400 Hz. Both the µ-law and the A-law speech encoding allow the audio codec to transfer and process audio signals larger than 0 dBm0 without clipping. The maximum PCM code is generated for a µ-law encoded sine wave of 3.17 dBm0 or an A-law encoded sine wave of 3.14 dBm0. The device overload clipping limits are driven by the PCM encoding process. Figure 6 on page 19 shows the acceptable limits for the analog-to-analog fundamental power transfer-function, which bounds the behavior of the device. The transmit path gain distortion versus frequency is shown in Figure 7 on page 19. The same figure also presents the minimum required attenuation for out-ofband analog signals applied on the line. The presence of a high-pass filter transfer-function ensures at least 30 dB of attenuation for signals below 65 Hz. The lowpass filter transfer function attenuates signals above 3.4 kHz. It is implemented as part of the A-to-D converter. The receive path transfer function requirement, shown in Figure 8 on page 20, is very similar to the transmit path transfer function. The PCM data rate is 8 kHz so no frequencies greater than 4 kHz are digitally encoded in PCLK the data stream. At frequencies greater than 4 kHz, the plot in Figure 8 is interpreted as the maximum allowable magnitude of spurious signals that are generated when a PCM data stream representing a sine wave signal in the range of 300 Hz to 3.4 kHz at a level of 0 dBm0 is applied at the digital input. The block diagram for the voice-band signal processing paths are shown in Figure 11 on page 22. Both the receive and the transmit paths employ the optimal combination of analog and digital signal processing for maximum performance while maintaining sufficient flexibility for users to optimize their particular application of the device. The two-wire (TIP/RING) voice-band interface to the device is implemented with a small number of external components. The receive path interface consists of a unity-gain current buffer, IBUF, while the transmit path interface is an ac coupling capacitor. Signal paths, although implemented differentially, are shown as single-ended for simplicity. System Clock Generation The Dual ProSLIC devices generate the internal clock frequencies from the PCLK input. PCLK must be synchronous to the 8 kHz FSYNC clock and run at one of the following rates: 256 kHz, 512 kHz, 786 kHz, 1.024 MHz, 1.536 MHz, 1.544 MHz, 2.048 MHz, 4.096 MHz or 8.192 MHz. The ratio of the PCLK rate to the FSYNC rate is determined by a counter clocked by PCLK. The three-bit ratio information is transferred into an internal register, PLL_MULT, after a device reset. The PLL_MULT controls the internal PLL which multiplies PCLK to generate the rate required to run the internal filters and other circuitry. The PLL clock synthesizer settles quickly after powerup or update of the PLL_MULT register. However, the settling time depends on the PCLK frequency and it is approximately predicted by the following equation: Tsettle = 64/FPCLK VCO PFD ÷2 ÷2 28.672 MHz DIV M RESET PLL_MULT Figure 40. PLL Frequency Synthesizer Preliminary Rev. 0.91 61 Si3220/Si3225 Interrupt Logic The Dual ProSLIC devices are capable of generating interrupts for the following events: ! Loop current/ring ground detected. Ring trip detected. ! Ground Key detected. ! Power alarm. ! DTMF digit detected. ! Active timer 1 expired. ! Inactive timer 1 expired. ! Active timer 2 expired. ! Inactive timer 2 expired. ! Ringing active timer expired. ! Ringing inactive timer expired. ! Pulse metering active timer expired. ! Pulse metering inactive timer expired. ! RAM address access complete. ! Receive path modem tone detected. ! Transmit path modem tone detected. The interface to the interrupt logic consists of six registers. Three interrupt status registers (IRQ0–IRQ3) contain 1 bit for each of the above interrupt functions. These bits are set when an interrupt is pending for the associated resource. Three interrupt mask registers (IRQEN1–IRQEN3) also contain 1 bit for each interrupt function. For interrupt mask registers, the bits are active high. Refer to the appropriate functional description text for operational details of the interrupt functions. ! When a resource reaches an interrupt condition, it signals an interrupt to the interrupt control block. The interrupt control block sets the associated bit in the interrupt status register if the mask bit for that interrupt is set. The INT pin is a NOR of the bits of the interrupt status registers. Therefore, if a bit in the interrupt status registers is asserted, IRQ asserts low. Upon receiving the interrupt, the interrupt handler should read interrupt status registers to determine which resource requests service. All interrupt bits in the interrupt status registers IRQ0–IRQ3 are cleared following a register read operation. If the interrupt status registers are non-0, the INT pin remains asserted. eight devices (up to sixteen channels). The device operates with both 8-bit and 16-bit SPI controllers. Each SPI operation consists of a control byte, an address byte (of which only the seven LSBs are used internally), and either one or two data bytes depending on the width of the controller and whether the access is to an 8-bit register or 16-bit RAM address. Bytes are always transmitted MSB first. There are variations of usage on this four-wire interface as follows: ! Continuous clocking. During continuous clocking, the data transfers are controlled by the assertion of the CS pin. CS must be asserted before the falling edge of SCLK on which the first bit of data is expected during a read cycle, and must remain low for the duration of the 8-bit transfer (command/ address or data), going high after the last rising of SCLK after the transfer. ! Clock during transfer only. In this mode, only the clock is cycling during the actual byte transfers. Each byte transfer will consist of eight clock cycles in a return to “1” format. ! SDI/SDO wired operation. Independent of the clocking options described, SDI and SDO can be treated as two separate lines or wired together if the master is capable of tri-stating its output during the data byte transfer of a read operation. ! Soft reset. The SPI state machine resets whenever CS asserts during an operation on an SCLK cycle that is not a multiple of eight. This is a mechanism for the controller to force the state machine to a known state when the controller and the device are out of synchronization. SPI Control Interface The control interface to the Dual ProSLIC devices is a 4-wire interface modeled after micro-controller and serial peripheral devices. The interface consists of a clock (SCLK), chip select (CS), serial data input (SDI), and serial data output (SDO). In addition, the Dual ProSLIC devices include a serial data through output (SDI_THRU) to support a daisy-chain operation of up to 62 Preliminary Rev. 0.91 Si3220/Si3225 The control byte has the following structure and is presented on the SDI pin MSB first. 7 6 BRDCST R/W 5 4 REG/RAM Reserved 3 2 1 0 CID[0] CID[1] CID[2] CID[3] The bits are defined as follows: Table 37. SPI Control Interface 7 6 BRDCST Indicates a broadcast operation that is intended for all devices in the daisy chain. This is only valid for write operations, since it would cause contention on the SDO pin during a read. R/W Read/Write Bit. 0 = Write operation. 1 = Read operation. 5 REG/RAM Register/RAM Access Bit. 0 = RAM access. 1 = Register access. 4 Reserved 3:0 CID[3:0] Indicates the channel that is targeted by the operation. The 4-bit channel value is provided LSB first. The devices reside on the daisy chain such that device 0 is nearest to the controller and device 15 is furthest down the SDI/SDU_THRU chain. (See Figure 41.) As the CID information propagates down the daisy chain, each channel decrements the CID by 1. The SDI nodes between devices reflects a decrement of 2 per device since each device contains two channels. The device receiving a value of 0 in the CID field responds to the SPI transaction. (See Figure 42.) If a broadcast to all devices connected to the chain is requested, the CID does not decrement. In this case, the same 8-bit or 16-bit data is presented to all channels regardless of the CID values. Preliminary Rev. 0.91 63 Si3220/Si3225 SDI0 SDI S DO C PU CS CS S DI SDO Channel 0 SDI1 Dual P roS LIC #1 Channel 1 SDITHRU SDI2 SDI CS Channel 2 SDI3 SDO Dual P roS LIC #2 Channel 3 SDITHRU SDI4 SDI14 SDI CS Channel 14 SDI15 SDO Channel 15 SDITHRU Figure 41. SPI Daisy-Chain Mode 64 Preliminary Rev. 0.91 Dual P roS LIC #8 Si3220/Si3225 In Figure 42 the CID field is 0. As this field is decremented (in LSB to MSB order) the value decrements for each SDI down the line. The BRDCST, R/W, and REG/RAM bits remain unchanged as the control word passes through the entire chain. The odd SDIs are internal to the device and represent the SDI to SDI_THRU connection between channels of the same device. A unique CID is presented to each channel, and the channel receiving a CID value of zero is the target of the operation (channel 0 in this case). The last line of Figure 42 illustrates that in Broadcast mode, all bits pass through the chain without permutation. SPI Control Word BRDCST R/W REG/RAM Reserved CID[0] CID[1] CID[2] CID[3] SDI0 0 A B C 0 0 0 0 SDI1 (Internal) 0 A B C 1 1 1 1 SDI2 0 A B C 0 1 1 1 SDI3 (Internal) 0 A B C 1 0 1 1 SDI 14 0 A B C 0 1 0 0 SDI15 (Internal) 0 A B C 1 0 0 0 SDI0-15 1 A B C D E F G Figure 42. Sample SPI Control Word to Address Channel 0 Preliminary Rev. 0.91 65 Si3220/Si3225 Figures 43 and 44 illustrate WRITE and READ operations to register addresses via an 8-bit SPI controller. These operations are performed as a 3-byte transfer. CS is asserted between each byte which is required for CS to be asserted before the first falling edge of SCLK after the DATA byte to indicate to the state machine that one byte only should be transferred. The state of SDI is a “don’t care” during the DATA byte of a read operation. CS SCLK SDI CONTROL ADDRESS DATA [7:0] Hi-Z SDO Figure 43. Register Write Operation via an 8-Bit SPI Port CS SCLK SDI CONTROL ADDRESS XXXXXXXX Data [7:0] SDO Figure 44. Register Read Operation via an 8-Bit SPI Port CS SCLK SDI CONTROL ADDRESS Data [7:0] XXXXXXXX Hi - Z SDO Figure 45. Register Write Operation via a 16-Bit SPI Port CS SCLK SDI CONTROL ADDRESS XXXXXXXX Data [7:0] SDO XXXXXXXX Data [7:0] Same byte repeated twice. Figure 46. Register Read Operation via a 16-Bit SPI Port 66 Preliminary Rev. 0.91 Si3220/Si3225 Figures 45 and 46 illustrate WRITE and READ operations to register addresses via a 16-bit SPI controller. These operations require a 4-byte transfer arranged as two 16-bit words. The absence of CS going high after the eighth bit of data indicates to the SPI state machine that eight more SCLK pulses follow to complete the operation. For a WRITE operation, the last eight bits are ignored. For a read operation, the 8-bit data value repeats so that the data is captured during the last half of a data transfer if required by the controller. During register accesses, the CONTROL, ADDRESS, and DATA are captured in the SPI module. At the completion of the ADDRESS byte of a READ access, the contents of the addressed register move into the data register of the SPI data register. At the completion of the DATA byte of a WRITE access, the data is transferred from the SPI to the addressed register. Figures 47–50 illustrate the various cycles for accessing RAM addresses. RAM addresses are 16-bit entities; therefore, the accesses always require four bytes. During RAM address accesses, the CONTROL, ADDRESS, and DATA are captured in the SPI module. At the completion of the ADDRESS byte of a READ access, the contents of the channel-based data buffer move into the data register in the SPI for shifting out during the DATA portion of the SPI transfer. This is the data loaded into the data buffer in response to the previous RAM address read request. Therefore, there is a one-deep pipeline nature to RAM address READ operations. At the completion of the DATA portion of the READ cycle, the ADDRESS is transferred to the channel-based address buffer register and a RAM address is logged for that channel. The RAMSTAT bit in each channel is polled to monitor the status of RAM address accesses that are serviced twice per sample period at dedicated windows in the DSP algorithm. A RAM access interrupt in each channel indicates that the pending RAM access request is serviced. For a RAM access, the ADDRESS and DATA is transferred from the SPI registers to the address and data buffers in the appropriate channel. The RAM WRITE request will be then logged. As for READ operations, the status of the pending request is monitored by either polling the RAMSTAT bit for the channel or enabling the RAM access interrupt for the channel. By keeping the address, data buffers, and RAMSTAT register on a per channel basis, RAM address accesses can be scheduled for both channels without interface. CS SCLK SDI CONTROL ADDRESS DATA [15:8] DATA [7:0] SDO Hi-Z Figure 47. RAM Write Operation via an 8-Bit SPI Port CS SCLK SDI SDO CONTROL ADDRESS xxxxxxxx xxxxxxxx DATA [15:8] DATA [7:0] Figure 48. RAM Read Operation via an 8-Bit SPI Port Preliminary Rev. 0.91 67 Si3220/Si3225 CS SCLK SDI CONTROL ADDRESS Data [15:8] Data [7:0] Hi - Z SDO Figure 49. RAM Write Operation via a 16-Bit SPI Port CS SCLK SDI CONTROL ADDRESS Data [15:8] SDO Figure 50. RAM Read Operation via a 16-Bit SPI Port 68 Preliminary Rev. 0.91 Data [7:0] Si3220/Si3225 PCM Interface The Dual ProSLIC devices contain a flexible programmable interface for the transmission and reception of digital PCM samples. PCM data transfer is controlled by the PCLK and FSYNC inputs, PCM Mode Select, PCM Transmit Start Count (PCMTXHI/ PCMTXLO), and PCM Receive Start Count (PCMRXHI/ PCMRXLO) registers. The interface can be configured to support from 4 to 128 8-bit timeslots in each frame. This corresponds to PCLK frequencies of 256 kHz to 8.192 MHz in power of 2 increments. (768 kHz, 1.536 MHz and 1.544 MHz also are available.) Timeslots for data transmission and reception are independently configured with the PCMTXHI, PCMTXLO, PCMRXHI, and PCMRXLO. Setting the correct starting point of the data configures the part to support long FSYNC and short FSYNC variants, IDL2 8bit, 10-bit, B1 and B2 channel time slots. DTX data is high-impedance except for the duration of the 8-bit PCM transmit. DTX returns to high-impedance on the negative edge of PCLK during the LSB or on the positive edge of PCLK following the LSB. This is based on the setting of the PCMTRI bit of the PCM Mode Select register. Tristating on the negative edge allows the transmission of data by multiple sources in adjacent timeslots without the risk of driver contention. In addition to 8-bit data modes, there is a 16-bit mode provided for testing. This mode can be activated via the PCMF bits of the PCM Mode Select register. Setting the PCMTXHI/ PCMTXLO or PCMRXHI/PCMRXLO register greater than the number of PCLK cycles in a sample period stops data transmission because PCMTXHI/PCMTXLO or PCMRXHI/PCMRXLO do not equal the PCLK count. Figures 51–53 illustrate the usage of the PCM highway interface to adapt to common PCM standards. PCLK FSYNC 0 PCLK_CNT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 DRX MSB LSB MSB LSB DTX HI-Z HI-Z Figure 51. Example, Timeslot 1, Short FSYNC (TXS/RXS = 1) PCLK FSYNC 0 PCLK_CNT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 DRX MSB LSB MSB LSB DTX HI-Z HI-Z Figure 52. Example, Timeslot 1, Long FSYNC (TXS/RXS = 0) Preliminary Rev. 0.91 69 Si3220/Si3225 PCM Companding The Dual ProSLIC devices support both µ-255 Law (µLaw) and A-Law companding formats in addition to Linear Data mode. The data format is selected via the PCMF bits of the PCM Mode Select register. µ-Law mode is more commonly used in North America and Japan, and A-Law is primarily used in Europe and other countries. These 8-bit companding schemes follow a segmented curve formatted as a sign bit (MSB) followed by three chord bits and four step bits. A-Law typically uses a scheme of inverting all even bits while µ-Law does not. Dual ProSLIC devices also support A-Law with inversion of even bits, inversion of all bits, or no bit inversion by programming the ALAW bits of the PCM Mode Select register to the appropriate setting. Tables 38 and 39 define the µ-Law and A-Law encoding formats. The Dual ProSLIC devices also support a 16-bit linear data format with no companding. This Linear mode is typically used in systems that convert to another companding format such as adaptive delta PCM (ADPCM) or systems that perform all companding in an external DSP. The data format is 2’s complement with MSB first (sign bit). Transmitting and receiving data via Linear mode requires two continuous time slots. An 8-bit Linear mode enables 8-bit transmission without companding. PCLK FSYNC 0 PCLK_CNT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 DRX MSB LSB MSB LSB DTX HI-Z HI-Z Figure 53. Example, IDL2 Long FSYNC, B2, 10-Bit Mode (TXS/RXS = 10) PCLK FSYNC 0 PCLK_CNT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 DRX DTX MSB LSB MSB LSB HI-Z HI-Z Figure 54. 16-Bit Linear Mode Example, Timeslots 1 and 2, Long FSYNC 70 Preliminary Rev. 0.91 Si3220/Si3225 Table 38. µ-Law Encode-Decode Characteristics* Segment Number #Intervals X Interval Size Value at Segment Endpoints Digital Code Decode Level 8 16 X 256 8159 . . . 4319 4063 10000000b 8031 10001111b 4191 . . . 2143 2015 10011111b 2079 . . . 1055 991 10101111b 1023 . . . 511 479 10111111b 495 . . . 239 223 11001111b 231 . . . 103 95 11011111b 99 . . . 35 31 11101111b 33 . . . 3 1 0 11111110b 11111111b 2 0 7 6 5 4 3 2 1 16 X 128 16 X 64 16 X 32 16 X 16 16 X 8 16 X 4 15 X 2 __________________ 1 X 1 *Note: Characteristics are symmetrical about analog zero with sign bit = 0 for negative analog values. Preliminary Rev. 0.91 71 Si3220/Si3225 Table 39. A-Law Encode-Decode Characteristics1,2 Segment Number #intervals X interval size Value at segment endpoints 7 16 X 128 4096 3968 . . 2176 2048 6 5 4 3 2 1 16 X 64 16 X 32 16 X 16 16 X 8 16 X 4 32 X 2 Digital Code Decode Level 10101010b 4032 10100101b 2112 . . . 1088 1024 10110101b 1056 . . . 544 512 10000101b 528 . . . 272 256 10010101b 264 . . . 136 128 11100101b 132 . . . 68 64 11110101b 66 . . . 2 0 11010101b 1 Notes: 1. Characteristics are symmetrical about analog zero with sign bit = 0 for negative values. 2. Digital code includes inversion of even numbered bits. Other available formats include inversion of odd bits, inversion of all bits, or no bit inversion. See "PCM Companding" on page 70 for more details. 72 Preliminary Rev. 0.91 Si3220/Si3225 General Circuit Interface The Dual ProSLIC devices also contain an alternate communication interface to the SPI and PCM control and data interface. The general circuit interface (GCI) is used for the transmission and reception of both control and data information onto a GCI bus. The PCM and GCI interfaces are both four-wire interfaces and share the same pins. The SPI control interface is not used as a communication interface in the GCI mode, but rather as hard-wired channel selector pins. The selection between PCM and GCI modes is performed out of reset using the SDITHRU pin. Tables 40 and 41 illustrate how to select the communication mode and how the pins are used in each mode. If GCI mode is selected, the following pins must be tied to the correct state to select one of eight sub-frame timeslots in the GCI frame (described below). These pins must remain in this state while the Dual ProSLIC is operating. Selecting a particular subframe causes that individual Dual ProSLIC device to transmit and receive on the appropriate sub-frame in the GCI frame, which is initiated by an FSYNC pulse. No further register settings are needed to select which sub-frame a device uses, and the sub-frame for a particular device cannot be changed while in operation. Table 42. GCI Mode Sub-Frame Selection SDI SDO CS GCI Subframe 0 Selected (Voice channels 1–2) 1 1 1 GCI Subframe 1 Selected (Voice channels 3–4) 1 1 0 GCI Subframe 2 Selected (Voice channels 5–6) 1 0 1 Note: Values shown are the states of the pins at the rising edge of RESET. GCI Subframe 3 Selected (Voice channels 7–8) 1 0 0 Table 41. Pin Functionality in PCM or GCI Mode GCI Subframe 4 Selected (Voice channels 9–10) 0 1 1 Pin Name PCM Mode 1 0 SPI Chip Select GCI Subframe 5 Selected (Voice channels 11–12) 0 CS GCI Subframe 6 Selected (Voice channels 13–14) 0 0 1 GCI Subframe 7 Selected (Voice channels 15–16) 0 0 0 Table 40. PCM or GCI Mode Selection SDITHRU SCLK 0 0 1 SCLK SDI SDO SDITHRU FSYNC PCLK DTX DRX 0 1 x Mode Selected GCI Mode—1x PCLK (2.048 MHz) GCI Mode—2x PCLK (4.096 MHz) PCM Mode GCI Mode Channel Selector, bit 0 SPI Clock Input PCLK Rate Selector SPI Serial Data Input Channel Selector, bit 2 SPI Serial Data Channel Selector, Output bit 1 SPI Data ThroughPCM/GCI Mode put pin for Daisy Selector Chaining Operation (Connects to the SDI pin of the subsequent device in the daisy chain) PCM Frame Sync GCI Frame Sync Input Input PCM Input Clock GCI Input Clock PCM Data Transmit GCI Data Transmit PCM Data Receive GCI Data Receive Note: This table denotes pin functionality after the rising edge of RESET and mode selection. In GCI mode, the PCLK input requires either a 2.048 MHz or a 4.096 MHz clock signal, and the FSYNC input requires an 8 kHz frame sync signal. The overall unit of data used to communicate on the GCI highway is a frame 125 µs in length. Each frame is initiated by a pulse on the FSYNC pin, whose rising edge signifies the beginning of the next frame. In 2x PCLK mode, the user sees twice as many PCLK cycles during each 125 µs frame versus 1x PCLK mode. Each frame consists of eight fixed timeslot sub-frames, which are assigned by the Sub-Frame Select pins as described above (SDI, SDO, and CS). Within each subframe are four channels (bytes) of data, including two voice data channels B1 and B2, one Monitor channel M used for initialization and setup of the device, and one Signaling and Control channel (SC) used for communicating status of the device and for initiating commands. Within the SC channel are six Command/ Preliminary Rev. 0.91 73 Si3220/Si3225 Indicate (C/I) bits and two handshaking bits, MR and MX. The C/I bits indicate status and command communication, while the handshaking bits Monitor Receive (MR) and Monitor Transmit (MX), exchange data in the Monitor channel. Figure 55 illustrates the contents of a GCI highway frame. to sixteen voice channels in 8-bit GCI mode). Table 43 describes the GCI mode sub-frame selection for 16-bit GCI mode. Table 43. Sub-Frame Selection 16-Bit GCI Mode SDI SDO GCI Subframe 0 Selected (Voice channels 0–1) 1 1 GCI Subframe 1 Selected (Voice channels 2–3) 1 0 GCI Subframe 2 Selected (Voice channels 4–5) 0 1 GCI Subframe 3 Selected (Voice channels 6–7) 0 0 16-Bit GCI Mode In addition to the standard 8-bit GCI mode, the Dual ProSLIC devices also offer a 16-bit GCI mode for passing 16-bit voice data to the upstream host processor. This mode can be used for testing purposes or for passing non-companded voice data to an upstream DSP for further processing. In 16-bit GCI mode, both of the 8-bit voice data channels (B1 and B2, Figure 56) of each sub-frame are required to pass the 16-bit voice data to the host. Each 125 µs frame can therefore accommodate up to eight voice channels (the Dual ProSLIC can accommodate up 125 µs = 1 Frame FS SF0 SF1 SF2 SF3 SF4 SF5 SF6 Sub-Frame 8 8 8 B1 B2 M SC 0 1 2 3 1 Channel C/I 1 MR MX Figure 55. Time-Multiplexed GCI Highway Frame Structure 74 Preliminary Rev. 0.91 SF7 Si3220/Si3225 125 µs = 1 Frame FS CH0 CH1 CH2 CH3 Sub-Frame 16 8 6 1 1 16 16 B1 M C/I MR MX B2 Unused Figure 56. GCI Highway Frame Structure for 16-Bit GCI Mode Monitor Channel as the data sent by the Dual ProSLIC devices to a host. The Monitor channel is used for initialization and setup of the Dual ProSLIC devices. It is also for general communication with the Dual ProSLIC by allowing read and write access to the Dual ProSLIC devices registers. Use of the monitor channel requires manipulation of the MR and MX handshaking bits, located in bits 1 and 0 of the SC channel described. For purposes of this specification, “downstream” is identified as the data sent by a host to the Dual ProSLIC. “Upstream” is identified The following diagram illustrates the Monitor channel communication protocol. For successful communication with the Dual ProSLIC, the transmitter should anticipate the falling edge of the receiver’s acknowledgement. This also maximizes communication speed. Because of the handshaking protocol required for successful communication, the data transfer rate using the Monitor channel is less than 8 kbps. 1st Byte 2nd Byte 3rd Byte MX Transm itter MX MR Receiver MR ACK 1st Byte ACK 2nd Byte ACK 3rd Byte 125 µ s Figure 57. Monitor Handshake Timing Preliminary Rev. 0.91 75 Si3220/Si3225 The Idle state is achieved by the MX and MR bits being held inactive for two or more frames. When a transmission is initiated by a host device, an active state is seen on the downstream MX bit. This signals the Dual ProSLIC that a transmission has begun on the Monitor channel and it should begin accepting data from it. The Dual ProSLIC, after reading the data on the Monitor channel, acknowledges the initial transmission by placing the upstream MR bit in an active state. The data is received and the upstream MR becomes active in the frame immediately following the downstream MX becoming active. The upstream MR then remains active until either the next byte is received or an end of message is detected (signaled by the downstream MX being held inactive for two or more consecutive frames). Upon receiving acknowledgement from the Dual ProSLIC that the initial data was received (signaled by the upstream MR bit transitioning from an inactive to an active state), the host device places the downstream MX bit in the inactive state for one frame and then either transmit another byte by placing the downstream MX bit in an active state again, or signal an end of message by leaving the downstream MX bit inactive for a second frame. When the host is performing a write command, the host only manipulates the downstream MX bit, and the Dual ProSLIC only manipulates the upstream MR bit. If a read command is performed, the host initially manipulates the downstream MX bit to communicate the command, but then manipulates the downstream MR bit in response to the Dual ProSLIC responding with the requested data. Similarly, the Dual ProSLIC initially manipulates its upstream MR bit to receive the read command, and will then manipulate its upstream MX bit to respond with the requested data. If the host is transmitting data, the Dual ProSLIC always transmits a $FF value on its Monitor data byte. While the Dual ProSLIC is transmitting data, the host should always transmit a $FF value on its Monitor byte. If the Dual ProSLIC is transmitting data and detects a value other than a $FF on the downstream Monitor byte, the Dual ProSLIC signals an Abort. For read and write commands, an initial address must be specified. The Dual ProSLIC responds to a read or a write command at this address, and then subsequently increment this address after every register access. In this manner, multiple consecutive registers can be read or written in one transmission sequence. By correctly manipulating the MX and MR bits, a transmission sequence can continue from the beginning specified address until an invalid memory location is reached. To end a transmission sequence, the host processor must signal an End-of-Message (EOM) by placing the 76 downstream MX and MR bits inactive for two consecutive frames. The transmission can also be stopped by the Dual ProSLIC by signaling an Abort. This is signaled by placing the upstream MR bit inactive for at least two consecutive cycles in response to the downstream MX bit going active. An abort is signaled by the Dual ProSLIC for the following reasons: ! A read or write to an invalid memory address is attempted. ! An invalid command sequence is received. ! A data byte was not received for at least two consecutive frames. ! A collision occurs on the Monitor data bytes while the Dual ProSLIC is transmitting data. ! Downstream monitor byte not $FF while upstream monitor byte is transmitting. ! MR/MX protocol violation Whenever the Dual ProSLIC aborts due to an invalid command sequence, the state of the Dual ProSLIC does not change. If a read or write to an invalid memory address is attempted, all previous reads or writes in that transmission sequence are valid up to the read or write to the invalid memory address. If an end-of-message is detected before a valid command sequence is communicated, the Dual ProSLIC returns to the idle state and remains unchanged. The data presented to the Dual ProSLIC in the downstream Monitor bits must be present for two consecutive frames to be considered valid data. The Dual ProSLIC is designed to ensure it has received the same data in two consecutive frames. If it does not, it does not acknowledge receipt of the data byte and waits until it does receive two consecutive identical data bytes before acknowledging to the transmitter it has received the data. If the transmitter attempts to signal transmission of a subsequent data byte by placing the downstream MX bit in an inactive state while the Dual ProSLIC is still waiting to receive a valid data byte transmission of two consecutive identical data bytes, the Dual ProSLIC signals an abort and ends the transmission. Figure 58 shows a state diagram for the Receiver Monitor channel for the Dual ProSLIC. Figure 59 shows a state diagram for the Transmitter Monitor channel for the Dual ProSLIC. Preliminary Rev. 0.91 Si3220/Si3225 Idle MR = 1 M X * LL Initial S tate MX 1s t By te Rec eiv ed MR = 0 MX A bort MR = 1 MX ABT MX A ny S tate MX MX Wait f or LL MR = 0 M X * LL M X * LL By te V alid MR = 0 M X * LL MX M X * LL MX New By te MR = 1 MX nth by te rec eiv ed MR = 1 M X * LL Wait f or LL MR = 0 MX MR : MR bit calcu lated and tran s m itted on d ata ups tream (D TX) line. MX: MX b it received d ata dow n s trea m (D R X) lin e. LL: Las t look of m onitor b yte received on D R X line. ABT: Abort ind ication to in terna l s ource. Figure 58. Dual ProSLIC Monitor Receiver State Diagram Preliminary Rev. 0.91 77 Si3220/Si3225 M R * M XR M XR Idle MR = 1 M R * M XR Wait MX = 1 M R * M XR A bort MX = 1 Initial S tate M R * RQT MR 1s t By te MX = 0 M R * RQT EOM MX = 1 MR M R * RQT nth By te ac k MX = 1 MR M R * RQT MR Wait f or ac k MX = 0 M R * RQT CLS /A B T A ny S tate MR : MR bit received on D R X line. MX: MX bit calculated and expected on D TX line. MXR : MX bit s am pled on D TX line. C LS: C ollis ion w ithin the m onitor data byte on D TX line. R QT: R eques t for trans m is s ion from internal s ource. ABT: Abort reques t/indication. Figure 59. Dual ProSLIC Monitor Transmitter State Diagram Figures 60 and 61 are example timing diagrams of a register read and a register write to the Dual ProSLIC using the GCI. As noted in Figure 59, the transmitter should always anticipate the acknowledgement of the 78 receiver for correct communication with the Dual ProSLIC. Devices that do not accept this “best case” timing scenario will not be able to communicate with the Dual ProSLIC. Preliminary Rev. 0.91 M onitor Da ta Dow nstre a m $FF $FF $91 $91 $81 $81 $10 $10 $FF $FF $FF $FF $FF $FF $FF $FF $FF 125 µ s 1 Frame M X Dow nstre a m Bit M R Dow nstre a m Bit Preliminary Rev. 0.91 EOM Signalled M onitor Da ta Upstre a m $FF $FF $FF $FF $FF $FF $FF $FF $FF $91 $91 C ontents of C ontents of C ontents of C ontents of C ontents of R eg ister $10 R eg ister $10 R eg ister $11 R eg ister $11 R eg ister $12 (ig nored by host) $FF M X Upstre a m Bit = Acknow ledgem ent of data reception s ends addres s before data Figure 60. Example Read of Registers $10 and $11 in Channel 0 of the Dual ProSLIC EOM Acknow ledge 79 Si3220/Si3225 M R Upstre a m Bit $FF $FF $91 $91 $01 $01 $10 $10 D ata to be D ata to be D ata to be D ata to be written to $10 written to $10 written to $11 written to $11 $FF $FF 125 µ s 1 Frame M X Dow nstre a m Bit M R Dow nstre a m Bit Preliminary Rev. 0.91 EOM Signalled M onitor Da ta Upstre a m $FF $FF $FF $FF $FF $FF $FF $FF $FF $FF $FF $FF $FF $FF M X Upstre a m Bit M R Upstre a m Bit = Acknow ledgem ent of data reception EOM Acknow ledge Figure 61. Example Write to Registers $10 and $11 in Channel 0 of the Dual ProSLIC Si3220/Si3225 80 M onitor Da ta Dow nstre a m Si3220/Si3225 Programming the Dual ProSLIC Using the Monitor Channel The Dual ProSLIC devices use the monitor channel to Transfer Status or Operating mode information to and from the host processor. Communication with the Dual ProSLIC should be in the following format: Byte 1: Device Address Byte Byte 2: Command Byte MSB LSB Bit 7 6 5 4 3 2 1 0 Address Byte 1 0 0 A 0 0 0 0 Command Byte 0 0 0 0 0 0 0 0 Immediately after the last bit of the CID command is received, the Dual ProSLIC responds with a fixed twobyte identification code as follows: Byte 3: Register Address Byte Bytes 4-n: Data Bytes Bytes n+1, N+2: EOM MSB Device Address Byte The Device Address Byte identifies which device receives the particular message. This address must be the first byte sent to the Dual ProSLIC at the beginning of each transmission sequence. The Device Address Byte has the following structure: MSB LSB 7 6 5 4 3 2 1 0 1 0 0 A B 0 0 C LSB Bit 7 6 5 4 3 2 1 0 Address Byte 1 0 0 A 0 0 0 0 Command Byte 1 0 1 1 1 1 1 0 A = 1: Channel A is the source A = 0: Channel B is the source A = 1: Channel A receives the command A = 0: Channel A does not receive the command Upon sending the two-byte CID command, the Dual ProSLIC sends an EOM signal (MR = MX = 1) for two consecutive frames. When C = 0, B must be 0 or the Dual ProSLIC signals an abort due to an invalid command. In this mode, only bit C is programmable. B = 1: Channel B receives the command Command Byte B = 0: Channel B does not receive the command The Command Byte has the following structure: C = 1: Normal command follows C = 0: Channel identification command MSB When C = 1, bits A and B are channel enable bits. When these bits are set to 1, the corresponding channels receives the command in the next command byte. The channels with corresponding bits set to 0 ignore the subsequent command byte. Channel Identification (CID) Command The lowest programmable bit of the Device Address Byte, C, enables a special Channel Identification Command to identify themselves by software. The structure of this command is as follows: A = 1: Channel A is the destination A = 0: Channel B is the destination LSB RW CMD[6:0] RW = 1: A Read operation is performed from the Dual ProSLIC RW = 0: A Write operation is performed to the Dual ProSLIC CMD[6:0] = 0000001: Read or Write from the Dual ProSLIC CMD[6:0] = 0000010-1111111: Reserved Register Address Byte The Register Address Byte has the following structure: MSB LSB ADDRESS[7:0] This byte contains the actual 8-bit address of the register to be read or written. Preliminary Rev. 0.91 81 Si3220/Si3225 SC Channel The downstream and upstream SC channels are continuously carrying I/O information to and from the Dual ProSLIC during every frame. The upstream processor has immediate access to the receive (downstream) and transmit (upstream) data present on the Dual ProSLIC’s digital I/O port when used in GCI mode. The SC channel consists of six C/I bits and two handshaking bits as described in the tables below. The functionality of the handshaking bits is defined in the Monitor Channel section. This section defines the functionality of the six C/I bits whether they are being transmitted to the GCI bus via the DTX pin (upstream) or received from the GCI bus via the DRX pin (downstream). The structure of the SC channel is shown in Figure 62. MSB LSB 7 6 5 4 3 2 1 0 CI2A CI1A CI0A CI2B CI1B CI0B MR MX Figure 62. SC Channel Structure Downstream (Receive) SC Channel Byte The first six bits in the downstream SC channel control both channels of the Dual ProSLIC where the C/I bits are defined as follows: CI2A, CI1A, CI0A Used to select operating mode for channel A CI2B, CI1B, CI0B Used to select operating mode for channel B MR, MX Monitor channel handshake bits Table 44. Programming Operating Modes Using Downstream SC Channel C/I Bits Channel Specific C/I bits Dual ProSLIC Operating Mode CI2x CI1x CI0x 0 0 0 Open (high impedence, no line monitoring) 0 0 1 Forward Active 0 1 0 Forward On-Hook Transmission 0 1 1 Ground Start (Tip Open) 82 Table 44. Programming Operating Modes Using Downstream SC Channel C/I Bits (Continued) 1 0 0 Ringing 1 0 1 Reverse Active 1 1 0 Reverse On-Hook Transmission 1 1 1 Ground Start (Ring Open) Note: x = A or B, corresponding to channel A or channel B. Figure 63 illustrates the transmission protocol for the C/I bits within the downstream SC channel. New data received by either channel must be present and match for two consecutive frames to be considered valid. When a new command is communicated via the downstream C/I bits, this data must be sent for at least two consecutive frames to be recognized by the Dual ProSLIC. The current state of the C/I bits is stored in a primary register P. If the received C/I bits are identical to the current state, no action is taken. If the received C/I bits differ from those in register P, the new set of C/I bits is loaded into secondary register S and a latch is set. When the next set of C/I bits is received during the frame that immediately follows, the following rules apply: ! If the received C/I bits are identical to the contents of register S, the stored C/I bits are loaded into register P and a valid C/I bit transition is recognized. The latch is reset and the Dual ProSLIC responds accordingly to the command represented by the new C/I bits. ! If the received C/I bits differ from both the contents of register S and the contents of register P, the newly received C/I bits are loaded into register S and the latch remains set. This cycle continues as long as any new set of C/I bits differs from the contents of registers S and P. ! If the newly received C/I bits are identical to the contents of register P, the contents of register P remain unchanged and the latch is reset. Preliminary Rev. 0.91 Si3220/Si3225 Receive New C/I Code = P? Yes No P: C/I Primary Register Contents Store in S S: C/I Secondary Register Contents Receive New C/I Code = S? Load C/I Register With New C/I Bits Yes No = P? Yes No Figure 63. Protocol for Receiving C/I Bits in the Dual ProSLIC When the Dual ProSLIC is set to GCI mode at initialization, the default setting ignores the downstream SC channel byte and allows linefeed state commands to be directed through the monitor channel. This default configuration is enabled by initializing the GCILINE bit of the PCMMODE register to 0, which prevents the Dual ProSLIC from transitioning between linefeed operating states due to invalid data that may exist within the downstream SC channel byte. To transfer direct linefeed control to the downstream SC channel, the user must set the GCILINE bit to 1. Once the GCILINE bit has been set, the Dual ProSLIC follows the commands that are contained in the downstream SC channel byte as described in Figure 62. The Dual ProSLIC architecture also enables automatic transitions between linefeed operating states to reduce the amount of interaction required between the host processor and the Dual ProSLIC. When a GCI bus is implemented, the user must ensure that these automatic linefeed state transitions are consistent with the linefeed commands contained within the downstream SC channel byte. In normal operation these automatic linefeed state transitions are accompanied by the setting of a threshold detection flag and an interrupt bit, if enabled. To allow the Dual ProSLIC to automatically detect the appropriate thresholds and control the linefeed transitions, the downstream SC channel byte should be updated accordingly once the interrupt bit is read from the upstream SC channel byte. To disable the automatic transitions, the user must set the GCILINE bit. Enabling this Manual mode requires the host processor to read the upstream SC channel information and provide the appropriate downstream SC channel byte command to program the correct linefeed state. Table 45 presents the automatic linefeed state transitions and their associated registers that cause the transition. The transition to the OPEN state stemming from power alarm detection is intended to protect the Dual ProSLIC circuit in the event that too much power is dissipated in the Si3200 LFIC. This alarm is typically due to a fault in the application circuit or on the subscriber loop, but can be caused by intermittent power spikes depending on the threshold to which the alarm is set. The user can reinitialize the linefeed operating state that was in effect just prior to the power alarm by toggling the downstream SC channel byte to the OPEN state for two consecutive cycles and then resetting the downstream SC channel byte to the intended linefeed state for two consecutive Preliminary Rev. 0.91 83 Si3220/Si3225 cycles. If the Dual ProSLIC continues to automatically transition to the OPEN state, the power alarm threshold might be set incorrectly. If this problem persists after the power alarm settings are verified, a system fault is probable and the user should take measures to diagnose the problem. Table 45. Automatic Linefeed State Transitions Initiating Action Automatic Linefeed State Transition Loop closure detected On-hook active → off-hook active, Off-hook active → on-hook active Ring trip detected Ringing → off-hook active Ringing burst cadence Ringing → on-hook transmission On-hook transmission → ringing Power alarm detected Any state → open Detection/Control Bits Interrupt Enable/Status Bits LCR (Register 9) LOOPE, LOOPS (Register 16/19) RTP (Register 9) RTRIPE, RTRIPS (Register 16/19) T1EN, T2EN (Register 23) RINGT1E, RINGT2E, RINGT1S, RINGT2S (Register 15/18) PQ1DL (RAM 50) PQ1E, PQ1S (Registers 17/20) Upstream (Transmit) SC Channel Byte The upstream SC channel byte looks similar to the downstream SC channel byte, except that the information quickly transfers the most time-critical information from the Dual ProSLIC to the GCI bus. Each upstream SC channel byte transfer from the Dual ProSLIC lasts for at least two consecutive frames to represent a valid transfer. The upstream C/I bits are defined as follows: CI2A, CI1A, CI0A Monitors status data for channel A CI2B, CI1B, CI0B Monitors status data for channel B MR, MX Monitor channel handshake bits (see Monitor Channel section) Table 46. Monitored Data via Upstream SC Channel C/I Bits C/I Bit Information Provided Context CI2A Interrupt information on channel A CI1A Hook status information on channel A CI1A = 0: Channel A is on-hook CI1A = 1: Channel A is off-hook CI0A Ground key information on channel A CI0A = 0: No longitudinal current detected CI0A = 1: Longitudinal current detected in ch A CI2B Interrupt information on channel B CI1B Hook status information on channel B CI1A = 0: Channel B is on-hook CI1A = 1: Channel B is off-hook CI0B Ground key information on channel B CI0A = 0: No longitudinal current detected CI0A = 1: Longitudinal current detected in ch B The interrupt information for channels A and B is a single bit that indicates that one or more interrupts might exist on the respective channel. Each of the individual interrupt flags (see registers 18–20) can be individually masked by writing the appropriate bit in registers 21–23 84 CI2A = 0: No interrupt on channel A CI2A = 1: Interrupt present on channel A CI2A = 0: No interrupt on channel B CI2A = 1: Interrupt present on channel B to ignore specific interrupts. When using the GCI mode, the user should verify that each of the desired interrupt bits are set so the upstream SC channel byte includes the required interrupt functions. Preliminary Rev. 0.91 Si3220/Si3225 System Testing Line Test and Diagnostics The Dual ProSLIC devices include a complete suite of test tools to test the functionality of the line card and detect fault conditions present on the TIP/RING pair. Using one of the loopback test modes with the signal generation and measurement tools eliminates the need for per-line test relays and centralized test equipment. The Dual ProSLIC devices provide a variety of signal generation and measurement tools that facilitate fault detection and parametric diagnostics on the TIP/RING pair and line card functionality verification. The Dual ProSLIC generates test signals, measures the appropriate voltage/current/signal levels, and processes the results to provide a meaningful result to the user. Interaction is required from the host microprocessor to load the test parameters into the appropriate registers, initiate the test(s), and read the results from the registers. In some cases, the host processor might also be required to perform some simple mathematics to achieve the results. Software modules are available to simplify integration of the diagnostics functions into the system. The need for test relays and a separate test head is eliminated in most applications. To address legacy applications, all versions of the Dual proSLIC include test-in and test-out relay drivers to switch in a centralized test head. Loopback Modes Three loopback test options are available for the Dual ProSLIC devices: ! The codec loopback path encompasses almost entirely the electronics of both the transmit and receive paths. The analog signal at the output of the receive path is fed back to the input of the transmit path through a feedback path on the analog side of the audio codec. Both the impedance synthesis and transhybrid balance functions are disabled in this mode. (See DLM3 path in Figure 11 on page 22.) The signal path starts with 8-bit PCM data input to the receive path and ends with 8-bit PCM data at the output of the transmit path. The user can bypass the companding process and interface directly to the 16bit data. ! A second digital loopback takes the receive path digital stream and routes it back to the transmit path via the transhybrid feedback path. (See DLM2 path through block H in Figure 11.) This mode characterizes the transhybrid filter response. The transhybrid block also can be disabled (set to unity gain) in this mode for diagnosing the digital gain blocks and filter stages in both transmit and receive paths. The signal path starts with 8-bit PCM data input to the receive path and ends with 8-bit PCM data at the output of the transmit path. The user can bypass the companding process and interface directly to the 16-bit data. ! A third digital loopback takes the digital stream at the output of the µ-Law/A-Law expander and feeds it back to the input of the µ-Law/A-Law compressor. (See DLM1 path in Figure 11.) This path verifies that the host is connected correctly with the Dual ProSLIC through the PCM interface and that the PCLK and FSYNC signals are correctly set. This mode also can test the µ-Law/A-Law companding process. The signal path starts with 8-bit PCM data input to the receive path and ends with 8-bit PCM data at the output of the transmit path. The user can also connect directly to the 16-bit data to eliminate the µ-Law/A-Law companding process when testing the PCM interface. The Dual ProSLIC’s line test and diagnostics capabilities are categorized into three sections: signal generation tools, measurement tools, and diagnostics capabilities. Using these signal generation and measurement tools, a variety of other diagnostics functions can also be performed to meet the unique requirements of specific applications. Table 47 summarizes the ranges and capabilities of the signal generation and measurement tools. Preliminary Rev. 0.91 85 Si3220/Si3225 Table 47. Summary of Signal Generation and Measurement Tools Function Range Accuracy/Resolution Comments Signal Generation Tools DC Current Generation 18 to 45 mA 0.875 mA DC Voltage Generation 0 to 63.3 V 1.005 V Audio Tone Generation 200 to 3400 Hz Ringing Signal Generation 4 to 15 Hz 16 to 100 Hz ±5% ±1% Measurement Tools 8-Bit DC/Low Frequency Monitor A/D Converter High Range: 0 to 160.173 V 0 to 101.09 mA 628 mV 396.4 µA Low Range: 0 to 64.07 V 0 to 50.54 mA 251 mV 198.2 µA Programmable Timer 0 to 8.19 s 125 µs AC Low Pass Filter 3 to 400 Hz 16-Bit Audio A/D Converter 0 to 2.5 V Transmit Path Notch Filter 300 to 3400 Hz Transmit Path Bandpass Filter 300 to 3400 Hz Signal Generation Tools ! TIP/RING DC signal generation. The Dual ProSLIC line feed D/A converter can program a constant current linefeed from 18–45 mA in 0.87 mA steps with a ±10% total accuracy. In addition, the opencircuit TIP/RING voltage can be programmed from 0 to 63 V in 1 V steps. The linefeed circuitry also can generate a controlled polarity reversal. ! Tone generation. The Dual ProSLIC devices can generate single or dual tones over the entire audio band, and can direct them into either the transmit or the receive path depending on the diagnostic requirements. Ringing signals from 4–100 Hz also can be generated. ! Diagnostics mode ringing generation. The Dual ProSLIC devices can generate an internal low-level ringing signal to test for the presence of REN without causing the terminal equipment to ring audibly. This ringing signal can be either balance or unbalanced 86 800 Hz update rate acrms, acPK, and dc post-processing blocks 38 µV Single or dual notch, ≥90 dB attenuation depending on the state of the RINGUNB bit of the RINGCON register. This feature is also available with the Si3225 provided that a sufficient battery voltage is present. Preliminary Rev. 0.91 Si3220/Si3225 PEAK DETECT DIAGPK VTIP VRING DIAGDCCO VLOOP VLONG DIAGDC LPF ILOOP DIAGACCO ILONG VRING,EXT FULL WAVE RECTIFY IRING,EXT LPF DIAGAC Figure 64. SLIC Diagnostic Filter Structure Measurement Tools " VLOOP = VTIP-VRING = metallic (loop) voltage ! " VLONG = (VTIP+VRING)/2 = longitudinal voltage " ILOOP = ITIP-IRING = metallic (loop) current " ILOOP = ITIP-IRING = metallic (loop) current " ILONG = (ITIP+IRING)/2 = longitudinal current " VRING, EXT = ringing voltage when using an external ringing source (Si3225 only) IRING,EXT = ringing current when using an external ringing source (Si3225 only) 8-Bit monitor A/D converter. This 8-bit A/D converter monitors all dc and low frequency voltage and current data from TIP to ground and RING to ground. Two additional values, TIP – RING and TIP + RING, are calculated and stored in on-chip registers to analyze metallic and longitudinal effects. The A/D operates at an 800 Hz update rate to allow measurement bandwidth from dc to 400 Hz. A dualrange capability allows high-voltage/high-current measurement in the high range but also can measure lower voltages and currents with a tighter resolution. ! Programmable bandpass filter. A bandpass filter discriminates certain frequency ranges such as ringing frequencies and 50 Hz/60 Hz induction from nearby or crossed power leads. ! SLIC diagnostics filter. Several post-processing filter blocks monitor peak dc and ac characteristics of the Monitor A/D converter outputs and values derived from these outputs. Setting the SDIAG bit in the DIAG register enables the filters. There are separate filters for each channel, and their control is independent. These filters require DSP processing which is available only when voice band processing is not being performed. If an off-hook or a ring trip condition is detected while the SDIAG bit is set, the bit is cleared and the diagnostic information is not processed. The following parameters can be selected as inputs to the diagnostic block by setting the SDIAG bits in the DIAG register to values 0–7 corresponding to the order below: " VTIP = voltage on the TIP lead " VRI NG = voltage on the RING lead " The SLIC diagnostic capability consists of a peak detect block and two filter blocks, one for dc and one for ac. The topology is illustrated in Figure 64. The peak detect filter block reports the magnitude of the largest positive or negative value without sign. The dc filter block consists of a single pole IIR low pass filter with a coefficient held in the DIAGDCCO RAM location. The filter output is read from the DIAGDC RAM location. The ac filter block consists of a full wave rectifier, followed by a single pole IIR low pass filter with a coefficient held in the DIAGACCO RAM location. The peak value is read from the DIAGPK RAM location. The peak value is cleared and the filters are flushed on the 0-1 transition of the SDIAG bit and when the input source changes. The user can write 0 to the DIAGPK RAM location to get peak information for a specific time interval. ! 16-bit audio A/D converter. The A/D converter portion of the audio codec is made available for processing test data received back through the transmit audio path. The audio path offers a 2.5 V peak voltage measurement capability and a coarse attenuation stage for scenarios where the incoming signal amplitude must be attenuated by as much as 3 dB to bring it into the allowable input range without clipping. Preliminary Rev. 0.91 87 Si3220/Si3225 ! Programmable timer. The Dual ProSLIC devices incorporate several digital oscillator circuits to program the on- and off-times of the ringing and pulse metering signals. The tone generation oscillator can be used to program a time period for averaging specific measured test parameters. ! Transmit audio path diagnostics filter. Transmit path audio diagnostics are facilitated by implementing a sixth-order IIR filter followed by peak detection and power estimation blocks. This filter can be programmed to eliminate or amplify specific signals for the purpose of measuring the peak amplitude and power content of individual components in the audio spectrum. Figure 11 on page 22 illustrates the location of the diagnostics filter block. The sixth order IIR filter operates at an 8 kHz sample rate and is implemented as three second-order filter stages in cascade. Each second-order filter offers five fully programmable coefficients (a1, a2, b0, b1, and b2) with 25-bit precision by providing several user-accessible registers. Each filter stage is implemented with the following format: –1 The power averaging filter time constant is absolute value programmable, and the average power result is read from the TESTAVO RAM location. Diagnostics Capabilities ! ! ! –2 ( b0 + b1z + b2z ) H ( z ) = ------------------------------------------------------–1 –2 ( 1 – a1z – a2z ) If any of the second-order filter stages are not required, they can be programmed to H(z)=1 by setting a1=0, a2=0, b0=1, b1=0, and b2=0. This flexible filter block can be programmed any of the following characteristics: " " " " Single notch. Used for measuring noise/distortion in the presence of a single tone. 90 dB attenuation is provided at the notched frequency. Implemented by placing two 0s on the unit circle at the notch frequency and two poles inside the unit circle at the notch frequency. Dual notch. Used for measuring noise/distortion in the presence of dual tones. Single notch/single peak. Used for measuring particular harmonic in the presence of a single tone. Dual notch/single peak. Used to measure particular intermodulation product in the presence of dual tones. Because each second-order filter stage is fully programmable, there are many other possible filter implementations. The IIR filter output is measured for power and peak post-processing. The peak measurement window duration is programmable by entering a value into the TESTWLN RAM address. The peak value (TESTPKO) is updated at the end of each window period. Power measurement is performed by using a single pole IIR filter to average the output of the sixth-order IIR filter. 88 ! ! Foreign voltages test. The Dual ProSLIC devices can detect the presence of foreign voltages according to GR-909 requirements of ac voltages > 10 V and dc voltages > 6 V from T-G or R-G. This test is performed when it has been determined that a hazardous voltage is not present on the line. Resistive faults (leakage current) test. Resistive fault conditions are measured from T-G, R-G, or T-R for dc resistance per GR-909 specifications. If the dc resistance is < 150 kΩ, it is considered a resistive fault. To perform this test, program the Dual ProSLIC chipset to generate a constant open-circuit voltage and measure the resulting current. The resistance is then calculated. Receiver off-hook test. Uses a similar procedure as described in the Resistive Faults test above, but is measured across T-R only. In addition, two measurements must be performed at different opencircuit voltages to verify the resistive linearity. If the calculated resistance has more than 15% nonlinearity between the two calculated points and the voltage/current origin, it is determined to be a resistive fault. Ringers (REN) test. Verifies the presence of REN at the end of the TIP/RING pair per TA-909 specifications. It can be implemented by generating a 20 Hz ringing signal between 7 Vrms and 17 Vrms and measuring the 20 Hz ac current using the 8-bit monitor ADC. The resistance (REN) can then be calculated using the software module. The acceptable REN range is > 0.175 REN (< 40 kΩ) or < 5 REN (> 1400 Ω). A returned value of < 1400 Ω is determined to be a resistive fault from T-R, and a returned value > 40 kΩ is determined to be a loop with no handset attached. ac line impedance measurement. Determines the ac loop impedence across T-R. It can be implemented by sending out multiple discrete tones, one at a time, and measuring the returned amplitude with the hybrid balance filter disabled. By calculating the voltage difference between the initial amplitude and the received amplitude and dividing the result by the audio current, the line impedance can then be calculated. Preliminary Rev. 0.91 Si3220/Si3225 ! ! ! ! ! ! Line capacitance measurement. Implemented like the ac line impedance measurement test above, but the frequency band of interest is between 1 kHz and 3.4 kHz. Knowing the synthesized 2-wire impedance of the Dual ProSLIC, the roll-off effect can be used to calculate the ac line capacitance. Ringing voltage verification. Verifies that the desired ringing signal is correctly applied to the TIP/ RING pair and can be measured in the 8-bit monitor ADC, which senses low frequency signals directly across T-R. Idle channel noise measurement. Given any transmission mode with no tone generated and the hybrid balance filter turned off, the voice band energy can be measured through the normal audio path and read through the appropriate register. Echo path gain measurement. Harmonic distortion measurement. Detects the power content of a particular harmonic. It can be implemented by programming two of the IIR diagnostics filter stages to provide a notch at the fundamental frequency and a peak at the harmonic of interest. Performing this procedure on all relevant harmonics individually and summing the results provide the total harmonic distortion. Intermodulation distortion measurement (twotone method). Measures the intermodulation distortion product in the presence of two tones. It can be implemented by programming the three IIR diagnostics filter stages to provide two notches at the two tone frequencies and a peak at the frequency of interest. Preliminary Rev. 0.91 89 Si3220/Si3225 8-Bit Control Register Summary Any register not listed here is reserved and must not be written. Shaded registers are read only. All registers are assigned a default value during initialization and following a system reset. Only registers 0, 2, 3, and 14 are available until a PLL lock is established or during a clock failure. Refer to AN58 “Dual ProSLIC Programmer Guide” for detailed register descriptions and recommended settings. (Ordered alphabetically by mnemonic except in cases of high, medium and low bytes which are ordered high to low.) Reg Addr3 Mnemonic Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W Def. Hex Init R/W 0x00 Audio 21 AUDGAIN Audio Gain Control ATXMUTE ARXMUTE Calibration 11 CALR1 Calibration Register 1 12 CALR2 Calibration Register 2 CAL CALOFFR CALOFFT CALOFFRN CALOFFTN CALDIFG CALCMG Init R/W 0x3F CALLKGR CALLKGT CALMADC CALDACO CALADCO CALCMBAL Init R/W 0x3F Diag R/W Diag R/W 0x00 Oper R/W 0x00 Init R 0x— Init R/W 0x05 Diagnostic Tools 13 DIAG Diagnostics Tool Enable IQ2HR IQ1HR TSTRING TXFILT SDIAG SDIAGIN[2:0] Digital Control and Loopback 22 DIGCON Digital Control and Loopback Enable CODECLB PCMLB HYBLB HYBDIS THPFDIS RHPFDIS DTXMUTE DRXMUTE FSK Data Byte 68 FSKDAT FSK Data Byte FSKBYTE[7:0] Chip ID 0 ID PARTNUM[2:0]4 Chip ID REV[3:0]4 Loop Current Limit 10 ILIM Loop Current Limit ILIM[4:0] Interrupts 14 IRQ0 Interrupt Status 0 CLKIRQ4,6 IRQ3B4,6 IRQ2B4,6 IRQ1B4,6 IRQ3A4,6 IRQ2A4,6 IRQ1A4,6 Oper R 0x00 15 IRQ1 Interrupt Status 1 PULSTAS PULSTIS RINGTAS RINGTIS OS2TAS OS2TIS OS1TAS OS1TIS Oper R/W 0x00 16 IRQ2 Interrupt Status 2 RXMDMS TXMDMS RAMIRS DTMFS VOCTRKS LONGS LOOPS RTRIPS Oper R/W 0x00 17 IRQ3 Interrupt Status 3 CMBALS PQ6S PQ5S PQ4S PQ3S PQ2S PQ1S Oper R/W 0x00 18 IRQEN1 Interrupt Enable 1 PULSTAE PULSTIE RINGTAE RINGTIE OS2TAE OS2TIE OS1TAE OS1TIE Init R/W 0x00 19 IRQEN2 Interrupt Enable 2 RXMDME TXMDME RAMIRE DTMFE VOCTRKE LONGE LOOPE RTRIPE Init R/W 0x00 20 IRQEN3 Interrupt Enable 3 CMBALE PQ6E PQ5E PQ4E PQ3E PQ2E PQ1E Init R/W 0x00 VOCTST4 LONGHI4 RTP4 LCR4 Oper R 0x40 Oper R/W 0x00 Linefeed Control 9 LCRRTP Loop Closure/Ring Trip/ Ground Key Detection CMH4 6 LINEFEED Linefeed LFS[2:0]4 Notes: 1. 2. 3. 4. 5. 6. 7. 90 SPEED4 LF[2:0] Any register not listed is reserved and must not be written. Default hex value is loaded to register following any RESET. Only registers ID, MSTREN, MSTRSTAT, and IRQ0 are valid while the PLL is not locked (MSTRSTAT[PLOCK]). Reserved bit values are indeterminate. Register address is in decimal. Read only. Protected bits. Per channel bit(s). Si3220 only. Preliminary Rev. 0.91 Si3220/Si3225 Reg Addr3 Mnemonic Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W Def. Hex Init R/W 0x00 Init R/W 0x00 SPI 2 MSTREN Master Initialization Enable PLLFLT FSFLT PCFLT 3 MSTRSTAT Master Initialization Status PLLFAULT FSFAULT PCFAULT SRCLR4 PLOCK4 FSDET4 FSVAL4 PCVAL4 Oscillators 61 O1TAHI Oscillator 1 Active Timer— High Byte OSC1TA[15:8] Init R/W 0x00 60 O1TALO Oscillator 1 Active Timer— Low Byte OSC1TA[7:0] Init R/W 0x00 63 O1TIHI Oscillator 1 Inactive Timer— High Byte OSC1TI[15:8] Init R/W 0x00 62 O1TILO Oscillator 1 Inactive Timer— Low Byte OSC1TI[7:0] Init R/W 0x00 65 O2TAHI Oscillator 2 Active Timer— High Byte OSC2TA[15:8] Init R/W 0x00 64 O2TALO Oscillator 2 Active Timer— Low Byte OSC2TA[7:0] Init R/W 0x00 67 O2TIHI Oscillator 2 Inactive Timer— High Byte OSC2TI[15:8] Init R/W 0x00 66 O2TILO Oscillator 2 Inactive Timer— Low Byte OSC2TI[7:0] Init R/W 0x00 59 OCON Oscillator Control ENSYNC24 OSC2TAEN Oper R/W 0x00 58 OMODE Oscillator Mode Select FSKSSEN ZEROEN2 ROUT1[1:0] Init R/W 0x00 6 6 PCMF[1:0]6 Init R/W 0x05 PCMRX[9:8] Init R/W 0x00 Init R/W 0x00 Init R/W 0x00 Init R/W 0x00 OSC2TIEN OSC2EN ROUT2[1:0] ENSYNC14 OSC1TAEN OSC1FSK ZEROEN1 OSC1TIEN OSC1EN PCM Control 53 PCMMODE PCM Mode Select 57 PCMRXHI PCM RX Clock Slot— High Byte 56 PCMRXL0 PCM RX Clock Slot— Low Byte 55 PCMTXHI PCM TX Clock Slot— High Byte 54 PCMTXLO PCM TX Clock Slot— Low Byte GCILINE PCLK2X PCMTRI6 ALAW[1:0]6 PCMEN PCMRX[7:0] PCMTX[9:8] PCMTX[7:0] Pulse Metering 28 PMCON Pulse Metering Control ENSYNC4,7 TAEN17 TIEN17 PULSE17 Oper R/W 0x00 Init R/W 0x00 30 PMTAHI Pulse Metering Oscillator Active Timer— High Byte PULSETA[15:8]7 29 PMTALO Pulse Metering Oscillator Active Timer— Low Byte PULSETA[7:0]7 Init R/W 0x00 32 PMTIHI Pulse Metering Oscillator Inactive Timer— High Byte PULSETI[15:8]7 Init R/W 0x00 Notes: 1. 2. 3. 4. 5. 6. 7. Any register not listed is reserved and must not be written. Default hex value is loaded to register following any RESET. Only registers ID, MSTREN, MSTRSTAT, and IRQ0 are valid while the PLL is not locked (MSTRSTAT[PLOCK]). Reserved bit values are indeterminate. Register address is in decimal. Read only. Protected bits. Per channel bit(s). Si3220 only. Preliminary Rev. 0.91 91 Si3220/Si3225 Reg Addr3 Mnemonic Description 31 PMTILO Pulse Metering Oscillator Inactive Timer— Low Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PULSETI[7:0]7 Type R/W Def. Hex Init R/W 0x00 Polarity Reversal 7 POLREV POLREV4 Polarity Reversal Settings VOCZERO PREN RAMP Init R/W RAM Access 103 RAMADDR RAM Address RAMADDR[7:0] Oper R/W 0x00 102 RAMDATHI RAM Data— High Byte RAMDAT[15:8] Oper R/W 0x00 101 RAMDATLO RAM Data— Low Byte RAMDAT[7:0] Oper R/W 0x00 4 RAMSTAT RAM Address Status RAMSTAT4 Init R 0x00 RESETB RESETA Init R/W 0x00 UNBPOLR TRAP Init R/W 0x00 Soft Reset 1 RESET Soft Reset Ringing ENSYNC4 RDACEN4 RINGUNB TAEN TIEN RINGEN4 23 RINGCON Ringing Configuration 25 RINGTAHI Ringing Oscillator Active Timer—High Byte RINGTA[15:8] Init R/W 0x00 24 RINGTALO Ringing Oscillator Active Timer—Low Byte RINGTA[7:0] Init R/W 0x00 27 RINGTIHI Ringing Oscillator Inactive Timer—High Byte RINGTI[15:8] Init R/W 0x00 26 RINGTILO Ringing Oscillator Inactive Timer—Low Byte RINGTI[7:0] Init R/W 0x00 Diag R/W 0x00 Init R/W 0xE0 Oper R/W 0x45 PASSCNT[3:0] Oper R/W 0x00 DTMFDIGIT[3:0]4 Oper R 0x00 Init R/W 0x00 Init R/W 0x00 Init R/W 0x00 Relay Configuration 5 RLYCON BSEL5 Relay Driver and Battery Switching Configuration RRAIL RDOE RRD/GPO TRD2 TRD1 SLIC Bias Control 8 SBIAS OBIAS[1:0]5 SLIC Bias Control ABIAS[1:0]5 Si3200 Thermometer 72 THERM Si3200 Thermometer 4 STAT Tone Detection 70 TONDET Modem Tone Detection 69 TONDTMF DTMF Detection 71 TONDEN Tone Detection Enable FAILCNT[3:0] VALID4 VALTONE4 DTMF RXMDM TXMDM Impedance Synthesis Coefficients 49 ZA1HI Impedance Synthesis Coeff A1— High Byte 48 ZA1MID Impedance Synthesis Coeff A1—Middle Byte Notes: 1. 2. 3. 4. 5. 6. 7. 92 COEFFA1[20:16]6 COEFFA1[15:8]6 Any register not listed is reserved and must not be written. Default hex value is loaded to register following any RESET. Only registers ID, MSTREN, MSTRSTAT, and IRQ0 are valid while the PLL is not locked (MSTRSTAT[PLOCK]). Reserved bit values are indeterminate. Register address is in decimal. Read only. Protected bits. Per channel bit(s). Si3220 only. Preliminary Rev. 0.91 Si3220/Si3225 Reg Addr3 Mnemonic Description 47 ZA1LO Impedance Synthesis Coeff A1—Low Byte 52 ZA2HI Impedance Synthesis Coeff A2—High Byte 51 ZA2MID Impedance Synthesis Coeff A2—Middle Byte 50 ZA2LO 37 Type R/W Def. Hex Init R/W 0x00 Init R/W 0x00 COEFFA2[15:8]6 Init R/W 0x00 Impedance Synthesis Coeff A2—Low Byte COEFFA2[7:0]6 Init R/W 0x00 ZB0HI Impedance Synthesis Coeff B0—High Byte COEFFB0[23:16]6 Init R/W 0x00 36 ZB0MID Impedance Synthesis Coeff B0—Middle Byte COEFFB0[15:8]6 Init R/W 0x00 35 ZB0LO Impedance Synthesis Coeff B0—Low Byte COEFFB0[7:0]6 Init R/W 0x00 40 ZB1HI Impedance Synthesis Coeff B1—High Byte COEFFB1[23:16]6 Init R/W 0x00 39 ZB1MID Impedance Synthesis Coeff B1—Middle Byte COEFFB1[15:8]6 Init R/W 0x00 38 ZB1LO Impedance Synthesis Coeff B1— Low Byte COEFFB1[7:0]6 Init R/W 0x00 43 ZB2HI Impedance Synthesis Coeff B2—High Byte COEFFB2[23:16]6 Init R/W 0x00 42 ZB2MID Impedance Synthesis Coeff B2—Middle Byte COEFFB2[15:8]6 Init R/W 0x00 41 ZB2LO Impedance Synthesis Coeff B2— Low Byte COEFFB2[7:0]6 Init R/W 0x00 46 ZB3HI Impedance Synthesis Coeff B3—High Byte COEFFB3[23:16]6 Init R/W 0x00 45 ZB3MID Impedance Synthesis Coeff B3—Middle Byte COEFFB3[15:8]6 Init R/W 0x00 44 ZB3LO Impedance Synthesis Coeff B3—Low Byte COEFFB3[7:0]6 Init R/W 0x00 33 ZRS Impedance Synthesis Analog Real Coeff Init R/W 0x00 34 ZZ Impedance Synthesis Analog Complex Coeff Init R/W 0x00 Notes: 1. 2. 3. 4. 5. 6. 7. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 COEFFA1[7:0] COEFFA2[20:16]6 RS[3:0]6 ZSDIS6 ZSOHT6 ZP[1:0]6 ZZ[1:0]6 Any register not listed is reserved and must not be written. Default hex value is loaded to register following any RESET. Only registers ID, MSTREN, MSTRSTAT, and IRQ0 are valid while the PLL is not locked (MSTRSTAT[PLOCK]). Reserved bit values are indeterminate. Register address is in decimal. Read only. Protected bits. Per channel bit(s). Si3220 only. Preliminary Rev. 0.91 93 Si3220/Si3225 16-Bit RAM Address Summary All internal 16-bit RAM addresses can be assigned unique values for each SLIC channel and are accessed in a similar manner as the 8-bit control registers except the data is twice as long. In addition, one more READ cycle is required during READ operations to accommodate the one-deep pipeline architecture. See "SPI Control Interface" on page 62 for more details. All internal RAM addresses are assigned a default value of 0 during initialization and following a system reset. Unless otherwise noted, all RAM addresses use a 2’s complement, MSB first date format. Refer to AN58 “Dual ProSLIC Programmer Guide” for detailed RAM location descriptions and recommended settings. Note: Any RAM address not listed is reserved and must not be written. (ordered alphabetically by mnemonic) RAM Addr Mnemonic Description Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type Example Hex Example Dec Unit Init 0E54 18 V Init 0A08 10 Hz Init 0D88 17 V Init 0A08 10 Hz Battery Selection and VOC Tracking 31 BATHTH High Battery Switch Threshold 34 BATLPF Battery Tracking Filter Coeff 32 BATLTH Low Battery Switch Threshold 33 BSWLPF RING Voltage Filter Coeff BATHTH[14:7]2 BATLPF[15:3] BATLTH[14:7]2 BSWLPF[15:3] Speedup 36 CMHITH Speedup Threshold— High Byte CMHITH[15:0] Init 0001 1 V 35 CMLOTH Speedup Threshold— Low Byte CMLOTH[15:0] Init 07F5 10 V SLIC Diagnostics Filter 53 DIAGAC SLIC Diags AC Detector Threshold 54 DIAGACCO SLIC Diags AC Filter Coeff 51 DIAGDC SLIC Diags DC Output 52 DIAGDCCO SLIC Diags DC Filter Coeff 55 DIAGPK SLIC Diags Peak Detector DIAGAC[15:0] DIAGACCO[15:3] DIAGDC[15:0] DIAGDCCO[15:3] DIAGPK[15:0] Diag Diag V 7FF8 127.3 Diag Diag Hz V 0A08 Diag 10 Hz V DTMF Detection 118 DTCOL2HTH DTMF Column Second Harmonic Threshold DTCOL2HTH[15:3] Init 1013 116 DTCOLRTH DTMF Column Ratio Threshold DTCOLRTH[15:3] Init 0CC5 112 DTCOLTH DTMF Column Peak Threshold DTCOLTH[15:3] Init 1999 113 DTFTWTH DTMF Forward Twist Threshold DTFTWTH[15:3] Init 1013 120 DTHOTTH DTMF Hot Limit Threshold DTHOTTH[15:0] Init 0A1C 119 DTMINPTH DTMF Minimum Power Threshold DTMINPTH[15:0] Init 00E5 Notes: 1. 2. 3. 4. 5. 6. 7. Any register not listed is reserved and must not be written. Only positive input values are valid for these RAM addresses. Si3225 only. Si3220 only. For the Si3220, the RINGFRHI RAM address location is used to store the high byte of the internal ringing signal frequency. For the Si3225, this address location stores the desired time delay between when the relay opens and when the LFS register transitions out of the ringing state. For the Si3220, the RINGAMP RAM address location is used to store the amplitude of the internal ringing signal. For the Si3225, this address location stores the desired time relay between the last zero current crossing and the next opportunity to open the ringing relay. RAM address in decimal. 94 Preliminary Rev. 0.91 Si3220/Si3225 RAM Addr Mnemonic Description 108 DTROW0TH DTMF Row 0 Peak Threshold 109 DTROW1TH 117 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type Example Hex DTROW0TH[15:3] Init 2AE1 DTMF Row 1 Peak Threshold DTROW1TH[15:3] Init 28FB DTROW2HTH DTMF Row Second Harmonic Threshold DTROW2HTH[15:3] Init 308C 110 DTROW2TH DTMF Row 2 Peak Threshold DTROW2TH[15:3] Init 25C2 111 DTROW3TH DTMF Row 3 Peak Threshold DTROW3TH[15:3] Init 249B 115 DTROWRTH DTMF Row Ratio Threshold DTROWRTH[15:3] Init 0CC5 114 DTRTWTH DTMF Reverse Twist Threshold DTRTWTH[15:3] Init 1013 Example Dec Unit Echo Cancellation 89 ECCO0 Echo Cancellation Coeff 0 ECCO0[15:3] Init 01B0 1728 82 ECCO1 Echo Cancellation Coeff 1 ECCO1[15:3] Init FF20 –896 83 ECCO2 Echo Cancellation Coeff 2 ECCO2[15:3] Init 1548 21792 84 ECCO3 Echo Cancellation Coeff 3 ECCO3[15:3] Init 1E38 30944 85 ECCO4 Echo Cancellation Coeff 4 ECCO4[15:3] Init 1238 18656 86 ECCO5 Echo Cancellation Coeff 5 ECCO5[15:3] Init 01B8 1760 87 ECCO6 Echo Cancellation Coeff 6 ECCO6[15:3] Init FD08 –3040 88 ECCO7 Echo Cancellation Coeff 7 ECCO7[15:3] Init FFA0 –384 92 ECIIRA1 Echo Cancel IIR Filter Coeff A1 ECIIRA1[15:3] Init 0370 3520 93 ECIIRA2 Echo Cancel IIR Filt Coeff A2 ECIIRA2[15:3] Init CB58 –53920 90 ECIIRB0 Echo Cancel IIR Filt Coeff B0 ECIIRB0[15:3] Init 0068 416 91 ECIIRB1 Echo Cancel IIR Filt Coeff B1 ECIIRB1[15:3] Init FEA0 –1408 FSK Generation 102 FSKAMP0 FSK Amplitude for Space FSKAMP0[15:3] Init 0100 .22 Vrms 103 FSKAMP1 FSK Amplitude for Mark FSKAMP1[15:3] Init 01E0 .22 Vrms 100 FSKFREQ0 FSK Frequency for Space FSKFREQ0[15:3] Init 3CE0 1200 Hz 101 FSKFREQ1 FSK Frequency for Mark FSKFREQ1[15:3] Init 35B0 2200 Hz 104 FSK01HI FSK 0-1 Transition Freq— High FSK01HI[15:3] Init 3BE0 105 FSK01LO FSK 0-1 Transition Frequency—Low FSK01LO[15:3] Init 1330 106 FSK10HI FSK 1-0 Transition Frequency—High FSK10HI[15:3] Init 1118 107 FSK10LO FSK 1-0 Transition Frequency—Low FSK10LO[15:3] Init 1D88 Notes: 1. 2. 3. 4. 5. 6. 7. Any register not listed is reserved and must not be written. Only positive input values are valid for these RAM addresses. Si3225 only. Si3220 only. For the Si3220, the RINGFRHI RAM address location is used to store the high byte of the internal ringing signal frequency. For the Si3225, this address location stores the desired time delay between when the relay opens and when the LFS register transitions out of the ringing state. For the Si3220, the RINGAMP RAM address location is used to store the amplitude of the internal ringing signal. For the Si3225, this address location stores the desired time relay between the last zero current crossing and the next opportunity to open the ringing relay. RAM address in decimal. Preliminary Rev. 0.91 95 Si3220/Si3225 RAM Addr Mnemonic Description Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type Example Hex Example Dec Unit Loop Currents 9 ILONG Longitudinal Current Sense Value ILONG[15:0]2 DIag 8 ILOOP Loop Current Sense Value ILOOP[15:0]2 Diag mA 18 IRING Q5 Current Measurement IRING[15:0] Diag mA 16 IRINGN Q3 Current Measurement IRINGN[15:0] Diag mA 15 IRINGP Q2 Current Measurement IRINGP[15:0] Diag mA Diag mA mA 21 IRNGNG External Ringing Generator Current Measurement IRNGNG[15:0]3 19 ITIP Q6 Current Measurement ITIP[15:0] Diag mA 17 ITIPN Q4 Current Measurement ITIPN[15:0] Diag mA 14 ITIPP Q1 Current Measurement ITIPP[15:0] Diag mA 24 LCRDBI Loop Closure Detection Debounce Interval 25 LCRLPF Loop Closure Filter Coefficient 26 LCRMASK Loop Closure Mask Interval Coeff 166 LCRMSKPR 22 23 Loop Closure Detection LCRDBI[15:0]2 Init 000C 15 ms Init 0A10 10 Hz LCRMASK[15:0]2 Init 0040 80 ms LCR Mask During Polarity Reversal LCRMSKPR[15:0] Init 0040 80 ms LCROFFHK Off-Hook Detect Threshold LCROFFHK[15:0]2 Init 0C0C 10 mA LCRONHK On-Hook Detect Threshold LCRONHK[15:0]2 Init 0DEO 11 mA LCRLPF[15:3] Longitudinal Current Detection 29 LONGDBI Ground Key Detection Debounce Interval LONGDBI[15:0]2 Init 27 LONGHITH Ground Key Detection Threshold LONGHITH[15:0]2 Init 08D4 7 mA 28 LONGLOTH Ground Key Removal Detection Threshold LONGLOTH[15:0]2 Init 0A17 8 mA 30 LONGLPF Ground Key Filter Coefficient Init 0A08 10 Hz Init 004F 0.0775 Vrms Init 3D98 350 Hz LONGLPF[15:3] ms Oscillator Coefficients 95 OSC1AMP Oscillator 1 Amplitude 94 OSC1FREQ Oscillator 1 Frequency OSC1AMP[15:0] 96 OSC1PHAS Oscillator 1 Initial Phase OSC1PHAS[15:0] Init 0000 98 OSC2AMP Oscillator 2 Amplitude OSC2AMP[15:0] Init 0063 0.0775 Vrms 97 OSC2FREQ Oscillator 2 Frequency Init 3C38 440 Hz 99 OSC2PHAS Oscillator 2 Initial Phase Init 0000 OSC1FREQ[15:3] OSC2FREQ[15:3] OSC2PHAS[15:0] Power Calculations Notes: 1. 2. 3. 4. 5. 6. 7. Any register not listed is reserved and must not be written. Only positive input values are valid for these RAM addresses. Si3225 only. Si3220 only. For the Si3220, the RINGFRHI RAM address location is used to store the high byte of the internal ringing signal frequency. For the Si3225, this address location stores the desired time delay between when the relay opens and when the LFS register transitions out of the ringing state. For the Si3220, the RINGAMP RAM address location is used to store the amplitude of the internal ringing signal. For the Si3225, this address location stores the desired time relay between the last zero current crossing and the next opportunity to open the ringing relay. RAM address in decimal. 96 Preliminary Rev. 0.91 Si3220/Si3225 RAM Addr Mnemonic Description 40 PLPFQ12 Q1/Q2 Thermal Low Pass Filter Coeff 41 PLFPQ34 42 PLFPQ56 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type Example Hex Example Dec Unit PLFPQ12[15:3] Init 0008 .3 s Q3/Q4 Thermal Low Pass Filter Coeff PLFPQ34[15:3] Init 0008 .3 s Q5/Q6 Thermal Low Pass Filter Coeff PLFPQ56[15:3] Init 0008 .3 s Pulse Metering 68 PMAMPL Pulse Metering Amplitude PMAMPL[15:0]4 Init 4000 65536 V 70 PMAMPTH Pulse Metering AGC Amplitude Threshold PMAMPTH[15:0]4 Init 00C8 798 V 67 PMFREQ Pulse Metering Frequency Init 0000 0 Hz 69 PMRAMP Pulse Metering Ramp Rate Init 008A 550 s PMFREQ[15:3]4 PMRAMP[15:0]4 Power Calculations 44 PQ1DH Q1 Calculated Power PQ1DH[15:0] Diag W 45 PQ2DH Q2 Calculated Power PQ2DH[15:0] Diag W 46 PQ3DH Q3 Calculated Power PQ3DH[15:0] Diag W 47 PQ4DH Q4 Calculated Power PQ4DH[15:0] Diag W 48 PQ5DH Q5 Calculated Power PQ5DH[15:0] Diag W 49 PQ6DH Q6 Calculated Power PQ6DH[15:0] Diag W 50 PSUM Total Calculated Power PSUM[15:0] Diag 37 PTH12 Q1/Q2 Power Threshold PTH12[15:0]2 Init 0007 .22 W 38 PTH34 Q3/Q4 Power Threshold PTH34[15:0]2 Init 003C 17 W 2 Init 002A 1.28 W 39 PTH56 Q5/Q6 Power Threshold 43 RB56 Q5/Q6 Base Resistor PTH56[15:0] RB56[15:0] W Ω Init Ringing 59 RINGAMP Ringing Amplitude/Zero Crossing Delay 57 RINGFRHI Ringing Frequency—High Byte/Linefeed Status Delay 58 RINGFRLO Ringing Frequency— Low Byte 56 RINGOF Ringing Waveform DC Offset 60 RINGPHAS Ringing Oscillator Initial Phase RINGAMP[15:0]6/ZERDELAY[15:0] Init 00D5 47 Vrms RINGFRHI[14:3]5/LFSDELAY[14:3] Init 3F78 20 Hz RINGFRLO[14:3]4 Init 6CE8 20 Hz Init 0000 0 V Init 0000 10 ms RINGOF[15:0]4 RINGPHAS[15:3]4 Ring Trip Detection 66 RTACDB AC Ring Trip Debounce Interval RTACDB[15:0] Init 0008 64 RTACTH AC Ring Trip Detect Threshold RTACTH[15:0] Init 1086 61 RTCOUNT Ring Trip Timeout Counter RTCOUNT[15:0] Init 0400 Notes: 1. 2. 3. 4. 5. 6. 7. mA 128 ms Any register not listed is reserved and must not be written. Only positive input values are valid for these RAM addresses. Si3225 only. Si3220 only. For the Si3220, the RINGFRHI RAM address location is used to store the high byte of the internal ringing signal frequency. For the Si3225, this address location stores the desired time delay between when the relay opens and when the LFS register transitions out of the ringing state. For the Si3220, the RINGAMP RAM address location is used to store the amplitude of the internal ringing signal. For the Si3225, this address location stores the desired time relay between the last zero current crossing and the next opportunity to open the ringing relay. RAM address in decimal. Preliminary Rev. 0.91 97 Si3220/Si3225 RAM Addr Mnemonic Description 65 RTDCDB DC Ring Trip Debounce Interval 62 RTDCTH 63 RTPER Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type Example Hex Example Dec Unit RTDCDB[15:0] Init 0008 10 ms DC Ring Trip Detect Threshold RTDCTH[15:0] Init 7FFF Ring Trip Low Pass Filter Coeff Period RTPER[15:0] Init 0028 20 mA Hz Receive Path Gain and Filters 81 RXIIRPOL RX IIR Filter Pole Coeff RXIIRPOL[15:3] Init 3CCC 62256 80 RXEQCO0 RX Equalizer Coeff 0 RXEQCO0[15:3] Init 4000 65536 79 RXEQCO1 RX Equalizer Coeff 1 RXEQCO1[15:3] Init 0000 0 78 RXEQCO2 RX Equalizer Coeff 2 RXEQCO2[15:3] Init 0000 0 77 RXEQCO3 RX Equalizer Coeff 3 RXEQCO3[15:3] Init 0000 0 4000 1 0000 60 71 RXGAIN RX Gain Setting RXGAIN[15:3] Init 123 RXMODPWR RX Path Modem Tone Power RXMODPWR[15:3] Init 121 RXPWR RX Path Input Signal Power RXPWR[15:0] Init DC Speedup 168 SPEEDUP DC Speedup Timer SPEEDUP[15:0] Init 132 TESTA1H1 TX Diag Filter Coeff A1H1 TESTA1H1[15:3] Diag 142 TESTA1H2 TX Diag Filter Coeff A1H2 TESTA1H2[15:3] Diag 152 TESTA1H3 TX Diag Filter Coeff A1H3 TESTA1H3[15:3] Diag 131 TESTA1L1 TX Diag Filter Coeff A1L1 TESTA1L1[15:3] Diag 141 TESTA1L2 TX Diag Filter Coeff A1L2 TESTA1L2[15:3] Diag 151 TESTA1L3 TX Diag Filter Coeff A1L3 TESTA1L3[15:3] Diag 134 TESTA2H1 TX Diag Filter Coeff A2H1 TESTA2H1[15:3] Diag 144 TESTA2H2 TX Diag Filter Coeff A2H2 TESTA2H2[15:3] Diag 154 TESTA2H3 TX Diag Filter Coeff A2H3 TESTA2H3[15:3] Diag 133 TESTA2L1 TX Diag Filter Coeff A2L1 TESTA2L1[15:3] Diag 143 TESTA2L2 TX Diag Filter Coeff A2L2 TESTA2L2[15:3] Diag 153 TESTA2L3 TX Diag Filter Coeff A2L3 TESTA2L3[15:3] 156 TESTAVO TX Diag Filter Avg Output 158 TESTAVBW TX Diag Filter Avg Bandwidth TESTAVBW[15:3] Diag 160 TESTAVFL TX Diag Filter Average Flag TESTAVFL[15:3] Diag ms Test Diagnostic Filters Notes: 1. 2. 3. 4. 5. 6. 7. TESTAVO[15:0] Diag Diag V Any register not listed is reserved and must not be written. Only positive input values are valid for these RAM addresses. Si3225 only. Si3220 only. For the Si3220, the RINGFRHI RAM address location is used to store the high byte of the internal ringing signal frequency. For the Si3225, this address location stores the desired time delay between when the relay opens and when the LFS register transitions out of the ringing state. For the Si3220, the RINGAMP RAM address location is used to store the amplitude of the internal ringing signal. For the Si3225, this address location stores the desired time relay between the last zero current crossing and the next opportunity to open the ringing relay. RAM address in decimal. 98 Preliminary Rev. 0.91 Si3220/Si3225 RAM Addr Mnemonic Description Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 162 TESTAVTH TX Diag Filter Avg Threshold TESTAVTH[15:3] Diag 126 TESTB0H1 TX Diag Filter Coeff B0H1 TESTB0H1[15:3] Diag 136 TESTB0H2 TX Diag Filter Coeff B0H2 TESTB1H2[15:3] Diag 146 TESTB0H3 TX Diag Filter Coeff B0H3 TESTB0H3[15:3] Diag 125 TESTB0L1 TX Diag Filter Coeff B0L1 TESTB0L1[15:3] Diag 135 TESTB0L2 TX Diag Filter Coeff B0L2 TESTB0L2[15:3] Diag 145 TESTB0L3 TX Diag Filter Coeff B0L3 TESTB0L3[15:3] Diag 128 TESTB1H1 TX Diag Filter Coeff B1H1 TESTB1H1[15:3] Diag 138 TESTB1H2 TX Diag Filter Coeff B1H2 TESTB1H2[15:3] Diag 148 TESTB1H3 TX Diag Filter Coeff B1H3 TESTB1H3[15:3] Diag 127 TESTB1L1 TX Diag Filter Coeff B1L1 TESTB1L1[15:3] Diag 137 TESTB1L2 TX Diag Filter Coeff B1L2 TESTB1L2[15:3] Diag 147 TESTB1L3 TX Diag Filter Coeff B1L3 TESTB1L3[15:3] Diag 130 TESTB2H1 TX Diag Filter Coeff B2H1 TESTB2H1[15:3] Diag 140 TESTB2H2 TX Diag Filter Coeff B2H2 TESTB2H2[15:3] Diag 150 TESTB2H3 TX Diag Filter Coeff B2H3 TESTB2H3[15:3] Diag 129 TESTB2L1 TX Diag Filter Coeff B2L1 TESTB2L1[15:3] Diag 139 TESTB2L2 TX Diag Filter Coeff B2L2 TESTB2L2[15:3] Diag 149 TESTB2L3 TX Diag Filter Coeff B2L3 TESTB2L3[15:3] Diag 159 TESTPKFL TX Diag Filter Peak Flag TESTPKFL[15:3] Diag 155 TESTPKO TX Diag Filter Peak Output TESTPKO[15:3] Diag 161 TESTPKTH TX Diag Filter Peak Threshold TESTPKTH[15:3] Diag 157 TESTWLN TX Diag Filter TESTWLN[15:3] Diag Type Example Hex Example Dec Unit V Transmit Path Gain and Filters 76 TXEQCO0 TX Equalizer Coefficient 0 TXEQCO0[15:3] Init 4A6A 76201 75 TXEQCO1 TX Equalizer Coefficient 1 TXEQCO1[15:3] Init F84C –7888 74 TXEQCO2 TX Equalizer Coefficient 2 TXEQCO2[15:3] Init 012C 1199 73 TXEQCO3 TX Equalizer Coefficient 3 TXEQCO3[15:3] Init 004C 302 4000 1 72 TXGAIN TX Gain Setting TXGAIN[15:3] Init 163 TXHPF1 TX HPF Coefficient 1 TXHPF1[15:3] Diag 164 TXHPF2 TX HPF Coefficient 2 TXHPF2[15:3] Diag 165 TXHPF3 TX HPF Coefficient 3 TXHPF3[15:3] Diag Notes: 1. 2. 3. 4. 5. 6. 7. Any register not listed is reserved and must not be written. Only positive input values are valid for these RAM addresses. Si3225 only. Si3220 only. For the Si3220, the RINGFRHI RAM address location is used to store the high byte of the internal ringing signal frequency. For the Si3225, this address location stores the desired time delay between when the relay opens and when the LFS register transitions out of the ringing state. For the Si3220, the RINGAMP RAM address location is used to store the amplitude of the internal ringing signal. For the Si3225, this address location stores the desired time relay between the last zero current crossing and the next opportunity to open the ringing relay. RAM address in decimal. Preliminary Rev. 0.91 99 Si3220/Si3225 RAM Addr Mnemonic Description 124 TXMODPWR TX Path Modem Tone Power 122 TXPWR TX Path Input Signal Power Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 TXMODPWR[15:3] TXPWR[15:0] Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type Example Hex Example Dec Unit Init Init Loop Voltages 13 VBAT Scaled Battery Voltage Measurement 4 VCM Common Mode Voltage 7 VLOOP Loop Voltage 0 VOC Open Circuit Voltage VOC[14:0]2 Init 2668 48 V VOC Delta for Off-Hook VOCDELTA[14:0]2 1 VOCDELTA VBAT[15:0] VCM[14:0]2 VLOOP[15:0]2 Diag Init V 0268 3 Diag V V Init 059A 7 V Init 0198 2 V F9A2 –8 V 3 VOCHTH VOC Delta Upper Threshold VOCHTH[15:0]2 2 VOCLTH VOC Delta Lower Threshold VOCLTH[15:0] Init 10 VOCTRACK Battery Tracking Open Circuit Voltage VOCTRACK[15:0]2 Diag 5 VOV Overhead Voltage VOV[14:0]2 Init 0334 4 V VOVRING[14:0]2 Init 0000 0 V 6 VOVRING Ringing Overhead Voltage 12 VRING Scaled RING Voltage Measurement 20 VRNGNG External Ringing Generator Voltage Measurement 11 VTIP Scaled TIP Voltage Measurement Notes: 1. 2. 3. 4. 5. 6. 7. VRING[15:0] VRNGNG[14:7]3 VTIP[15:0] V Diag V Diag V Diag V Any register not listed is reserved and must not be written. Only positive input values are valid for these RAM addresses. Si3225 only. Si3220 only. For the Si3220, the RINGFRHI RAM address location is used to store the high byte of the internal ringing signal frequency. For the Si3225, this address location stores the desired time delay between when the relay opens and when the LFS register transitions out of the ringing state. For the Si3220, the RINGAMP RAM address location is used to store the amplitude of the internal ringing signal. For the Si3225, this address location stores the desired time relay between the last zero current crossing and the next opportunity to open the ringing relay. RAM address in decimal. 100 Preliminary Rev. 0.91 Si3220/Si3225 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 BATSELa TRD2a TRD1a RTRPa BLKRNG THERMa IRINGPa GND1 VDD1 ITIPPa IRINGNa ITIPNa SRINGDCa SRINGACa STIPACa STIPDCa BATSELa TRD2a TRD1a NC NC THERMa IRINGPa GND1 VDD1 ITIPPa IRINGNa ITIPNa SRINGDCa SRINGACa STIPACa STIPDCa Pin Descriptions: Si3220/25 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 SVBATa 1 48 GPOa SVBATa 1 RPOa 2 47 CS 48 RRDa RPOa 2 47 RPIa 3 46 CS SDITHRU RPIa 3 46 RNIa 4 SDITHRU 45 SDI RNIa 4 45 RNOa SDI 5 44 SDO RNOa 5 44 SDO CAPPa 6 43 SCLK CAPPa 6 43 SCLK CAPMa 7 42 VDD4 CAPMa 7 42 VDD4 QGND 8 41 GND4 QGND 8 41 GND4 IREF 9 40 INT IREF 9 40 INT CAPMb 10 39 PCLK CAPMb 10 39 PCLK CAPPb 11 38 GND3 CAPPb 11 38 GND3 RNOb 12 37 VDD3 RNOb 12 37 VDD3 RNIb 13 36 DTX RNIb 13 36 DTX RPIb 14 35 DRX RPIb 14 35 DRX RPOb 15 34 FSYNC RPOb 15 34 FSYNC SVBATb 16 33 RESET SVBATb 16 33 RESET Pin Number(s) Symbol Input/ Output BATSELb RRDb TRD2b TRD1b RTRPb THERMb IRINGPb GND2 VDD2 ITIPPb IRINGNb ITIPNb SRINGDCb SRINGACb STIPDCb 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 BATSELb GPOb TRD2b TRD1b NC THERMb IRINGPb GND2 VDD2 ITIPPb IRINGNb ITIPNb SRINGDCb SRINGACb STIPACb STIPDCb 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Si3225 64-Lead TQFP (epad) STIPACb Si3220 64-Lead TQFP (epad) Description Si3220 Si3225 1, 16 1, 16 SVBATa, SVBATb I Battery Sensing Input. Analog current input used to sense battery voltage. 2,15 2,15 RPOa, RPOb O Transconductance Amplifier External Resistor Connection. 3, 14 3, 14 RPIa, RPIb I Transconductance Amplifier External Resistor Connection. 4, 13 4, 13 RNIa, RNIb I Transconductance Amplifier Resistor Connection. 5, 12 5, 12 RNOa, RNOb O Transconductance Amplifier Resistor Connection. 6, 11 6, 11 CAPPa, CAPPb Differential Capacitor. Capacitor used in low pass filter to stabilize SLIC feedback loops. 7, 10 7, 10 CAPMa, CAPMb Common Mode Capacitor. Capacitor used in low pass filter to stabilize SLIC feedback loops. 8 8 QGND Component Reference Ground. Return path for differential and common mode capacitors. Do not connect to system ground. Preliminary Rev. 0.91 101 Si3220/Si3225 Pin Number(s) Symbol Input/ Output Description Si3220 Si3225 9 9 IREF I IREF Current Reference. Connects to an external resistor to provide a high accuracy reference current. Return path for IREF resistor should be routed to QGND pin. 17, 64 17, 64 STIPDCb, STIPDCa I TIP Sense. Analog current input senses dc voltage on TIP side of subscriber loop. 18, 63 18, 63 STIPACb, STIPACa I TIP Transmit Input. Analog input senses ac voltage on TIP side of subscriber loop. 19, 62 19, 62 SRINGACb, SRINGACa I RING Transmit Input. Analog input senses ac voltage on RING side of subscriber loop. 20, 61 20, 61 SRINGDCb, SRINGDCa I RING Sense. Analog current input senses dc voltage on RING side of subscriber loop. 21, 60 21, 60 ITIPNb, ITIPNa O Negative TIP Current Control. Analog current output provides dc current return path to VBAT from TIP side of the loop. 22, 59 22, 59 IRINGNb, IRINGNa O Negative RING Current Control. Analog current output provides dc current return path to VBAT from RING side of loop. 23, 58 23, 58 ITIPPb, ITIPPa O Positive TIP Current Control. Analog current output drives dc current onto TIP side of subscriber loop in normal polarity. Also modulates ac current onto TIP side of loop. 24, 37, 42, 57 24, 37, 42, 57 VDD2,VDD3, VDD4,VDD1 Supply Voltage. Power supply for internal analog and digital circuitry. Connect all VDD pins to the same supply and decouple to adjacent GND pin as close to the pins as possible. 25, 38, 41, 56 25, 38, 41, 56 GND2,GND3, GND4,GND1 Ground. Ground connection for internal analog and digital circuitry. Connect all pins to low-impedance ground plane. 26, 55 26, 55 IRINGPb, IRINGPa O Positive RING Current Control. Analog current output drives dc current onto RING side of subscriber loop in reverse polarity. Also modulates ac current onto RING side of loop. 27,54 27,54 THERMb, THERMa I Temperature Sensor. Senses Internal temperature of Si3200. 29, 51 29, 51 TRD1b, TRD1a O Test Relay Driver Output. Drives test relays for connecting loop test equipment. 28, 52, 53 102 NC No Internal Connection. Leave unconnected or connect to ground plane. Preliminary Rev. 0.91 Si3220/Si3225 Pin Number(s) Si3220 30, 50 Symbol Input/ Output 28, 52 RTRPb, RTRPa I External Ring Trip Sensing Input. Used to sense ring-trip condition when using centralized ring generator. Connect to low side of ring sense resistor. 30, 50 TRD2b, TRD2a O Test Relay Driver Output. Drives test relays for connecting loop test equipment. 31, 48 RRDb, RRDa O Ring Relay Driver Output. Connects an external centralized ring generator to the subscriber loop. GPOb, GPOa O General Purpose Output Driver. Used as a relay driver or as a second battery select pin when using a third battery supply. Si3225 31, 48 Description 32, 49 32, 49 BATSELb, BATSELa O Battery Voltage Select Pin. Switches between high and low external battery supplies. 35 35 DRX I Receive PCM Data. Input data from PCM/GCI bus. 36 36 DTX O Transmit PCM Data. Output data to PCM/GCI bus. 39 39 PCLK I PCM Bus Clock. Clock input for PCM/GCI bus timing. 33 33 RESET I Reset. Active low. Hardware reset used to place all control registers in known state. An internal pulldown resistor asserts this pin low when not driven externally. 34 34 FSYNC I Frame Sync. 8 kHz frame synchronization signal for PCM/GCI bus. May be short or long pulse format. 40 40 INT O Interrupt. Maskable interrupt output. Open drain output for wire-ORed operation. 43 43 SCLK I Serial Port Bit Clock Input. Controls serial data on SDO and latches data on SDI. 44 44 SDO O Serial Port Data Out. Serial port control data output. 45 45 SDI I Serial Port Data In. Serial port control data input. 46 46 SDITHRU O Serial Data Daisy Chain. Enables multiple devices to use a single CS for serial port control. Connect SDITHRU pin from master device to SDI pin of slave device. An internal pullup resistor holds this pin high during idle periods. Preliminary Rev. 0.91 103 Si3220/Si3225 Pin Number(s) Symbol Input/ Output Description Si3220 Si3225 47 47 CS I Chip Select. Active low. When inactive, SCLK and SDI are ignored and SDO is high impedance. When active, serial port is operational. 53 BLKRNG I Ring Generator Sensing Input. Senses ring-trip condition when using centralized ring generator. Connect to high side of ring sense resistor. Shared by channel a and b. epad GND epad 104 Exposed Die Paddle Ground. Connect to a low-impedance ground plane via top side PCB pad directly under the part. See Package Outlines: 64-Pin TQFP for PCB pad dimensions. Preliminary Rev. 0.91 Si3220/Si3225 Pin Descriptions: Si3200 Si3200 16-Lead SOIC (epad) TIP 1 16 ITIPP NC 2 15 RING 3 14 ITIPN THERM VBAT 4 13 IRINGP VBATH 5 12 IRINGN VBATL 6 11 GND 7 10 NC NC VDD 8 9 BATSEL Pin #(s) Symbol Input/ Output Description 1 TIP I/O TIP Output. Connect to the TIP lead of the subscriber loop. 2, 10, 11 NC — No Internal Connection. Do not connect to any electrical signal. 3 RING I/O RING Output. Connect to the RING lead of the subscriber loop. 4 VBAT — Operating Battery Voltage. Si3200 internal system battery supply. Connect SVBATa/b pin from Si3220/ 25 and decouple with a 0.1 µF/100 V filter capacitor. 5 VBATH — High Battery Voltage. Connect to the system ringing battery supply. Decouple with a 0.1 µF/100 V filter capacitor. 6 VBATL — Low Battery Voltage. Connect to lowest system battery supply for off-hook operation driving short loops. An internal diode prevents leakage current when operating from VBATH. 7 GND — Ground. Connect to a low-impedance ground plane. 8 VDD — Supply Voltage. Main power supply for all internal circuitry. Connect to a 3.3 V or 5 V supply. Decouple locally with a 0.1 µF/10 V capacitor. 9 BATSEL I Battery Voltage Select. Connect to the BATSEL pin of the Si3220 or Si3225 through an external resistor to enable automatic battery switching. No connection is required when used with the Si3225 in a single battery system configuration. Preliminary Rev. 0.91 105 Si3220/Si3225 Pin #(s) Symbol Input/ Output 12 IRINGN I Negative RING Current Control. Connect to the IRINGN lead of the Si3220 or Si3225. 13 IRINGP I Positive RING Current Drive. Connect to the IRINGP lead of the Si3220 or Si3225. 14 THERM O Thermal Sensor. Connection to internal temperature sensing circuit. Connect to THERM pin of Si3220 or Si3225. 15 ITIPN I Negative TIP Current Control. Connect to the ITIPN lead of the Si3220 or Si3225. 16 ITIPP I Positive TIP Current Control. Connect to the ITIPP lead of the Si3220 or Si3225. epad GND 106 Description Exposed Die Paddle Ground. For adequate thermal management, the exposed die paddle should be soldered to a PCB pad that is connected to low-impedance inner and/or backside ground planes using multiple vias. See “Package Outline: 16-Pin SOIC” for PCB pad dimensions. Preliminary Rev. 0.91 Si3220/Si3225 Dual ProSLIC Selection Guide Part Number Description On-Chip Ringing External Ringing Support Pulse Metering Temp Range Package Si3200-KS Linefeed interface 0 to 70 °C SOIC-16 Si3200-BS Linefeed interface –40 to 85 °C SOIC-16 Si3220-KQ Dual ProSLIC " " 0 to 70 °C TQFP-64 Si3220-BQ Dual ProSLIC " " –40 to 85 °C TQFP-64 Si3225-KQ Dual ProSLIC " 0 to 70 °C TQFP-64 Si3225-BQ Dual ProSLIC " –40 to 85 °C TQFP-64 Preliminary Rev. 0.91 107 Si3220/Si3225 Package Outline: 64-Pin TQFP Figure 65 illustrates the package details for the Dual ProSLIC. Table 48 lists the values for the dimensions shown in the illustration. 64 0° Min. 49 1 0.08/0.20 R 48 A2 0-7° E1 E 0.08 R. Min. A1 e 0.20 Min. 33 16 17 Detail A 32 D1 L 1.00 REF Exposed Pad 6 x 6 mm b D with lead finish See Detail A A 0.09/0.20 0.09/0.16 base metal b1 See Detail B Detail B Figure 65. 64-Pin Thin Quad Flat Package (TQFP) Table 48. 64-Pin Package Diagram Dimensions Symbol Millimeters Min Nom Max A — — 1.20 A1 0.05 — 0.15 A2 0.95 1.00 1.05 D 12.00 BSC D1 10.00 BSC E 12.00 BSC E1 10.00 BSC L 0.45 e 108 0.60 0.75 0.50 BSC b 0.17 0.22 0.27 b1 0.17 0.20 0.23 Preliminary Rev. 0.91 GAUGE PLANE Si3220/Si3225 Package Outline: 16-Pin SOIC Figure 66 illustrates the package details for the Si3200. Table 49 lists the values for the dimensions shown in the illustration. 16 9 h E H 0.010 θ 1 8 B GAUGE PLANE L Exposed Pad 2.3 x 3.6 mm Detail F D A2 e C A L1 A1 See Detail F Seating Plane γ Figure 66. 16-Pin Small Outline Integrated Circuit (SOIC) Package Table 49. Package Diagram Dimensions Symbol A A1 A2 B C D E e H h L L1 γ θ Millimeters Min Max 1.35 1.75 .10 .25 1.30 1.50 .33 .51 .19 .25 9.80 10.01 3.80 4.00 1.27 BSC 5.80 6.20 .25 .50 .40 1.27 1.07 BSC — 0.10 0º 8º Preliminary Rev. 0.91 109 Si3220/Si3225 Document Change List Revision 0.9 to Revision 0.91 ! Table 8 on page 12 " " " ! "Calculating Overhead Voltages" on page 27 " ! TIP/RING Pulldown Transistor Saturation Voltage updated. TIP/RING Pullup Transistor Saturation Voltage updated. Note added. Second paragraph updated. "Internal Trapezoidal Ringing" on page 42 " 110 RINGAMP equation updated. Preliminary Rev. 0.91 Si3220/Si3225 Notes: Preliminary Rev. 0.91 111 Si3220/Si3225 Contact Information Silicon Laboratories Inc. 4635 Boston Lane Austin, TX 78735 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: productinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories, Silicon Labs, ProSLIC, and Modfeed are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. 112 Preliminary Rev. 0.91