SI5013-EVB

Si 5 0 1 3 - EVB E V A L U A T I O N B O A R D F O R S i 5 0 1 3 S i P H Y ™ M U L TI -R A T E S O N E T / S D H C L O C K A N D D ATA R E C O V E R Y I C Description Features The Si5013 evaluation board provides a platform for testing and characterizing Silicon Laboratories’ Si5013 SiPHY™ multi-rate SONET/SDH clock and data recovery IC. The Si5013 CDR supports OC-12/3, STM 4/1 data rates.  Single 3.3 V power supply Differential I/Os ac coupled  Simple jumper configuration  All high-speed I/Os are ac coupled to ease interfacing to industry standard test equipment. Function Block Diagram VDD 210  Pulse Generator Jitter Analyzer ZC = 50  ZC = 50  ZC = 50  ZC = 50  Si5013 348  Pattern Generator + CLKOUT – + REFCLK – ZC = 50  ZC = 50  + DATAIN – Scope + DATAOUT – ZC = 50  ZC = 50  Pattern Analyzer LOS RATESEL LOL LTR BER_ALM DSQLCH RESET/CAL CLKDSBL Test Points Jumpers LOS_LVL REXT SLICE_LVL 10 k BER_LVL Si5013-EVB Rev. 1.0 12/02 Copyright © 2002 by Silicon Laboratories Si5013-EVB-DS10 Si5013-EVB CAUTION: The evaluation board is designed so that the body of the SMA jacks and GND are shorted. Care must be taken when powering the PCB at potentials other than GND at 0.0 V and VDD at 3.3 V relative to chassis GND. Device Powerdown The CDR can be powered down via the RESET/CAL signal. When asserted, the evaluation board draws minimal current. RESET/CAL is controlled via one jumper located in the lower left-hand corner of the evaluation board. RESET/CAL is wired to the signal post adjacent to the VDD post. For a valid reset to occur when using external reference clock mode, a proper external reference clock frequency must be applied as specified in Table 1. CLKOUT, DATAOUT, DATAIN CLKOUT, DATAOUT, and DATAIN (all high-speed I/Os) are wired to the board perimeter on 30 mil (0.030 inch) 50  microstrip lines to the end-launch SMA jacks as labeled on the PCB. These I/Os are ac coupled to simplify direct connection to a wide array of standard test hardware. Because each of these signals are differential, both the positive (+) and negative (–) terminals must be terminated to 50 . Terminating only one side will adversely degrade the performance of the CDR. The inputs are terminated on the die with 50  resistors. Note: The 50  termination is for each terminal/side of a differential signal, thus the differential termination is actually 50  + 50  = 100 . REFCLK REFCLK is optional for clock and data recovery within the Si5013 device. If REFCLK is not used, jumper both JP15 and JP16. These jumpers pull the REFCLK+ input to VDD and REFCLK– input to GND, which configures the device to operate without an external reference. 2 Table 1. Typical REFCLK Frequencies SONET/SDH Gigabit Ethernet SONET/SDH with 15/14 FEC Ratio of VCO to REFCLK 19.44 MHz 19.53 MHz 20.83 MHz 128 77.76 MHz 78.125 MHz 83.31 MHz 32 155.52 MHz 156.25 MHz 166.63 MHz 16 RATESEL RATESEL is used to configure the CDR to recover clock and data at different data rates. RATESEL is an input controlled via a jumper (JP10) located in the lower lefthand corner of the evaluation board. RATESEL is wired to the center post (signal post) between VDD and GND. For example, the OC-12 data rate is selected by jumping RATESEL to a 1 (VDD). GND The evaluation board requires one 3.3 V supply. Supply filtering is placed on the board to filter typical system noise components; however, initial performance testing should use a linear supply capable of supplying the nominal voltage ±5% dc. VDD Power Supply GND The evaluation board simplifies characterization of the Si5013 Clock and Data Recovery (CDR) device by providing access to all of the Si5013 I/Os. Device performance can be evaluated by following the “Test Configuration” section. Specific performance metrics include input sensitivity, jitter tolerance, jitter generation, and jitter transfer. When applied, REFCLK is used to center the frequency of the DSPLL™ so the device can lock to the data. Ideally, the REFCLK frequency should be 1/128th, 1/32nd, or 1/16th the VCO frequency and must have a frequency accuracy of ±100 ppm. Internally, the CDR automatically recognizes the REFCLK frequency within one of these three frequency ranges. Typical REFCLK frequencies are given in Table 1. REFCLK is ac coupled to the SMA jacks located on the top side of the evaluation board. VDD Functional Description RATESEL RATESEL 622 Mbps 155 Mbps Figure 1. RATESEL Jumper Configurations Loss-of-Lock (LOL) Loss-of-lock (LOL) is an indicator of the relative frequency between the data and the REFCLK. LOL asserts when the frequency difference is greater than ±600 ppm. To prevent LOL from de-asserting prematurely, there is hysterisis in returning from the outof-lock condition. LOL will be de-asserted when the frequency difference is less than ±300 ppm. LOL is wired to a test point which is located on the upper right-hand side of the evaluation board. Rev. 1.0 Si5013-EVB Loss-of-signal Alarm Threshold Control The loss-of-signal alarm (LOS) is used to signal low incoming data amplitude levels. The programmable threshold control is set by applying a dc voltage level from a low-noise voltage source to the LOS_LVL pin. The LOS_LVL is controllable through the BNC jack J10. The mapping of the LOS_LVL voltage to input signal alarm threshold level is shown in Figure 2. The LOS Threshold to LOS Level is mapped as follows: V LOS_LVL – 1.5 V LOS = --------------------------------------25 If this function is not used, install jumper to JP1 header 30 mV 15 mV LOS Undefined LOS Disabled LOS Threshold (mVPP) 40 mV V SLICE_LVL – 1.5 V SLICE = -------------------------------------------50 If this function is not used, install jumper to JP6 header. Bit-Error-Rate Alarm Threshold The bit-error-rate of the incoming data can be monitored by the BER_ALM pin. When the bit-error-rate exceeds an externally set threshold level, BER_ALM is asserted. BER_ALM is brought to a test point located in the upper right-hand corner of the board. The BER_ALM threshold level is set by applying a dc voltage to the BER_LVL pin. BER_LVL is controllable through the BNC jack J12. Jumper JP7 to disable the BER alarm. Refer to the “BER Detection” section of the Si5012/Si5013 data sheet for threshold level programming. Test Configuration The three critical jitter tests typically performed on a CDR device are jitter transfer, jitter tolerance, and jitter generation. By connecting the Si5013 Evaluation Board as shown in Figure 3, all three measurements can be easily made. 40 mV/V 0 mV 0V 1.00 V SLICE_LVL is controllable through the BNC jack J11. The SLICE_LVL to the data slicing level is mapped as follows: 1.50 V 1.875 V 2.25 V 2.5 V When applied, REFCLK should be within ±100 ppm of the frequency selected from Table 1 and RESET/CAL must be unjumpered. LOS_LVL (V) Figure 2. LOS_LVL Mapping Extended LOS Hysteresis Option An optional LOS Hysteresis Extension circuit is included on the Si5013-EVB to provide a convenient means of increasing the amount of LOS Alarm hysteresis when testing and evaluating the Si5013 LOS functionality. This simple network will extend the LOS hysteresis to approximately 6 dB, thereby preventing unnecessary switching on LOS for low-level DATAIN signals in the range of 20 mVPPD. Hysteresis is defined as the ratio of the LOS deassert level (LOSD) and the LOS assert level (LOSA). The hysteresis in decibels is calculated as 20log(LOSD/LOSA). This circuit is constructed with one CMOS inverter (U2) and two resistors (R12, R13) mounted on the underside of the PCB. If desired, this circuit can be enabled by installing a jumper on JP17 (HYST ENABLE) located near the power entry block. Data Slicing Level The slicing level allows optimization of the input crossover point for systems where the slicing level is not at the amplitude average. The data slicing level can be adjusted from the nominal cross-over point of the data by applying a voltage to the SLICE_LVL pin. Jitter Tolerance: Referring to Figure 3, this test requires a pattern generator, a clock source (synthesizer signal source), a modulation source, a jitter analyzer, a pattern analyzer, and a pulse generator (all unconnected high-speed outputs must be terminated to 50 ). During this test, the Jitter Analyzer directs the Modulation Source to apply prescribed amounts of jitter to the synthesizer source. This “jitters” the pattern generator timebase which drives the DATAIN ports of the CDR. The Bit-Error-Rate (BER) is monitored on the Pattern Analyzer. The modulation (jitter) frequency and amplitude is recorded when the BER approaches a specified threshold. The Si5013 limiting amplifier can also be examined during this test. Simply lower the amplitude of the incoming data to the minimum value typically expected at the limiting amplifier inputs (typically 10 mVPP for the Si5013 device). Jitter Generation: Referring to Figure 3, this test requires a pattern generator, a clock source (synthesizer signal source), a jitter analyzer, and a pulse generator (all unconnected high-speed outputs must be terminated to 50 ). During this test, there is no modulation of the Data Clock, so the data that is sent to the CDR is jitter free. The Jitter Analyzer measures the Rev. 1.0 3 Si5013-EVB must be terminated to 50 ). During this test, the Jitter Analyzer modulates the data pattern and data clock reference. The modulated data clock reference is compared with the CLKOUT of the CDR. Jitter on CLKOUT relative to the jitter on the data clock reference is plotted versus modulation frequency at predefined jitter amplitudes. RMS and peak-to-peak jitter on the CDR CLKOUT. Thus, any jitter measured is jitter generated by the CDR. Jitter Transfer: Referring to Figure 3, this test requires a pattern generator, a clock source (synthesizer signal source), a modulation source, a jitter analyzer, and a pulse generator (all unconnected high-speed outputs Pulse Generator Scope DATAOUT– Pattern Analyzer GPIB 3.3 V + – REFCLK+ Data Clock- REFCLK– DATAIN+ + REFCLK – (optional) + DATAIN – DATAIN– Pattern Generator DATAOUT + – CLKOUT + – Si5013-EVB DATAOUT+ CLKOUT+ CLKOUT– Jitter Analyzer Data Clock+ GPIB GPIB Clock Synthesizer Signal Source FM Modulation Source GPIB Figure 3. Test Configuration for Jitter Tolerance, Transfer, and Generation 4 Rev. 1.0 POS2 POS1 2 1 Rev. 1.0 J8 J7 REFCLK- J2 J1 REFCLK+ DIN- DIN+ BER_LVL SLICE_LVL LOS_LVL AMP 449692 AMP 449692 AMP 449692 AMP 449692 J12 BNC J11 BNC J10 BNC MKDSN 2,5/3-5,08 J13 L1 0603 0.1uF C6 0603 0.1uF C5 0603 0.1uF C7 0603 0.1uF C8 JP7 JP6 JP1 tantalum 10uF C12 VDD VDD R6 0603 210 0603 806 R12 LOS_N 2 Reference Less Operation (jumper both JP15 and JP16) 0603 0.1uF C20 0603 0.1uF C19 0603 0.1uF C18 0603 0.1uF C17 JP15 NC7SZ04 U2 4 R5 0603 348 JP16 3 5 VDD HYSTERESIS ENABLE CLKDSBL R8 0603 100 RESET/CAL JP3 DSQLCH JP5 Figure 4. Si5013 Schematic NO LOAD JP4 JP17 R13 0603 10K JP2 REXT TDI REFCLK- REFCLK+ DIN- DIN+ Si5013 CLKOUT+ CLKOUT- DOUT+ DOUT- BER_MON LOL LOS BER_ALM 23 22 17 16 28 7 9 27 0603 100pF C16 0603 100pF C15 0603 100pF C14 0603 100pF C13 NO LOAD JP9 Si5013 LOS_LVL SLICE_LVL BER_LVL RESET/CAL CLKDSBL RATESEL RES/GND LTR DSQLCH U1 R1 0603 10k (1%) 20 15 6 5 13 12 3 4 26 19 24 1 2 8 10 NO LOAD 0603 0 R11 0603 0 R10 VDD ------LTR JP8 11 14 18 21 25 VDDA VDDB VDDC VDDD VDDE 3.3V R9 0603 0 RATESEL JP10 LOS_N 0603 0.1uF C1 0603 0.1uF C2 0603 0.1uF C3 0603 0.1uF C4 DOUT- JP14 JP13 JP12 JP11 CLKOUT+ J6 AMP 449692 J5 AMP 449692 CLKOUT- DOUT+ J4 AMP 449692 J3 AMP 449692 R7 0603 4.99K BER_MON ---------------BER_ALM ------LOS ------LOL Si5013-EVB 5 Si5013-EVB Bill of Materials Si5013EVB Assy Rev B-01 BOM 6 3/29/2002 Reference Description Manufacturer's # Manufacturer C1,C2,C3,C4,C5,C6, C7,C8,C17,C18,C19, C20 C12 C13,C14,C15,C16 JP1,JP6,JP7,JP11, JP12,JP13,JP14, JP15,JP16,JP17 JP2,JP3,JP5,JP8, JP10 J1,J2,J3,J4,J5,J6, J7,J8 J10,J11,J12 J13 L1 R1,R13 R5 R6 R7 R8 R9 R12 U1 U2 PCB No Load JP4,JP9 R10,R11 CAP,SM,0.1UF,16V,20%,X7R,0603 C0603X7R160-104KNE VENKEL CAP,SM,10UF,10V,10%,TANTALUM,3216 CAP,SM,100PF,50V,10%,C0G,0603 CONN,HEADER,2X1 TA010TCM106KAR VENKEL C0603C0G500-101KNE VENKEL 2340-6111TN or 2380-6121TN 3M CONN,HEADER,3X1 2340-6111TN or 2380-6121TN 3M CONN,SMA SIDE MOUNT 901-10003 AMPHENOL CONN,BNC,VERT CONN,POWER,2 POSITION FERRITE,SM,600,1206 RES,SM,10K,1%,0603 RES,SM,348,1%,0603 RES,SM,210,1%,0603 RES,SM,4.99K,1%,0603 RES,SM,100,1%,0603 RES,SM,0 OHM,0603 RES,SM,806,1%,0603 Si5013 Rev B Device IC,SM,7SZ04,SINGLE GATE INVERTER,5 PIN SOT23 Printed Circuit Board 161-9317 1729018 BLM31A601S CR0603-16W-1002FT CR0603-16W-3480FT CR0603-16W-2100FT CR0603-16W-4991FT CR0603-16W-1000FT CR0603-16W-000T CR0603-16W-8060FT Si5013-BM Rev B NC7SZ04M5X Si5013-EVB PCB Rev C MOUSER PHOENIX CONTACT MURATA VENKEL VENKEL VENKEL VENKEL VENKEL VENKEL VENKEL SILICON LABORATORIES FAIRCHILD SILICON LABORATORIES CONN,HEADER,3X1 RES,SM,0 OHM,0603 2340-6111TN or 2380-6121TN 3M CR0603-16W-000T VENKEL Rev. 1.0 Si5013-EVB Figure 5. Si5013 Top View Rev. 1.0 7 Si5013-EVB Figure 6. Si5013 Component Side 8 Rev. 1.0 Si5013-EVB Figure 7. Si5013 Solder Side Rev. 1.0 9 Si5013-EVB Document Change List Revision 0.22 to Revision 1.0  “Preliminary” language removed. Evaluation Board Assembly Revision History 10 Assembly Level PCB Rev. Si5013 Rev. B-01 Rev. C Rev. B Assembly Notes Assemble per BOM rev B-01 Rev. 1.0 ClockBuilder Pro One-click access to Timing tools, documentation, software, source code libraries & more. Available for Windows and iOS (CBGo only). www.silabs.com/CBPro Timing Portfolio www.silabs.com/timing SW/HW Quality Support and Community www.silabs.com/CBPro www.silabs.com/quality community.silabs.com Disclaimer Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or intending to use the Silicon Laboratories products. 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