Si52212/Si52208/Si52204/Si52202
Data Sheet
12/8/4/2-Output PCI-Express Gen 1/2/3/4/5 and SRIS Clock
Generator
The Si52212/08/04/02 are the industry's highest performance and lowest power PCI Express clock generator family for 1.5–1.8 V PCIe Gen 1/2/3/4/5 and SRIS applications.
The Si52212, Si52208, and Si52204 can source twelve, eight, and four 100 MHz PCIe
differential clock outputs, respectively, plus one 25 MHz LVCMOS reference clock output. The Si52202 can source two 100 MHz PCIe clock outputs only. All differential clock
outputs are compliant to PCIe Gen1/2/3/4/5 common clock and separate reference clock
architectures specifications.
The Si52212/08/04/02 feature individual hardware control pins for enabling and disabling each output, spread spectrum enable/disable for EMI reduction, and frequency select to select 100, 133, or 200 MHz differential output frequencies. These features can
also be controlled via I2C.
The small footprint and low power consumption make this family of PCIe clock generators ideal for industrial and consumer applications.
For more information about PCI-Express, Silicon Labs' complete PCIe portfolio, application notes, and design tools, including the Silicon Labs PCIe Clock Jitter Tool for PCIExpress compliance, please visit the Silicon Labs PCI Express Learning Center.
Applications
• Servers
• Storage
• Data Centers
• PCIe Add-on Cards
• Network Interface Cards (NIC)
• Graphics Adapter Cards
• Multi-function Printers
• Digital Single-Lens Reflex (DSLR) Cameras
• Digital Still Cameras
• Digital Video Cameras
• Docking Stations
silabs.com | Building a more connected world.
KEY FEATURES
• 12/8/4/2-output low-power, push-pull HCSL
compatible PCI-Express Gen 1, Gen 2,
Gen 3, Gen 4, Gen 5, and SRIS-compliant
outputs
• Low jitter: 0.13 ps rms max, Gen 5
• Individual hardware control pins and I2C
controls for Output Enable, Spread
Spectrum Enable and Frequency Select
• Triangular spread spectrum for EMI
reduction, down spread 0.25% or 0.5%
• Internal 100 Ω or 85 Ω line matching
• Adjustable output slew rate
• Power down (PWRDNb) function supports
Wake-on LAN (except Si52202)
• One non-spread, LVMCOS reference clock
output (except Si52202)
• Frequency Select to select 133 MHz or
200 MHz (except Si52202)
• 25 MHz crystal input or clock input
• I2C support with readback capabilities
• Extended temperature: –40 to 85 °C
• 1.5–1.8 V power supply, with separate
VDD and VDD_IO
• Small QFN packages
• Pb-free, RoHS-6 compliant
Rev. 1.0
Data Sheet
Feature List
1. Feature List
• 12/8/4/2-output 100 MHz PCIe Gen 1/2/3/4/5 and SRIS compliant clock generator, with push-pull HCSL output drivers
• High port count with push-pull HCSL outputs to support highly integrated solution, eliminating external resistors for the HCSL output drivers
• Low jitter of 0.13 ps rms max to meet PCIe Gen5 specifications with design margin
• Low power consumption.
• Lowest power consumption in the industry for a 2-output PCIe clock generator
• Individual hardware control pins and I2C controls for Output Enable, Spread Spectrum Enable and Frequency Select
• Output Enable function easily disables unused outputs for power saving
• Spread Enable function to turn on/off spread spectrum and to select spread levels, either down spread 0.25% or 0.5%
• Frequency Select function to select output frequency of 100 MHz, 133 MHz, or 200 MHz (except Si52202 where the output frequency is limited to 100 MHz. Please contact Silicon Labs for 133 MHz or 200 MHz in Si52202)
• All above functions are controlled by individual hardware pins or I2C
• Internal 100 Ω or 85 Ω impedance matching
• Eliminates external line matching resistor to reduce board space
• Adjustable slew rate to improve signal quality for different applications and board designs
• Power down (PWRDNb) function supports Wake-on LAN (except Si52202)
• One non-spread, 25 MHz LVMCOS reference clock output (except Si52202)
• A buffered 25 MHz LVCMOS clock output to drive ASICS or SoCs on board
• 25 MHz reference input
• Supports a standard crystal or clock input for flexibility
• I2C support with readback capabilities
• 1.5–1.8 V power supply with separate VDD and VDD_IO (1.05 to 1.8 V)
• Temperature range: –40 °C to 85 °C
• Small QFN packages to optimize board space. Smallest 2-output PCIe clock generator in the industry
• 64-pin QFN (9 x 9 mm) : 12-output
• 48-pin QFN (6 x 6 mm) : 8-output
• 32-pin QFN (5 x 5 mm) : 4-output
• 20-pin QFN (3 x 3 mm) : 2-output
• Pb-free, RoHS-6 compliant
silabs.com | Building a more connected world.
Rev. 1.0 | 2
Data Sheet
Ordering Guide
2. Ordering Guide
Table 2.1. Si522x Ordering Guide
Number of Outputs
Internal Termination
100 Ω
12-output
85 Ω
100 Ω
8-output
85 Ω
100 Ω
4-output
85 Ω
100 Ω
2-output
85 Ω
Part Number
Package Type
Temperature
Si52212-A01AGM
64-QFN
Extended, –40 to 85 °C
Si52212-A01AGMR
64-QFN - Tape and Reel
Extended, –40 to 85 °C
Si52212-A02AGM
64-QFN
Extended, –40 to 85 °C
Si52212-A02AGMR
64-QFN - Tape and Reel
Extended, –40 to 85 °C
Si52208-A01AGM
48-QFN
Extended, –40 to 85 °C
Si52208-A01AGMR
48-QFN - Tape and Reel
Extended, –40 to 85 °C
Si52208-A02AGM
48-QFN
Extended, –40 to 85 °C
Si52208-A02AGMR
48-QFN - Tape and Reel
Extended, –40 to 85 °C
Si52204-A01BGM
32-QFN
Extended, –40 to 85 °C
Si52204-A01BGMR
32-QFN - Tape and Reel
Extended, –40 to 85 °C
Si52204-A02BGM
32-QFN
Extended, –40 to 85 °C
Si52204-A02BGMR
32-QFN - Tape and Reel
Extended, –40 to 85 °C
Si52202-A01BGM
20-QFN
Extended, –40 to 85 °C
Si52202-A01BGMR
20-QFN - Tape and Reel
Extended, –40 to 85 °C
Si52202-A02BGM
20-QFN
Extended, –40 to 85 °C
Si52202-A02BGMR
20-QFN - Tape and Reel
Extended, –40 to 85 °C
2.1 Technical Support
Table 2.2. Technical Support URLs
Frequently Asked Questions
www.silabs.com/Si522xx-FAQ
PCIe Clock Jitter Tool
www.silabs.com/products/timing/pci-express-learning-center
PCIe Learning Center
www.silabs.com/products/timing/pci-express-learning-center
Development Kit
www.silabs.com/products/development-tools/timing/clock/si52204-evb-evaluation-kit.html
silabs.com | Building a more connected world.
Rev. 1.0 | 3
Table of Contents
1. Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. Ordering Guide
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2.1 Technical Support .
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. 3
3. Functional Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . .
20
5.1 Crystal Recommendations .
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.20
5.2 Crystal Loading .
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.20
5.3 Calculating Load Capacitors
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.21
5.4 Power Supply Filtering Recommendations.
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.22
5.5 PWRGD/PWRDNb (Power Down) Pin .
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.22
5.6 PWRDNb (Power Down) Assertion .
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.23
5.7 PWRDNb (Power Down) Deassertion .
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.23
5.8 OEb Pin .
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.23
5.9 OEb Assertion .
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.23
5.10 OEb Deassertion .
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.24
5.11 FS Pin .
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.24
5.12 SS_EN Pin .
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.24
5.13 Recommendations for Driving Tri-State Pins
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.24
5.14 REF/SA Pin
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6. Test and Measurement Setup
7. PCIe Clock Jitter Tool
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8. Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.1 I2C Interface .
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.29
8.2 Block Read/Write .
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.29
8.3 Block Read .
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.29
8.4 Block Write .
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.30
8.5 Byte Read/Write
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.30
8.6 Byte Read
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.30
8.7 Byte Write
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.31
8.8 Data Protocol
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.32
8.9 Register Tables. . .
8.9.1 Si52212 Registers
8.9.2 Si52208 Registers
8.9.3 Si52204 Registers
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.34
.34
.37
.40
silabs.com | Building a more connected world.
Rev. 1.0 | 4
8.9.4 Si52202 Registers .
9. Pin Descriptions
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.43
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9.1 Si52212 Pin Descriptions
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.46
9.2 Si52208 Pin Descriptions
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.49
9.3 Si52204 Pin Descriptions
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.52
9.4 Si52202 Pin Descriptions
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.54
10. Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
10.1 Si52212 Package
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.56
10.2 Si52212 Land Pattern .
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.57
10.3 Si52208 Package
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.58
10.4 Si52208 Land Pattern .
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.59
10.5 Si52204 Package
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.60
10.6 Si52204 Land Pattern .
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.62
10.7 Si52202 Package
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.63
10.8 Si52202 Land Pattern .
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10.9 Si52212 Top Markings .
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.66
10.10 Si52208 Top Markings
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10.11 Si52204 Top Markings
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.68
10.12 Si52202 Top Markings
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.69
11. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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silabs.com | Building a more connected world.
Rev. 1.0 | 5
Data Sheet
Functional Block Diagrams
3. Functional Block Diagrams
Si52212
XIN/CLKIN
REF
XOUT
FS
SCLK
SDA
PWRGD/PWRDNb
SS_EN
PLL
(SSC)
Divider
DIFF[11:0]
Control
&
Memory
OEb[11:0]
Figure 3.1. Si52212 Block Diagram 12-output, 64-QFN
Si52208
XIN/CLKIN
REF
XOUT
FS
SCLK
SDA
PWRGD/PWRDNb
SS_EN
PLL
(SSC)
Divider
DIFF[7:0]
Control
&
Memory
OEb[7:0]
Figure 3.2. Si52208 Block Diagram 8-output, 48-QFN
Si52204
XIN/CLKIN
REF
XOUT
FS
SCLK
SDA
PWRGD/PWRDNb
SS_EN
PLL
(SSC)
Divider
DIFF[3:0]
Control
&
Memory
OEb[3:0]
Figure 3.3. Si52204 Block Diagram 4-output, 32-QFN
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Rev. 1.0 | 6
Data Sheet
Functional Block Diagrams
Si52202
PLL
(SSC)
XIN/CLKIN
XOUT
SCLK
SDA
PWRGD/PWRDNb
SS_EN
Divider
DIFF[1:0]
Control
&
Memory
OEb[1:0]
Figure 3.4. Si52202 Block Diagram 2-output, 20-QFN
silabs.com | Building a more connected world.
Rev. 1.0 | 7
Data Sheet
Electrical Specifications
4. Electrical Specifications
Table 4.1. DC Electrical Specifications (VDD = 1.5 V ±5%)
VDD = VDDR = VDDX = VDDA = 1.5 V ±5%
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
VDD
1.5 V ±5%
1.425
1.5
1.575
V
VDD_IO
Supply voltage for differential Low
Power outputs
0.9975
1.05–1.5
1.575
V
1.5 V Input High Voltage
VIH
Control input pins, except SDATA,
SCLK
0.75 VDD
—
VDD + 0.3
V
1.5V Input Mid Voltage
VIM
Tri-level control input pins, except
SDATA, SCLK
0.4 VDD
0.5 VDD
0.6 VDD
V
1.5 V Input Low Voltage
VIL
Control input pins, except SDATA,SCLK
–0.3
—
0.25 VDD
V
Input High Voltage
VIHI2C
SDATA, SCLK
1.14
—
3.3
V
Input Low Voltage
VILI2C
SDATA, SCLK
—
—
0.6
V
IPULLUP
At VOL
4
—
IIN
Single-ended inputs, VIN = GND,
VIN = VDD
–5
—
5
uA
IINP
Single-ended inputs, VIN = 0 V, inputs with internal pull-up resistors
VIN = VDD, inputs with internal
pull-down resistors
–200
—
200
uA
CIN
1.5
—
5
pF
COUT
—
—
6
pF
LIN
—
—
7
nH
1.5 V Operating Voltage
Output Supply Voltage
SDATA, SCLK Sink Current
Input current
Input Pin Capacitance
Output Pin Capacitance
Pin Inductance
mA
Si52212 Current Consumption (VDD = VDDR = VDDX = VDDA = 1.5 V ±5%)
Power Down Current
PWRGD/PWRDNb = "0"
Byte 2, bit 2 = 0
Wake-on LAN Current
PWRGD_PWRDNb = "0"
Byte 2, bit 2 = 1
IDD_PD_total
All outputs off
—
1.3
1.8
mA
IDD_PD
VDD, except VDDA and VDD_IO,
all outputs off
—
0.4
1.0
mA
IDD_APD
VDDA, all outputs off
—
0.6
0.75
mA
IDD_IOPD
VDD_IO, all outputs off
—
0.3
0.5
mA
IDD_WOL
VDD, except VDDA and VDD_IO,
all differential outputs off, REF
running
—
2.5
3.2
mA
IDD_AWOL
VDDA, all differential outputs off,
REF running
—
0.6
0.75
mA
IDD_IOWOL
VDD_IO, all differential outputs off,
REF running
—
0.3
0.5
mA
silabs.com | Building a more connected world.
Rev. 1.0 | 8
Data Sheet
Electrical Specifications
Parameter
Dynamic Supply Current
Symbol
Test Condition
Min
Typ
Max
Unit
IDD_1.5V_Total
All outputs enabled. Differential
clocks with 5” traces and 2 pF
load.
—
66
77
mA
IDD_OP
VDD, except VDDA and VDD_IO,
all differential outputs active at 100
MHz
—
13
14.5
mA
IDD_AOP
VDDA, all differential outputs active at 100 MHz
—
7
8.5
mA
IDD_IOOP
VDD_IO, all differential outputs active at 100 MHz
—
46
55.5
mA
Si52208 Current Consumption (VDD = VDDR = VDDX = VDDA = 1.5 V ±5%)
Power Down Current
PWRGD/PWRDNb = "0"
Byte 2, bit 2 = 0
Wake-on LAN Current
PWRGD_PWRDNb = "0"
Byte 2, bit 2 = 1
Dynamic Supply Current
IDD_PD_total
All outputs off
—
1.3
1.8
mA
IDD_PD
VDD, except VDDA and VDD_IO,
all outputs off
—
0.4
1.0
mA
IDD_APD
VDDA, all outputs off
—
0.6
0.75
mA
IDD_IOPD
VDD_IO, all outputs off
—
0.3
0.5
mA
IDD_WOL
VDD, except VDDA and VDD_IO,
all differential outputs off, REF
running
—
2.5
3.2
mA
IDD_AWOL
VDDA, all differential outputs off,
REF running
—
0.6
0.75
mA
IDD_IOWOL
VDD_IO, all differential outputs off,
REF running
—
0.3
0.5
mA
IDD_1.5V_Total
All outputs enabled. Differential
clocks with 5” traces and 2 pF
load.
—
48
58.5
mA
IDD_OP
VDD, except VDDA and VDD_IO,
all differential outputs active at 100
MHz
—
11
12.5
mA
IDD_AOP
VDDA, all differential outputs active at 100 MHz
—
7
8.5
mA
IDD_IOOP
VDD_IO, all differential outputs active at 100 MHz
—
30
37.5
mA
Si52204 Current Consumption (VDD = VDDR = VDDX = VDDA = 1.5 V ±5%)
Power Down Current
PWRGD/PWRDNb = "0"
Byte 2, bit 2 = 0
Wake-on LAN Current
PWRGD_PWRDNb = "0"
Byte 2, bit 2 = 1
IDD_PD_total
All outputs off
—
1.3
1.8
mA
IDD_PD
VDD, except VDDA and VDD_IO,
all outputs off
—
0.4
1.0
mA
IDD_APD
VDDA, all outputs off
—
0.6
0.75
mA
IDD_IOPD
VDD_IO, all outputs off
—
0.3
0.5
mA
IDD_WOL
VDD, except VDDA and VDD_IO,
all differential outputs off, REF
running
—
2.5
3.2
mA
IDD_AWOL
VDDA, all differential outputs off,
REF running
—
0.6
0.75
mA
IDD_IOWOL
VDD_IO, all differential outputs off,
REF running
—
0.3
0.5
mA
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Data Sheet
Electrical Specifications
Parameter
Dynamic Supply Current
Symbol
Test Condition
Min
Typ
Max
Unit
IDD_1.5V_Total
All outputs enabled. Differential
clocks with 5” traces and 2 pF
load.
—
32
37
mA
IDD_OP
VDD, except VDDA and VDD_IO,
all differential outputs active at 100
MHz
—
9.5
11
mA
IDD_AOP
VDDA, all differential outputs active at 100 MHz
—
7
8.5
mA
IDD_IOOP
VDD_IO, all differential outputs active at 100 MHz
—
15.5
19
mA
Si52202 Current Consumption (VDD = VDDR = VDDX = VDDA = 1.5 V ±5%)
Power Down Current
PWRGD/PWRDNb = "0"
Dynamic Supply Current
IDD_PD_total
All outputs off
—
1.3
1.8
mA
IDD_PD
VDD, except VDDA and VDD_IO,
all outputs off
—
0.4
1.0
mA
IDD_APD
VDDA, all outputs off
—
0.3
0.75
mA
IDD_IOPD
VDD_IO, all outputs off
—
0.6
0.5
mA
IDD_1.5V_Total
All outputs enabled. Differential
clocks with 5” traces and 2 pF
load.
—
22
25.5
mA
IDD_OP
VDD, except VDDA and VDD_IO,
all differential outputs active at 100
MHz
—
7
8
mA
IDD_AOP
VDDA, all differential outputs active at 100 MHz
—
7
8.5
mA
IDD_IOOP
VDD_IO, all differential outputs active at 100 MHz
—
8
10
mA
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Data Sheet
Electrical Specifications
Table 4.2. DC Electrical Specifications (VDD = 1.8 V ±5%)
VDD = VDDR = VDDX = VDDA = 1.8 V ±5%
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
VDD
1.8 V ±5%
1.71
1.8
1.89
V
VDD_IO
Supply voltage for differential Low
Power outputs
0.9975
1.05–1.8
1.9
V
1.8 V Input High Voltage
VIH
Control input pins, except SDATA,
SCLK
0.75 VDD
—
VDD+0.3
V
1.8 V Input Mid Voltage
VIM
Tri-level control input pins, except
SDATA, SCLK
0.4 VDD
0.5 VDD
0.6 VDD
V
1.8 V Input Low Voltage
VIL
Control input pins, except SDATA,SCLK
-0.3
—
0.25 VDD
V
Input High Voltage
VIHI2C
SDATA, SCLK
1.11
—
3.3
V
Input Low Voltage
VILI2C
SDATA, SCLK
—
—
0.6
V
IPULLUP
At VOL
4
—
IIN
Single-ended inputs, VIN = GND,
VIN = VDD
–5
—
5
uA
IINP
Single-ended inputs, VIN = 0V, inputs with internal pull-up resistors
VIN = VDD, inputs with internal
pull-down resistors
–200
—
200
uA
CIN
1.5
—
5
pF
COUT
—
—
6
pF
LIN
—
—
7
nH
1.8 V Operating Voltage
Output Supply Voltage
SDATA, SCLK Sink Current
Input current
Input Pin Capacitance
Output Pin Capacitance
Pin Inductance
mA
Si52212 Current Consumption (VDD = VDDR = VDDX = VDDA = 1.8 V ±5%)
Power Down Current
PWRGD/PWRDNb = "0"
Byte 2, bit 2 = 0
Wake-on LAN Current
PWRGD/PWRDNb = "0"
Byte 2, bit 2 = 1
IDD_PD_total
All outputs off
—
1.4
2.9
mA
IDD_PD
VDD, except VDDA and VDD_IO,
all outputs off
—
0.5
2.0
mA
IDD_APD
VDDA, all outputs off
—
0.6
0.9
mA
IDD_IOPD
VDD_IO, all outputs off
—
0.3
0.65
mA
IDD_WOL
VDD, except VDDA and VDD_IO,
all differential outputs off, REF
running
—
3.0
4.6
mA
IDD_AWOL
VDDA, all differential outputs off,
REF running
—
0.7
0.9
mA
IDD_IOWOL
VDD_IO, all differential outputs
off, REF running
—
0.5
0.65
mA
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Data Sheet
Electrical Specifications
Parameter
Dynamic Supply Current
Symbol
Test Condition
Min
Typ
Max
Unit
IDD_1.8V_Total
All outputs enabled. Differential
clocks with 5” traces and 2 pF
load.
—
67
78
mA
IDD_OP
VDD, except VDDA and VDD_IO,
all differential outputs active at
100 MHz
—
13
16
mA
IDD_AOP
VDDA, all differential outputs active at 100 MHz
—
7
8.5
mA
IDD_IOOP
VDD_IO, all differential outputs
active at 100 MHz
—
47
56.5
mA
Si52208 Current Consumption (VDD = VDDR = VDDX = VDDA = 1.8 V ±5%)
Power Down Current
PWRGD/PWRDNb = ''0"
Byte 2, bit 2 = 0
Wake-on LAN Current
PWRGD/PWRDNb = "0"
Byte 2, bit 2 = 1
Dynamic Supply Current
IDD_PD_total
All outputs off
—
1.4
2.9
mA
IDD_PD
VDD, except VDDA and VDD_IO,
all outputs off
—
0.5
2.0
mA
IDD_APD
VDDA, all outputs off
—
0.6
0.9
mA
IDD_IOPD
VDD_IO, all outputs off
—
0.3
0.65
mA
IDD_WOL
VDD, except VDDA and VDD_IO,
all differential outputs off, REF
running
—
3.0
4.6
mA
IDD_AWOL
VDDA, all differential outputs off,
REF running
—
0.7
0.9
mA
IDD_IOWOL
VDD_IO, all differential outputs
off, REF running
—
0.5
0.65
mA
IDD_1.8V_Total
All outputs enabled. Differential
clocks with 5” traces and 2 pF
load.
—
49.5
58.5
mA
IDD_OP
VDD, except VDDA and VDD_IO,
all differential outputs active at
100 MHz
—
11.5
14
mA
IDD_AOP
VDDA, all differential outputs active at 100 MHz
—
7
8.5
mA
IDD_IOOP
VDD_IO, all differential outputs
active at 100 MHz
—
31
38
mA
Si52204 Current Consumption (VDD = VDDR = VDDX = VDDA = 1.8 V ±5%)
Power Down Current
PWRGD/PWRDNb = "0"
Byte 2, bit 2 = 0
Wake-on LAN Current
PWRGD/PWRDNb = ''0"
Byte 2, bit 2 = 1
IDD_PD_total
All outputs off
—
1.4
2.9
mA
IDD_PD
VDD, except VDDA and VDD_IO,
all outputs off
—
0.5
2.0
mA
IDD_APD
VDDA, all outputs off
—
0.6
0.9
mA
IDD_IOPD
VDD_IO, all outputs off
—
0.3
0.65
mA
IDD_WOL
VDD, except VDDA and VDD_IO,
all differential outputs off, REF
running
—
3.0
4.6
mA
IDD_AWOL
VDDA, all differential outputs off,
REF running
—
0.7
0.9
mA
IDD_IOWOL
VDD_IO, all differential outputs
off, REF running
—
0.5
0.65
mA
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Data Sheet
Electrical Specifications
Parameter
Dynamic Supply Current
Symbol
Test Condition
Min
Typ
Max
Unit
IDD_1.8V_Total
All outputs enabled. Differential
clocks with 5” traces and 2 pF
load.
—
33
38
mA
IDD_OP
VDD, except VDDA and VDD_IO,
all differential outputs active at
100 MHz
—
10
12
mA
IDD_AOP
VDDA, all differential outputs active at 100 MHz
—
7
8.5
mA
IDD_IOOP
VDD_IO, all differential outputs
active at 100 MHz
—
16
19.5
mA
Si52202 Current Consumption (VDD = VDDR = VDDX = VDDA = 1.8 V ±5%)
Power Down Current
PWRGD/PWRDNb = "0"
Dynamic Supply Current
IDD_PD_total
All outputs off
—
1.4
2.9
mA
IDD_PD
VDD, except VDDA and VDD_IO,
all outputs off
—
0.5
2.0
mA
IDD_APD
VDDA, all outputs off
—
0.6
0.9
mA
IDD_IOPD
VDD_IO, all outputs off
—
0.3
0.65
mA
IDD_1.8V_Total
All outputs enabled. Differential
clocks with 5” traces and 2 pF
load.
—
24
26.5
mA
IDD_OP
VDD, except VDDA and VDD_IO,
all differential outputs active at
100 MHz
—
8
9
mA
IDD_AOP
VDDA, all differential outputs active at 100 MHz
—
7
8.5
mA
IDD_IOOP
VDD_IO, all differential outputs
active at 100 MHz
—
8
10.5
mA
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Data Sheet
Electrical Specifications
Table 4.3. AC Electrical Specifications
Parameter
Symbol
Condition
Min
Typ
Max
Unit
—
25
—
MHz
Clock Input
CLKIN Frequency
TDC
Measured at VDD/2
45
—
55
%
TR/TF
Measured between 0.2 VDD and
0.8 VDD
0.5
—
4
V/ns
Input High Voltage
VIH
XIN/CLKIN pin
0.75 VDD
—
—
V
Input Low Voltage
VIL
XIN/CLKIN pin
—
—
0.25 VDD
V
VCOM
Common mode input voltage
300
—
1000
mV
VSWING
Peak to Peak value
300
—
1450
mV
Trise
Tr
Rise time of single-ended control
inputs
—
—
5
ns
Tfall
Tf
Fall time of single-ended control
inputs
—
—
5
ns
SDATA, SCLK Rise Time
TrI2C
(Max VIL – 0.15) to
(Min VIH + 0.15)
—
—
1000
ns
SDATA, SCLK Fall Time
TfI2C
(Min VIH + 0.15) to
(Max VIL – 0.15)
—
—
300
ns
FmaxI2C
Maximum I2C operating
frequency
—
—
400
kHz
CLKIN Duty Cycle
CLKIN Rising and Falling
Slew Rate
Input Common Mode
Input Amplitude
Control Input Pins
I2C Operating
Frequency
LVCMOS – REF (VDD = 1.5 V ±5%)
Long Accuracy
Clock Period
ppm
Variation from reference
frequency
TPERIOD
25 MHz output
—
40
—
ns
Trf
Byte 2[1:0] = 48 (Slowest), 20% to
80% of VDDREF
—
0.5
1.0
V/ns
Byte 2[1:0] = 49 (Slow), 20% to
80% of VDDREF
—
0.7
1.3
V/ns
Byte 2[1:0] = 4A (Fast), 20% to
80% of VDDREF
—
0.9
1.5
V/ns
Byte 2[1:0] = 4B (Fastest), 20% to
80% of VDDREF
—
0.9
1.6
V/ns
Slew Rate
0
ppm
Duty Cycle1
TDC_REF
VT = VDD/2 V
45
50
55
%
Cycle-to-Cycle Jitter
TCCJ_REF
VT = VDD/2 V using "SLOW" Setting
—
40
70
ps
Phase Jitter
RMSREF
12 kHz to 5 MHz
—
0.35
0.45
ps
REF Noise Floor
TJ1kHz_REF
1 kHz offset
—
–132
–124
dBc/Hz
REF Noise Floor
TJ10kHz_REF
10 kHz offset to Nyquist
—
–145
–138
dBc/Hz
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Data Sheet
Electrical Specifications
Parameter
Symbol
Condition
Min
Typ
Max
Unit
LVCMOS – REF (VDD = 1.8 V ±5%)
Long Accuracy
Clock Period
ppm
Variation from reference
frequency
TPERIOD
25 MHz output
—
40
—
ns
Trf
Byte 2[1:0] = 48 (Slowest), 20% to
80% of VDDREF
—
0.7
1.3
V/ns
Byte 2[1:0] = 49 (Slow), 20% to
80% of VDDREF
—
1.0
1.6
V/ns
Byte 2[1:0] = 4A (Fast), 20% to
80% of VDDREF
—
1.1
1.9
V/ns
Byte 2[1:0] = 4B (Fastest), 20% to
80% of VDDREF
—
1.2
2.0
V/ns
Slew Rate
0
ppm
Duty Cycle1
TDC_REF
VT = VDD/2 V
45
50
55
%
Cycle-to-Cycle Jitter
TCCJ_REF
VT = VDD/2 V using "SLOW" Setting
—
30
50
ps
Phase Jitter
RMSREF
12 kHz to 5 MHz
—
0.3
0.4
ps
REF Noise Floor
TJ1kHz_REF
1 kHz offset
—
–132
–124
dBc
REF Noise Floor
TJ10kHz_REF
10 kHz offset to Nyquist
—
–145
–139
dBc
TDC
Measured at 0 V differential
45
50
55
%
TSKEW
Measured at 0 V differential
—
10
50
ps
Measured differentially from
±150 mV (fast setting)
—
2.4
3.7
V/ns
Measured differentially from
±150 mV (slow setting)
—
1.9
2.9
V/ns
—
2
10
%
—
—
1250
ppm/usec
DIFF HCSL
Duty Cycle
Output-to-Output Skew
Slew Rate
TR/TF
Slew Rate Matching
Delta TR/TF
Max modulation frequency
df/dt
Tmax-freqmodslew
Voltage High
VHIGH
600
—
850
mV
Voltage Low
VLOW
–150
—
150
mV
Max Voltage
VMAX
—
750
1150
mV
Min Voltage
VMIN
–300
0
—
mV
Crossing Point Voltage
VOX
Absolute crossing point voltage at
0.7 V Swing
250
—
550
mV
VOX_DELTA
Variation of VOX over all rising
clock edges
—
35
70
mV
30
31.5
33
kHz
—
1
5
ms
Crossing Point Voltage (var)
Modulation Frequency
FMOD
Enable/Disable and Setup
Clock Stabilization from
Power-up
TSTABLE
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Rev. 1.0 | 15
Data Sheet
Electrical Specifications
Parameter
Symbol
Condition
Min
Typ
Max
Unit
OE_b Latency
TOEBLAT
Differential outputs start after
OE_b assertion Differential outputs stop after OE_b deassertion
—
2
3.5
clocks
PWRDNb Latency to differential outputs enable
TPWRDNb
Differential outputs enable after
PD_b de-assertion
—
490
520
µs
Note:
1. This is for XTAL mode only. For CLKIN mode, there would be a duty cycle distortion spec of ±0.5 ns.
Table 4.4. PCIe and Intel QPI Jitter Specifications
Parameter
Jitter
Limit
Symbol
Condition
Min
Typ
Max
Unit
Cycle to Cycle Jitter
JCCJ
Measured at 0 V differential
—
16
23
PCIe Gen 1 Pk-Pk Jitter
JPk-Pk
PCIe Gen 1
0
25
33
86
ps
(pk-pk)
10 kHz < F < 1.5 MHz
0
0.18
0.24
3
ps
(RMS)
1.5 MHz < F < Nyquist
0
1.4
1.7
3.1
ps
(RMS)
DIFF HCSL
PCIe Gen 2 Phase Jitter
ps
(pk-pk)
JRMSGEN2
PCIe Gen 3 Phase Jitter
JRMSGEN3
Includes PLL BW 2–4 MHz,
CDR = 10 MHz
—
0.3
0.38
1.0
ps
(RMS)
PCIe Gen 3 SRIS1
Phase Jitter
JRMSGen3_SRIS
Includes PLL BW 2–4 MHz,
CDR = 10 MHz
—
0.37
0.44
0.7
ps
(RMS)
PCIe Gen 4 Phase Jitter
JRMSGen4
Includes PLL BW 2–4 MHz,
CDR = 10 MHz
—
0.3
0.38
0.5
ps
(RMS)
PCIe Gen 4 SRIS1
Phase Jitter
JRMSGen4_SRIS
Includes PLL BW 2–4 MHz,
CDR = 10 MHz
—
0.38
0.45
0.5
ps
(RMS)
PCIe Gen 5 5
Phase Jitter
JRMSGen5
Includes PLL BW 500 kHz–1.8 MHz,
CDR = 20 MHz
—
0.11
0.135
0.15
ps
(RMS)
PCIe Gen 5 SRIS1
Phase Jitter
JRMSGen5_SRIS
Includes PLL BW 500 kHz–1.8 MHz,
CDR = 20 MHz
—
0.11
0.13
0.18
ps
(RMS)
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Data Sheet
Electrical Specifications
Parameter
Symbol
Condition
Min
Typ
Max
Jitter
Limit
Unit
100 kHz
—
–63.4
—
—
dBc
200 kHz
—
–61.5
—
—
dBc
300 kHz
—
–59.1
—
—
dBc
500 kHz
—
–54.5
—
—
dBc
1 MHz
—
–50.4
—
—
dBc
100 kHz
—
–65.9
—
—
dBc
200 kHz
—
–63.9
—
—
dBc
300 kHz
—
–60.3
—
—
dBc
500 kHz
—
–53.5
—
—
dBc
1 MHz
—
–46.0
—
—
dBc
PSNR2
PSNR1.8V
Spurs Induced by External
Power Supply Noise on
VDDA, 100 mVpp Ripple
PSNR1.5V
Intel QPI Specifications for 100 MHz and 133 MHz
Intel QPI and SMI REFCLK
accummulated jitter3, 4
JRMSQPI_SMI
8 Gb/s, 100 MHz, 12UI
—
0.13
0.22
0.3
ps
(RMS)
Intel QPI and SMI REFCLK
accummulated jitter3, 4
JRMSQPI_SMI
9.6 Gb/s, 100 MHz, 12UI
—
0.11
0.19
0.2
ps
(RMS)
Intel QPI & SMI REFCLK
accummulated jitter3, 6
JRMSQPI_SMI
6.4 Gb/s, 100/133 MHz, 12UI, 7.8M
—
0.15
0.35
0.5
ps
(RMS)
Note:
1. The SRIS jitter limit is the system RefClk simulation budget divided by sqrt (2) for equal allocation of uncorrelated jitter between
two clocks.
2. For PSNR testing methodology, please see "AN491: Power Supply Rejection for Low-Jitter Clocks".
3. Post processed evaluation through Intel supplied Matlab scripts.
4. Measuring on 100 MHz output using the template file in the PCIe Jitter Tool.
5. Based on PCI Express® Base Specifications Revision 5.0 Version 0.7.
6. Measuring on 100 MHz, 133 MHz outputs using the template file in the PCIe Jitter Tool. Visit www.pcisig.com for complete PCIe
specifications.
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Data Sheet
Electrical Specifications
Table 4.5. Thermal Conditions
Parameter
Symbol
Test Condition
Value
Still Air
60
Air Flow 1 m/s
56
Air Flow 2 m/s
54.4
Units
Si52202 - 20-QFN
Thermal Resistance, Junction to Ambient1
θJA
°C/W
Thermal Resistance, Junction to Case1
θJC
10.8
°C/W
Thermal Resistance, Junction to Board1
θJB
34.1
°C/W
Thermal Resistance, Junction to Top Center1
ΨJT
3.1
°C/W
Thermal Resistance, Junction to Board1
ΨJB
33.9
°C/W
Si52204 - 32-QFN
Thermal Resistance, Junction to Ambient2
θJA
Still Air
50.3
Air Flow 1 m/s
47
Air Flow 2 m/s
45.6
°C/W
Thermal Resistance, Junction to Case2
θJC
10.3
°C/W
Thermal Resistance, Junction to Board2
θJB
30.9
°C/W
Thermal Resistance, Junction to Top Center2
ΨJT
2.3
°C/W
Thermal Resistance, Junction to Board2
ΨJB
30.9
°C/W
Si52208 - 48-QFN
Thermal Resistance, Junction to Ambient3
θJA
Still Air
27.9
Air Flow 1 m/s
24.5
Air Flow 2 m/s
23.5
°C/W
Thermal Resistance, Junction to Case3
θJC
17
°C/W
Thermal Resistance, Junction to Board3
θJB
13.4
°C/W
Thermal Resistance, Junction to Top Center3
ΨJT
0.5
°C/W
Thermal Resistance, Junction to Board3
ΨJB
13.1
°C/W
Si52212 - 64-QFN
Thermal Resistance, Junction to Ambient4
θJA
Still Air
27.2
Air Flow 1 m/s
23.9
Air Flow 2 m/s
22.5
°C/W
Thermal Resistance, Junction to Case4
θJC
13.7
°C/W
Thermal Resistance, Junction to Board4
θJB
14.4
°C/W
Thermal Resistance, Junction to Top Center4
ΨJT
0.5
°C/W
Thermal Resistance, Junction to Board4
ΨJB
14.2
°C/W
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Rev. 1.0 | 18
Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Value
Units
Note:
1. Based on a 4 layer, PCB with Dimension 3"x4.5". PCB Thickness of 1.6mm. PCB Center Land with 4 Via to top plane.
2. Based on PCB with dimension 3" x 4.5", PCB Thickness of 1.6 mm. PCB Center Land with 4 Via to top plane.
3. Based on 4 layer PCB with dimension 3" x 4.5", PCB Thickness of 1.6 mm. PCB Center Land with 9 Via to top plane.
4. Based on 4 Layer PCB with dimension 3" x 4.5", PCB Thickness of 1.6 mm. PCB Center Land with 25 Via to top plane.
Table 4.6. Absolute Maximum Conditions
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
VDD_1.8V
Functional
—
—
2.5
V
VIN
Relative to VSS
–0.5
—
VDD + 0.5
V
Input High Voltage I2C
VIH_I2C
SDATA and SCLK
—
3.6
V
Temperature, Storage
TS
Non-functional
–65
—
150
Celsius
Temperature, Operating Ambient
TA
Functional
–40
—
85
Celsius
Temperature, Junction
TJ
Functional
—
—
125
Celsius
ESD Protection
(Human Body Model)
ESDHBM
JEDEC
(JESD 22-A114)
–2000
—
2000
V
UL-94
UL (Class)
Main Supply Voltage
Input Voltage
Flammability Rating
V–0
Note: While using multiple power supplies, the voltage on any input or I/O pin cannot exceed the power pin during power-up. Power
supply sequencing is not required.
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Data Sheet
Functional Description
5. Functional Description
5.1 Crystal Recommendations
The clock device requires a parallel resonance crystal.
Table 5.1. Crystal Recommendations
Frequency
(Fund)
Cut
Loading
Load Cap
Shunt Cap
(max)
Motional
(max)
Tolerance
(max)
Stability
(max)
Aging (max)
25 MHz
AT
Parallel
8–15 pF
5 pF
0.016 pF
35 ppm
30 ppm
5 ppm
5.2 Crystal Loading
Crystal loading is critical in achieving low ppm performance. To realize low ppm performance, use the total capacitance the crystal sees
to calculate the appropriate capacitive loading (CL).
The figure below shows a typical crystal configuration using the two trim capacitors. It is important that the trim capacitors are in series
with the crystal.
Figure 5.1. Crystal Capacitive Clarification
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Data Sheet
Functional Description
5.3 Calculating Load Capacitors
In addition to the standard external trim capacitors, consider the trace capacitance and pin capacitance to calculate the crystal loading
correctly. The total capacitance on both sides is twice the specified crystal load capacitance (CL). Trim capacitors are calculated to
provide equal capacitive loading on both sides.
Clock Chip
Ci2
Ci1
Cs1
X1
Pin
3 to 6 pF
X2
Cs2
Trace
2.8 pF
XTAL
Ce1
Ce2
Trim
7-24 pF
Figure 5.2. Crystal Loading Example
Use the following formulas to calculate the trim capacitor values for Ce1 and Ce2:
Load Capacitance (each side)
Ce = 2 × CL − (Cs + Ci)
Total Capacitance (as seen by the crystal)
CLe =
•
•
•
•
•
(
1
1
1
+
Ce + Cs1 + Ci1 Ce2 + Cs2 + Ci2
)
CL: Crystal load capacitance
CLe: Actual loading seen by crystal using standard value trim capacitors
Ce: External trim capacitors
Cs: Stray capacitance (terraced)
Ci : Internal capacitance (lead frame, bond wires, etc.)
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Data Sheet
Functional Description
5.4 Power Supply Filtering Recommendations
Placed near
the part
Si52202/04/08/12
VDD
FB1
VDD_CORE
( 1.5V or 1.8V)
0.1uF
VDD
1uF
0.1uF
FB2
VDDA
FB3
1uF
FB4
1uF
VDD_IO
(1V to VDD_CORE) FB5
For parts that have
multiple VDD pins, use
one 0.1uF capacitor
per pin.
1uF
0.1uF
VDDX
0.1uF
VDDR
0.1uF
VDD_IO
0.1uF
VDD_IO
1uF
For parts that have
multiple VDD_IO pins,
use one 0.1uF
capacitor per pin.
0.1uF
Recommended ferrite bead specs:
600 Ω at 100 MHz, ≤ 0.1 Ω DCR max., ≥40mA current rating
Figure 5.3. Power Supply Filtering
Separate out each type of VDD (VDD, VDDA, VDDX, VDDR, and VDD_IO) using ferrite beads. Then, for each VDD type use one 1 µF
bulk capacitor along with an additional 0.1 µF capacitor for each individual VDD pin. All VDD Core (VDD, VDDA, VDDX, and VDDR)
pins should be tied to the same voltage, either 1.8 V or 1.5 V. The VDD_IO pins can be tied to a voltage between 1 V and the selected
VDD Core voltage. Note, the VDD_IO pins must all be tied to the same voltage.
5.5 PWRGD/PWRDNb (Power Down) Pin
The PWRGD/PWRDNb pin is a dual-function pin. During initial power up, the pin functions as the PWRGD pin. Upon the first power up,
if the PWRGD pin is low, all outputs, the crystal oscillator, and the I2C logics will be disabled. Once the PWRGD pin has been sampled
high by the clock chip, the pin assumes a PWRDNb functionality. When the pin has assumed a PWRDNb functionality and is pulled
low, the device will be placed in power down mode. The assertion and dessertion of PWRDNb is asynchronous. This pin has a 100 kΩ
internal pull-up.
Figure 5.4. Initial Sample High of PWRGD/PWRDNb After Power Up
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Data Sheet
Functional Description
5.6 PWRDNb (Power Down) Assertion
The PWRDNb pin is an asynchronous active low input used to disable all output clocks in a glitch-free manner. In power down mode, all
outputs, the crystal oscillator, and the I2C logic are disabled. In cases where the REF PWRDN (Byte 2, bit 2) is set to 1, the crystal
oscillator and REF output will still be enabled. All disabled outputs will be driven low.
Figure 5.5. PWRDNb Assertion
5.7 PWRDNb (Power Down) Deassertion
When a valid rising edge on PWRGD/PWRDNb pin is applied, all outputs are enabled in a glitch-free manner within 520 µs.
Figure 5.6. Subsequent Deassertion of PWRDNb
5.8 OEb Pin
The OEb pin is an active low input used to enable and disable the output clock. To enable the output clock, the OEb pin needs to be
logic low, and I2C OE bit needs to be logic high. By default, the OEb pin is set to logic low, and I2C OE bit is set to logic high.There are
two methods to disable the output clock: the OEb pin is pulled to a logic high, or the I2C OE bit is set to a logic low. This pin has a 100
kΩ internal pull-down.
5.9 OEb Assertion
The OEb pin is an active low input used for synchronous stopping and starting the respective output clock while the rest of the clock
generator continues to function. The assertion of the OEb function is achieved by pulling the OEb pin low while the I2C OE bit is high,
which causes the respective stopped output to resume normal operation. No short or stretched clock pulses are produced when the
clocks resume.
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Data Sheet
Functional Description
5.10 OEb Deassertion
The OEb function is deasserted by pulling high or writing the I2C OE bit to a logic low. The corresponding output is stopped cleanly and
the final output state is driven low.
5.11 FS Pin
The FS pin will select 0 = 100 MHz, mid = 200 MHz, and 1 = 133 MHz. This is a tri-state pin, which has a weak internal pull-down of
approximately 100 kΩ.
The default output frequency is 100 MHz.
5.12 SS_EN Pin
The SS_EN pin will select 0 = –0.25% spread, mid = Spread is off, and 1 = –0.5% spread. This is a tri-state pin, which has a weak
internal pull-up of approximately 100 kΩ.
The default is –0.5% spread.
5.13 Recommendations for Driving Tri-State Pins
VDD
R1
VDD
1 KΩ
1 KΩ
Si522xx
Tri-State Pin
(FS/SS_EN)
R2
1 KΩ
Static Option
User can remove either R1, R2, or
neither to constantly maintain low,
high, or mid levels respectively
Si522xx
Tri-State Pin
(FS/SS_EN)
MCU
With Tri-State Outputs
(0, High Z and VDD)
MCU
With Tri-State Outputs
(0, VDD/2 and VDD)
Si522xx
Tri-State Pin
(FS/SS_EN)
1 KΩ
Tri-State Dynamic Option
User can use a MCU with strong Tri-State
outputs to drive the Tri-State input pin. 1 KΩ
resistors should be adequate for most MCU
drivers.
3-Level Dynamic Option
A MCU with 3-level output capability
can be directly connected to the TriState input pin to drive it either low,
high, or mid level.
Figure 5.7. Tri-State Pin Schematics
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Data Sheet
Functional Description
5.14 REF/SA Pin
Figure 5.8. REF/SA Pin Function
The REF/SA pin is a dual-function input/output pin.
The SA functionality sets the Slave Address of the part. This address is latched to the value of the pin when the part initially powers up.
See Table 8.1 SA State on First Application of PWRGD/PWRDNb on page 32 for the available addresses. By default, the internal 60
kΩ pull-up resistor will set SA to a value of 1. To drive the pin low, use a 10 kΩ pull-down resistor.
After the I2C address is latched on first power up, the REF/SA pin assumes its REF functionality. In REF mode, it will output a 25 MHz
LVCMOS signal.
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Rev. 1.0 | 25
Data Sheet
Test and Measurement Setup
6. Test and Measurement Setup
The following diagrams show the test load configuration for the differential clock signals.
Measurement
Point
L1
OUT+
50
2 pF
L1 = 5"
Measurement
Point
L1
OUT-
50
2 pF
Figure 6.1. 0.7 V Differential Load Configuration
Clock Period (Differential)
Positive Duty Cycle (Differential)
Negative Duty Cycle (Differential)
0.0 V
0.0 V
Clock-Clock#
Rise Edge
Rate
Fall Edge
Rate
VIH = +150 mV
VIH = +150 mV
0.0 V
VIL = -150 mV
0.0 V
VIL = -150 mV
Clock-Clock#
Figure 6.2. Differential Output Signals (for AC Parameters Measurement)
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Rev. 1.0 | 26
Data Sheet
Test and Measurement Setup
VMAX
VMAX
VcrossMAX
VcrossMAX
VcrossMIN
VcrossMIN
VMIN
VMIN
CLK#
Vcross delta
Vcross delta
CLK
Figure 6.3. Single-Ended Measurement for Differential Output Signals (for AC Parameters Measurement)
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Rev. 1.0 | 27
Data Sheet
PCIe Clock Jitter Tool
7. PCIe Clock Jitter Tool
The PCIe Clock Jitter Tool is designed to enable users to quickly and easily take jitter measurements for PCIe Gen1/2/3/4/5 and SRNS/
SRIS. This software removes all the guesswork for PCIe Gen1/2/3/4/5 and SRNS/SRIS jitter measurements and margins in board designs. This software tool will provide accurate results in just a few clicks, and is provided in an executable format to support various
common input waveform files, such as .csv, .wfm, and .bin. The easy-to-use GUI and helpful tips guide users through each step. Release notes and other documentation are also included in the software package.
Download it for free at http://www.silabs.com/pcie-learningcenter.
Figure 7.1. PCIe Clock Jitter Tool
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Rev. 1.0 | 28
Data Sheet
Control Registers
8. Control Registers
8.1 I2C Interface
To enhance the flexibility and function of the clock synthesizer, an I2C interface is provided. Through the I2C interface, various device
functions, such as individual clock output buffers, are individually enabled or disabled. The registers associated with the I2C interface
initialize to their default setting at power-up. The use of this interface is optional. Clock device register changes are normally made at
system initialization, if any are required.
8.2 Block Read/Write
The clock driver I2C protocol accepts block write and block read operations from the controller. For block write/read operation, access
the bytes in sequential order from lowest to highest (most significant bit first) with the ability to stop after any complete byte is transferred. The block write and block read protocol is outlined in Table 8.2 Block Read and Block Write Protocol on page 32.
8.3 Block Read
After the slave address is sent with the R/W condition bit set, the command byte is sent with the MSB = 0. The slave acknowledges the
register index in the command byte. The master sends a repeat start function. After the slave acknowledges this, the slave sends the
number of bytes it wants to transfer (>0 and
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