SI53323-B-GM

Si53320-28 Data Sheet Low-Jitter LVPECL Fanout Clock Buffers with up to 10 LVPECL Outputs from Any-Format Input and Wide Frequency Range from DC up to 1250 MHz The Si53320–28 family of LVPECL fanout buffers is ideal for clock/data distribution and redundant clocking applications. These devices feature typical ultra-low jitter characteristics of 50 fs and operate over a wide frequency range from dc to 725/1250 MHz. Built-in LDOs deliver high PSRR performance and reduce the need for external components, simplifying low-jitter clock distribution in noisy environments. The Si53320–28 family is available in multiple configurations, with some versions offering a selectable input clock using a 2:1 input mux. Other features include independent output enable and built-in format translation. These buffers can be paired with the Si534x clocks and Si5xx oscillators to deliver end-to-end clock tree performance. KEY FEATURES • Ultra-low additive jitter: 50 fs rms • Built-in LDOs for high PSRR performance • Up to 10 LVPECL Outputs • Any-format Inputs (LVPECL, Low-power LVPECL, LVDS, CML, HCSL, LVCMOS) • Wide frequency range: dc to 1250 MHz • Output Enable option • Multiple configuration options • Dual Bank option • 2:1 Input Mux operation • RoHS compliant, Pb-free • Temperature range: –40 to +85 °C VDD VDD Power Supply Filtering 4 4 Outputs OEb 5 CLK0* 5 Outputs Power Supply Filtering Si53323 Si53320 2 CLK 2 Outputs Si53322 0 VDDOA CLK1* OEAb 1 CLK_SEL 3 3 Outputs 3 3 Outputs VDD Si53327/28 Power Supply Filtering OEBb VDDOB CLK0 5 5 Outputs Si53325 10 10 Outputs Si53321/26 CLK1 5 5 Outputs *Si53326/28 require Single-ended Inputs 1 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • December 3, 2021 1 Si53320-28 Data Sheet • Ordering Guide 1. Ordering Guide Table 1.1. Si5332x Ordering Guide 2 Part Number Input LVPECL Output Output Enable Frequency Range Package Si53320-B-GT 2:1 selectable MUX Any-format 1 bank / 5 Outputs Single dc to 725 MHz 20-TSSOP Si53321-B-GM 2:1 selectable MUX Any-format 1 bank / 10 Outputs — dc to 1250 MHz 32-QFN 5 x 5 mm Si53321-B-GQ 2:1 selectable MUX Any-format 1 bank / 10 Outputs — dc to 1250 MHz 32-eLQFP 7 x 7 mm Si53322-B-GM 1 bank / 1 Input Any-format 1 bank / 2 Outputs — dc to 1250 MHz 16-QFN 3 x 3 mm Si53323-B-GM 2:1 selectable MUX Any-format 1 bank / 4 Outputs — dc to 1250 MHz 16-QFN 3 x 3 mm Si53325-B-GM 2 banks / 2 Inputs Any-format 2 banks / 5 Outputs — dc to 1250 MHz 32-QFN 5 x 5 mm Si53325-B-GQ 2 banks / 2 Inputs Any-format 2 banks / 5 Outputs — dc to 1250 MHz 32-eLQFP 7 x 7 mm Si53326-B-GM 2:1 selectable MUX LVCMOS 1 bank / 10 Outputs — dc to 200 MHz 32-QFN 5 x 5 mm Si53327-B-GM 2:1 selectable MUX Any-format 2 banks / 3 Outputs 1 per bank dc to 1250 MHz 24-QFN 4 x 4 mm Si53328-B-GM 2:1 selectable MUX LVCMOS 2 banks / 3 Outputs 1 per bank dc to 200 MHz 24-QFN 4 x 4 mm Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • December 3, 2021 2 Si53320-28 Data Sheet • Functional Description 2. Functional Description The Si53320-28 are a family of low-jitter, low-skew, fixed-format (LVPECL) buffers. All devices except the Si53326 and Si53328 have a universal input that accepts most common differential or LVCMOS input signals. The Si53326 and Si53328 accept only single-ended LVCMOS inputs. These devices are available in multiple configurations customized for the end application (refer to 1. Ordering Guide for more details on configurations). 2.1 Universal, Any-Format Input Termination (Si53320/21/22/23/25/27) The universal input stage enables simple interfacing to a wide variety of clock formats, including LVPECL, low-power LVPECL, LVCMOS, LVDS, HCSL, and CML. The tables below summarize the various ac- and dc-coupling options supported by the device. For the best high-speed performance, the use of differential formats is recommended. For both single-ended and differential input clocks, the fastest possible slew rate is recommended since low slew rates can increase the noise floor and degrade jitter performance. Though not required, a minimum slew rate of 0.75 V/ns is recommended for differential formats and 1.0 V/ns for single-ended formats. See “AN766: Understanding and Optimizing Clock Buffer’s Additive Jitter Performance” for more information. Table 2.1. Clock Input Options Clock Format 1.8 V 2.5/3.3 V LVPECL/Low-power LVPECL N/A Yes LVCMOS No Yes LVDS Yes Yes HCSL No Yes (3.3 V) CML Yes Yes LVPECL/Low-power LVPECL N/A Yes LVCMOS No Yes LVDS No Yes HCSL No Yes (3.3 V) CML No No AC-Coupled DC-Coupled 3 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • December 3, 2021 3 Si53320-28 Data Sheet • Functional Description VDD 0.1 µF CLKx 100 Ω Si53320/21/22/23/25/27 CLKxb 0.1 µF Figure 2.1. Differential (HCSL, LVPECL, Low-Power LVPECL, LVDS, CML) AC-Coupled Input Termination VDD DC-Coupled 1 kΩ VDD = 3.3 V or 2.5 V CMOS Driver VDD Si53320/21/22/23/25/27 CLKx 50 CLKxb Rs VTERM = VDD/2 1 kΩ VDD VDD AC-Coupled 1 kΩ VBIAS = VDD/2 VDD = 3.3 V or 2.5 V CMOS Driver 1 kΩ VDD Si53320/21/22/23/25/27 CLKx 50 CLKxb Rs 1 kΩ Note: Value for Rs should be chosen so that the total source impedance matches the characteristic impedance of the PCB trace. 1 kΩ VTERM = VDD/2 Figure 2.2. Single-Ended (LVCMOS) Input Termination 4 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • December 3, 2021 4 Si53320-28 Data Sheet • Functional Description VDD DC Coupled LVPECL Input Termination Scheme 1 R1 VDD R1 VDD = 3.3 V or 2.5 V Si53320/21/22/23/25/27 50 Ω “Standard” LVPECL Driver CLKx CLKxb 50 Ω R2 VTERM = VDD – 2V R1 // R2 = 50 Ohm R2 3.3 V LVPECL: R1 = 127 Ohm, R2 = 82.5 Ohm 2.5 V LVPECL: R1 = 250 Ohm, R2 = 62.5 Ohm DC Coupled LVPECL Input Termination Scheme 2 VDD VDD = 3.3 V or 2.5 V Si53320/21/22/23/25/27 50 Ω “Standard” LVPECL Driver CLKx CLKxb 50 Ω 50 Ω 50 Ω VTERM = VDD – 2 V DC Coupled LVDS Input Termination VDD VDD = 3.3 V or 2.5 V Si53320/21/22/23/25/27 50 Ω Standard LVDS Driver CLKx 100 Ω CLKxb 50 Ω DC Coupled HCSL Input Termination Scheme VDD = 3.3 V Standard HCSL Driver Si53320/21/22/23/25/27 33 Ω 50 Ω 33 Ω 50 Ω VDD 50 Ω CLKx CLKxb 50 Ω Note: 33 Ohm series termination is optional depending on the location of the receiver. Figure 2.3. Differential DC-Coupled Input Terminations (Si53320/21/22/23/25/27) 5 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • December 3, 2021 5 Si53320-28 Data Sheet • Functional Description 2.3 Input Bias Resistors Internal bias resistors ensure a differential output low condition in the event that the clock inputs are not connected. The non-inverting input is biased with a 18.75 kΩ pull-down to GND and a 75 kΩ pull-up to VDD. The inverting input is biased with a 75 kΩ pull-up to VDD. VDD RPU CLK0 or CLK1 RPU + RPD – RPU = 75 kΩ RPD = 18.75 kΩ Figure 2.4. Input Bias Resistors Note: To minimize the possibility of system noise coupling into the Si5332x differential inputs and adversely affecting the buffered output, Skyworks recommends 1 PPS clocks and disabled/gapped clocks be dc-coupled and driven “stop-low”. 2.4 Input Mux The Si53320/21/23/26/27/28 provide two clock inputs for applications that need to select between one of two clock sources. The CLK_SEL pin selects the active clock input. The following table summarizes the input and output clock based on the input mux and output enable pin settings. Table 2.2. Input Mux Logic CLK_SEL CLK0 CLK1 Q1 Qb L L X L H L H X H L H X L L H H X H H L Note: 1. On the next negative transition of CLK0 or CLK1. 6 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • December 3, 2021 6 Si53320-28 Data Sheet • Functional Description 2.5 Output Clock Termination Options The recommended output clock termination options for dc and ac are shown below. Unused outputs should be left unconnected. DC Coupled LVPECL Output Termination Scheme 1 VDDO R1 R1 VDDXX Si5332x VDD = VDDO Q 50 LVPECL Receiver Qb 50 R2 VTERM = VDDO – 2 V R1 // R2 = 50 Ohm R2 3.3 V LVPECL: R1 = 127 Ohm; R2 = 82.5 Ohm 2.5 V LVPECL: R1 = 250 Ohm; R2 = 62.5 Ohm DC Coupled LVPECL Output Termination Scheme 2 VDDXX Si5332x VDD = VDDO Q 50 LVPECL Receiver Qb 50 50 50 VTERM = VDDO – 2 V Note: For Si53320/21/22/23/25/26, VDDXX = VDD = 3.3 V, 2.5 V For Si53327/28, VDDXX = VDDOA or VDDOB = 3.3 V, 2.5 V Figure 2.5. LVPECL DC Output Terminations 7 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • December 3, 2021 7 Si53320-28 Data Sheet • Functional Description AC Coupled LVPECL Output Termination Scheme 1 VDDO R1 VDDXX Si5332x R1 0.1 uF VDD = 3.3 V or 2.5 V 50 Q LVPECL Receiver Qb 50 0.1 uF Rb R2 Rb VBIAS = VDD – 1.3 V R1 // R2 = 50 Ohm R2 3.3 V LVPECL: R1 = 82.5 Ohm; R2 = 127 Ohm; Rb = 120 Ohm 2.5 V LVPECL: R1 = 62.5 Ohm; R2 = 250 Ohm; Rb = 90 Ohm AC Coupled LVPECL Output Termination Scheme 2 VDDXX Si5332x 0.1 uF VDD = 3.3 V or 2.5 V 50 Q LVPECL Receiver Qb 50 0.1 uF Rb Rb 50 50 VBIAS = VDD – 1.3 V 3.3 V LVPECL: Rb = 120 Ohm 2.5 V LVPECL: Rb = 90 Ohm Note: For Si53320/21/22/23/25/26, VDDXX = VDD = 3.3 V, 2.5 V For Si53327/28, VDDXX = VDDOA or VDDOB = 3.3 V, 2.5 V Figure 2.6. LVPECL AC Output Terminations 8 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • December 3, 2021 8 Si53320-28 Data Sheet • Functional Description 2.6 AC Timing Waveforms TPHL CLK TSK QN VPP/2 Q VPP/2 QM VPP/2 VPP/2 TPLH TSK Propagation Delay Output-Output Skew TF Q 80% VPP 20% VPP 80% VPP Q 20% VPP TR Rise/Fall Time Figure 2.7. AC Timing Waveforms 9 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • December 3, 2021 9 Si53320-28 Data Sheet • Functional Description 2.7 Typical Phase Noise Performance: Differential Input Clock Each of the phase noise plots superimposes Source Jitter, Total SE Jitter, and Total Diff Jitter on the same diagram. • Source Jitter—Reference clock phase noise (measured Single-ended to PNA). • Total Jitter (SE)—Combined source and clock buffer phase noise measured as a single-ended output to the phase noise analyzer and integrated from 12 kHz to 20 MHz. • Total Jitter (Diff)—Combined source and clock buffer phase noise measured as a differential output to the phase noise analyzer and integrated from 12 kHz to 20 MHz. The differential measurement as shown in each figure is made using a balun. For more information, see 3. Electrical Specifications. Note: To calculate the total RMS phase jitter when adding a buffer to your clock tree, use the root-sum-square (RSS). Total jitter (Single-Ended) measured here PSPL 5310A CLKx CLK SYNTH SMA103A Si5332x DUT Balun AG E5052 Phase Noise Analyzer PSPL 5310A 50 50 Ohm CLKxb 50 Balun Source jitter measured here Total jitter (Differential) measured here Figure 2.8. Differential Measurement Method Using a Balun The total jitter is a measure of the source plus the buffer's additive phase jitter. The additive jitter (rms) of the buffer can then be calculated (via root-sum-square addition). Frequency (MHz) Differential Input Slew Rate (V/ns) Source Jitter (fs) Total Jitter (SE) (fs) Additive Jitter (SE) (fs) Total Jitter (Differential) (fs) Additive Jitter (Differential) (fs) 156.25 1.0 38.2 147.8 142.8 118.3 112.0 Figure 2.9. Total Jitter Differential Input (156.25 MHz) 10 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • December 3, 2021 10 Si53320-28 Data Sheet • Functional Description Frequency (MHz) Differential Input Slew Rate (V/ns) Source Jitter (fs) Total Jitter (SE) (fs) Additive Jitter (SE) (fs) Total Jitter (Differential) (fs) Additive Jitter (Differential) (fs) 312.5 1.0 33.10 94.39 88.39 83.80 76.99 Figure 2.10. Total Jitter Differential Input (312.5 MHz) Frequency (MHz) Differential Input Slew Rate (V/ns) Source Jitter (fs) Total Jitter (SE) (fs) Additive Jitter (SE) (fs) Total Jitter (Differential) (fs) Additive Jitter (Differential) (fs) 625 1.0 23 57 52 59 54 Figure 2.11. Total Jitter Differential Input (625 MHz) 11 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • December 3, 2021 11 Si53320-28 Data Sheet • Functional Description 2.8 Typical Phase Noise Performance: Single-Ended Input Clock For single-ended input phase noise measurements, the input was connected directly without the use of a balun. The following figure shows three phase noise plots superimposed on the same diagram. Frequency (MHz) Single-Ended Input Slew Rate (V/ns) Source Jitter (fs) Total Jitter (SE) (fs) Additive Jitter (SE) (fs) Total Jitter (Differential) (fs) Additive Jitter (Differential) (fs) 156.25 1.0 40.74 182.12 177.51 125.22 118.41 Figure 2.12. Total Jitter Single-Ended Input (156.25 MHz) 12 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • December 3, 2021 12 Si53320-28 Data Sheet • Functional Description 2.9 Input Mux Noise Isolation The input clock mux is designed to minimize crosstalk between the CLK0 and CLK1. This improves phase jitter performance when clocks are present at both the CLK0 and CLK1 inputs. The following figure shows a measurement of the input mux’s noise isolation. Figure 2.13. Input Mux Noise Isolation (Differential Input Clock, 44-QFN Package) Figure 2.14. Input Mux Noise Isolation (Single-Ended Input Clock, 24-QFN Package) 13 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • December 3, 2021 13 Si53320-28 Data Sheet • Functional Description 2.10 Power Supply Noise Rejection The device supports on-chip supply voltage regulation to reject power supply noise and simplify low-jitter operation in real-world environments. This feature enables robust operation alongside FPGAs, ASICs and SoCs and may reduce board-level filtering requirements. See “AN491: Power Supply Rejection for Low-Jitter Clocks” for more information. 14 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • December 3, 2021 14 Si53320-28 Data Sheet • Electrical Specifications 3. Electrical Specifications Table 3.1. Recommended Operating Conditions Parameter Symbol Ambient Operating Temperature TA Supply Voltage Range VDD Test Condition LVPECL Min Typ Max Unit –40 — 85 °C 2.38 2.5 2.63 V 2.97 3.3 3.63 V Min Typ Max Unit Table 3.2. Input Clock Specifications VDD = 2.5 V ± 5% or 3.3 V ± 10%; TA = –40 to 85 °C Parameter Symbol Test Condition Differential Input Common Mode Voltage VCM 0.05 — — V Differential Input Swing (peak-to-peak) VIN 0.2 — 2.2 V LVCMOS Input High Voltage VIH VDD x 0.7 — — V LVCMOS Input Low Voltage VIL — — VDD x 0.3 V Input Capacitance CIN — 5 — pF Test Condition Min Typ Max Unit Si53320 — 260 — mA Si53321/25/26 — 440 — mA Si53322 — 130 — mA Si53323 — 210 — mA Si53327/28 — 80 — mA CLK0 and CLK1 pins with respect to GND Table 3.3. DC Common Characteristics VDD = 2.5 V ± 5% or 3.3 V ± 10%; TA = –40 to 85 °C Parameter Core Supply Current Symbol IDD1 Output Supply Current (Per Clock Output) IDDOx1 Si53327/28 — 35 — mA Input High Voltage VIH CLK_SEL, OExb VDD x 0.8 — — V Input Low Voltage VIL CLK_SEL, OExb — — VDD x 0.2 V Internal Pull-down Resistor RDOWN CLK_SEL, OExb — 25 — kΩ Note: 1. Measured using ac-coupled termination at VDD/VDDOX = 3.3 V. 15 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • December 3, 2021 15 Si53320-28 Data Sheet • Electrical Specifications Table 3.4. Output Characteristics (LVPECL) VDD = 2.5 V ± 5% or 3.3 V ± 10%; TA = –40 to 85 °C Parameter Symbol Single-Ended Output Swing1 Output Common Mode Voltage Test Condition Min Typ Max Unit VSE 0.55 0.80 1.05 V VCOM VDD – 1.595 — VDD – 1.245 V Note: 1. Unused outputs can be left floating. Do not short unused outputs to ground. Table 3.5. AC Characteristics VDD = 2.5 V ± 5% or 3.3 V ± 10%; TA = –40 to 85 °C Parameter Frequency Duty Cycle (50% input duty cycle) Symbol F DC Min Typ Max Unit Si53326/28 dc — 200 MHz Si53320 dc — 725 MHz Si53321/22/23/25/27 dc — 1250 MHz 20/80% TR/TF