Si5338
I 2 C - P R O G R A M M A B L E A N Y - F R EQ U ENC Y, A N Y - O U T P U T
Q UAD C LOC K G EN ERATOR
Features
Independent output voltage per driver:
1.5, 1.8, 2.5, or 3.3 V
Ethernet switch/router
PCIe Gen1/2/3/4
Broadcast video/audio timing
Processor and FPGA clocking
23
22
21
20
19
18 CLK1A
IN2 2
17 CLK1B
IN3 3
16 VDDO1
GND
GND
Pad
IN4 4
15 VDDO2
IN5 5
Applications
24
IN1 1
IN6 6
Any-frequency clock conversion
MSAN/DSLAM/PON
Fibre Channel, SAN
Telecom line cards
1 GbE and 10 GbE
14 CLK2A
7
8
9
10
11
12
SCL
0.16 to 710 MHz
HCSL: 0.16 to 250 MHz
CMOS: 0.16 to 200 MHz
SSTL/HSTL: 0.16 to 350 MHz
VDDO3
LVPECL/LVDS:
I2C/SMBus compatible interface
Easy to use programming software
Small size: 4 x 4 mm, 24-QFN
Low power: 45 mA core supply typ
Wide temperature range: –40 to
+85 °C
SDA
VDDO0
Independently configurable outputs
support any frequency or format:
Top View
CLK0B
CLK3A
Pin Assignments
External feedback mode allows
zero-delay mode
Loss of lock and loss of signal
alarms
crystal: 8 to 30 MHz
CMOS input: 5 to 200 MHz
SSTL/HSTL input: 5 to 350 MHz
Differential input: 5 to 710 MHz
External
frequency from 5 to 350 MHz
spread from 0.5 to 5.0%
Any modulation rate from 33 to
63 kHz
Any
RSVD_GND
Any
CLK0A
CLK3B
Ordering Information:
See page 42.
VDD
Single supply core with excellent
PSRR: 1.8, 2.5, 3.3 V
Independent frequency
increment/decrement feature
enables glitchless frequency
adjustments in 1 ppm steps
Independent phase adjustment on
each of the output drivers with an
accuracy of
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