Si5341/40 Rev D Data Sheet
Low-Jitter, 10 or 4-Output, Any-Frequency, Any-Output Clock
Generator
KEY FEATURES
• Generates any combination of output
frequencies from any input frequency
The any-frequency, any-output Si5341/40 clock generators combine a wide-band PLL
with proprietary MultiSynth™ fractional synthesizer technology to offer a versatile and
high performance clock generator platform. This highly flexible architecture is capable
of synthesizing a wide range of integer and non-integer related frequencies up to 1
GHz on 10 differential clock outputs while delivering sub-100 fs rms phase jitter performance with 0 ppm error. Each of the clock outputs can be assigned its own format
and output voltage enabling the Si5341/40 to replace multiple clock ICs and oscillators
with a single device making it a true "clock tree on a chip."
• Ultra-low jitter of 90 fs rms
• Input frequency range:
• External crystal: 25 to 54 MHz
• Differential clock: 10 to 750 MHz
• LVCMOS clock: 10 to 250 MHz
• Output frequency range:
• Differential: 100 Hz to 1028 MHz
The Si5341/40 can be quickly and easily configured using ClockBuilderPro software.
Custom part numbers are automatically assigned using a ClockBuilder Pro™ for fast,
free, and easy factory pre-programming or the Si5341/40 can be programmed via I2C
and SPI serial interfaces.
• LVCMOS: 100 Hz to 250 MHz
• Highly configurable outputs compatible with
LVDS, LVPECL, LVCMOS, CML, and HCSL
with programmable signal amplitude
• Si5341: 4 input, 10 output, 64-QFN 9x9 mm
• Si5340: 4 input, 4 output, 44-QFN 7x7 mm
Applications:
• Clock tree generation replacing XOs, buffers, signal format translators
• Any-frequency clock translation
• Clocking for FPGAs, processors, memory
• Ethernet switches/routers
• OTN framers/mappers/processors
• Test equipment and instrumentation
• Broadcast video
25-54 MHz XTAL
XA
4 Input
Clocks
XB
OSC
IN0
IN2
÷INT
PLL
÷INT
Zero Delay
FB_IN
I2C / SPI
1
Status Monitor
Control
NVM
÷INT
OUT0
MultiSynth
÷INT
OUT1
MultiSynth
÷INT
OUT2
MultiSynth
÷INT
OUT3
MultiSynth
÷INT
OUT4
÷INT
OUT5
÷INT
OUT6
÷INT
OUT7
÷INT
OUT8
÷INT
OUT9
Up to 10
Output Clocks
Si5341
Status Flags
÷INT
MultiSynth
Si5340
IN1
÷INT
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • November 30, 2021
1
Si5341/40 Rev D Data Sheet • Features List
1. Features List
The Si5341/40 Rev D features are listed below:
• Generates any combination of output frequencies from any
input frequency
• Ultra-low jitter of 90 fs rms
• Input frequency range:
• External crystal: 25 to 54 MHz
• Differential clock: 10 to 750 MHz
• LVCMOS clock: 10 to 250 MHz
• Output frequency range:
• Differential: 100 Hz to 1028 MHz
• LVCMOS: 100 Hz to 250 MHz
• Highly configurable outputs compatible with LVDS, LVPECL,
LVCMOS, CML, and HCSL with programmable signal amplitude
• Locks to gapped clock inputs
• Optional zero delay mode
• Glitchless on the fly output frequency changes
2
• DCO mode: as low as 0.001 ppb steps
• Core voltage
• VDD: 1.8 V ±5%
• VDDA: 3.3 V ±5%
• Independent output clock supply pins
• 3.3 V, 2.5 V, or 1.8 V
• Serial interface: I2C or SPI
•
•
•
•
•
•
In-circuit programmable with non-volatile OTP memory
ClockBuilder Pro software simplifies device configuration
Si5341: 4 input, 10 output, 64-QFN 9x9 mm
Si5340: 4 input, 4 output, 44-QFN 7x7 mm
Temperature range: –40 to +85 °C
Pb-free, RoHS-6 compliant
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • November 30, 2021
2
Si5341/40 Rev D Data Sheet • Ordering Guide
2. Ordering Guide
Table 2.1. Si5341/40 Ordering Guide
Ordering Part Number
(OPN)
Number of Input/Output
Clocks
Output Clock Frequency
Range (MHz)
Frequency Synthesis Mode
0.0001 to 1028 MHz
Integer and
0.0001 to 350 MHz
Fractional
Package
Temperature
Range
Si5341
Si5341A-D-GM1, 2
Si5341B-D-GM1, 2
Si5341C-D-GM1, 2
4/10
Si5341D-D-GM1, 2
0.0001 to 1028 MHz
0.0001 to 350 MHz
64-QFN
9x9 mm
–40 to 85 °C
Integer Only
Si5340
Si5340A-D-GM1, 2
Si5340B-D-GM1, 2
Si5340C-D-GM1, 2
4/4
Si5340D-D-GM1, 2
0.0001 to 1028 MHz
Integer and
0.0001 to 350 MHz
Fractional
0.0001 to 1028 MHz
0.0001 to 350 MHz
44-QFN
7x7 mm
–40 to 85 °C
Integer Only
Si5341/40-D-EVB
Si5341-D-EVB
Si5340-D-EVB
—
—
—
Evaluation
Board
—
Note:
1. Add an R at the end of the OPN to denote tape and reel ordering options.
2. Custom, factory pre-programmed devices are available. Ordering part numbers are assigned by Skyworks and the ClockBuilder
Pro software utility. Custom part number format is: e.g., Si5341A-Dxxxxx-GM, where "xxxxx" is a unique numerical sequence
representing the preprogrammed configuration.
3. See 3.9 Custom Factory Preprogrammed Devicesand 3.10 Enabling Features and/or Configuration Settings Not Available in
ClockBuilder Pro for Factory Pre-Programmed Devices for important notes about specifying a preprogrammed device to use
features or device register settings not yet available in CBPro.
3
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • November 30, 2021
3
Si5341/40 Rev D Data Sheet • Ordering Guide
Si534fg-Rxxxxx-GM
Timing product family
f = Multi-PLL clock family member (7, 6)
g = Device grade (A, B, C, D)
Product Revision*
Custom ordering part number (OPN) sequence ID**
Package, ambient temperature range (QFN, -40 °C to +85°C)
*See Ordering Guide table for current product revision
** 5 digits; assigned by ClockBuilder Pro
Figure 2.1. Ordering Part Number Fields
4
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • November 30, 2021
4
Table of Contents
1. Features List
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. Ordering Guide
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3. Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1 Power-up and Initialization .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. 7
3.2 Frequency Configuration
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. 7
3.3 Inputs . . . . . . . . . . . . .
3.3.1 XA/XB Clock and Crystal Input . . .
3.3.2 Input Clocks (IN0, IN1, IN2) . . . .
3.3.3 Input Selection (IN0, IN1, IN2, XA/XB)
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
3.4 Fault Monitoring . . .
3.4.1 Status Indicators . .
3.4.2 Interrupt Pin (INTRb)
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. 9
. 9
. 9
3.5 Outputs . . . . . . . . . . . . . . . . . . . .
3.5.1 Output Signal Format . . . . . . . . . . . . . .
3.5.2 Differential Output Terminations . . . . . . . . . . .
3.5.3 Programmable Common Mode Voltage for Differential Outputs
3.5.4 LVCMOS Output Terminations . . . . . . . . . . .
3.5.5 LVCMOS Output Impedance and Drive Strength Selection . .
3.5.6 LVCMOS Output Signal Swing . . . . . . . . . . .
3.5.7 LVCMOS Output Polarity . . . . . . . . . . . . .
3.5.8 Output Enable/Disable . . . . . . . . . . . . . .
3.5.9 Output Driver State When Disabled . . . . . . . . .
3.5.10 Synchronous/Asynchronous Output Disable Feature . . .
3.5.11 Zero Delay Mode . . . . . . . . . . . . . . .
3.5.12 Output Crosspoint . . . . . . . . . . . . . . .
3.5.13 Digitally Controlled Oscillator (DCO) Modes . . . . . .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.10
.10
.10
.11
.11
.11
.11
.11
.11
.12
.12
.12
.12
.13
3.6 Power Management .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
7
8
8
9
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.13
3.7 In-Circuit Programming .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.13
3.8 Serial Interface .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.13
3.9 Custom Factory Preprogrammed Devices .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.13
3.10 Enabling Features and/or Configuration Settings Not Available in ClockBuilder Pro for Factory
Pre-Programmed Devices . . . . . . . . . . . . . . . . . . . . . . . .
.
.14
4. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16
5. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . .
17
6. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . .
32
7. Detailed Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . .
33
8. Typical Operating Characteristics
. . . . . . . . . . . . . . . . . . . . . .
35
9. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
37
5
.
.
.
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • November 30, 2021
5
10. Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . .
42
10.1 Si5341 9x9 mm 64-QFN Package Diagram .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.42
10.2 Si5340 7x7 mm 44-QFN Package Diagram .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.43
11. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . .
44
12. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
46
13. Device Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
47
14. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
48
6
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • November 30, 2021
6
Si5341/40 Rev D Data Sheet • Functional Description
3. Functional Description
The Si5340/41-D combines a wide band PLL with next generation MultiSynth technology to offer the industry's most versatile and high
performance clock generator. The PLL locks to either an external crystal between XA/XB or to an external clock connected to XA/XB
or IN0, 1, 2. A fractional or integer multiplier takes the selected input clock or cystal frequency up to a very high frequency that is
then divided by the MultiSynth output stage to any frequency in the range of 100 Hz to 1 GHz on each output. The MultiSynth stage
can divide by both integer and fractional values. The high-resolution fractional MultiSynth dividers enable true any-frequency input to
any-frequency on any of the outputs. The output drivers offer flexible output formats which are independently configurable on each of
the outputs. This clock generator is fully configurable via its serial interface (I2C/SPI) and includes in-circuit programmable non-volatile
memory.
3.1 Power-up and Initialization
Once power is applied, the device begins an initialization period where it downloads default register values and configuration data
from NVM and performs other initialization tasks. Communicating with the device through the serial interface is possible once this
initialization period is complete. No clocks will be generated until the initialization is done. There are two types of resets available. A
hard reset is functionally similar to a device power-up. All registers will be restored to the values stored in NVM, and all circuits will be
restored to their initial state including the serial interface. A hard reset is initiated using the RSTb pin or by asserting the hard reset bit.
A soft reset bypasses the NVM download. It is simply used to initiate register configuration changes.
Power-Up
Hard Reset
bit asserted
RSTb
pin asserted
NVM download
Soft Reset
bit asserted
Initialization
Serial interface
ready
Figure 3.1. Si5341 Power-Up and Initialization
3.2 Frequency Configuration
The phase-locked loop is fully contained and does not require external loop filter components to operate. Its function is to phase lock to
the selected input and provide a common reference to the MultiSynth high-performance fractional dividers.
A crosspoint mux connects any of the MultiSynth divided frequencies to any of the outputs drivers. Additional output integer dividers
provide further frequency division by an even integer from 2 to (225)-2. The frequency configuration of the device is programmed by
setting the input dividers (P), the PLL feedback fractional divider (Mn/Md), the MultiSynth fractional dividers (Nn/Nd), and the output
integer dividers (R). Skyworks's ClockBuilder Pro configuration utility determines the optimum divider values for any desired input and
output frequency plan.
3.3 Inputs
The Si5340/41-D requires either an external crystal at its XA/XB pins or an external clock at XA/XB or IN0, 1, 2.
7
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • November 30, 2021
7
Si5341/40 Rev D Data Sheet • Functional Description
3.3.1 XA/XB Clock and Crystal Input
An internal crystal oscillator exists between pin XA and XB. When this oscillator is enabled, an external crystal connected across these
pins will oscillate and provide a clock input to the PLL. A crystal frequency of 25 MHz can be used although crystals in the frequency
range of 48 MHz to 54 MHz are recommended for best jitter performance. Frequency offsets due to CL mismatch can be adjusted
using the frequency adjustment feature which allows frequency adjustments of ± 1000 ppm. The Si5340/41 Family Reference Manual
provides additional information on PCB layout recommendations for the crystal to ensure optimum jitter performance. Refer to Table
5.12 Crystal Specifications on page 30 for crystal specifications.
To achieve optimal jitter performance and minimize BOM cost, a crystal is recommended on the XA/XB reference input. A clock (e.g.,
XO) may be used in lieu of the crystal, but it will result in higher output jitter. See the Si5340/41 Reference Manual for more information.
Selection between the external XTAL or input clock is controlled by register configuration. The internal crystal load capacitors (CL) are
disabled in the input clock mode. Refer to Table 5.3 Input Clock Specifications on page 19 for the input clock requirements at XAXB.
Both a single-ended or a differential input clock can be connected to the XA/XB pins as shown in the figure below. A PXAXB divider is
available to accommodate external clock frequencies higher than 54 MHz.
Differential Connection
Single-ended XO Connection
nc X1
nc X2
nc X1
nc X2
Note: 2.0 Vpp_se max
0.1 µf
50
2xCL
0.1 µf
XA
50
OSC
2xCL
XA
OSC
XB
XO with Clipped Sine
Wave Output
Si5341/40
0.1 µf
2xCL
0.1 µf
XB
2xCL
Si5341/40
Note: 2.5 Vpp diff max
Crystal Connection
Single-ended Connection
nc X1
nc X2
Note: 2.0 Vpp_se max
CMOS/XO Output
R1
0.1 µf
X1
2xCL
XA
XTA
L
OSC
XO VDD
R1
R2
3.3 V
523 Ohms 422 Ohms
2.5 V
475 Ohms 649 Ohms
158 Ohms 866 Ohms
1.8 V
R2
0.1 µf
0.1 µf
2xCL
XA
OSC
XB
XB
2xCL
Si5341/40
X2
2xCL
Si5341/40
Figure 3.2. XAXB External Crystal and Clock Connections
Note: See Table 5.3 Input Clock Specifications on page 19 for more information.
3.3.2 Input Clocks (IN0, IN1, IN2)
A differential or single-ended clock can be applied at IN2, IN1, or IN0.
The recommended input termination schemes are can be found in Si5341/40 Rev D Family Reference Manual.
8
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • November 30, 2021
8
Si5341/40 Rev D Data Sheet • Functional Description
3.3.3 Input Selection (IN0, IN1, IN2, XA/XB)
The active clock input is selected using the IN_SEL[1:0] pins or by register control. A register bit determines input selection as pin or
register selectable. There are internal pull ups on the IN_SEL pins.
Table 3.1. Manual Input Selection Using IN_SEL[1:0] Pins
IN_SEL[1:0]
Selected Input
0
0
IN0
0
1
IN1
1
0
IN2
1
1
XA/XB
3.4 Fault Monitoring
The Si5340/41-D provides fault indicators which monitor loss of signal (LOS) of the inputs (IN0, IN1, IN2, XA/XB, FB_IN) and loss of
lock (LOL) for the PLL as shown in the figure below.
IN0
÷P0
IN0b
Si5341/40
LOS0
LOL
IN1
IN1b
IN2
IN2b
÷P1
LOS1
÷P2
LOS2
PLL
PD
LPF
÷
Mn
Md
LOSXAB
FB_IN
÷Pfb
LOSFB
LOSXAB
(Si5340)
FB _INb
OSC
INTRb
XB
LOLb
XA
Figure 3.3. LOS and LOL Fault Monitors
3.4.1 Status Indicators
The state of the status monitors are accessible by reading registers through the serial interface or with dedicated pin (LOLb). Each
of the status indicator register bits has a corresponding sticky bit in a separate register location. Once a status bit is asserted its
corresponding sticky bit (_FLG) will remain asserted until cleared. Writing a logic zero to a sticky register bit clears its state.
3.4.2 Interrupt Pin (INTRb)
An interrupt pin (INTRb) indicates a change in state with any of the status registers. All status registers are maskable to prevent
assertion of the interrupt pin. The state of the INTRb pin is reset by clearing the status registers.
9
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • November 30, 2021
9
Si5341/40 Rev D Data Sheet • Functional Description
3.5 Outputs
The Si5341 supports 10 differential output drivers which can be independently configured as differential or LVCMOS. The Si5340
supports 4 output drivers independently configurable as differential or LVCMOS.
3.5.1 Output Signal Format
The differential output amplitude and common mode voltage are both fully programmable and compatible with a wide variety of signal
formats including LVDS and LVPECL. In addition to supporting differential signals, any of the outputs can be configured as LVCMOS
(3.3 V, 2.5 V, or 1.8 V) drivers providing up to 20 single-ended outputs, or any combination of differential and single-ended outputs.
3.5.2 Differential Output Terminations
The differential output drivers support both ac-coupled and dc-coupled terminations as shown in the figure below.
DC Coupled LVDS/LVPECL
LVDS: VDDO = 3.3V, 2.5V, 1.8V
LVPECL: VDDO = 2.5V, 1.8V
50
OUTx
100
OUTxb
50
Si5341/40
AC Coupled LVDS/LVPECL
VDDO = 3.3V, 2.5V, 1.8V
50
OUTx
100
OUTxb
50
Internally
self-biased
Si5341/40
AC Coupled LVPECL/CML
VDD – 1.3V
VDDO = 3.3V, 2.5V
50
50
50
OUTx
OUTxb
50
Si5341/40
AC Coupled HCSL
VDDRX
VDDO = 3.3V, 2.5V, 1.8V
R1
OUTx
OUTxb
Si5341/40
R1
50
50
R2
R2
Standard
HCSL
Receiver
Figure 3.4. Supported Differential Output Terminations
Note: See the Si5341/40 Rev D Family Reference Manual for resistor values.
10
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • November 30, 2021
10
Si5341/40 Rev D Data Sheet • Functional Description
3.5.3 Programmable Common Mode Voltage for Differential Outputs
The common mode voltage (VCM) for the differential modes are programmable so that LVDS specifications can be met and for the best
signal integrity with different supply voltages. When dc coupling the output driver it is essential that the receiver should have a relatively
high common mode impedance so that the common mode current from the output driver is very small.
3.5.4 LVCMOS Output Terminations
LVCMOS outputs are typically dc-coupled, as shown in the figure below.
DC Coupled LVCMOS
3.3V , 2.5V , 1.8 V
LVCMOS
VDDO = 3.3V , 2.5V , 1.8V
50
OUTx
Rs
OUTxb
50
Rs
Figure 3.5. LVCMOS Output Terminations
3.5.5 LVCMOS Output Impedance and Drive Strength Selection
Each LVCMOS driver has a configurable output impedance. It is highly recommended that the minimum output impedance (strongest
drive setting) is selected and a suitable series resistor (Rs) is chosen to match the trace impedance.
Table 3.2. Nominal Output Impedance vs. OUTx_CMOS_DRV (register)
VDDO
CMOS_DRIVE_Selection
OUTx_CMOS_DRV=1
OUTx_CMOS_DRV=2
OUTx_CMOS_DRV=3
3.3 V
38 Ω
30 Ω
22 Ω
2.5 V
43 Ω
35 Ω
24 Ω
1.8 V
—
46 Ω
31 Ω
Note: Refer to the Si5340/41 Family Reference Manual for more information on register settings.
3.5.6 LVCMOS Output Signal Swing
The signal swing (VOL/VOH) of the LVCMOS output drivers is set by the voltage on the VDDO pins. Each output driver has its own
VDDO pin allowing a unique output voltage swing for each of the LVCMOS drivers.
3.5.7 LVCMOS Output Polarity
When a driver is configured as an LVCMOS output it generates a clock signal on both pins (OUTx and OUTxb). By default the clock on
the OUTxb pin is generated with complementary polarity with the clock on the OUTx pin. The LVCMOS OUTx and OUTxb outputs can
also be generated in phase.
3.5.8 Output Enable/Disable
The OEb pin provides a convenient method of disabling or enabling the output drivers. When the OEb pin is held high all outputs will be
disabled. When held low, the outputs will be enabled. Outputs in the enabled state can be individually disabled through register control.
11
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • November 30, 2021
11
Si5341/40 Rev D Data Sheet • Functional Description
3.5.9 Output Driver State When Disabled
The disabled state of an output driver is configurable as: disable low or disable high.
3.5.10 Synchronous/Asynchronous Output Disable Feature
Outputs can be configured to disable synchronously or asynchronously. The default state is synchronous output disable. In synchronous disable mode the output will wait until a clock period has completed before the driver is disabled. This prevents unwanted runt
pulses from occurring when disabling an output. In asynchronous disable mode the output clock will disable immediately without waiting
for the period to complete.
3.5.11 Zero Delay Mode
A zero delay mode is available for applications that require fixed and consistent minimum delay between the selected input and outputs.
The zero delay mode is configured by opening the internal feedback loop through software configuration and closing the loop externally
as shown in the figure below. This helps to cancel out the internal delay introduced by the dividers, the crosspoint, the input, and the
output drivers. Any one of the outputs can be fed back to the FB_IN pins, although using the output driver that achieves the shortest
trace length will help to minimize the input-to-output delay. It is recommended to connect OUT9 (Si5341) or OUT3 (Si5340) to FB_IN
for external feedback. The FB_IN input pins must be terminated and ac-coupled when zero delay mode is used. A differential external
feedback path connection is necessary for best performance.
VDDO0
OUT0
OUT0b
Si5341
IN0
IN0b
fIN
IN1
IN1b
IN2
IN2b
VDDO1
OUT1
OUT1b
÷ P0
÷ P1
VDDO2
OUT2
OUT2b
÷ P2
VDDO3
OUT3
OUT3b
IN_ SEL[1:0]
FB_IN
100
fFB = fIN
Zero Delay
Mode
PLL
PD
VDDO7
OUT7
OUT7b
LPF
÷Pfb
÷
FB_INb
MultiSynth
& Dividers
Mn
Md
VDDO8
OUT8
OUT8b
÷
N9n
N9d
÷R9
VDDO9
OUT9
OUT9b
External Feedback Path
Figure 3.6. Si5341 Zero Delay Mode Setup
3.5.12 Output Crosspoint
The output crosspoint allows any of the N dividers to connect to any of the clock outputs.
12
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • November 30, 2021
12
Si5341/40 Rev D Data Sheet • Functional Description
3.5.13 Digitally Controlled Oscillator (DCO) Modes
Each MultiSynth can be digitally controlled so that all outputs connected to the MultiSynth change frequency in real time without any
transition glitches. There are two ways to control the MultiSynth to accomplish this task:
• Use the Frequency Increment/Decrement Pins or register bits.
• Write directly to the numerator of the MultiSynth divider.
An output that is controlled as a DCO is useful for simple tasks such as frequency margining or CPU speed control. The output can also
be used for more sophisticated tasks such as FIFO management by adjusting the frequency of the read or write clock to the FIFO or
using the output as a variable Local Oscillator in a radio application.
3.5.13.1 DCO with Frequency Increment/Decrement Pins/Bits
Each of the MultiSynth fractional dividers can be independently stepped up or down in predefined steps with a resolution as low as
0.001 ppb. Setting of the step size and control of the frequency increment or decrement is accomplished by setting the step size with
the 44 bit Frequency Step Word (FSTEPW). When the FINC or FDEC pin or register bit is asserted the output frequency will increment
or decrement respectively by the amount specified in the FSTEPW.
3.5.13.2 DCO with Direct Register Writes
When a MultiSynth numerator and its corresponding update bit is written, the new numerator value will take effect and the output
frequency will change without any glitches. The MultiSynth numerator and denominator terms can be left and right shifted so that the
least significant bit of the numerator word represents the exact step resolution that is needed for your application.
3.6 Power Management
Several unused functions can be powered down to minimize power consumption. Consult the Si5340/41 Family Reference Manual and
ClockBuilder Pro configuration utility for details.
3.7 In-Circuit Programming
The Si5341/40 is fully configurable using the serial interface (I2C or SPI). At power-up the device downloads its default register values
from internal non-volatile memory (NVM). Application specific default configurations can be written into NVM allowing the device to
generate specific clock frequencies at power-up. Writing default values to NVM is in-circuit programmable with normal operating power
supply voltages applied to its VDD and VDDA pins. The NVM is two time writable. Once a new configuration has been written to NVM,
the old configuration is no longer accessible. Refer to the Si5340/41 Family Reference Manual for a detailed procedure for writing
registers to NVM.
3.8 Serial Interface
Configuration and operation of the Si5341/40 is controlled by reading and writing registers using the I2C or SPI interface. The I2C_SEL
pin selects I2C or SPI operation. Communication with both 3.3 V and 1.8 V host is supported. The SPI mode operates in either 4-wire or
3-wire. See the Si5340/41 Family Reference Manual for details.
3.9 Custom Factory Preprogrammed Devices
For applications where a serial interface is not available for programming the device, custom pre-programmed parts can be ordered
with a specific configuration written into NVM. A factory pre-programmed device will generate clocks at power-up. Custom, factory-preprogrammed devices are available. Use the ClockBuilder Pro custom part number wizard (https://www.skyworksinc.com/en/applicationpages/clockbuilder-pro-software) to quickly and easily request and generate a custom part number for your configuration. In less than
three minutes, you will be able to generate a custom part number with a detailed data sheet addendum matching your design’s
configuration. Once you receive the confirmation email with the data sheet addendum, simply place an order with your local Skyworks
sales representative. Samples of your pre-programmed device will ship to you typically within two weeks.
13
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • November 30, 2021
13
Si5341/40 Rev D Data Sheet • Functional Description
3.10 Enabling Features and/or Configuration Settings Not Available in ClockBuilder Pro for Factory Pre-Programmed Devices
As with essentially all software utilities, ClockBuilder Pro is continuously updated and enhanced. By registering at https://www.skyworksinc.com/ and opting in for updates to software, you will be notified whenever changes are made and what the impact of those changes
are. This update process will ultimately enable ClockBuilder Pro users to access all features and register setting values documented in
this data sheet and the Si5341/40 Family Reference Manual. However, if you must enable or access a feature or register setting value
so that the device starts up with this feature or a register setting, but the feature or register setting is NOT yet available in CBPro, you
must contact a Skyworks applications engineer for assistance. An example of this type of feature or custom setting is the customizable
amplitudes for the clock outputs. After careful review of your project file and custom requirements, a Skyworks applications engineer
will email back your CBPro project file with your specific features and register settings enabled, using what is referred to as the manual
"settings override" feature of CBPro. "Override" settings to match your request(s) will be listed in your design report file. Examples of
setting "overrides" in a CBPro design report are shown below:
Table 3.3. Setting Overrides
Location
Name
Type
Target
Dec Value
Hex Value
0128[6:4]
OUT6_AMPL
User
OPN & EVB
5
5
Once you receive the updated design file, simply open it in CBPro. After you create a custom OPN, the device will begin operation after
startup with the values in the NVM file, including the Skyworks-supplied override settings.
14
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • November 30, 2021
14
Si5341/40 Rev D Data Sheet • Functional Description
End: Place
sample order
Start
Do I need a
pre-programmed device with
a feature or setting which is
unavailable in ClockBuilder
Pro?
No
Configure device
using CBPro
Generate
Custom OPN
in CBPro
Yes
Contact Skyworks
Technical Support
to submit & review
your
non-standard
configuration
request & CBPro
project file
Receive
updated CBPro
project file
from
Skyworks
with “Settings
Override”
Yes
Load project file
into CBPro and test
Does the updated
CBPro Project file
match your
requirements?
Figure 3.7. Flowchart to Order Custom Parts with Features not Available in CBPro
Note: Contact Skyworks Technical Support at https://www.skyworksinc.com/en/Support.
15
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • November 30, 2021
15
Si5341/40 Rev D Data Sheet • Register Map
4. Register Map
Refer to the Si5340/41 Family Reference Manual for a complete list of register descriptions and settings.
16
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • November 30, 2021
16
Si5341/40 Rev D Data Sheet • Electrical Specifications
5. Electrical Specifications
Table 5.1. Recommended Operating Conditions1
(VDD=1.8 V ± 5%, VDDA=3.3 V ± 5%, TA= –40 to 85°C)
Parameter
Symbol
Min
Typ
Max
Units
Ambient Temperature
TA
–40
25
85
°C
Junction Temperature
TJMAX
—
—
125
°C
Core Supply Voltage
VDD
1.71
1.80
1.89
V
VDDA
3.14
3.30
3.47
V
VDDO
3.14
3.30
3.47
V
2.37
2.50
2.62
V
1.71
1.80
1.89
V
Output Driver Supply Voltage
Note:
1. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical
values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted.
17
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • November 30, 2021
17
Si5341/40 Rev D Data Sheet • Electrical Specifications
Table 5.2. DC Characteristics
(VDD=1.8V ± 5%, VDDA=3.3V ± 5%, VDDO=1.8V ± 5%, 2.5V ± 5%, or 3.3V ± 5%, TA= -40 to 85°C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Core Supply Current1, 2
IDD
Si5340/41
—
115
230
mA
IDDA
Si5340/41
—
120
130
mA
IDDOx
LVPECL Output3
—
22
26
mA
—
15
18
mA
—
22
30
mA
—
18
23
mA
—
12
16
mA
Si5341
—
880
1150
mW
Si5340
—
680
875
mW
Output Buffer Supply Current
@ 156.25 MHz
LVDS Output3
@ 156.25 MHz
3.3 V LVCMOS4 output
@ 156.25 MHz
2.5 V LVCMOS4 output
@ 156.25 MHz
1.8 V LVCMOS4 output
@ 156.25 MHz
Pd
Total Power Dissipation1, 5
Note:
1. Si5341 test configuration: 7 x 2.5 V LVDS outputs enabled @ 156.25 MHz. Excludes power in termination resistors.
2. Si5340 test configuration: 4 x 2.5 V LVDS outputs enabled @ 156.25 MHz. Excludes power in termination resistors.
3. Differential outputs terminated into an ac-coupled 100 Ω load.
4. LVCMOS outputs measured into a 6-inch 50 W PCB trace with 5 pF load. The LVCMOS outputs were set to
OUTx_CMOS_DRV=3, which is the strongest driver setting. Refer to the Si5341/40 Family Reference Manual for more details on
register settings.
Differential Output Test Configuration
LVCMOS Output Test Configuration
Trace length 5 inches
IDDO
50
OUT
499
4.7 pF
DC Block
50 probe, scope
56
OUTb
I DDO
OUT
50
0. 1 uF
499
100
OUTb
50
DC Block
50 probe, scope
50
4.7 pF
56
0. 1 uF
5. Detailed power consumption for any configuration can be estimated using ClockBuilderPro when an evaluation board (EVB) is not
available. All EVBs support detailed current measurements for any configuration.
18
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • November 30, 2021
18
Si5341/40 Rev D Data Sheet • Electrical Specifications
Table 5.3. Input Clock Specifications
(VDD =1.8 V ± 5%, VDDA = 3.3 V ± 5%, TA= –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Standard Input Buffer with Differential or Single-Ended - AC-Coupled (IN0/IN0b, IN1/IN1b, IN2/IN2b, FB_IN/FB_INb)
Input Frequency Range
fIN
Differential
10
—
750
MHz
All Single-ended Signals
10
—
250
MHz
100
—
1800
mVpp_se
225
—
1800
mVpp_se
100
—
3600
mVpp_se
(including LVCMOS)
Input Voltage Swing1
VIN
Differential AC-coupled
fIN < 250 MHz
Differential AC-coupled
250 MHz < fIN < 750 MHz
Single-ended AC-coupled
fIN < 250 MHz
Slew Rate2, 3
SR
400
—
—
V/μs
Input Capacitance
CIN
—
2.4
—
pF
RIN_DIFF
—
16
—
kΩ
RIN_SE
—
8
—
kΩ
Input Resistance Differential
Input Resistance Single-Ended
Pulsed CMOS Input Buffer - DC Coupled (IN0, IN1, IN2)
Input Frequency
fIN
10
—
250
MHz
Input Voltage
VIL
–0.2
—
0.4
V
VIH
0.8
—
—
V
Slew Rate2, 3
SR
400
—
—
V/μs
Minimum Pulse Width
PW
1.6
—
—
ns
Input Resistance
RIN
—
8
—
kΩ
Full operating range. Jitter performance may be
reduced.
10
—
200
MHz
Range for best jitter.
48
—
54
MHz
VIN_SE
365
—
2000
mVpp_se
VIN_DIFF
365
—
2500
mVpp_diff
400
—
—
V/μs
40
—
60
%
Pulse Input
REFCLK (Applied to XA/XB)
Input Frequency Range
Input Single-ended Voltage
Swing
Input Differential Voltage Swing
fIN
Slew Rate2, 3
SR
Input Duty Cycle
DC
19
Imposed for best jitter performance
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • November 30, 2021
19
Si5341/40 Rev D Data Sheet • Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Note:
Vcm
Vpp_se
Vcm
Vpp_se
Vpp_diff = 2*Vpp_se
1. Voltage swing is specified as single-ended mVpp.
2. Recommended for specified jitter performance. Jitter performance can degrade if the minimum slew rate specification is not met
(see the Family Reference Manual).
3. Pulsed CMOS mode is intended primarily for single-ended LVCMOS input clocks < 1 MHz, which must be dc-coupled because
they have a duty cycle significantly less than 50%. A typical application example is a low frequency video frame sync pulse. Since
the input thresholds (VIL, VIH) of this buffer are non-standard (0.4 and 0.8 V, respectively), refer to the input attenuator circuit for
DC-coupled Pulsed LVCMOS in the Family Reference Manual. Otherwise, for standard LVCMOS input clocks, use the Standard
AC-Coupled, Single-ended input mode.
Table 5.4. Control Input Pin Specifications
(VDD =1.8 V ± 5%, VDDA = 3.3 V ± 5%, VDDIO= 3.3 V ± 5%, 1.8 V ± 5%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Si5341 Control Input Pins (I2C_SEL, IN_SEL[1:0], RSTb, OEb, SYNCb, A1, SCLK, A0/CSb, FINC, FDEC, SDA/SDIO)
Input Voltage
VIL
—
—
0.3xVDDIO1
V
VIH
0.7xVDDIO1
—
—
V
Input Capacitance
CIN
—
2
—
pF
Input Resistance
RIN
—
20
—
kΩ
Minimum Pulse Width
TPW
RSTb, SYNCb, FINC, and
FDEC
100
—
—
ns
Frequency Update Rate
FUR
FINC and FDEC
—
—
1
MHz
Si5340 Control Input Pins (I2C_SEL, IN_SEL[1:0], RSTb, OEb, A1, SCLK, A0/CSb, SDA/SDIO)
Input Voltage
VIL
—
—
0.3xVDDIO1
V
VIH
0.7xVDDIO1
—
—
V
Input Capacitance
CIN
—
2
—
pF
Input Resistance
RIN
—
20
—
kΩ
Minimum Pulse Width
TPW
100
—
—
ns
RSTb only
Note:
1. VDDIO is determined by the IO_VDD_SEL bit. It is selectable as VDDA or VDD. Refer to the Family Reference Manual for more
details on register settings.
20
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • November 30, 2021
20
Si5341/40 Rev D Data Sheet • Electrical Specifications
Table 5.5. Differential Clock Output Specifications
(VDD=1.8 V ± 5%, VDDA= 3.3 V ± 5%, VDDO= 1.8 V ± 5%, 2.5 V ± 5%, or 3.3 V ± 5%, TA= –40 to 85 °C)
Parameter
Output Frequency
Duty Cycle
Output-Output Skew
Using Same MultiSynth
OUT-OUTb Skew
Output Voltage Swing1
Common Mode Voltage1, 2
Symbol
Test Condition
Min
Typ
Max
Units
fOUT
MultiSynth not used
0.0001
—
720
MHz
733.33
—
800.00
825
—
1028
MultiSynth used
0.0001
—
720
MHz
fOUT < 400 MHz
48
—
52
%
400 MHz < fOUT < 1028 MHz
45
—
55
%
TSKS
Outputs on same MultiSynth
(Measured at 712.5 MHz)
—
0
75
ps
TSK_OUT
Measured from the positive
to negative output pins
—
0
50
ps
VOUT
LVDS
350
430
510
mVpp_se
LVPECL
640
750
900
LVDS
1.1
1.2
1.3
LVPECL
1.9
2.0
2.1
LVPECL
1.1
1.2
1.3
0.8
0.9
1.0
tR/tF
—
100
150
ps
ZO
—
100
—
Ω
10 kHz sinusoidal noise
—
–101
—
dBc
100 kHz sinusoidal noise
—
–96
—
500 kHz sinusoidal noise
—
–99
—
1 MHz sinusoidal noise
—
–97
—
Si5341
—
–72
—
dBc
Si5340
—
–88
—
dBc
DC
VCM
VDDO = 3.3 V
VDDO = 2.5 V
V
LVDS
VDDO = 1.8 V
Rise and Fall Times
Sub-LVDS
(20% to 80%)
Differential Output Impedance
Power Supply Noise Rejection2
Output-Output Crosstalk3
21
PSRR
XTALK
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • November 30, 2021
21
Si5341/40 Rev D Data Sheet • Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Notes:
1. Output amplitude and common-mode settings are programmable through register settings and can be stored in
NVM. Each output driver can be programmed independently. The maximum LVDS single-ended amplitude can be
up to 110 mV higher than the TIA/EIA-644 maximum. Refer to the Family Reference Manual for more suggested output settings. Not all combinations of voltage amplitude and common mode voltages settings are possible.
OUTx
Vcm
Vpp_se
Vcm
Vpp_se
Vpp_ diff = 2* Vpp_se
OUTxb
2. Measured for 156.25 MHz carrier frequency. 100 mVpp sinewave noise added to VDDO = 3.3 V and noise spur amplitude
measured.
3. Measured across two adjacent outputs, both in LVDS mode, with the victim running at 155.52 MHz and the aggressor at 156.25
MHz. Refer to application note, AN862: Optimizing Si534x Jitter Performance in Next Generation Internet Infrastructure Systems,
guidance on crosstalk minimization.
Table 5.6. LVCMOS Clock Output Specifications
(VDD =1.8 V ± 5%, VDDA= 3.3 V ± 5%, VDDO= 1.8 V ± 5%, 2.5 V ± 5%, or 3.3 V ± 5%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
0.0001
—
250
MHz
fOUT < 100 MHz
48
—
52
%
100 MHz < fOUT < 250 MHz
45
—
55
VDDO x 0.85
—
—
Output Frequency
Duty Cycle
Output Voltage High1, 2, 3
DC
VOH
VDDO = 3.3 V
OUTx_CMOS_DRV=1
IOH = -10 mA
OUTx_CMOS_DRV=2
IOH = -12 mA
—
—
OUTx_CMOS_DRV=3
IOH = -17 mA
—
—
—
—
V
VDDO = 2.5 V
VDDO x 0.85
OUTx_CMOS_DRV=1
IOH = -6 mA
OUTx_CMOS_DRV=2
IOH = -8 mA
—
—
OUTx_CMOS_DRV=3
IOH = -11 mA
—
—
—
—
—
—
V
VDDO = 1.8 V
22
OUTx_CMOS_DRV=2
IOH = -4 mA
OUTx_CMOS_DRV=3
IOH = -5 mA
VDDO x 0.85
V
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • November 30, 2021
22
Si5341/40 Rev D Data Sheet • Electrical Specifications
Parameter
Symbol
Output Voltage Low1, 2, 3
VOL
Test Condition
Min
Typ
Max
Units
VDDO x 0.15
V
VDDO x 0.15
V
VDDO x 0.15
V
VDDO = 3.3 V
OUTx_CMOS_DRV=1
IOL = 10 mA
—
—
OUTx_CMOS_DRV=2
IOL = 12 mA
—
—
OUTx_CMOS_DRV=3
IOL = 17 mA
—
—
OUTx_CMOS_DRV=1
IOL = 6 mA
—
—
OUTx_CMOS_DRV=2
IOL = 8 mA
—
—
OUTx_CMOS_DRV=3
IOL = 11 mA
—
—
OUTx_CMOS_DRV=2
IOL = 4 mA
—
—
OUTx_CMOS_DRV=3
IOL = 5 mA
—
—
VDDO = 3.3V
—
400
600
ps
VDDO = 2.5 V
—
450
600
ps
VDDO = 1.8 V
—
550
750
ps
VDDO = 2.5 V
VDDO = 1.8 V
LVCMOS Rise and Fall
Times3
tr/tf
(20% to 80%)
Notes:
1. Driver strength is a register programmable setting and stored in NVM. Options are OUTx_CMOS_DRV = 1, 2, 3. Refer to the
Family Reference Manual for more details on register settings.
2. IOL/IOH is measured at VOL/VOH as shown in the dc test configuration.
3. A series termination resistor (Rs) is recommended to help match the source impedance to a 50 W PCB
trace. A 5 pF capacitive load is assumed. The LVCMOS outputs were set to OUTx_CMOS_DRV = 3.
AC Test Configuration
DC Test Configuration
Trace length 5 inches
IOL/IOH
IDDO
50
OUT
Zs
VOL/VOH
499
4.7 pF
DC Block
OUTb
499
DC Block
50 probe, scope
50
4.7 pF
23
50 probe, scope
56
56
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • November 30, 2021
23
Si5341/40 Rev D Data Sheet • Electrical Specifications
Table 5.7. Output Status Pin Specifications
(VDD =1.8 V ± 5%, VDDA= 3.3 V ± 5%, VDDIO/VDDS = 3.3 V +/- 5%, 1.8 V ± 5%, TA = –40 to 85°C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
VOH
IOH = -2 mA
VDDIO2 x
0.85
—
—
V
VOL
IOL = 2 mA
—
—
VDDIO2x
0.15
V
VOH
IOH = -2 mA
VDDIO2 x
0.85
—
—
V
VOL
IOL = 2 mA
—
—
VDDIO2 x
0.15
V
VOH
IOH = -2 mA
VDDS x 0.85
—
—
V
VOL
IOL = 2 mA
—
—
VDDSx 0.15
V
Si5341/40 Status Output Pins (INTRb, SDA/SDIO)1
Output Voltage
Si5341 Status Output Pins (LOLb)
Output Voltage
Si5340 Status Output Pins (LOLb, LOS_XAXBb)
Output Voltage
Notes:
1. The VOH specification does not apply to the open-drain SDA/SDIO output when the serial interface is in I2C mode or is unused
with I2C_SEL pulled high. VOL remains valid in all cases.
2. VDDIO is determined by the IO_VDD_SEL bit. It is selectable as VDDA or VDD. Refer to the Family Reference Manual for more
details on register settings.
Table 5.8. Performance Characteristics
(VDD= 1.8 V ± 5%, VDDA= 3.3 V ± 5%, TA= –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
—
1.0
—
MHz
PLL Loop Bandwidth
fBW
Initial Start-Up Time
tSTART
Time from power-up to
when the device generates clocks (Input Frequency >48 MHz)
—
30
45
ms
PLL Lock Time1
tACQ
fIN = 19.44 MHz
15
—
150
ms
POR2 to Serial Interface Ready
tRDY
—
—
15
ms
24
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • November 30, 2021
24
Si5341/40 Rev D Data Sheet • Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Jitter Generation Locked to External Clock3
JGEN
Integer Mode4
—
140
180
fs rms
—
160
210
fs rms
—
110
—
fs rms
—
180
—
fs rms
—
4710
—
fs pk-pk
—
4000
—
fs pk
—
90
140
fs rms
—
115
170
fs rms
—
110
—
fs rms
—
180
—
fs rms
—
5080
—
fs pk-pk
—
4340
—
fs pk
115
140
fs rms
140
190
fs rms
12 kHz to 20 MHz
Fractional/DCO Mode5
12 kHz to 20 MHz
JPER
JCC
JPER
JCC
Jitter Generation Locked to External XTAL
Derived from integrated
phase noise
N = 10,000 cycles Integer
or Fractional Mode4, 5 .
Measured in the time domain. Performance is limited by the noise floor of
the equipment.
XTAL Frequency = 48 MHz
JGEN
Integer Mode4
12 kHz to 20 MHz
Fractional/DCO Mode5
12 kHz to 20 MHz
JPER
JCC
JPER
JCC
Derived from integrated
phase noise
N = 10, 000 cycles Integer or Fractional Mode.4,
5 Measured in the time domain. Performance is limited by the noise floor of
the equipment.
XTAL Frequency = 25 MHz
JGEN
Integer Mode4
12 kHz to 20 MHz
Fractional Mode5
12 kHz to 20 MHz
Notes:
1. PLL lock time is measured by first letting the PLL lock, then turning off the input clock, and then turning on the input clock. The
time from the first edge of the input clock being re-applied until LOL de-asserts is the PLL lock time.
2. Measured as time from valid VDD and VDD33 rails (90% of their value) to when the serial interface is ready to respond to
commands. Measured in SPI 4-wire mode, with SCLK @ 10 MHz.
3. Jitter generation test conditions fIN = 100 MHz, fOUT = 156.25 MHz LVPECL.
4. Integer mode assumes that the output dividers (Nn/Nd) are configured with an integer value.
5. Fractional and DCO modes assume that the output dividers (Nn/Nd) are configured with a fractional value and the feedback
divider is integer.
25
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • November 30, 2021
25
Si5341/40 Rev D Data Sheet • Electrical Specifications
Table 5.9. I2C Timing Specifications (SCL,SDA)
Parameter
Symbol
Test Condition
Standard Mode
Fast Mode
100 kbps
400 kbps
Min
Max
Min
Max
Units
SCL Clock Frequency
fSCL
—
100
—
400
kHz
Hold Time (Repeated)
START Condition
tHD:STA
4.0
—
0.6
—
μs
Low Period of the SCL Clock
tLOW
4.7
—
1.3
—
μs
HIGH Period of the SCL
Clock
tHIGH
4.0
—
0.6
—
μs
Set-up Time for a Repeated
START Condition
tSU:STA
4.7
—
0.6
—
μs
Data Hold Time
tHD:DAT
100
—
100
—
ns
Data Set-up Time
tSU:DAT
250
—
100
—
ns
Rise Time of Both SDA and
SCL Signals
tr
—
1000
20
300
ns
Fall Time of Both SDA and
SCL Signals
tf
—
300
—
300
ns
Set-up Time for STOP Condition
tSU:STO
4.0
—
0.6
—
μs
Bus Free Time between a
STOP and START Condition
tBUF
4.7
—
1.3
—
μs
Data Valid Time
tVD:DAT
—
3.45
—
0.9
μs
Data Valid Acknowledge
Time
tVD:ACK
—
3.45
—
0.9
μs
26
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • November 30, 2021
26
Si5341/40 Rev D Data Sheet • Electrical Specifications
Figure 5.1. I2C Serial Port Timing Standard and Fast Modes
27
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • November 30, 2021
27
Si5341/40 Rev D Data Sheet • Electrical Specifications
Table 5.10. SPI Timing Specifications (4-Wire)
(VDD=1.8 V ± 5%, VDDA=3.3 V ± 5%, TA= –40 to 85 °C)
Parameter
Symbol
Min
Typ
Max
Units
SCLK Frequency
fSPI
—
—
20
MHz
SCLK Duty Cycle
TDC
40
—
60
%
SCLK Period
TC
50
—
—
ns
Delay Time, SCLK Fall to SDO Active
TD1
—
12.5
18
ns
Delay Time, SCLK Fall to SDO
TD2
—
10
15
ns
Delay Time, CSb Rise to SDO Tri-State
TD3
—
10
15
ns
Setup Time, CSb to SCLK
TSU1
5
—
—
ns
Hold Time, SCLK Fall to CSb
TH1
5
—
—
ns
Setup Time, SDI to SCLK Rise
TSU2
5
—
—
ns
Hold Time, SDI to SCLK Rise
TH2
5
—
—
ns
Delay Time Between Chip Selects (CSb)1
TCS
2
—
—
TC
Note:
1. The minimum time is based on 20 MHz SPI clock (50 ns). So the minimum wait time between two frames should be 2*50 ns =
100 ns.
TSU1
TC
TD1
SCLK
TH1
CSb
TSU2
TH2
TCS
SDI
TD2
TD3
SDO
Figure 5.2. 4-Wire SPI Serial Interface Timing
28
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • November 30, 2021
28
Si5341/40 Rev D Data Sheet • Electrical Specifications
Table 5.11. SPI Timing Specifications (3-Wire)
(VDD=1.8 V ± 5%, VDDA= 3.3 V ± 5%, TA= –40 to 85 °C)
Parameter
Symbol
Min
Typ
Max
Units
SCLK Frequency
fSPI
—
—
20
MHz
SCLK Duty Cycle
TDC
40
—
60
%
SCLK Period
TC
50
—
—
ns
Delay Time, SCLK Fall to SDO Turn-on
TD1
—
12.5
20
ns
Delay Time, SCLK Fall to SDO Next-bit
TD2
—
10
15
ns
Delay Time, CSb Rise to SDO Tri-State
TD3
—
10
15
ns
Setup Time, CSb to SCLK
TSU1
5
—
—
ns
Hold Time, SCLK Fall to CSb
TH1
5
—
—
ns
Setup Time, SDI to SCLK Rise
TSU2
5
—
—
ns
Hold Time, SDI to SCLK Rise
TH2
5
—
—
ns
Delay Time Between Chip Selects (CSb)1
TCS
2
—
—
TC
Note:
1. The minimum time is based on 20 MHz SPI clock (50 ns). So the minimum wait time between two frames should be 2*50 ns =
100 ns.
TSU1
TC
SCLK
TD1
CSb
TSU2
TH2
TH1
TD2
TCS
SDIO
TD3
Figure 5.3. 3-Wire SPI Serial Interface Timing
29
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • November 30, 2021
29
Si5341/40 Rev D Data Sheet • Electrical Specifications
Table 5.12. Crystal Specifications
Parameter
Crystal Frequency Range
Symbol
Test Condition
Min
Typ
Max
Units
fXTAL
Full operating range. Jitter performance may be reduced.
24.97
—
54.06
MHz
Range for best jitter.
48
—
54
MHz
Load Capacitance
CL
—
8
—
pF
Crystal Drive Level
dL
—
—
200
μW
rESR
Refer to the Si5341/40 Family Reference Manual to determine ESR and shunt
capacitance.
Equivalent Series Resistance
Shunt Capacitance
CO
Note:
1. Refer to the Si534x/8x Recommended Crystal, TCXO and OCXOs Reference Manual for recommended 48 to 54 MHz crystals.
The Si5341/40 are designed to work with crystals that meet these specifications.
Table 5.13. Thermal Characteristics
Parameter
Symbol
Test Condition1
Value
Units
ϴJA
Still Air
22
°C/W
Air Flow 1 m/s
19.4
Air Flow 2 m/s
18.3
Si5341 - 64QFN
Thermal Resistance
Junction to Ambient
Thermal Resistance
ϴJC
9.5
Thermal Resistance
ϴJB
9.4
Junction to Board
ΨJB
9.3
Thermal Resistance
ΨJT
0.2
Junction to Case
Junction to Top Center
Si5340 - 44QFN
Thermal Resistance
ϴJA
Junction to Ambient
Thermal Resistance
Still Air
22.3
Air Flow 1 m/s
19.4
Air Flow 2 m/s
18.4
ϴJC
10.9
Thermal Resistance
ϴJB
9.3
Junction to Board
ΨJB
9.2
Thermal Resistance
ΨJT
0.23
°C/W
Junction to Case
Junction to Top Center
Note:
1. Based on PCB Dimension: 3" x 4.5", PCB Land/Via under GND pad: 36, Number of Cu Layers: 4
30
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • November 30, 2021
30
Si5341/40 Rev D Data Sheet • Electrical Specifications
Table 5.14. Absolute Maximum Ratings1, 2, 3, 4, 5
Parameter
Symbol
Test Condition
Value
Units
Storage Temperature Range
TSTG
-55 to +150
°C
DC Supply Voltage
VDD
-0.5 to 3.8
V
VDDA
-0.5 to 3.8
V
VDDO
-0.5 to 3.8
V
Input Voltage Range
Latch-up Tolerance
VI1
IN0-IN2, FB_IN
-1.0 to 3.8
V
VI2
IN_SEL[1:0], RSTb, OEb,
SYNCb, I2C_SEL, SDI, SCLK,
A0/CSb, A1, SDA/SDIO, FINC/
FDEC
-0.5 to 3.8
V
VI3
XA/XB
-0.5 to 2.7
V
LU
ESD Tolerance
HBM
Maximum Junction Temperature in Operation
Soldering Temperature (Pb-free profile)5
Soldering Temperature Time at TPEAK
JESD78 Compliant
100 pF, 1.5 kΩ
2.0
kV
TJCT
125
°C
TPEAK
260
°C
TP
20 to 40
sec
(Pb-free profile)5
Notes:
1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be restricted
to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
2. 64-QFN and 44-QFN packages are RoHS-6 compliant.
3. Moisture sensitivity level is MSL2. For more packaging information, go to the Skyworks RoHS information page.
4. The minimum voltage at these pins can be as low as –1.0 V when an AC input signal of 10 MHz or greater is applied. See Table
5.3 Input Clock Specifications on page 19 spec for single-ended AC-coupled fIN < 250 MHz.
5. The device is compliant with JEDEC J-STD-020.
31
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • November 30, 2021
31
Si5341/40 Rev D Data Sheet • Typical Application Schematic
6. Typical Application Schematic
161.1328125
MHz
Buffer
Buffer
2x 161.1328125 MHz
LVDS
133.33 MHz
2x 133.33 MHz
1.8V LVCMOS
Buffer
Level
Translator
3x 125 MHz
LVPECL
125 MHz
Buffer
Clock
Generator
Level
Translator
XA
4x 125 MHz
3.3V LVCMOS
200 MHz
2.5V LVCMOS
25 MHz
XB
“Traditional Discrete” Clock Tree
One Si5341 replaces:
3x crystal oscillators (XO)
2x buffers
1x Clock Generator
2x level translators
1x 161.1328125 MHz
LVDS
1x 161.1328125 MHz
LVDS
XA
2x 133.33 MHz
1.8V LVCMOS
25 MHz
XB
1x 125 MHz
LVPECL
Si5341
1x 125 MHz
LVPECL
1x 125 MHz
LVPECL
2x 125 MHz
3.3V LVCMOS
2x 125 MHz
3.3V LVCMOS
“Clock Tree
On-a-Chip”
2x 200 MHz
2.5V LVCMOS
2x 200 MHz
2.5V LVCMOS
Figure 6.1. Using the Si5341 to Replace a Traditional Clock Tree
32
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • November 30, 2021
32
Si5341/40 Rev D Data Sheet • Detailed Block Diagrams
VDD
VDDA
7. Detailed Block Diagrams
3
Si5341
IN_ SEL[1:0]
Clock
Generator
÷P0
PD
÷P2
IN2b
LPF
÷
÷ PXAXB
Mn
Md
MultiSynth
N
÷ 0n
N0d
XB
25-54 MHz
XTAL
OSC
XA
N
÷ 1n
N1d
Zero Delay
Mode
÷
FB_IN
÷Pfb
FB_ INb
÷
I2C_ SEL
RSTb
A0/CSb
NVM
Status
Monitors
N2n
N2d
N3n
N3d
N4n
N4d
÷R2
VDDO2
OUT2
OUT2b
÷R3
VDDO3
OUT3
OUT3b
÷R4
VDDO4
OUT4
OUT4b
÷R5
VDDO5
OUT5
OUT5b
÷R6
VDDO6
OUT6
OUT6b
÷R7
VDDO7
OUT7
OUT7b
÷R8
VDDO8
OUT8
OUT8b
÷R9
VDDO9
OUT9
OUT9b
Frequency
Control
FINC
SCLK
SPI /
I2 C
INTRb
A1/ SDO
÷
LO Lb
SDA/ SDIO
÷R1
VDDO1
OUT1
OUT1b
PLL
÷P1
IN2
VDDO0
OUT0
OUT0b
OEb
IN1
IN1b
FDEC
IN0b
÷R0
SYNCb
IN0
Dividers/
Drivers
Figure 7.1. Si5341 Block Diagram
33
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • November 30, 2021
33
4
VDDS
VDDA
VDD
Si5341/40 Rev D Data Sheet • Detailed Block Diagrams
2
1
Si5340
Clock
Generator
÷P XAXB
XB
25-54 MHz
XTAL
OSC
XA
MultiSynth
÷
Nn0
Nd0
÷R0
VDDO0
OUT0
OUT0b
÷
Nn1
Nd1
÷R1
VDDO1
OUT1
OUT1b
N
÷ 2n
N2d
÷R2
VDDO2
OUT2
OUT2b
N3n
N3d
÷R3
VDDO3
OUT3
OUT3b
PLL
IN0
IN0b
IN1
IN1b
IN2
IN2b
Dividers/
Drivers
÷P0
÷P1
LPF
PD
Md
÷
Mn
÷P2
÷
IN_SEL[1:0]
Zero Delay
Mode
OEb
SCLK
NVM
A0/CSb
A1/SDO
I2C_SEL
LOSXAB
SDA/SDIO
SPI/
I2 C
Status
Monitors
LO Lb
RSTb
÷Pfb
I NT Rb
FB_IN
FB_INB
Figure 7.2. Si5340 Detailed Block Diagram
34
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • November 30, 2021
34
Si5341/40 Rev D Data Sheet • Typical Operating Characteristics
8. Typical Operating Characteristics
Figure 8.1. Integer Mode--48 MHz Crystal, 625 MHz Output (2.5 V LVDS)
35
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • November 30, 2021
35
Si5341/40 Rev D Data Sheet • Typical Operating Characteristics
Figure 8.2. Integer Mode--48 MHz Crystal, 156.25 MHz Output (2.5 V LVDS)
Figure 8.3. Fractional Mode--48 MHz Crystal, 155.52 MHz Output (2.5 V LVDS)
36
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • November 30, 2021
36
Si5341/40 Rev D Data Sheet • Pin Descriptions
9. Pin Descriptions
37
OUT3
OUT3b
VDDO3
36
35
34
VDD
I2C_SEL
IN_SEL1
FB_IN
VDD
41
38
FB_INb
42
39
IN0b
IN0
VDDO7
49
43
OUT7b
50
44
VDDO8
OUT7
51
OUT8b
Si 5340 44QFN
Top View
52
53
RSVD
56
RSVD
VDDO9
57
OUT8
OUT9
OUT9b
59
54
VDD
60
55
FB_IN
61
58
IN0
FB_INb
62
IN0b
63
64
Si 5341 64QFN
Top View
FINC
48
2
47
LOLb
IN_ SEL0
3
46
VDD
IN1
1
33
INTRb
IN_ SEL1
4
45
OUT 6
IN1b
2
32
SYNCb
5
44
OUT6b
IN_ SEL0
3
31
VDD
OUT2
RSTb
6
43
VDDO6
4
30
OUT2b
X1
7
42
OUT5
X1
XA
29
VDDO2
41
OUT5b
5
8
XA
XB
40
VDDO 5
6
9
XB
X2
VDDA
7
8
26
VDDS
VDDA
9
25
OUT1
IN2
10
24
OUT1b
IN2b
11
23
VDDO1
22
NC
32
VDD
21
31
OUT2
20
30
OUT2b
OUT0
VDD
29
19
28
OUT1
VDDO2
OUT0b
27
OUT1b
18
26
VDDO1
17
25
23
OUT0b
24
22
VDDO0
OUT0
21
FDEC
20
VDDO 3
RSVD
OUT3b
33
RSVD
34
16
19
15
A0/CSb
IN2b
SCLK
18
OUT3
17
35
A1/SDO
14
SDA/SDIO
IN2
RSTb
VDDO4
VDDO0
OUT4b
36
16
37
13
A0/CSb
12
VDDA
15
INTRb
14
OUT4
SCLK
I2C_SEL
38
A1/SDO
39
11
13
10
12
X2
OEb
GND
Pad
OEb
SDA/ SDIO
GND
Pad
37
1
40
IN1
IN1b
28
LOS_XAXBb
27
LOLb
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • November 30, 2021
37
Si5341/40 Rev D Data Sheet • Pin Descriptions
Table 9.1. Pin Descriptions
Pin Name
Pin Number
Pin Type1
Si5341
Si5340
XA
8
5
I
XB
9
6
I
X1
7
4
I
X2
10
7
I
IN0
63
43
I
IN0b
64
44
I
IN1
1
1
I
IN1b
2
2
I
IN2
14
10
I
IN2b
15
11
I
FB_IN
61
41
I
FB_INb
62
42
I
Function
Inputs
38
Crystal and External Clock Input. These pins are used to connect an external crystal or an external clock. See 3.3.1 XA/XB
Clock and Crystal Input and Figure 3.2 XAXB External Crystal
and Clock Connections on page 8 for connection information. If
IN_SEL[1:0] = 11b, then the XAXB input is selected. If the XAXB
input is not used and powered down, then both inputs can be left
unconnected. ClockBuilder Pro will power down an input that is
set as "Unused".
XTAL Shield. Connect these pins directly to the XTAL ground
pins. X1, X2, and the XTAL ground pins must not be connected
to the PCB ground plane. DO NOT GROUND THE CRYSTAL
GROUND PINS. Refer to the Si5341/40 Family Reference Manual for layout guidelines. These pins should be left disconnected
when connecting XA/XB pins to an external reference clock.
Clock Inputs. These pins accept both differential and singleended clock signals. Refer 3.3.2 Input Clocks (IN0, IN1, IN2) for
input termination options. These pins are high-impedance and
must be terminated externally. If both the INx and INx (with overstrike) inputs are un-used and powered down, then both inputs
can be left floating. ClockBuilder Pro will power down an input that
is set as "Unused".
External Feedback Input. These pins are used as the external
feedback input (FB_IN/FB_INb) for the optional zero delay mode.
See 3.5.11 Zero Delay Mode for details on the optional zero delay
mode. If FB_IN and FB_IN (with overstrike) are un-used and powered down, then both inputs can be left floating. ClockBuilder Pro
will power down an input that is set as "Unused".
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • November 30, 2021
38
Si5341/40 Rev D Data Sheet • Pin Descriptions
Pin Name
Pin Number
Pin Type1
Function
Output Clocks. These output clocks support a programmable
signal amplitude when configured as a differential output. Desired
output signal format is configurable using register control. Termination recommendations are provided in 3.5.2 Differential Output
Terminations and 3.5.4 LVCMOS Output Terminations. Unused
outputs should be left unconnected.
Si5341
Si5340
OUT0
24
20
O
OUT0b
23
19
O
OUT1
28
25
O
OUT1b
27
24
O
OUT2
31
31
O
OUT2b
30
30
O
OUT3
35
36
O
OUT3b
34
35
O
OUT4
38
—
O
OUT4b
37
—
O
OUT5
42
—
O
OUT5b
41
—
O
OUT6
45
—
O
OUT6b
44
—
O
OUT7
51
—
O
OUT7b
50
—
O
OUT8
54
—
O
OUT8b
53
—
O
OUT9
59
—
O
OUT9b
58
—
O
I2C_SEL
39
38
I
SDA/SDIO
18
13
I/O
Serial Data Interface.2 This is the bidirectional data pin (SDA) for
the I2C mode, or the bidirectional data pin (SDIO) in the 3-wire
SPI mode, or the input data pin (SDI) in 4-wire SPI mode. When
in I2C mode, this pin must be pulled-up using an external resistor
of at least 1 kΩ. No pull-up resistor is needed when in SPI mode.
A1/SDO
17
15
I/O
Address Select 1/Serial Data Output.2 In I2C mode, this pin
functions as the A1 address input pin and does not have an
internal pull up or pull down resistor. In 4-wire SPI mode this is
the serial data output (SDO) pin (SDO) pin and drives high to the
voltage selected by the IO_VDD_SEL pin.
SCLK
16
14
I
Outputs
Serial Interface
39
I2C Select.2 This pin selects the serial interface mode as I2C
(I2C_SEL = 1) or SPI (I2C_SEL = 0). This pin is internally
pulled up by a ~ 20 kΩ resistor to the voltage selected by the
IO_VDD_SEL register bit.
Serial Clock Input.2 This pin functions as the serial clock input for
both I2C and SPI modes.This pin is internally pulled up by a ~20
kΩ resistor to the voltage selected by the IO_VDD_SEL register
bit. In I2C mode this pin should have an external pull up of at least
1 kΩ. No pull-up resistor is needed when in SPI mode.
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • November 30, 2021
39
Si5341/40 Rev D Data Sheet • Pin Descriptions
Pin Name
Pin Number
Pin Type1
Function
Si5341
Si5340
19
16
I
Address Select 0/Chip Select.2 This pin functions as the hardware controlled address A0 in I2C mode. In SPI mode, this pin
functions as the chip select input (active low). This pin is internally
pulled up by a ~20 kΩ resistor to the voltage selected by the
IO_VDD_SEL register bit.
INTRb
12
33
O
Interrupt. 2 This pin is asserted low when a change in device
status has occurred. This interrupt has a push pull output and
should be left unconnected when not in use.
RSTb
6
17
I
Device Reset. 2 Active low input that performs power-on reset
(POR) of the device. Resets all internal logic to a known state and
forces the device registers to their default values. Clock outputs
are disabled during reset. This pin is internally pulled up with a
~20 kΩ resistor to the voltage selected by the IO_VDD_SEL bit.
OEb
11
12
I
Output Enable.2 This pin disables all outputs when held high.
This pin is internally pulled low and can be left unconnected when
not in use.
LOLb
47
—
O
Loss Of Lock.2 This output pin indicates when the DSPLL™ is
locked (high) or out-of-lock (low). An external pull up or pull down
is not needed.
—
27
O
Loss Of Lock.3 This output pin indicates when the DSPLL is
locked (high) or out-of-lock (low). An external pull up or pull down
is not needed.
LOS_XAXBb
—
28
O
Loss Of Signal.3 This output pin indicates a loss of signal at the
XA/XB pins.
SYNCb
5
—
I
Output Clock Synchronization.2 An active low signal on this pin
resets the output dividers for the purpose of re-aligning the output
clocks. For a tighter alignment of the clocks, a soft reset should
be applied. This pin is internally pulled up with a ~20 kΩ resistor
to the voltage selected by the IO_VDD_SEL bit and can be left
unconnected when not in use.
FDEC
25
—
I
Frequency Decrement Pin.2 This pin is used to step-down the
output frequency of a selected output. The affected output driver
and its frequency change step size is register configurable. This
pin is internally pulled low with a ~20 kΩ resistor and can be left
unconnected when not in use.
FINC
48
—
I
Frequency Increment Pin.2 This pin is used to step-up the output frequency of a selected output. The affected output and its
frequency change step size is register configurable. This pin is
internally pulled low with a ~20 kΩ resistor and can be left unconnected when not in use.
IN_SEL0
3
3
I
IN_SEL1
4
37
I
Input Reference Select.2 The IN_SEL[1:0] pins are used in the
manual pin controlled mode to select the active clock input. These
pins are internally pulled up with a ~20 kΩ resistor to the voltage
selected by the IO_VDD_SEL bit and can be left unconnected
when not in use.
A0/CSb
Control/Status
40
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • November 30, 2021
40
Si5341/40 Rev D Data Sheet • Pin Descriptions
Pin Name
Pin Number
Function
Pin Type1
Si5341
Si5340
20
—
—
21
—
—
55
—
—
56
—
—
—
22
—
No Connect. These pins are not connected to the die. Leave
disconnected.
32
21
P
46
32
Core Supply Voltage. The device core operates from a 1.8 V
supply. A 1.0 µf bypass capacitor is recommended.
60
39
—
40
13
8
P
—
9
P
Core Supply Voltage 3.3 V. This core supply pin requires a 3.3 V
power source. A 1.0 µf bypass capacitor is recommended.
VDDS
—
26
P
Status Output Voltage. The voltage on this pin determines the
VOL/VOH on LOLb and LOS_XAXBb status output pins. A 0.1 µf to
1.0 µf bypass capacitor is recommended.
VDDO0
22
18
P
VDDO1
26
23
P
VDDO2
29
29
P
VDDO3
33
34
P
Output Clock Supply Voltage 0–9. Supply voltage (3.3 V, 2.5 V,
1.8 V) for OUTx, OUTx outputs. See the Si5341/40 Family Reference Manual for power supply filtering recommendations. Leave
VDDO pins of unused output drivers unconnected. An alternate
option is to connect the VDDO pin to a power supply and disable
the output driver to minimize current consumption.
VDDO4
36
—
P
VDDO5
40
—
P
VDDO6
43
—
P
VDDO7
49
—
P
VDDO8
52
—
P
VDDO9
57
—
P
RSVD
NC
Reserved. These pins are connected to the die. Leave disconnected.
Power
VDD
VDDA
GND PAD
P
Ground Pad This pad provides electrical and thermal connection
to ground and must be connected for proper operation. Use as
many vias as practical and keep the via length to an internal
ground plan as short as possible.
Note:
1. I = Input, O = Output, P = Power.
2. The IO_VDD_SEL control bit (0x0943 bit 0) selects 3.3 V or 1.8 V operation.
3. The voltage on the VDDS pin(s) determines 3.3 V or 1.8 V operation.
4. Refer to the Family Reference Manual for more information on register setting names.
5. All status pins except I2C and SPI are push-pull.
41
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • November 30, 2021
41
Si5341/40 Rev D Data Sheet • Package Outlines
10. Package Outlines
10.1 Si5341 9x9 mm 64-QFN Package Diagram
The figure below illustrates the package details for the Si5341. The table below lists the values for the dimensions shown in the
illustration.
Figure 10.1. 64-Pin Quad Flat No-Lead (QFN)
Table 10.1. Package Dimensions
Dimension
Min
Nom
Max
A
0.80
0.85
0.90
A1
0.00
0.02
0.05
b
0.18
0.25
0.30
D
D2
9.00 BSC
5.10
5.20
e
0.50 BSC
E
9.00 BSC
5.30
E2
5.10
5.20
5.30
L
0.30
0.40
0.50
aaa
—
—
0.10
bbb
—
—
0.10
ccc
—
—
0.08
ddd
—
—
0.10
eee
—
—
0.05
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-220.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
42
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • November 30, 2021
42
Si5341/40 Rev D Data Sheet • Package Outlines
10.2 Si5340 7x7 mm 44-QFN Package Diagram
The figure below illustrates the package details for the Si5340. The table below lists the values for the dimensions shown in the
illustration.
Figure 10.2. 44-Pin Quad Flat No-Lead (QFN)
Table 10.2. Package Dimensions
Dimension
Min
Nom
Max
A
0.80
0.85
0.90
A1
0.00
0.02
0.05
b
0.18
0.25
0.30
D
D2
7.00 BSC
5.10
5.20
e
0.50 BSC
E
7.00 BSC
5.30
E2
5.10
5.20
5.30
L
0.30
0.40
0.50
aaa
—
—
0.10
bbb
—
—
0.10
ccc
—
—
0.08
ddd
—
—
0.10
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-220.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
43
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • November 30, 2021
43
Si5341/40 Rev D Data Sheet • PCB Land Pattern
11. PCB Land Pattern
The figure below illlustrates the PCB land pattern details for the devices. The table below lists the values for the dimensions shown in
the illustration.
Si5341
Si5340
Figure 11.1. PCB Land Pattern
44
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • November 30, 2021
44
Si5341/40 Rev D Data Sheet • PCB Land Pattern
Table 11.1. PCB Land Pattern Dimensions
Dimension
Si5341 (Max)
Si5340 (Max)
C1
8.90
6.90
C2
8.90
6.90
E
0.50
0.50
X1
0.30
0.30
Y1
0.85
0.85
X2
5.30
5.30
Y2
5.30
5.30
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
3. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition is calculated based on a fabrication
Allowance of 0.05 mm.
Solder Mask Design
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm
minimum, all the way around the pad.
Stencil Design
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
4. A 3×3 array of 1.25 mm square openings on 1.80 mm pitch should be used for the center ground pad.
Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
45
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • November 30, 2021
45
Si5341/40 Rev D Data Sheet • Top Marking
12. Top Marking
Figure 12.1. Si5341-40 Top Markings
Table 12.1. Si5341-40 Top Marking Explanation
Line
Characters
1
Si5341gSi5340g-
Description
Base part number and Device Grade for Low Jitter, Any-Frequency, 10-output Clock
Generator.
Si5341: 10-output, 64-QFN
Si5340: 4-output, 44-QFN
g = Device Grade (A, B, C, D). See 2. Ordering Guide for more information.
– = Dash character.
2
Rxxxxx-GM
R = Product revision. (See ordering guide for current revision).
xxxxx = Customer specific NVM sequence number. Optional NVM code assigned for
custom, factory pre-programmed devices.
Characters are not included for standard, factory default configured devices. See
Ordering Guide for more information.
–GM = Package (QFN) and temperature range (–40 to +85 °C)
3
YYWWTTTTTT
YYWW = Characters correspond to the year (YY) and work week (WW) of package
assembly.
TTTTTT = Manufacturing trace code.
4
46
Circle w/ 1.6 mm (64-QFN) or
1.4 mm (44-QFN) diameter
Pin 1 indicator; left-justified
e4
Pb-free symbol; Center-Justified
TW
TW = Taiwan; Country of Origin (ISO Abbreviation)
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • November 30, 2021
46
Si5341/40 Rev D Data Sheet • Device Errata
13. Device Errata
Please log in or register at http://www.skyworksinc.com to access the device errata document.
47
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • November 30, 2021
47
Si5341/40 Rev D Data Sheet • Revision History
14. Revision History
Revision 1.1
July, 2020
• Updated Figure 3.2 XAXB External Crystal and Clock Connections on page 8.
• Updated Figure 3.4 Supported Differential Output Terminations on page 10.
• Removed "Output Delay Control (t0–t4)" section.
•
•
•
•
•
•
•
•
•
•
Added Zero Delay Mode.
Removed section on Sync Pin (Synchronizing R Dividers).
Updated 4. Register Map.
Removed Addressing Scheme section.
Removed High-Level Register Map section.
Updated Table 5.3 Input Clock Specifications on page 19.
• Updated Input Capacitance specification typical value.
• Updated the Notes section.
• Min input frequency updated to 10 MHz.
Updated Table 5.5 Differential Clock Output Specifications on page 21.
• Updated Output-Output Skew Using Same Multisynth specification typical and max values.
Updated Table 5.6 LVCMOS Clock Output Specifications on page 22.
• Removed Output-to-Output Skew specification.
Updated Table 5.8 Performance Characteristics on page 24.
• Removed Output Delay Adjustment specification.
• Min VCO Frequency Range (FVCO) updated to 13.2 GHz.
Updated Table 5.10 on page 28 SPI Timing Specifications (4-Wire).
• Updated TH1 description for Hold Time to SCLK Fall to CSb.
• Added Note for Delay Time Between Chip Selects (CSb).
• Updated Figure 5.2 4-Wire SPI Serial Interface Timing on page 28.
• Updated Table 5.11 on page 29 SPI Timing Specifications (3-Wire).
• Updated TH1 description for Hold Time to SCLK Fall to CSb.
• Added Note for Delay Time Between Chip Selects (CSb).
• Updated Figure 5.3 3-Wire SPI Serial Interface Timing on page 29.
• Updated Table 5.13 Thermal Characteristics on page 30.
• Updated PCB size from mm to inches.
• Updated Figure 6.1 Using the Si5341 to Replace a Traditional Clock Tree on page 32.
• Removed output delay adjustment features.
• Updated 7. Detailed Block Diagrams.
• Removed Δt blocks from block diagrams.
• Updated Table 10.1 Package Dimensions on page 42 for 64-Pin QFN.
• Max dimension "aaa" updated to 0.10 mm.
• Updated Table 10.2 Package Dimensions on page 43 for 44-Pin QFN.
• Max dimension "aaa" updated to 0.10 mm.
Revision 1.0
July, 2016
• Initial release. (See "AN1006: Differences between Si534x/8x Revision B and Revision D Silicon" for a list of changes from Rev B to
Rev D.)
48
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • November 30, 2021
48
ClockBuilder Pro
Customize Skyworks clock generators,
jitter attenuators and network
synchronizers with a single tool. With
CBPro you can control evaluation
boards, access documentation, request
a custom part number, export for
in-system programming and more!
www.skyworksinc.com/CBPro
Portfolio
SW/HW
Quality
Support & Resources
www.skyworksinc.com/ia/timing
www.skyworksinc.com/CBPro
www.skyworksinc.com/quality
www.skyworksinc.com/support
Copyright © 2021 Skyworks Solutions, Inc. All Rights Reserved.
Information in this document is provided in connection with Skyworks Solutions, Inc. (“Skyworks”) products or services. These materials, including the
information contained herein, are provided by Skyworks as a service to its customers and may be used for informational purposes only by the customer.
Skyworks assumes no responsibility for errors or omissions in these materials or the information contained herein. Skyworks may change its documentation,
products, services, specifications or product descriptions at any time, without notice. Skyworks makes no commitment to update the materials or
information and shall have no responsibility whatsoever for conflicts, incompatibilities, or other difficulties arising from any future changes.
No license, whether express, implied, by estoppel or otherwise, is granted to any intellectual property rights by this document. Skyworks assumes no liability
for any materials, products or information provided hereunder, including the sale, distribution, reproduction or use of Skyworks products, information or
materials, except as may be provided in Skyworks’ Terms and Conditions of Sale.
THE MATERIALS, PRODUCTS AND INFORMATION ARE PROVIDED “AS IS” WITHOUT WARRANTY OF ANY KIND, WHETHER EXPRESS, IMPLIED, STATUTORY, OR
OTHERWISE, INCLUDING FITNESS FOR A PARTICULAR PURPOSE OR USE, MERCHANTABILITY, PERFORMANCE, QUALITY OR NON-INFRINGEMENT OF ANY
INTELLECTUAL PROPERTY RIGHT; ALL SUCH WARRANTIES ARE HEREBY EXPRESSLY DISCLAIMED. SKYWORKS DOES NOT WARRANT THE ACCURACY OR
COMPLETENESS OF THE INFORMATION, TEXT, GRAPHICS OR OTHER ITEMS CONTAINED WITHIN THESE MATERIALS. SKYWORKS SHALL NOT BE LIABLE FOR
ANY DAMAGES, INCLUDING BUT NOT LIMITED TO ANY SPECIAL, INDIRECT, INCIDENTAL, STATUTORY, OR CONSEQUENTIAL DAMAGES, INCLUDING WITHOUT
LIMITATION, LOST REVENUES OR LOST PROFITS THAT MAY RESULT FROM THE USE OF THE MATERIALS OR INFORMATION, WHETHER OR NOT THE RECIPIENT
OF MATERIALS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Skyworks products are not intended for use in medical, lifesaving or life-sustaining applications, or other equipment in which the failure of the Skyworks
products could lead to personal injury, death, physical or environmental damage. Skyworks customers using or selling Skyworks products for use in such
applications do so at their own risk and agree to fully indemnify Skyworks for any damages resulting from such improper use or sale.
Customers are responsible for their products and applications using Skyworks products, which may deviate from published specifications as a result of
design defects, errors, or operation of products outside of published parameters or design specifications. Customers should include design and operating
safeguards to minimize these and other risks. Skyworks assumes no liability for applications assistance, customer product design, or damage to any
equipment resulting from the use of Skyworks products outside of Skyworks’ published specifications or parameters.
Skyworks, the Skyworks symbol, Sky5®, SkyOne®, SkyBlue™, Skyworks Green™, Clockbuilder®, DSPLL®, ISOmodem®, ProSLIC®, and SiPHY® are trademarks or
registered trademarks of Skyworks Solutions, Inc. or its subsidiaries in the United States and other countries. Third-party brands and names are for
identification purposes only and are the property of their respective owners. Additional information, including relevant terms and conditions, posted at
www.skyworksinc.com, are incorporated by reference.
Skyworks Solutions, Inc. | Nasdaq: SWKS | sales@skyworksinc.com | www.skyworksinc.com
USA: 781-376-3000 | Asia: 886-2-2735 0399 | Europe: 33 (0)1 43548540 |
工商网监
湘ICP备2023018690号
