SI5350A-A-GTR

Si5350A F ACTORY - P ROGRAMMABLE A NY - F REQUENCY CMOS C L O C K G ENERATOR Features          Generates up to 8 non-integer-related frequencies from 8 kHz to 160 MHz Exact frequency synthesis at each output (0 ppm error) Glitchless frequency changes Low output period jitter: 100 ps pp Configurable Spread Spectrum selectable at each output User-configurable control pins: Output Enable (OEB_0/1/2) Power Down (PDN) Frequency Select (FS_0/1) Spread Spectrum Enable (SSEN) Supports static phase offset Rise/fall time control       Operates from a low-cost, fixed frequency crystal: 25 or 27 MHz Separate voltage supply pins: Core VDD: 2.5 V or 3.3 V Output VDDO: 2.5 V or 3.3 V Excellent PSRR eliminates external power supply filtering Very low power consumption ( 1 MHz — 2 10 ms Power-Down Time TPD From VDD = VDDmin, CL = 5 pF, fCLKn > 1 MHz — 5 100 ms Output Enable Time TOE From OEB assertion to valid clock output, CL = 5 pF, fCLKn > 1 MHz — — 10 µs Output Frequency Transition Time TFREQ fCLKn > 1 MHz — — 10 µs Spread Spectrum Frequency Deviation SSDEV Down spread –0.5 — –2.5 % Spread Spectrum Modulation Rate SSMOD 30 31.5 33 kHz 4 Rev. 0.9 Si5350A Table 4. Input Characteristics (VDD = 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C) Parameter Symbol Min Typ Max Units fXTAL 25 — 27 MHz P0-P4 Input Low Voltage VIL-P0-4 –0.1 — 0.3 x VDD V P0-P4 Input High Voltage VIH_P0-4 0.7 x VDD — 3.60 V Crystal Frequency Test Condition Table 5. Output Characteristics (VDD = 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Units 0.008 — 160 MHz Frequency Range FCLK Load Capacitance CL FCLK < 100 MHz — 5 15 pF Duty Cycle DC Measured at VDD/2 45 50 55 % Rise/Fall Time tr/tf 20%–80%, CL = 5 pF 0.5 1 1.5 ns Output High Voltage VOH VDD – 0.6 — — V Output Low Voltage VOL — — 0.6 V Period Jitter JPER Measured over 10k cycles — 60 100 ps pk-pk Cycle-to-Cycle Jitter JCC Measured over 10k cycles — 50 90 ps pk JRMS 12 kHz–20 MHz — 5.0 10 ps rms RMS Phase Jitter Table 6. 25 MHz Crystal Requirements1,2 Parameter Symbol Min Typ Max Unit Crystal Frequency fXTAL — 25 — MHz Load Capacitance CL 6 — 12 pF rESR — — 150  dL — — 150 µW Equivalent Series Resistance Crystal Max Drive Level Notes: 1. Crystals which require load capacitances of 6, 8, or 10 pF should use the device’s internal load capacitance for optimum performance. See register 183 bits 7:6. A crystal with a 12 pF load capacitance requirement should use a combination of the internal 10 pF load capacitors in addition to external 2 pF load capacitors. Adding external 2 pF load capacitors can minimize jitter by 20%. 2. Refer to “AN551: Crystal Selection Guide” for more details. Rev. 0.9 5 Si5350A Table 7. 27 MHz Crystal Requirements1,2 Parameter Symbol Min Typ Max Unit Crystal Frequency fXTAL — 27 — MHz Load Capacitance CL 6 — 12 pF Equivalent Series Resistance rESR — — 150  Crystal Max Drive Level Spec dL — — 150 µW Notes: 1. Crystals which require load capacitances of 6, 8, or 10 pF should use the device’s internal load capacitance for optimum performance. See register 183 bits 7:6. A crystal with a 12 pF load capacitance requirement should use a combination of the internal 10 pF load capacitors in addition to external 2 pF load capacitors. Adding external 2 pF load capacitors can minimize jitter by 20%. 2. Refer to “AN551: Crystal Selection Guide” for more details. Table 8. Thermal Characteristics Parameter Thermal Resistance Junction to Ambient Thermal Resistance Junction to Case Symbol Test Condition JA Still Air JC Still Air Package Value Unit 10-MSOP 131 °C/W 24-QSOP 80 °C/W 20-QFN 51 °C/W 10-MSOP 43 °C/W 24-QSOP 31 °C/W 20-QFN 16 °C/W Value Unit –0.5 to 3.8 V Table 9. Absolute Maximum Ratings Parameter Symbol DC Supply Voltage VDD_max Input Voltage Junction Temperature Test Condition VIN_P1-4 Pins P1, P2, P3, P4 –0.5 to 3.8 V VIN_P0 P0 –0.5 to (VDD+0.3) V VIN_XA/B Pins XA, XB –0.5 to 1.3 V V –55 to 150 °C TJ Note: Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 6 Rev. 0.9 Si5350A 2. Typical Application 2.1. Si5350A Replaces Multiple Clocks and XOs The Si5350A is a user-definable custom clock generator that is ideally suited for replacing crystals and crystal oscillators in cost-sensitive applications. An example application is shown in Figure 1. 74.25 MHz or 74.25 MHz 1.001 33.3333 MHz CPU XA 27 MHz Video Processor CLK2 CLK1 CLK0 27 MHz Si5350A CLK3 24.576 MHz CLK4 22.5792 MHz Audio Processor XB Ethernet PHY 125 MHz CLK5 48 MHz CLK6 CLK7 USB Controller 28.322 MHz HDMI Port Figure 1. Example of an Si5350A in an Audio/Video Application 2.2. Replacing a Crystal with a Clock The Si5350A can be driven with a clock signal through the XA input pin. VIN = 1 VPP 25/27 MHz XA 0.1 µF XB PLLA Multi Synth 0 Multi Synth 1 OSC PLLB Note: Float the XB input while driving the XA input with a clock Multi Synth N Figure 2. Si5350A Driven by a Clock Signal Rev. 0.9 7 Si5350A 2.3. HCSL Compatible Outputs The Si5350A can be configured to support HCSL compatible swing when the VDDO of the output pair of interest is set to 2.5 V (i.e., VDDOA must be 2.5 V when using CLK0/1; VDDOB must be 2.5 V for CLK2/3 and so on). The circuit in the figure below must be applied to each of the two clocks used, and one of the clocks in the pair must also be inverted to generate a differential pair. ZO = 70  PLLA Multi Synth 0 0 R1 511  240  OSC PLLB Multi Synth 1 ZO = 70  0 R1 511  240  Multi Synth N R2 Note: The complementary -180 degree out of phase output clock is generated using the INV function Figure 3. Si5350A Output is HCSL Compatible 8 R2 Rev. 0.9 HCSL CLKIN Si5350A 3. Functional Description The Si5350A’s synthesis architecture consists of two high-frequency PLLs in addition to one high-resolution fractional MultiSynthTM divider per output. A block diagram of both the 3-output and 8-output versions are shown in Figure 4. This unique architecture allows the Si5350A to generate up to eight independent, non-integer-related frequencies at any of its outputs. Each MultiSynthTM is configurable with two frequencies (F1_x, F2_x). This allows a pin controlled glitchless frequency change at each output (CLK0 to CLK5). 10-MSOP XA OSC VDDO VDD MultiSynth 0 F1_0 PLL A XB F2_0 R0 CLK0 R1 CLK1 R2 CLK2 FS MultiSynth 1 F1_1 PLL B F2_1 FS P0 P1 MultiSynth 2 F1_2 Control Logic F2_2 FS MultiSynth 3 GND VDD 20-QFN, 24-QSOP MultiSynth 0 F1_0 F2_0 XA OSC PLL A CLK0 FS MultiSynth 1 F1_1 XB PLL B VDDOA R0 F2_1 CLK1 R1 FS MultiSynth 2 F1_2 F2_2 VDDOB R2 CLK2 FS MultiSynth 3 F1_3 F2_3 CLK3 R3 FS MultiSynth 4 F1_4 F2_4 VDDOC R4 CLK4 FS MultiSynth 5 F1_5 P0 F2_5 P1 P2 CLK5 R5 FS Control Logic F1_6 P3 VDDOD MultiSynth 6 R6 CLK6 P4 MultiSynth 7 F1_7 CLK7 R7 GND Figure 4. Block Diagrams of 3-Output and 8-Output Si5350A Devices Rev. 0.9 9 Si5350A 4. Configuring the Si5350A The Si5350A is a factory-programmed custom clock generator that is user definable with a simple to use webbased utility (www.silabs.com/ClockBuilder). The ClockBuilder utility provides a simple graphical interface that allows the user to enter input and output frequencies along with other custom features as described in the following sections. All synthesis calculations are automatically performed by ClockBuilder to ensure an optimum configuration. A unique part number is assigned to each custom configuration. 4.1. Crystal Inputs (XA, XB) The Si5350A uses a fixed-frequency standard AT-cut crystal as a reference to synthesize its output clocks. 4.1.1. Crystal Frequency The Si5350A can operate using either a 27 MHz or a 25 MHz crystal. 4.1.2. Internal XTAL Load Capacitors Internal load capacitors (CL) are provided to eliminate the need for external components when connecting a XTAL to the Si5350A. Options for internal load capacitors are 6, 8, or 10 pF. XTALs with alternate load capacitance requirements are supported using external load capacitors < 2 pF as shown in Figure 5. CL CL XA XB Optional additional external load capacitors (< 2 pF) CL CL Optional internal load capacitors 6 pF, 8 pF, 10 pF Figure 5. External XTAL with Optional Load Capacitors 4.2. Output Clocks (CLK0–CLK7) The Si5350A is orderable as a 3-output (10-MSOP) or 8-output (24-QSOP, 20-QFN) clock generator. Output clocks CLK0 to CLK5 can be ordered with two clock frequencies (F1_x, F2_x) which are selectable with the optional frequency select pins (FS0/1). See “4.3.3. Frequency Select (FS_0, FS_1)” for more details on the operation of the frequency select pins. 4.2.1. Output Clock Frequency Outputs can be configured at any frequency from 8 kHz up to 100 MHz. In addition, the device can generate any frequency up to 160 MHz on two of its outputs. 4.2.2. .Spread Spectrum Spread spectrum can be enabled on any of the clock outputs that use PLLA as its reference. Spread spectrum is useful for reducing electromagnetic interference (EMI). Enabling spread spectrum on an output clock modulates its frequency, which effectively reduces the overall amplitude of its radiated energy. See “AN554: Si5350/51 PCB Layout Guide” for details. Note that spread spectrum is not available on clocks synchronized to PLLB. The Si5350A supports several levels of spread spectrum allowing the designer to choose an ideal compromise between system performance and EMI compliance. An optional spread spectrum enable pin (SSEN) is configurable to enable or disable the spread spectrum feature. See “4.3.1. Spread Spectrum Enable (SSEN)” for details. 10 Rev. 0.9 Si5350A Reduced Am plitude and EM I Center Frequency Am plitude fc fc No Spread Spectrum D ow n Spread Figure 6. Available Spread Spectrum Profiles 4.2.3. Invert/Non-Invert By default, each of the output clocks are generated in phase (non-inverted) with respect to each other. An option to invert any of the clock outputs is also available. 4.2.4. Output State When Disabled There are up to three output enable pins configurable on the Si5350A as described in “4.3.4. Output Enable (OEB_0, OEB_1, OEB_2)” . The output state when disabled for each of the outputs is configurable as one of the following: disable low, disable high, or disable in high-impedance. 4.2.5. Powering Down Unused Outputs Unused clock outputs can be completely powered down to conserve power. 4.3. Programmable Control Pins (P0–P4) Options Up to five programmable control pins (P0-P4) are configurable allowing direct pin control of the following features: 4.3.1. Spread Spectrum Enable (SSEN) An optional control pin allows disabling the spread spectrum feature for all outputs that were configured with spread spectrum enabled. Hold SSEN low to disable spread spectrum. The SSEN pin provides a convenient method of evaluating the effect of using spread spectrum clocks during EMI compliance testing. 4.3.2. Power Down (PDN) An optional power down control pin allows a full shutdown of the Si5350A to minimize power consumption when its output clocks are not being used. The Si5350A is in normal operation when the PDN pin is held low and is in power down mode when held high. Power consumption when the device is in power down mode is indicated in Table 2 on page 4. 4.3.3. Frequency Select (FS_0, FS_1) The Si5350A offers the option of configuring up to two frequencies per clock output on CLK0-CLK5. This is a useful feature for applications that need to support more than one clock rate on the same output. An example of this is shown in Figure 7 where the FS pins selects which frequency is generated from the clock output: F1_0 is generated when FS is set low, and F2_0 is generated when FS is set high. 27 MHz 74.25 MHz FS0 Bit Level Output Frequency Selected 0 F1_0: 74.25 MHz 1 F2_0: 74.25 MHz 1.001 XA XB or 74.25 MHz 1.001 FS0 Si5350A CLK0 Video Processor Figure 7. Example of Generating Two Clock Frequencies from the Same Clock Output Rev. 0.9 11 Si5350A Up to two frequency select pins are available on the Si5350A. Each of the frequency select pins can be linked to any of the clock outputs as shown in Figure 8. For example, FS_0 can be linked to control clock frequency selection on CLK0, CLK3, and CLK5; FS_1 can be used to control clock frequency selection on CLK1, CLK2, and CLK4. Any other combination is also possible. The Si5350A uses control circuitry to ensure that frequency changes are glitchless. This ensures that the clock always completes its last cycle before starting a new clock cycle of a different frequency. Customizable FS Control FS FS FS_0 Output Frequency 0 F1_0, F1_3, F1_5 1 F2_0, F2_3, F2_5 FS_0 FS FS FS FS_1 Output Frequency 0 F1_1, F1_2, F1_4 1 F2_1, F2_2, F2_4 FS_1 FS Glitchless Frequency Changes MultiSynth 0 CLK0 MultiSynth 1 CLK1 MultiSynth 2 CLK2 MultiSynth 3 CLK3 MultiSynth 4 CLK4 MultiSynth 5 CLK5 New frequency starts at its leading edge Frequency_A Frequency_B Frequency_A CLKx Cannot be controlled by FS pins Full cycle completes before changing to a new frequency CLK6 CLK7 Figure 8. Example Configuration of a Pin-Controlled Frequency Select (FS) 4.3.4. Output Enable (OEB_0, OEB_1, OEB_2) Up to three output enable pins (OEB_0/1/2) are available on the Si5350A. Similar to the FS pins, each OEB pin can be linked to any of the output clocks. In the example shown in Figure 9, OEB_0 is linked to control CLK0, CLK3, and CLK5; OEB_1 is linked to control CLK6 and CLK7, and OEB_2 is linked to control CLK1, CLK2, CLK4, and CLK5. Any other combination is also possible. If more than one OEB pin is linked to the same CLK output, the pin forcing a disable state will be dominant. Clock outputs are enabled when the OEB pin is held low. The output enable control circuitry ensures glitchless operation by starting the output clock cycle on the first leading edge after OEB is asserted (OEB = low). When OEB is released (OEB = high), the clock is allowed to complete its full clock cycle before going into a disabled state. This is shown in Figure 9. When disabled, the output state is configurable as disabled high, disabled low, or disabled in high-impedance. Customizable OEB Control Glitchless Output Enable CLK0 OEB_0 0 1 Output State CLK Enabled CLK Disabled OEB OEB_0 CLK1 OEB Clock starts on the first leading edge CLK2 OEB OEB_1 0 1 Output State CLK Enabled CLK Disabled Clock continues until cycle is complete CLK3 OEB_1 CLKx OEB CLK4 OEBx OEB CLK5 OEB OEB_2 0 1 Output State CLK Enabled CLK Disabled CLK6 OEB_2 OEB CLK7 OEB Figure 9. Example Configuration of a Pin-Controlled Output Enable 12 Rev. 0.9 Si5350A 4.4. Design Considerations The Si5350A is a self-contained clock generator that requires very few external components. The following general guidelines are recommended to ensure optimum performance. 4.4.1. Power Supply Decoupling/Filtering The Si5350A has built-in power supply filtering circuitry to help keep the number of external components to a minimum. All that is recommended is one 0.1 µF decoupling capacitor per power supply pin. This capacitor should be mounted as close to the VDD and VDDO pins as possible without using vias. 4.4.2. Power Supply Sequencing The VDD and VDDOx (i.e., VDDO0, VDDO1, VDDO2, VDDO3) power supply pins have been separated to allow flexibility in output signal levels. It is important that power is applied to all supply pins (VDD, VDDOx) at the same time. Unused VDDOx pins should be tied to VDD. 4.4.3. External Crystal The external crystal should be mounted as close to the pins as possible using short PCB traces. The XA and XB traces should be kept away from other high-speed signal traces. See “AN551: Crystal Selection Guide” for more details. 4.4.4. External Crystal Load Capacitors The Si5350A provides the option of using internal and external crystal load capacitors. If external load capacitors are used, they should be placed as close to the XA/XB pads as possible. See “AN551: Crystal Selection Guide” for more details. 4.4.5. Unused Pins Unused control pins (P0–P4) should be tied to GND. Unused output pins (CLK0–CLK7) should be left floating. 4.4.6. Trace Characteristics The Si5350A features various output current drives ranging from 2 to 8 mA (default). It is recommended to configure the trace characteristics as shown in Figure 10 when an output drive setting of 8 mA is used. ZO = 85 ohms R = 0 ohms CLK (Optional resistor for EMI management) Length = No Restrictions Figure 10. Recommended Trace Characteristics with 8 mA Drive Strength Setting Note: Jitter is only specified at 6 and 8 mA drive strength. Rev. 0.9 13 Si5350A 5. Pin Descriptions (20-Pin QFN, 24-Pin QSOP) XB P0 16 CLK6 17 CLK5 2 GND PAD 3 Si5350A 24-QSOP (Top View) CLK5 1 24 CLK6 VDDOC 2 23 CLK7 CLK4 3 22 VDD0D 15 CLK7 VDD 4 21 CLK0 14 VDDOD GND 5 20 CLK1 XA 6 19 GND XB 7 18 VDDOA GND 8 17 GND P0 9 16 VDD0B P1 10 15 CLK2 P2 11 14 CLK3 P3 12 13 P4 1 13 CLK0 11 VDDOA CLK2 CLK3 P4 9 5 VDDOB 10 P2 8 12 CLK1 7 4 6 P1 P3 Pin Name 18 VDDOC 20 VDD XA 19 CLK4 Si5350A 20-QFN (Top View) Pin Number Pin Type* Function 20-QFN 24-QSOP XA 1 6 I Input pin for external XTAL XB 2 7 I Input pin for external XTAL CLK0 13 21 O Output clock 0 CLK1 12 20 O Output clock 1 CLK2 9 15 O Output clock 2 CLK3 8 14 O Output clock 3 CLK4 19 3 O Output clock 4 CLK5 17 1 O Output clock 5 CLK6 16 24 O Output clock 6 CLK7 15 23 O Output clock 7 P0 3 9 I User configurable input pin 0. See 4.4.5. P1 4 10 I User configurable input pin 1. See 4.4.5. P2 5 11 I User configurable input pin 2. See 4.4.5. P3 6 12 I User configurable input pin 3. See 4.4.5. P4 7 13 I User configurable input pin 4. See 4.4.5. VDD 20 4 P Core voltage supply pin. See 4.4.2 VDDOA 11 18 P Output voltage supply pin for CLK0 and CLK1. See 4.4.2 VDDOB 10 16 P Output voltage supply pin for CLK2 and CLK3. See 4.4.2 VDDOC 18 2 P Output voltage supply pin for CLK4 and CLK5. See 4.4.2 VDDOD 14 22 P Output voltage supply pin for CLK6 and CLK7. See 4.4.2 GND Center Pad 5, 8, 17, 19 P Ground *Note: I = Input, O = Output, P = Power 14 Rev. 0.9 Si5350A 6. Pin Descriptions (10-Pin MSOP) Si5350A 10-MSOP Top View Pin Name Pin Number VDD 1 10 CLK0 XA 2 9 CLK1 XB 3 8 GND P0 4 7 VDDO P1 5 6 CLK2 Pin Type* Function 10-MSOP XA 2 I Input pin for external XTAL XB 3 I Input pin for external XTAL CLK0 10 O Output clock 0 CLK1 9 O Output clock 1 CLK2 6 O Output clock 2 P0 4 I User configurable input pin 0 P1 5 I User configurable input pin 1 VDD 1 P Core voltage supply pin. See 4.4.2 VDDO 7 P Output clock voltage supply pin for CLK0, CLK1, and CLK2. See 4.4.2 GND 8 P Ground *Note: I = Input, O = Output, P = Power Rev. 0.9 15 Si5350A 7. Ordering Information Factory programmed Si5350A devices can be requested using the ClockBuilder web-based utility available at: www.silabs.com/ClockBuilder. A unique part number is assigned to each custom configuration as indicated in Figure 11. Si5350A AXXXXX XX GT - 10-MSOP GM - 20-QFN GU – 24-QSOP A = Product Revision A XXXXX = Unique Custom Code. A five character code will be assigned for each unique custom configuration Figure 11. Custom Clock Part Numbers An evaluation kit containing ClockBuilder Desktop software and hardware allows easy evaluation of the Si5350A. 16 Rev. 0.9 Si5350A 8. Package Outline (24-Pin QSOP) Table 10. 24-QSOP Package Dimensions Dimension Min Nom Max A — — 1.75 A1 0.10 — 0.25 b 0.19 — 0.30 c 0.15 — 0.25 D 8.55 8.65 8.75 E E1 6.00 BSC 3.81 3.90 e L 0.635 BSC 0.40 — L2 q 3.99 1.27 0.25 BSC 0 — aaa 0.10 bbb 0.17 ccc 0.10 8 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to the JEDEC Solid State Outline MO-137, Variation C 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components. Rev. 0.9 17 Si5350A 9. Package Outline (20-Pin QFN)   Table 11. Package Dimensions Dimension A A1 b D D2 e E E2 L aaa bbb ccc ddd eee Min 0.80 0.00 0.18 Nom 0.85 0.02 0.25 4.00 BSC 2.70 0.50 BSC 4.00 BSC 2.70 0.40 2.65 2.65 0.30 Max 0.90 0.05 0.30 2.75 2.75 0.50 0.10 0.10 0.08 0.10 0.10 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to the JEDEC Outline MO-220, variation VGGD-8. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 18 Rev. 0.9 Si5350A 10. Package Outline (10-Pin MSOP)   Table 12. 24-QSOP Package Dimensions Dimension A A1 A2 b c D E E1 e L L2 q aaa bbb ccc ddd Min — 0.00 0.75 0.17 0.08 Nom — — 0.85 — — 3.00 BSC 4.90 BSC 3.00 BSC 0.50 BSC 0.60 0.25 BSC — — — — — 0.40 0 — — — — Max 1.10 0.15 0.95 0.33 0.23 0.80 8 0.20 0.25 0.10 0.08 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to the JEDEC Solid State Outline MO-137, Variation C 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. Rev. 0.9 19 Si5350A DOCUMENT CHANGE LIST Revision 0.2 to Revision 0.9  Updated maximum output frequency. Added "2.3. HCSL Compatible Outputs" on page 8.  Updated "4.2.2. .Spread Spectrum" on page 10.  Added "4.4.6. Trace Characteristics" on page 13.  20 Rev. 0.9 Si5350A NOTES: Rev. 0.9 21 Si5350A CONTACT INFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Please visit the Silicon Labs Technical Support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. 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Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. 22 Rev. 0.9