SI5380A-D08751-GMR

Ultra-Low Phase Noise, 12-output JESD204B Clock Generator KEY FEATURES D • DSPLL eliminates external VCXO and analog loop filter components • Supports JESD204B clocking: DCLK and SYSREF • Ultra-low jitter of 65 fs N ew The Si5380 is a high performance, integer-based (M/N) clock generator for small cell applications which demand the highest level of integration and phase noise performance. Based on Silicon Laboratories’ 4th generation DSPLL™ technology, the Si5380 combines frequency synthesis and jitter attenuation in a highly integrated digital solution that eliminates the need for external VCXO and loop filter components. A low-cost, fixed-frequency crystal provides frequency stability for free-run and holdover modes. This all-digital solution provides superior performance that is highly immune to external board disturbances such as power supply noise. es ig ns Si5380 Rev D Data Sheet • Input frequency range: • External Crystal: 54 MHz • Differential: 11.52 MHz to 737.28 MHz • LVCMOS: 11.52 MHz to 245.76 MHz m en de d fo r Applications: • JESD204B clock generation • Remote Radio Units (RRU), Remote Access Networks (RAN), picocells, small cells • Wireless base stations (3G, GSM, W-CDMA, 4G/LTE, LTE-A) • Remote Radio Head (RRH), wireless repeaters, wireless backhaul • Data conversion sampling clocks (ADC, DAC, DDC, DUC) • Output frequency range: • Differential: 480 kHz to 1.47456 GHz • LVCMOS: 480 kHz to 245.76 MHz • Status monitoring • Hitless switching • Si5380: 4 input, 12 output, 64-QFN 9×9 mm 54 MHz XTAL XA XB OSC om IN0 ÷INT IN1 ÷INT IN2 ÷INT ec 4 Input Clocks DSPLL N ot Status Flags I2C / SPI Delay Delay ÷INT R IN3/FB_IN Delay Delay Status Monitor Control silabs.com | Smart. Connected. Energy-friendly. Delay NVM ÷INT OUT0A ÷INT OUT0 ÷INT OUT1 ÷INT OUT2 ÷INT OUT3 ÷INT OUT4 ÷INT OUT5 ÷INT OUT6 ÷INT OUT7 ÷INT OUT8 ÷INT OUT9 ÷INT OUT9A Device and System Clocks Si5380 Rev. 1.0 Si5380 Rev D Data Sheet Feature List 1. Feature List The Si5380-D features are listed below: D • • • • • Adjustable output-output delay: 68 ps/step, ±128 steps Optional Zero Delay mode Independent output clock supply pins: 3.3, 2.5, or 1.8 V Core voltage: • VDD = 1.8 V ±5% • VDDA = 3.3 V ±5% Automatic free-run, lock, and holdover modes Programmable jitter attenuation bandwidth: 0.1 Hz to 100 Hz Hitless input clock switching Status monitoring (LOS, OOF, LOL) Serial interface: I2C or SPI In-circuit programmable with nonvolatile OTP memory es ig ns • • • • N ew • ClockBuilderTM Pro software tool simplifies device configuration • Si5380: 4 input, 12 output, 64-QFN 9×9 mm • Temperature range: –40 to +85 °C • Pb-free, RoHS-6 compliant N ot R ec om m en de d fo r • Digital frequency synthesis eliminates external VCXO and analog loop filter components • Supports JESD204B clocking: DCLK and SYSREF • Ultra-low jitter: • 65 fs typ (12 kHz to 20 MHz) • Input frequency range: • Differential: 11.52 MHz to 737.28 MHz • LVCMOS: 11.52 MHz to 245.76 MHz • Output frequency range: • Differential: up to 1.47456 GHz • LVCMOS: up to 245.76 MHz • Phase noise floor: –159 dBc/Hz • Spur performance: –103 dBc max (relative to a 122.88 MHz carrier) • Configurable outputs: • Signal swing: 200 to 3200 mVpp • Compatible with LVDS, LVPECL • LVCMOS 3.3, 2.5, or 1.8 V • Output-output skew using same N-divider: 65 ps (Max) silabs.com | Smart. Connected. Energy-friendly. Rev. 1.0 | 1 Si5380 Rev D Data Sheet Ordering Guide 2. Ordering Guide Table 2.1. Ordering Guide Number of Outputs Output Clock Frequency Range Package RoHS-6, Pb-Free 12 0.480 MHz to 1464.56 MHz 64-Lead 9x9 mm QFN Yes Si5380A-D-GM Si5380-D-EVB Evaluation Board Temperature Range es ig ns Ordering Part Number –40 to +85 °C Figure 2.1. Ordering Part Number Fields N ot R ec om m en de d fo r N ew D Note: 1. Add an “R” at the end of the device to denote tape and reel options. 2. Custom, factory pre-programmed devices are available. Ordering part numbers are assigned by ClockBuilder Pro. Part number format is: Si5380A-Dxxxxx-GM, where “xxxxx” is a unique numerical sequence representing the pre-programmed configuration. silabs.com | Smart. Connected. Energy-friendly. Rev. 1.0 | 2 Si5380 Rev D Data Sheet Functional Description 3. Functional Description The Si5380 is a high performance clock generator that is capable of synthesizing up to 10 unique integer related frequencies at any of the device’s 12 outputs. The output clocks can be generated in free-run mode or synchronized to any one of the four external inputs. Clock generation is provided by Silicon Laboratories’ 4th generation DSPLL technology which combines frequency synthesis and jitter attenuation in a highly integrated digital solution that eliminates the need for external VCXO and loop filter components. The Si5380 device is fully configurable using the I2C or SPI serial interface and has in-circuit programmable non-volatile memory. es ig ns 3.1 Frequency Configuration D The DSPLL provides the synthesis for generating the output clock frequencies which are synchronous to the selected input clock frequency or free-running XTAL. It consists of a phase detector, a programmable digital loop filter, a high-performance ultra-low phase noise analog 15 GHz VCO, and a user configurable feedback divider. An internal oscillator (OSC) provides the DSPLL with a stable low-noise clock source for frequency synthesis and for maintaining frequency accuracy in the free-run or holdover modes. The oscillator simply requires an external, low cost 54 MHz fundamental mode crystal to operate. No other external components are required for frequency generation. A key feature of this DSPLL is that it provides immunity to external noise coupling from power supplies and other uncontrolled noise sources that normally exist on printed circuit boards. 3.1.1 Si5380 LTE Frequency Configuration N ot R ec om m en de d fo r N ew The device’s frequency configuration is fully programmable through the serial interface and can also be stored in non-volatile memory. The combination of flexible integer dividers and a high frequency VCO allows the device to generate multiple output clock frequencies for applications that require ultra-low phase noise and spurious performance. At the core of the device are the N dividers which determine the number of unique frequencies that can be generated from the device. The table below shows a list of some possible output frequencies for LTE applications. The Si5380’s DSPLL core can generate up to five unique top frequencies. These frequencies are distributed to the output dividers using a configurable crosspoint mux. The R dividers allow further division for up to 10 unique integer-ratio related frequencies on the Si5380. The ClockBuilder Pro software utility provides a simple means of automatically calculating the optimum divider values (P, M, N and R) for the frequencies listed in the table below. silabs.com | Smart. Connected. Energy-friendly. Rev. 1.0 | 3 Si5380 Rev D Data Sheet Functional Description Table 3.1. Example of Possible LTE Clock Frequencies LTE Device Clock Frequencies Fout (MHz)2 15.36 15.36 19.20 19.20 30.72 30.72 38.40 38.40 61.44 61.44 76.80 76.80 122.88 122.88 153.60 153.60 D es ig ns FIN (MHz)1 184.32 N ew 184.32 245.76 245.76 307.20 307.20 368.64 368.64 614.40 737.28 m en de d — 491.52 fo r 491.52 614.40 737.28 983.04 — 1228.80 — 1474.56 Note: 1. The Si5380 locks to any one of the frequencies listed in the FIN column and generates LTE device clock frequencies. 2. R output dividers allow other frequencies to be generated. These are useful for applications like JESD204B SYSREF clocks. om 3.1.2 Si5380 Configuration for JESD204B Clock Generation N ot R ec The Si5380 can be used as a high performance, fully integrated JEDEC JESD204B jitter cleaner while eliminating the need for discrete VCXO and loop filter components. The Si5380 supports JESD204B subclass 0 and subclass 1 clocking by providing both device clocks (DCLK) and system reference clocks (SYSREF). The 12 clock outputs can be independently configured as device clocks or SYSREF clocks to drive JESD204B converters, FPGAs, or other logic devices. The Si5380 will clock up to four JESD204B targets using four or more DCLKs and four SYSREF clocks with adjustable delay.Each DCLK is grouped with a SYSREF clock in this configuration.If SYSREF clocking is implemented in external logic, then the Si5380 will clock up to 12 JESD204B targets.Not limited to JESD204B applications, each of the 12 outputs is individually configurable as a high performance output for traditional clocking applications. An example of a JESD204B frequency configuration is shown in the figure below. In this case, the N dividers determine the device clock frequency and the R dividers provide the divided SYSREF clock which is used as the lower frequency frame clock. The N divider path also includes a configurable delay path (∆t) for controlling deterministic latency. The example shows a configuration where all the device clocks are controlled by a single delay path (∆t0) while the SYSREF clocks each have their own independent delay paths (∆t1 – ∆t4), though other combinations are also possible. Delay is programmable in steps of 68 ps in the range of ±128 steps (±8.6 ns). See the 3.5.14 Output Skew Control (Δt0 - Δt4) section for details on skew control. The SYSREF clock is always periodic and can be controlled (on/off) without glitches by enabling or disabling its output through register writes. silabs.com | Smart. Connected. Energy-friendly. Rev. 1.0 | 4 Si5380 Rev D Data Sheet Functional Description Si5380 IN_SEL[1:0] IN0b IN1 IN1b IN2 IN2b IN3/FB_IN IN3b/FB_INb ÷P0 DSPLL ÷P1 PD ÷P2 ÷P3 LPF ÷M ÷5 VDDO0 ÷R0 OUT0 OUT0b ÷R5 VDDO5 OUT5 OUT5b ÷R6 VDDO6 OUT6 OUT6b ÷R7 VDDO7 OUT7 OUT7b ÷R8 VDDO8 OUT8 OUT8b D OUT0A OUT0Ab Device Clocks N ew t0 fo r ÷N0 ÷R0A es ig ns IN0 ÷R9 m en de d ÷R9A OUT9 OUT9b OUT9A OUT9Ab VDDO9 t1 ÷R1 VDDO1 OUT1 OUT1b ÷N2 t2 ÷R2 VDDO2 OUT2 OUT2b ÷N3 t3 ÷R3 VDDO3 OUT3 OUT3b ÷N4 t4 ÷R4 VDDO4 OUT4 OUT4b SYSREF Clocks om ÷N1 Figure 3.1. Example Divider Configuration for Generating JESD204B Subclass 1 Clocks ec 3.1.3 DSPLL Loop Bandwidth R The DSPLL loop bandwidth determines the amount of input clock jitter attenuation. Register configurable DSPLL loop bandwidth settings in the range of 0.1 Hz to 100 Hz are available for selection. The DSPLL will always remain stable with less than 0.1 dB of peaking regardless of the DSPLL loop bandwidth selection. N ot 3.1.4 Fastlock Selecting a low DSPLL loop bandwidth (e.g., 1 Hz) will generally lengthen the lock acquisition time. The fastlock feature allows setting a temporary fastlock loop bandwidth that is used during the lock acquisition process. Higher fastlock loop bandwidth settings will enable the DSPLL to lock faster. Once lock acquisition has completed, the DSPLL’s loop bandwidth will automatically revert to the DSPLL Loop Bandwidth setting. Fastlock loop bandwidth settings in the range of 100 Hz to 4 kHz are available for selection. The fastlock feature can be enabled or disabled by register configuration. silabs.com | Smart. Connected. Energy-friendly. Rev. 1.0 | 5 Si5380 Rev D Data Sheet Functional Description 3.1.5 Modes of Operation Once initialization is complete, the Si5380 operates in one of four modes: Free-run Mode, Lock Acquisition Mode, Locked Mode, or Holdover Mode. A state diagram showing the modes of operation is shown in the figure below. The following sections describe each of these modes in greater detail. es ig ns Power-Up Reset and Initialization No valid input clocks selected Valid input clock selected Lock Acquisition (Fast Lock) Phase lock on selected input clock is achieved N ew An input is qualified and available for selection Locked Mode Holdover Mode Input Clock Switch fo r No valid input clocks available for selection D Free-run Selected input clock fails Yes m en de d Yes No Holdover History Valid? Other Valid Clock Inputs No Available? Figure 3.2. Modes of Operation om 3.1.6 Initialization and Reset ec When power is applied, the device begins an initialization period where it downloads default register values and configuration data from NVM and performs other initialization tasks. Communicating with the device through the serial interface is possible once this initialization period is complete. No clocks will be generated until the initialization is complete. There are two types of resets available. A hard reset is functionally similar to a device power-up. All registers will be restored to the values stored in NVM and all circuits, including the serial interface, will be restored to their initial state. A hard reset is initiated using the RSTb pin or by asserting the hard reset bit. A soft reset bypasses the NVM download. It is simply used to initiate register configuration changes. R 3.1.7 Freerun Mode N ot Once power is applied to the Si5380 and initialization is complete, the device will automatically enter freerun mode. Output clocks will be generated on the outputs with their configured frequencies. The frequency accuracy of the generated output clocks in freerun mode is dependent on the frequency accuracy of the external crystal or reference clock on the XA/XB pins. For example, if the crystal frequency is ±100 ppm, then all the output clocks will be generated at their configured frequency ±100 ppm in freerun mode. Any change or drift of the crystal frequency or external reference on the XA/XB pins will be tracked at the output clock frequencies. 3.1.8 Lock Acquisition If a valid input clock is selected for synchronization, the DSPLL will automatically start the lock acquisition process. If the fast lock feature is enabled, the DSPLL will acquire lock using the Fastlock Loop Bandwidth setting and then transition to the DSPLL Loop Bandwidth setting when lock acquisition is complete. During lock acquisition the outputs will generate a clock that follows the VCO frequency change as it pulls-in to the input clock frequency. silabs.com | Smart. Connected. Energy-friendly. Rev. 1.0 | 6 Si5380 Rev D Data Sheet Functional Description 3.1.9 Locked Mode Once lock is achieved, the Si5380 will generate output clocks that are both frequency and phase locked to the input clock. The DSPLL will provide jitter attenuation of the input clock using the selected DSPLL loop bandwidth. At this point, any XTAL frequency drift inside of the loop bandwidth will not affect the output frequencies. When lock is achieved, the LOLb pin will output a logic high level. The LOL status bit and LOLb status pin will also indicate that the DSPLL is locked. See the 3.4.6 LOL Detection section for more details on LOLb detection time. es ig ns 3.1.10 Holdover Mode N ew Figure 3.3. Programmable Holdover Window D The DSPLL will automatically enter holdover mode when the selected input clock becomes invalid and no other valid input clocks are available for selection. The DSPLL uses an averaged input clock frequency as its final holdover frequency to minimize the disturbance of the output clock phase and frequency when an input clock suddenly fails. The holdover circuit stores up to 120 seconds of historical frequency data while the DSPLL is locked to a valid clock input. The final averaged holdover frequency value is calculated from a programmable window within the stored historical frequency data. Both the window size and the delay are programmable as shown in the figure below. The window size determines the amount of holdover frequency averaging. The delay value allows ignoring frequency data that may be corrupt just before the input clock failure. Clock Failure and Entry into Holdover fo r Historical Frequency Data Collected Programmable historical data window used to determine the final holdover value m en de d 120s time Programmable delay 30ms, 60ms, 1s,10s, 30s, 60s 0s 1s,10s, 30s, 60s When entering holdover, the DSPLL will pull the output clock frequencies referred to the calculated averaged holdover frequency. While in holdover, the output frequency drift is entirely dependent on the external crystal or external reference clock connected to the XA/XB pins. If a new clock input becomes valid, the DSPLL will automatically exit the holdover mode and re-acquire lock to the new input clock. This process involves pulling the output clock frequencies to achieve frequency and phase lock with the new input clock. This pull-in process is glitchless and its rate is controlled by the DSPLL bandwidth and the Fastlock bandwidth. These options are register programmable. ec om The DSPLL output frequency when exiting holdover can be ramped (recommend). Just before the exit is initiated, the difference between the current holdover frequency and the new desired frequency is measured. Using the calculated difference and a user-selectable ramp rate, the output is linearly ramped to the new frequency. The ramp rate can be 0.2 ppm/s, 40,000 ppm/s, or any of about 40 values in between. The DSPLL loop BW does not limit or affect ramp rate selections (and vice versa). CBPro defaults to ramped exit from holdover. The same ramp rate settings are used for both exit from holdover and ramped input switching. For more information on ramped input switching, see 3.3.5 Ramped Input Switching. N ot R Note: If ramped holdover exit is not selected, the holdover exit is governed either by (1) the DSPLL loop BW or (2) a user-selectable holdover exit BW. silabs.com | Smart. Connected. Energy-friendly. Rev. 1.0 | 7 Si5380 Rev D Data Sheet Functional Description 3.2 External Reference (XA/XB) es ig ns An external crystal (XTAL) is used in combination with the internal oscillator (OSC) to produce an ultra-low phase noise reference clock for the DSPLL and for providing a stable reference for the free-run and holdover modes. A simplified diagram is shown in the figure below. The Si5380 includes internal XTAL loading capacitors which eliminates the need for external capacitors and also has the benefit of reduced noise coupling from external sources. Refer to the Table 5.12 Crystal Specifications on page 34 for crystal specifications. A crystal frequency of 54 MHz is required, with a total accuracy of ±100 ppm* recommended for best performance. The Si5380 includes built-in XTAL load capacitors (CL) of 8 pF, which are switched out of the circuit when using an external XO. The Si5380 Reference Manual provides additional information on PCB layout recommendations for the crystal to ensure optimum jitter performance. To achieve optimal jitter performance and minimize BOM cost, a crystal is recommended on the XA/XB reference input. A clock (e.g., XO) may be used in lieu of the crystal, but it may result in higher output jitter. See the Si5380 Reference Manual for more information. Selection between the external XTAL or REFCLK is controlled by register configuration. The internal crystal loading capacitors (CL) are disabled in this mode. It is important to note that when using the REFCLK option the phase noise of the outputs is directly affected by the phase noise of the external XO reference. Refer to the Table 5.3 Input Clock Specifications on page 24 for REFCLK requirements when using the REFCLK mode. D Note: Including initial frequency tolerance and frequency variation over the full operating temperature range, voltage range, load conditions, and aging. XB m en de d XA 100 XA 2xCL 2xCL OSC XA XB 2xCL 2xCL om 2xCL OSC ÷PREF ÷PREF Si5380 Differential XO Connection Si5380 Single-Ended XO Connection ec Crystal Resonator Connection XB 2xCL OSC ÷PREF Si5380 54MHz XO fo r 54MHz XTAL N ew 54MHz XO R Figure 3.4. XAXB Crystal Resonator and External Reference Clock Connection Options 3.3 Inputs (IN0, IN1, IN2, IN3/FB_IN) N ot Four clock inputs are available to synchronize the DSPLL. The inputs are compatible with both single-ended and differential signals. Input selection can be manual (pin or register controlled) or automatic with definable priorities. silabs.com | Smart. Connected. Energy-friendly. Rev. 1.0 | 8 Si5380 Rev D Data Sheet Functional Description 3.3.1 Input Configuration and Terminations Each of the inputs can be configured as differential or single-ended LVCMOS. The recommended input termination schemes are shown in the figure below. Standard 50% duty cycle signals must be ac-coupled, while low duty cycle Pulsed CMOS signals can be DC-coupled. Unused inputs can be disabled and left unconnected when not in use. Standard AC-coupled Differential LVDS INx Standard 100 3.3 V, 2.5 V LVDS or CML INxb 50 es ig ns Si5380 50 Pulsed CMOS D Standard AC-coupled Differential LVPECL Si5380 50 INx Standard N ew 100 INxb 50 3.3 V, 2.5 V LVPECL Pulsed CMOS fo r Standard AC-coupled Single-ended 50 INx m en de d 3.3 V, 2.5 V, 1.8 V LVCMOS Si5380 Standard INxb Pulsed CMOS Pulsed CMOS DC-coupled Single-ended Si5380 R1 INx om 50 3.3 V, 2.5 V, 1.8 V LVCMOS INxb Pulsed CMOS VDD 1.8V 2.5V 3.3V R1 (Ohm) R2 (Ohm) 324 665 511 475 634 365 Figure 3.5. Termination of Differential and LVCMOS Input Signals N ot R ec Resistor values for fIN_PULSED < 1 MHz R2 Standard 3.3.2 Manual Input Selection (IN0, IN1, IN2, IN3/FB_IN) Input clock selection can be made manually using the IN_SEL[1:0] pins or through a register. A register bit determines input selection as pin selectable or register selectable. The IN_SEL pins are selected by default. If there is no clock signal on the selected input, the device will automatically enter free-run or holdover mode. * NOTE: When the zero delay mode is enabled, IN3 becomes the feedback input (FB_IN) and is not available for selection as a clock input. silabs.com | Smart. Connected. Energy-friendly. Rev. 1.0 | 9 Si5380 Rev D Data Sheet Functional Description Table 3.2. Manual Input Selection Using IN_SEL[1:0] Pins IN_SEL[1:0] Selected Input 0 IN0 0 1 IN1 1 0 1 1 es ig ns 0 IN2 IN3* 3.3.3 Automatic Input Switching (IN0, IN1, IN2, IN3/FB_IN) N ew D An automatic input selection state machine is available in addition to the manual switching option. In automatic mode, the selection criteria is based on reference qualification, input priority, and the revertive option. Only references which are valid can be selected by the automatic state machine. If there are no valid references available, the DSPLL will enter the holdover mode. With revertive switching enabled, the highest priority input with a valid reference is always selected. If an input with a higher priority becomes valid, then an automatic switchover to that input will be initiated. With non-revertive switching, the active input will always remain selected while it is valid. If it becomes invalid, an automatic switchover to a valid input with the highest priority will be initiated. 3.3.4 Hitless Input Switching fo r Hitless switching is a feature that prevents a phase transient from propagating to the output when switching between two frequency locked clock inputs that have a fixed phase difference between them. A hitless switch can only occur when the two input frequencies are frequency locked meaning that they have to be exactly at the same frequency, or have an integer frequency relationship to each other. When this feature is enabled, the DSPLL simply absorbs the phase difference between the two input clocks during an input switch. When disabled (normal switching), the phase difference between the two inputs is propagated to the output at a rate determined by the DSPLL loop bandwidth. m en de d 3.3.5 Ramped Input Switching When switching between two plesiochronous input clocks (i.e., the frequencies are "almost the same" but not quite), ramped input switching should be enabled to ensure a smooth transition between the two inputs. Ramped input switching avoids frequency transients and overshoot when switching between frequencies and so is the default switching mode in CBPro. The feature should be turned off when switching between input clocks that are always frequency locked (i.e., are always the same exact frequency). The same ramp rate settings are used for both holdover exit and clock switching. For more information on ramped exit from holdover, see 3.1.10 Holdover Mode. 3.3.6 Glitchless Input Switching N ot R ec om The DSPLL has the ability of switching between two input clocks that are up to 40 ppm apart in frequency. The DSPLL will pull-in to the new frequency using the DSPLL loop bandwidth or using the Fastlock loop bandwidth if it is enabled. The loss of lock (LOL) indicator will be asserted while the DSPLL is pulling-in to the new clock frequency. There will be no output runt pulses generated at the output. Glitchless input switching is available regardless of whether the hitless switching feature is enabled or disabled. silabs.com | Smart. Connected. Energy-friendly. Rev. 1.0 | 10 Si5380 Rev D Data Sheet Functional Description 3.3.7 Zero Delay Mode Si5380 ÷P0 DSPLL ÷P1 IN2 PD ÷P2 IN2b LPF ÷M IN3/FB_IN 100 ÷P3 ÷5 N ew IN1 IN1b D IN0 IN0b es ig ns A zero delay mode is available for applications that require fixed and consistent minimum delay between the selected input and outputs. The zero delay mode is configured by opening the internal feedback loop through software configuration and closing the loop externally as shown in the figure below. This helps to cancel out the internal delay introduced by the dividers, the crosspoint, the input, and the output drivers. Any one of the outputs can be fed back to the IN3/FB_IN pins, although using the output driver that achieves the shortest trace length will help to minimize the input-to-output delay. The OUT9A and IN3/FB_IN pins are recommended for the external feedback connection. The FB_IN input pins must be terminated and ac-coupled when zero delay mode is used. A differential external feedback path connection is necessary for best performance. The order of the OUT9A and FB_IN polarities is such that they may be routed on the device side of the PCB without requiring vias or needing to cross each other. VDDO0 IN3b/FB_INb t0 ÷N1 t1 ÷N2 t2 ÷N3 t3 ÷N4 t4 OUT0A OUT0Ab ÷R0 OUT0 OUT0b ÷R2 VDDO2 OUT2 OUT2b ÷R8 VDDO8 OUT8 OUT8b ÷R9 OUT9 OUT9b ÷R9A OUT9A OUT9Ab VDDO9 External Feedback Path Figure 3.6. Si5380 Zero Delay Mode Set-up N ot R ec om m en de d fo r ÷N0 ÷R0A silabs.com | Smart. Connected. Energy-friendly. Rev. 1.0 | 11 Si5380 Rev D Data Sheet Functional Description 3.4 Fault Monitoring All four input clocks (IN0, IN1, IN2, IN3/FB_IN) are monitored for loss of signal (LOS) and out-of-frequency (OOF) as shown in the figure below. The reference at the XA/XB pins is also monitored for LOS since it provides a critical reference clock for the DSPLL. The DSPLL also has a Loss Of Lock (LOL) indicator, which is asserted when the DSPLL has lost synchronization with the selected input clock. es ig ns XA XB Si5380 OSC IN1 IN1b IN2 IN2b IN3/FB_IN OOF Precision Fast ÷P1 LOS OOF Precision Fast ÷P2 LOS OOF Precision Fast ÷P3 LOS OOF LOS XAXB DSPLL LOL PD LPF Feedback Clock Precision Fast ÷M ÷5 fo r IN3b/FB_INb LOS D IN0b ÷P0 N ew IN0 3.4.1 Input LOS Detection m en de d Figure 3.7. Si5380 Fault Monitors The loss of signal monitor measures the period of each input clock cycle to detect phase irregularities or missing clock edges. Each of the input LOS circuits have their own programmable sensitivity which allows ignoring missing edges or intermittent errors. Loss of signal sensitivity is configurable using the ClockBuilder Pro utility. The LOS status for each of the monitors is accessible by reading a status register. The live LOS register always displays the current LOS state and a sticky register always stays asserted until cleared. An option to disable any of the LOS monitors is also available. LOS ec om Monitor en Sticky LOS LOS Live Figure 3.8. LOS Status Indicators R 3.4.2 XA/XB LOS Detection N ot An LOS monitor is available to ensure that the external crystal or reference clock is valid. By default, the output clocks are disabled when XAXB LOS is detected. This feature can be disabled such that the device will continue to produce output clocks when XAXB LOS is detected. See the 3.5.11 Output Disable During XAXB_LOS section for details. silabs.com | Smart. Connected. Energy-friendly. Rev. 1.0 | 12 Si5380 Rev D Data Sheet Functional Description 3.4.3 OOF Detection Monitor Sticky en Precision OOF es ig ns Each input clock is monitored for frequency accuracy with respect to a OOF reference which it considers as its “0_ppm” reference. This OOF reference can be selected as either: XAXB, IN0, IN1, IN2 or IN3. IN3 is only available as the OOF reference when not in ZDM. The final OOF status is determined by the combination of both a precise OOF monitor and a fast OOF monitor as shown in the figure below. An option to disable either monitor is also available. The live OOF register always displays the current OOF state, and its sticky register bit stays asserted until cleared. LOS OOF Fast Live en D Figure 3.9. OOF Status Indicator 3.4.4 Precision OOF Monitor OOF Declared OOF Cleared m en de d Hysteresis fo r N ew The Precision OOF monitor circuit measures the frequency of all input clocks to within ±1 ppm accuracy with respect to the frequency at the XA/XB pins. The OOF monitor considers the frequency at the XA/XB pins as its 1/16 ppm OOF reference. A valid input frequency is one that remains within the OOF frequency range which is register configurable up to ±500 ppm in steps of 1/16 ppm. A configurable amount of hysteresis is also available to prevent the OOF status from toggling at the failure boundary. An example is shown in the figure below. In this case the OOF monitor is configured with a valid frequency range of ±6 ppm and with 2 ppm of hysteresis. An option to use one of the input pins (IN0–IN3) as the 0 ppm OOF reference instead of the XA/XB pins is available. This option is register configurable. -6 ppm (Set) -4 ppm (Clear) 0 ppm OOF Reference fIN Hysteresis +4 ppm (Clear) +6 ppm (Set) Figure 3.10. Example of Precise OOF Monitor Assertion and De-assertion Triggers 3.4.5 Fast OOF Monitor N ot R ec om Because the precision OOF monitor needs to provide 1/16 ppm of frequency measurement accuracy, it must measure the monitored input clock frequencies over a relatively long period of time. This may be too slow to detect an input clock that is quickly ramping in frequency. An additional level of OOF monitoring called the Fast OOF monitor runs in parallel with the precision OOF monitors to quickly detect a ramping input frequency. The Fast OOF monitor asserts OOF on an input clock frequency that has changed by 1,000 to 16,000 ppm. silabs.com | Smart. Connected. Energy-friendly. Rev. 1.0 | 13 Si5380 Rev D Data Sheet Functional Description 3.4.6 LOL Detection LOL Monitor RS Latch LOL Clear Timer Reset Sticky LOL LOL Q Live LOL Set D Set es ig ns A loss of lock (LOL) monitor asserts the LOL bit when the DSPLL has lost synchronization with the selected input clock. There is also a dedicated active-low LOLb pin which reflects the loss of lock condition. The LOL monitor measures the frequency difference between the input and feedback clocks at the phase detector. There are two LOL frequency monitors, one that sets the LOL indicator (LOL Set) and another that clears the indicator (LOL Clear). A block diagram of the LOL monitor is shown in the figure below. The live LOL register always displays the current LOL state and a sticky register always stays asserted until cleared. The LOLb pin reflects the current state of the LOL monitor. LOLb N ew DSPLL fIN PD ÷M ÷5 Si5380 fo r Feedback Clock LPF m en de d Figure 3.11. LOL Status Indicators Each of the frequency monitors have adjustable sensitivity which is register configurable from 0.1 ppm to 10,000 ppm. Having two separate frequency monitors allows for hysteresis to help prevent chattering of LOL status. An example configuration where LOCK is indicated when there is less than 0.1 ppm frequency difference at the inputs of the phase detector and LOL is indicated when there is more than 1 ppm frequency difference is shown in the figure below. om Clear LOL Threshold Set LOL Threshold Lock Acquisition LOL Hysteresis Lost Lock 0 0.1 1 10,000 Phase Detector Frequency Difference (ppm) Figure 3.12. LOL Set and Clear Thresholds N ot R ec LOCKED An optional timer is available to delay clearing of the LOL indicator to allow additional time for the DSPLL to completely phase lock to the input clock. The timer is also useful to prevent the LOL indicator from toggling or chattering as the DSPLL completes lock acquisition. The configurable delay value depends on frequency configuration and loop bandwidth of the DSPLL and is automatically calculated using the ClockBuilder Pro utility. silabs.com | Smart. Connected. Energy-friendly. Rev. 1.0 | 14 Si5380 Rev D Data Sheet Functional Description 3.4.7 Interrupt Pin INTRb An interrupt pin INTRb indicates a change in state of the status indicators shown in the figure below. All of the status indicators are maskable to prevent assertion of the interrupt pin. The state of the INTRb pin is reset by clearing the status register that caused the interrupt. The sticky version of the fault monitors is used for this function to ensure that the fault condition is still available when responding to the interrupt. es ig ns Si5380 LOS_FLG 0x0012[0] IN0 OOF_FLG 0x0012[4] LOS_FLG 0x0012[1] IN1 LOS_FLG 0x0012[2] IN2 OOF_FLG 0x0012[6] LOS_FLG 0x0012[3] LOL_FLG 0x0013[1] PLL m en de d HOLD_FLG 0x0013[5] INTRb fo r IN3 OOF_FLG 0x0012[7] N ew D OOF_FLG 0x0012[5] CAL_FLG 0x0014[5] SYSINCAL_FLG 0x0011[0] LOSXAXB_FLG 0x0011[1] LOSREF_FLG 0x0011[2] Device om XAXB_ERR_FLG 0x0011[3] SMBUS_TIMEOUT_FLG 0x0011[5] ec Figure 3.13. Interrupt Triggers and Masks R 3.5 Outputs The Si5380 supports 12 differential output drivers which can be independently configured as differential or LVCMOS. N ot 3.5.1 Output Crosspoint The output crosspoint allows any of the N dividers to connect to any of the clock outputs. 3.5.2 Output Signal Format The differential output amplitude and common mode voltage are both fully programmable covering a wide variety of signal formats including LVPECL, LVDS, HCSL, and CML. In addition to supporting differential signals, any of the outputs can be configured as LVCMOS (3.3 V, 2.5 V, or 1.8 V) drivers providing up to 24 single-ended outputs, or any combination of differential and single-ended outputs. silabs.com | Smart. Connected. Energy-friendly. Rev. 1.0 | 15 Si5380 Rev D Data Sheet Functional Description 3.5.3 Output Terminations The output drivers support both ac-coupled and dc-coupled terminations as shown in the following figure. AC-coupled LVDS/LVPECL DC-coupled LVDS VDDO = 3.3 V, 2.5 V, 1.8 V 50 OUTx OUTx OUTxb 100 OUTxb Si5380 VDDO = 3.3 V, 2.5 V, 1.8 V R1 VDDO = 3.3 V, 2.5 V R1 Standard HCSL Receiver 50 Si5380 R2 3.3 V 56.2 Ω 2.5 V 332 Ω 59 Ω 1.8 V 243 Ω 63.4 Ω 50 50 OUTxb 50 R2 fo r R2 50 m en de d R1 442 Ω VDD – 1.3 V Si5380 For VCM = 0.35 V VDDRX OUTx N ew 50 D VDDRX OUTxb Internally self-biased AC-coupled LVPECL / CML AC-coupled HCSL OUTx 100 50 50 Si5380 50 es ig ns VDDO = 3.3 V, 2.5 V Figure 3.14. Supported Output Terminations 3.5.4 Programmable Common Mode Voltage For Differential Outputs The common mode voltage (VCM) for the differential modes is programmable in 100 mV increments from 0.7 V to 2.3 V depending on the voltage available at the output’s VDDO pin. Setting the common mode voltage is useful when dc-coupling the output drivers. om 3.5.5 LVCMOS Output Terminations R ec LVCMOS outputs are dc-coupled with source-side series termination as shown in the figure below. DC-coupled LVCMOS 3.3 V, 2.5 V, 1.8 V LVCMOS VDDO = 3.3V, 2.5V, 1.8V 50 N ot OUTx silabs.com | Smart. Connected. Energy-friendly. Rs OUTxb 50 Rs Figure 3.15. LVCMOS Output Terminations Rev. 1.0 | 16 Si5380 Rev D Data Sheet Functional Description 3.5.6 LVCMOS Output Impedance and Drive Strength Selection Each LVCMOS driver has a configurable output impedance to accommodate different trace impedances and drive strengths. A source termination resistor is recommended to help match the selected output impedance to the trace impedance. There are three programmable output impedance selections for each VDDO options as shown in the table below. VDDO CMOS_DRIVE_Selection OUTx_CMOS_DRV = 2 3.3 V 38 Ω 30 Ω 2.5 V 43 Ω 35 Ω 1.8 V — 46 Ω OUTx_CMOS_DRV = 3 22 Ω 24 Ω 31 Ω D OUTx_CMOS_DRV = 1 es ig ns Table 3.3. Typical Output Impedance (ZS) 3.5.7 LVCMOS Output Signal Swing N ew The signal swing (VOL/VOH) of the LVCMOS output drivers is set by the voltage on the VDDO pins. Each output driver has its own VDDO pin allowing a unique output voltage swing for each of the LVCMOS drivers. OUT0 and OUT0A share the same VDDO pin. OUT9 and OUT9A also share the VDDO pin. All other outputs have their own individual VDDO pins. 3.5.8 LVCMOS Output Polarity fo r When a driver is configured as an LVCMOS output it generates a clock signal on both pins (OUTx and OUTxb). By default the clock on the OUTxb pin is generated with the same polarity (in phase) with the clock on the OUTx pin. The polarity of these clocks is configurable enabling complimentary clock generation and/or inverted polarity with respect to other output drivers. m en de d 3.5.9 Output Enable/Disable The OEb pin provides a convenient method of disabling or enabling all of the output drivers at the same time. When the OEb pin is held high all outputs will be disabled. When held low, the outputs will all be enabled. Outputs in the enabled state can still be individually disabled through register control. 3.5.10 Output Disable During LOL By default, a DSPLL that is out of lock will generate either free-running clocks or generate clocks in holdover mode. There is an option to disable the outputs when a DSPLL is LOL. This option can be useful to force a downstream PLL into holdover. om 3.5.11 Output Disable During XAXB_LOS R ec The internal oscillator circuit (OSC) in combination with the external crystal (XTAL) provides a critical function for the operation of the DSPLLs. In the event of a crystal failure, the device will assert an XAXB_LOS alarm. By default, all outputs will be disabled during assertion of the XAXB_LOS alarm. There is an option to leave the outputs enabled during an XAXB_LOS alarm, but the frequency accuracy and stability will be indeterminate during this fault condition.The internal oscillator circuit (OSC) in combination with the external crystal (XTAL) provides a critical function for the operation of the DSPLLs. In the event of a crystal failure, the device will assert an XAXB_LOS alarm. By default, all outputs will be disabled during assertion of the XAXB_LOS alarm. There is an option to leave the outputs enabled during an XAXB_LOS alarm, but the frequency accuracy and stability will be indeterminate during this fault condition. 3.5.12 Output Driver State When Disabled N ot The disabled state of an output driver is configurable as either disable low or disable high. 3.5.13 Synchronous Enable/Disable Feature The output drivers provide a selectable synchronous enable/disable feature. Output drivers with synchronous disable active will wait until a clock period has completed before the driver is disabled or enabled. This prevents unwanted shortened pulses from occurring when enabling or disabling an output. When this feature is turned off, the output clock will disable immediately without waiting for the clock period to complete. silabs.com | Smart. Connected. Energy-friendly. Rev. 1.0 | 17 Si5380 Rev D Data Sheet Functional Description 3.5.14 Output Skew Control (Δt0 - Δt4) es ig ns The Si5380 uses independent dividers (N0 - N4) to generate up to 5 unique frequencies to its 12 outputs through a crosspoint switch. A delay path (Δt0 - Δt4) associated with each of these dividers is available for applications that need a specific output skew configuration. This is useful for compensating PCB trace delay differences or for applications that require quadrature clock generation. The resolution of the phase adjustment is approximately 68 ps per step up to 128 steps of added phase delay (+8.6 ns late), or 128 steps of negative delay (–8.6 ns early). Phase adjustments are register configurable. An example of generating two frequencies with unique configurable path delays is shown in the following figure. OUT0A OUT0Ab ÷R0 OUT0 OUT0b VDDO1 OUT1 OUT1b VDDO2 OUT2 OUT2b ÷N1 t1 ÷R1 ÷N2 t2 ÷R2 ÷N3 t3 ÷N4 t4 ÷R3 ÷R4 N ew ÷N0 t0 ÷R0A D VDDO0 VDDO3 OUT3 OUT3b VDDO4 OUT4 OUT4b VDDO5 OUT5 OUT5b ÷R6 VDDO6 OUT6 OUT6b fo r ÷R5 VDDO7 OUT7 OUT7b ÷R8 VDDO8 OUT8 OUT8b ÷R9 OUT9 OUT9b ÷R9A OUT9A OUT9Ab VDDO9 om m en de d ÷R7 Figure 3.16. Example of Independently Configurable Path Delays R ec All phase delay values are restored to their default values after power-up, power-on reset, or hardware reset using the RSTb pin. Phase delay default values can be written to NVM allowing a custom phase offset configuration at power-up or after power-on reset, or after a hardware reset using the RSTb pin. 3.5.15 Output Divider (R) Synchronization N ot All the output R dividers are reset to a known state during the power-up initialization period. This ensures consistent and repeatable phase alignment across all output drivers. Resetting the device using the RSTb pin or asserting the reset bit will have the same result. Asserting the sync register bit provides another method of realigning the R dividers without resetting the device. 3.6 Power Management Unused inputs and output drivers can be powered down when unused. Consult the Si5380 Reference Manual and ClockBuilder Pro configuration utility for details. silabs.com | Smart. Connected. Energy-friendly. Rev. 1.0 | 18 Si5380 Rev D Data Sheet Functional Description 3.6.1 Power Down Pin (PDNb) A power down pin is provided to force the device in a low power mode. The device’s configuration will be maintained but no output clocks will be generated. Most of the internal blocks will be shut down but device communication via the serial interface will still be available. When the PDNb pin is pulled low the outputs will shut down without glitching (the clock’s complete period will be generated before shutting down). When PDNb is released the device will start generating clocks without glitches. The device will generate freerunning clocks until the DSPLL has acquired lock to the selected input clock source. es ig ns 3.7 In-Circuit Programming The Si5380 is fully configurable using the serial interface (I2C or SPI). At power-up, the device downloads its default register values from internal non-volatile memory (NVM). Application specific default configurations can be written into NVM allowing the device to generate specific clock frequencies at power-up. Writing default values to NVM is in-circuit programmable with normal operating power supply voltages applied to its VDD and VDDA pins. The NVM is writable two times. Once a new configuration has been written to NVM, the old configuration is no longer accessible. Refer to the Si5380 Reference Manual for a detailed procedure for writing registers to NVM. D 3.8 Serial Interface N ew Configuration and operation of the Si5380 is controlled by reading and writing registers using the I2C or SPI interface. The I2C_SEL pin selects I2C or SPI operation. The Si5380 supports communication with a 3.3 V or 1.8 V host by setting the IO_VDD_SEL configuration bit. The SPI mode supports 4-wire or 3-wire by setting the SPI_3WIRE configuration bit. See the Si5380 Reference Manual for details. 3.9 Custom Factory Preprogrammed Devices fo r For applications where a serial interface is not available for programming the device, custom pre-programmed parts can be ordered with a specific configuration written into NVM. A factory pre-programmed device will generate clocks at power-up. Custom, factory-preprogrammed devices are available. Use the ClockBuilder Pro custom part number wizard (www.silabs.com/clockbuilderpro) to quickly and easily request and generate a custom part number for your configuration. m en de d In less than three minutes, you will be able to generate a custom part number with a detailed data sheet addendum matching your design’s configuration. Once you receive the confirmation email with the data sheet addendum, simply place an order with your local Silicon Labs sales representative. Samples of your pre-programmed device will ship to you typically within two weeks. 3.10 Enabling Features and/or Configuration Settings Not Available in ClockBuilder Pro for Factory Pre-programmed Devices As with essentially all software utilities, ClockBuilder Pro is continuously updated and enhanced. By registering at www.silabs.com and opting in for updates to software, you will be notified whenever changes are made and what the impact of those changes are. This update process will ultimately enable ClockBuilder Pro users to access all features and register setting values documented in this data sheet and the Si5380 Reference Manual . ec om However, if you must enable or access a feature or register setting value so that the device starts up with this feature or a register setting, but the feature or register setting is NOT yet available in CBPro, you must contact a Silicon Labs applications engineer for assistance. Examples of this type of feature or custom setting are the customizable output amplitude and common voltages for the clock outputs. After careful review of your project file and custom requirements, all Silicon Labs applications engineer will email back your CBPro project file with your specific features and register settings enabled, using what is referred to as the manual "settings override" feature of CBPro. "Override" settings to match your request(s) will be listed in your design report file. Examples of setting "overrides" in a CBPro design report are shown below: Table 3.4. Setting Overrides Name Type Target Dec Value Hex Value 0x0535[0] FORCE_HOLD No NVM N/A 1 0x1 0128[6:4] OUT6_AMPL User OPN and EVB 5 0x5 N ot R Location Once you receive the updated design file, simply open it in CBPro. After you create a custom OPN, the device will begin operation after startup with the values in the NVM file, including the Silicon Labs-supplied override settings. silabs.com | Smart. Connected. Energy-friendly. Rev. 1.0 | 19 Si5380 Rev D Data Sheet Functional Description Place sample order Do I need a pre-programmed device with a feature or setting which is unavailable in ClockBuilder Pro? No Configure device using CBPro N ew m en de d Receive updated CBPro project file from Silicon Labs with “Settings Override” Yes fo r Contact Silicon Labs Technical Support to submit & review your non-standard configuration request & CBPro project file D Yes Generate Custom OPN in CBPro es ig ns Start Load project file into CBPro and test Does the updated CBPro Project file match your requirements? om Figure 3.17. Flowchart to Order Custom Parts with Features not Available in CBPro N ot R ec Note: Contact Silicon Labs Technical Support at www.silabs.com/support/Pages/default.aspx. silabs.com | Smart. Connected. Energy-friendly. Rev. 1.0 | 20 Si5380 Rev D Data Sheet Register Map 4. Register Map N ot R ec om m en de d fo r N ew D es ig ns This document provides a brief list of available registers. For a complete list of registers and settings, please refer to the Si5380 Reference Manual . silabs.com | Smart. Connected. Energy-friendly. Rev. 1.0 | 21 Si5380 Rev D Data Sheet Electrical Specifications 5. Electrical Specifications Table 5.1. Recommended Operating Conditions 1 Maximum Junction Temperature Core Supply Voltage Output Driver Supply Voltage Min Typ Max Unit TA –40 25 85 °C TJMAX — — 125 °C VDD 1.71 1.80 1.89 V VDDA 3.14 3.30 3.47 V VDDO 3.14 3.30 3.47 V 2.37 2.50 2.62 V 1.71 1.80 1.89 V es ig ns Ambient Temperature Symbol D Parameter N ot R ec om m en de d fo r N ew Note: 1. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted. silabs.com | Smart. Connected. Energy-friendly. Rev. 1.0 | 22 Si5380 Rev D Data Sheet Electrical Specifications Table 5.2. DC Characteristics Symbol Core Supply Current 1,2 Test Condition Min Typ Max Unit IDD — 190 310 mA IDDA — 125 135 mA — 36 — 22 — 25 IDDO Output Buffer Supply Current 2, 5 LVPECL Output 3 @ 1474.56 MHz LVPECL Output 3 LVDS Output 3 @ 1474.56 MHz 15 41 mA 26 mA 29 mA 18 mA — 22 30 mA — 18 23 mA fo r @ 153.6 MHz — N ew LVDS Output 3 D @ 153.6 MHz es ig ns Parameter — 12 16 mA — 1300 1600 mW 3.3 V LVCMOS Output 4 @ 153.6 MHz 2.5 V LVCMOS Output 4 @ 153.6 MHz 1.8 V LVCMOS Output 4 Total Power Dissipation 1, 2 m en de d @ 153.6 MHz Pd Typical Outputs om Notes: 1. Si5380 test configuration: 3 × 3.3 V LVPECL outputs enabled at 122.88 MHz, 2 × 3.3 V LVPECL outputs enabled at 491.52 MHz, 1 × 3.3 V LVPECL output enabled at 983.04 MHz. Excludes power in termination resistors. 2. Detailed power consumption for any configuration can be estimated using ClockBuilder Pro when an evaluation board (EVB) is not available. All EVBs support detailed current measurements for any configuration. 3. Differential outputs terminated into an ac-coupled 100 Ω load. 4. LVCMOS outputs measured into a 5-inch 50 Ω PCB trace with 5 pF load. The LVCMOS outputs were set to OUTx_CMOS_DRV=3, which is the strongest driver setting. Refer to the Si5380 Reference Manual for more details on register settings. 5. VDDO0 supplies power to both OUT0 and OUT0A buffers. Similarly, VDDO9 supplies power to both OUT9 and OUT9A buffers. LVCMOS Output Test Configuration ec Differential Output Test Configuration IDDO R OUT 50 Trace length 5 inches 0.1 uF IDDO 100 OUTb N ot 50 silabs.com | Smart. Connected. Energy-friendly. 0.1 uF 50 OUT OUTb 499 Ω 4.7 pF 50 499 Ω 4.7 pF 0.1 uF 50 Ω Scope Input 56 Ω 0.1 uF 50 Ω Scope Input 56 Ω Rev. 1.0 | 23 Si5380 Rev D Data Sheet Electrical Specifications Table 5.3. Input Clock Specifications Parameter Symbol Test Condition Min Typ Max Unit 737.28 MHz Input Frequency Range fIN_DIFF Differential 11.52 — fIN_SE All Single-ended Signals 11.52 — 100 — 225 — (including LVCMOS) VIN Voltage Swing1 Differential AC-coupled FIN < 245.76 MHz 245.76 MHz 1800 mVpp_se 1800 mVpp_se D Differential AC-coupled es ig ns Standard Input Buffer with Differential or Single-Ended/LVCMOS—AC-coupled (IN0, IN1, IN2, IN3/FB_IN) 245.76 MHz < FIN < 737.28 MHz 100 — 3600 mVpp_se 400 — — V/µs 40 — 60 % — 0.3 — pF — 16 — kΩ 11.52 — 245.76 MHz VIL –0.2 — 0.4 V VIH 0.8 — — V SR 400 — — V/µs Slew Rate 2, 3 SR Duty Cycle DC Capacitance CIN Input Resistance RIN fo r FIN < 245.76 MHz N ew Single-Ended AC-coupled Input Frequency m en de d Pulsed CMOS Input Buffer—DC-coupled (IN0, IN1, IN2, IN3/FB_IN) 4 fIN_PULSED_CM OS Input Voltage Thresholds4 Slew Rate 2, 3 Duty Cycle Input Resistance Clock Input 40 — 60 % PW Pulse Input 1.6 — — ns — 8 — kΩ — 54 — MHz om Minimum Pulse Width DC RIN ec REFCLK (applied to XA/XB) fIN_REF Total Frequency Tolerance 6 fRANGE –100 — +100 ppm Input Voltage Swing VIN_SE 365 — 2000 mVpp_se VIN_DIFF 365 — 2500 mVpp_diff 400 — — V/µs 40 — 60 % N ot R REFCLK Frequency 5 Slew Rate 2 , 3 SR Input Duty Cycle DC silabs.com | Smart. Connected. Energy-friendly. Frequency required for optimum performance Imposed for best phase noise performance Rev. 1.0 | 24 Si5380 Rev D Data Sheet Electrical Specifications Parameter Symbol Test Condition Min Typ Max Unit Notes: 1. Voltage swing is specified as single-ended mVpp. OUTx Vcm Vpp_se Vcm Vpp_se Vpp_diff = 2*Vpp_se OUTxb es ig ns 2. Imposed for phase noise performance. 3. Rise and fall times can be estimated using the following simplified equation: tr/tf80-20 = ((0.8 – 0.2) * VIN_Vpp_se) / SR. N ew D 4. Pulsed CMOS mode is intended primarily for single-end LVCMOS input clocks < 1 MHz, which must be dc-coupled, having a duty cycle significantly less than 50%. A common application example is a low frequency video frame sync pulse. Since the input thresholds (VIL, VIH) of the input buffer are non-standard (0.40 and 0.80 V, respectively), refer to the input attenuator circuit for dc-coupled Pulsed LVCMOS in the in the Si5380 Reference Manual . Otherwise, for standard LVCMOS input clocks, use the "AC-coupled Single-Ended" mode as shown in Figure 3.14 Supported Output Terminations on page 16. 5. The REFCLK frequency for the Si5380 is fixed at 54 MHz. Contact Silicon Labs technical support for more information. 6. Includes initial tolerance, drift after reflow, change over temperature (–40 °C to +85 °C), VDD variation, load pulling, and aging. Table 5.4. Serial and Control Input Pin Specifications Parameter Symbol Test Condition Min Typ Max Unit Si5380 Serial and Control Input Pins (I2C_SEL, IN_SEL[1:0], RSTb, OEb, SYNCb, PDNb, A1/SDO, SDA/SDIO, SCLK, A0/CSb) VIL — — 0.3xVDDIO1 V 0.7 x VDDIO1 — — V CIN — 2 — pF IL — 20 — kΩ 100 — — ns Input Capacitance Input Resistance Minimum Pulse Width m en de d VIH fo r Input Voltage Thresholds PW RSTb, SYNCb, PDNb N ot R ec om Note: 1. VDDIO is determined by the IO_VDD_SEL bit. It is selectable as VDDA or VDD. See the Si5380 Reference Manual for more details on the register settings. silabs.com | Smart. Connected. Energy-friendly. Rev. 1.0 | 25 Si5380 Rev D Data Sheet Electrical Specifications Table 5.5. Differential Clock Output Specifications fOUT Duty Cycle DC Output-Output Skew TSK OUT-OUTb Skew TSK_OUT VOUT Output Voltage Amplitude 1 Min Typ Max Unit 0.480 — 1474.56 MHz f ≤ 400 MHz 48 — 52 % f > 400 MHz 45 — Outputs at 737.28 MHz connected to the same "N-divider" — — Outputs at 737.28 MHz connected to different "N-dividers" — — Measured from the positive to negative output pins — VDDO = 55 % 65 ps 90 ps 0 50 ps mVpp_se LVDS 350 430 510 VDDO = 3.3 V or 2.5 V LVPECL 640 750 900 VDDO = LVDS 1.10 1.2 1.3 3.3 V LVPECL 1.90 2.0 2.1 VDDO = LVPECL 1.1 1.2 1.3 2.5 V LVDS VDDO = sub-LVDS 0.8 0.9 1.00 tR/tF — 100 150 ps ZO — 100 — Ω 10 kHz sinusoidal noise — –101 — dBc 100 kHz sinusoidal noise — –96 — dBc 500 kHz sinusoidal noise — –99 — dBc 1 MHz sinusoidal noise — –97 — dBc Measured spur from adjacent output — –72 — dB 3.3 V or 2.5 V or VCM m en de d fo r 1.8 V Common Mode Voltage1 es ig ns Output Frequency Test Condition D Symbol N ew Parameter V 1.8 V om Rise and Fall Times (20% to 80%) Differential Output Impedance PSRR R ec Power Supply Noise Rejection 2 XTALK N ot Output-Output Crosstalk3 silabs.com | Smart. Connected. Energy-friendly. Rev. 1.0 | 26 Si5380 Rev D Data Sheet Electrical Specifications Parameter Symbol Test Condition Min Typ Max Unit es ig ns Notes: 1. Output amplitude and common mode voltage are programmable through register settings and can be stored in NVM. Each output driver can be programmed independently. The maximum LVDS single-ended amplitude can be up to 110 mV higher than the TIA/ EIA-644 maximum. Refer to the Si5380 Reference Manual for recommended output register settings. Not all combinations of voltage amplitude and common mode voltages settings are possible. 2. Measured for 153.6 MHz carrier frequency. 100 mVpp of sinewave noise added to VDDO when programmed at 3.3 V. 3. Measured across two adjacent outputs, both in LVDS mode, with the victim running at 155.52 MHz and the aggressor at 156.25 MHz. These output frequencies are generated using non-production engineering modes only for test. Refer to application note, "AN862: Optimizing Si534x Jitter Performance in Next Generation Internet Infrastructure Systems", for guidance on crosstalk optimization. Note that all active outputs must be terminated when measuring crosstalk Parameter Symbol Test Condition Min 0.480 Duty Cycle DC fOUT < 100 MHz TSK Unit — 245.76 MHz % 48 — 52 45 — 55 — 30 140 ps — — V IOH = –12 mA — — IOH = –17 mA — — — — 100 MHz < fOUT < 245.76 MHz Output-to-Output Skew Max N ew Output Frequency Typ D Table 5.6. LVCMOS Clock Output Specifications Outputs at 153.6 MHz OUTx_CMOS_DRV=1 OUTx_CMOS_DRV=2 VOH VDDO x 0.85 VDDO = 2.5 V OUTx_CMOS_DRV=1 IOH = –6 mA OUTx_CMOS_DRV=2 IOH = –8 mA — — OUTx_CMOS_DRV=3 IOH = –11 mA — — — — — — OUTx_CMOS_DRV=2 IOH = –4 mA OUTx_CMOS_DRV=3 IOH = –5 mA VDDO x 0.85 V VDDO = 1.8 V VDDO x 0.85 V N ot R ec om Output Voltage High 1, 2, 3 IOH = –10 mA m en de d OUTx_CMOS_DRV=3 fo r VDDO = 3.3 V silabs.com | Smart. Connected. Energy-friendly. Rev. 1.0 | 27 Si5380 Rev D Data Sheet Electrical Specifications Parameter Symbol Test Condition Min Typ Max Unit VDDO x 0.15 V VDDO = 3.3 V IOL = 10 mA — — OUTx_CMOS_DRV=2 IOL = 12 mA — — OUTx_CMOS_DRV=3 IOL = 17 mA — — es ig ns OUTx_CMOS_DRV=1 VDDO = 2.5 V Output Voltage Low 1, 2, 3 VOL OUTx_CMOS_DRV=1 IOL = 6 mA — — OUTx_CMOS_DRV=2 IOL = 8 mA — — OUTx_CMOS_DRV=3 IOL = 11 mA — — OUTx_CMOS_DRV=2 IOL = 4 mA — OUTx_CMOS_DRV=3 IOL = 5 mA — — — VDDO = 3.3 V tr/tf VDDO = 2.5 V (20% to 80%) — VDDO x 0.15 V 400 600 ps — 450 600 ps — 550 750 ps N ew LVCMOS Rise and Fall Times 3 VDDO = 1.8 V V D VDDO = 1.8 V VDDO x 0.15 fo r Notes: 1. Driver strength is a register programmable setting and stored in NVM. Options are OUTx_CMOS_DRV = 1, 2, 3. Refer to the Si5380 Reference Manual for recommended output register settings. 2. IOL/IOH is measured at VOL/VOH as shown in the DC test configuration DC Test Configuration m en de d 3. A 5 pF capacitive load is assumed. The LVCMOS outputs were set to OUTx_CMOS_DRV = 3. AC Output Test Configuration Trace length 5 inches IOL/IOH IDDO 50 OUT Zs 499 Ω 4.7 pF 0.1 uF 50 Ω Scope Input 56 Ω OUTb 499 Ω 0.1 uF 50 4.7 pF 50 Ω Scope Input 56 Ω N ot R ec om VOL/VOH silabs.com | Smart. Connected. Energy-friendly. Rev. 1.0 | 28 Si5380 Rev D Data Sheet Electrical Specifications Table 5.7. Output Serial and Status Pin Specifications Parameter Symbol Test Condition Min Typ Max Unit — V Output Voltage 1, 2 VOH IOH = –2 mA VDDIO x 0.85 — VOL IOL = 2 mA — — es ig ns Si5380 Output Serial and Status Pins (LOLb, INTRb, SDA/SDIO2, A1/SDO) VDDIO x 0.15 V N ew D Notes: 1. VDDIO is determined by the IO_VDD_SEL bit. It is selectable as VDDA or VDD. See the Si5380 Reference Manual for more details on the register settings. 2. The VOH specification does not apply to the open-drain SDA/SDIO output when the serial interface is in I2C mode or is unused, with I2C_SEL pulled high internally. VOL remains valid in all cases. Table 5.8. Performance Characteristics PLL Bandwidth Programming Range 1 PLL Lock Time2 Test Condition fBW Bandwidth is register programmable tSTART Time from power-up to when the device generates free-running clocks tACQ Fastlock enabled m en de d Initial Start-Up Time Symbol Min Typ Max Unit 0.1 — 4000 Hz — 370 450 ms — 280 300 ms — — 15 ms fo r Parameter FIN = 19.2 MHz POR to Serial Interface Ready 3 Output Delay Adjustment fVCO = 14.7456 GHz — 68 — ps tRANGE ±128 / fVCO — 8.6 — ns JPK Measured with a frequency plan running a 24.576 MHz input, 24.576 MHz output, and a Loop Bandwidth of 4 Hz — — 0.1 dB JTOL Compliant with G.8262 Options 1 and 2 Carrier Frequency = 2.103125 GHz; Jitter Modulation Frequency = 10 Hz — 3180 — UI pk-pk tSWITCH Only valid for a single automatic switch between two input clocks at same frequency — — 2.0 ns Only valid for a single manual switch between two input clocks at same frequency — — 1.3 ns –20 — 20 ppm R ec Jitter Tolerance tDELAY_int om Jitter Peaking tRDY N ot Maximum Phase Transient During a Hitless Switch Pull-in Range ωP silabs.com | Smart. Connected. Energy-friendly. Rev. 1.0 | 29 Si5380 Rev D Data Sheet Electrical Specifications Symbol Test Condition Min Typ Max Unit Input-to-Output Delay Variation tIODELAY Note 5 — — 1.8 ns tZDELAY Note 6 — 110 — ps JGEN 12 kHz to 20 MHz — 65 80 fs rms 10Hz — –72 100 Hz — –98 1 kHz — –126 10 kHz — –140 100 kHz — –148 1 MHz — 10 MHz RMS Phase Jitter 4 (measured @ 983.04 MHz) (122.88 MHz Carrier Frequency) Spur Performance 4 (122.88 MHz Carrier Frequency) SPUR Up to 1 MHz offset From 1 MHz to 30 MHz offset — dBc/Hz — dBc/Hz — dBc/Hz — dBc/Hz — dBc/Hz –154 — dBc/Hz — –165 — dBc/Hz — –103 — dBc — –95 — dBc D PN N ew Phase Noise Performance 4 es ig ns Parameter N ot R ec om m en de d fo r Notes: 1. Actual loop bandwidth might be lower; refer to ClockBuilder Pro for actual value on your frequency plan. 2. Lock Time can vary significantly depending on several parameters, such as bandwidths, LOL thresholds, etc. For this case, lock time was measured with nominal and fastlock bandwidths both set to 100 Hz, LOL set/clear thresholds of 3/0.3 ppm respectively, using IN0 as clock reference by removing the reference and enabling it again, then measuring the delta time between the first rising edge of the clock reference and the LOL indicator de-assertion. 3. Measured as time from valid VDD/VDDA rails (both >90% of settled voltage) to when the serial interface is ready to respond to commands. 4. Jitter generation test conditions: fIN = 30.72 MHz, 3.3V LVPECL, DSPLL LBW = 100 Hz. Jitter integrated from 12 kHz to 20 MHz offset. Does not include jitter from PLL input reference. 5. Measured between a common 2 MHz input and 2 MHz output with different N-dividers on the same unit and a loop bandwidth of 4 kHz. These output frequencies are generated using non-production engineering modes only for test. 6. Delay between reference and feedback input both clocks at 10 MHz and same slew rate. Ref clock rise time must be = 1 kΩ. No pull-up resistor is needed when in SPI mode. A1/SDO 17 I/O Address Select 1/Serial Data Output. In I2C mode this pin functions as the A1 address input pin. In 4-wire SPI mode, this is the serial data output (SDO) pin. This pin should be externally pulled up or down when unused. SCLK 16 I Serial Clock Input. This pin functions as the serial clock input for both I2C and SPI modes. When in I2C mode or unused, this pin must be pulled-up using an external resistor of >= 1 kΩ. No pull-up resistor is needed when in SPI mode. ec I2C_SEL Output Clocks. These output clocks support programmable signal amplitude and common mode voltage. Desired output signal format is configurable using register control. Termination recommendations are provided in 3.5.5 LVCMOS Output Terminations. Unused outputs should be left unconnected. m en de d OUT8 Serial Interface Function N ot R SDA/SDIO silabs.com | Smart. Connected. Energy-friendly. Rev. 1.0 | 42 Si5380 Rev D Data Sheet Pin Description Pin Name Pin Number Pin Type1 Function A0/CSb 19 I Address Select 0/Chip Select. This pin functions as the hardware controlled address A0 in I2C mode. In SPI mode, this pin functions as the chip select input (active low). This pin is internally pulled-up. INTRb 12 O Interrupt. 2 This pin is asserted low when a change in device status has occurred. This pin must be pulled-up externally using a resistor of >= 1 kΩ. It should be left unconnected when not in use. PDNb 5 I Power Down. 2 The device enters into a low power mode when this pin is pulled low. This pin is internally pulled-up. It can be left unconnected when not in use. RSTb 6 I Device Reset. 2 Active low input that performs power-on reset (POR) of the device. Resets all internal logic to a known state and forces the device registers to their default values. Clock outputs are disabled during reset. This pin is internally pulled-up. OEb 11 I Output Enable. 2 This pin disables all outputs when held high. This pin is internally pulled low and can be left unconnected when not in use. LOLb 47 O Loss Of Lock. 2 This output pin indicates when the DSPLL is locked (high) or out-of-lock (low). When in use, this pin must be pulled-up using an external resistor of >= 1 kΩ. It can be left unconnected when not in use. SYNCb 48 I Output Clock Synchronization. 2 An active low signal on this pin resets the output dividers for the purpose of realigning the output clocks. This pin is internally pulled-up and can be left unconnected when not in use. 3 I 4 I Input Reference Select. 2 The IN_SEL[1:0] pins are used in manual pin controlled mode to select the active clock input as shown in Table 3.2 Table 6.2 on page 10. These pins are internally pulled-down and may be left unconnected when unused. m en de d fo r N ew D es ig ns Control/Status IN_SEL0 IN_SEL1 Power VDD 25 om RSVD 32 P 46 P VDD 60 P VDDA 13 P Core Supply Voltage. The device operates from a 1.8 V supply. A 1 µF bypass capacitor should be placed very close to each pin. Core Supply Voltage 3.3 V. This core supply pin requires a 3.3 V power source. A 1 µF bypass capacitor should be placed very close to this pin. N ot R ec VDD Reserved. Leave disconnected. silabs.com | Smart. Connected. Energy-friendly. Rev. 1.0 | 43 Si5380 Rev D Data Sheet Pin Description Pin Name Pin Number Pin Type1 VDDO0 22 P VDDO1 26 P VDDO2 29 P VDDO3 33 P VDDO4 36 P VDDO5 40 P VDDO6 43 P VDDO7 49 P VDDO8 52 P VDDO9 57 P D es ig ns Output Clock Supply Voltage. Supply voltage (3.3 V, 2.5 V, 1.8 V) for OUTx, OUTxb Outputs. Note that VDDO0 supplies power to OUT0 and OUT0A; VDDO9 supplies power to OUT9 and OUT9A. Leave VDDO pins of unused output drivers unconnected. An alternative option is to connect the VDDO pin to a power supply and disable the output driver to minimize current consumption. A 1 µF bypass capacitor should be placed very close to each connected VDDO pin. P Ground Pad. This pad provides connection to ground and must be connected for proper operation. N ew GND PAD Function N ot R ec om m en de d fo r Note: 1. I = Input, O = Output, P = Power 2. The IO_VDD_SEL control bit (0x0943 bit 0) selects 3.3 V or 1.8 V operation. 3. All status pins except I2C and SPI are push-pull. silabs.com | Smart. Connected. Energy-friendly. Rev. 1.0 | 44 Si5380 Rev D Data Sheet Package Outline N ew D es ig ns 10. Package Outline fo r Figure 10.1. Si5380 9x9 mm 64-QFN Package Diagram Table 10.1. Package Diagram Dimensions A A1 b D D2 om E2 NOM MAX 0.80 0.85 0.90 0.00 0.02 0.05 0.18 0.25 0.30 5.10 e E MIN m en de d Dimension 9.00 BSC 5.20 5.30 0.50 BSC 9.00 BSC 5.10 5.20 5.30 0.30 0.40 0.50 aaa — — 0.15 bbb — — 0.10 ccc — — 0.08 ddd — — 0.10 N ot R ec L Note: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to the JEDEC Solid State Outline MO-220. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. silabs.com | Smart. Connected. Energy-friendly. Rev. 1.0 | 45 Si5380 Rev D Data Sheet PCB Land Pattern N ew D es ig ns 11. PCB Land Pattern Figure 11.1. 9x9 mm 64-QFN Land Pattern Dimension C1 fo r Table 11.1. PCB Land Pattern Dimensions 8.90 8.90 E 0.50 X1 0.30 Y1 0.85 X2 5.30 Y2 5.30 m en de d C2 om Notes: Max ec General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This Land Pattern Design is based on the IPC-7351 guidelines. 3. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition is calculated based on a fabrication Allowance of 0.05 mm. N ot R Solder Mask Design 1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 μm minimum, all the way around the pad. Stencil Design 1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. The stencil thickness should be 0.125 mm (5 mils). 3. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads. 4. A 3x3 array of 1.25 mm square openings on 1.80 mm pitch should be used for the center ground pad. Card Assembly 1. A No-Clean, Type-3 solder paste is recommended. 2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. silabs.com | Smart. Connected. Energy-friendly. Rev. 1.0 | 46 Si5380 Rev D Data Sheet Top Marking 64-QFN D N ew Si5380ARxxxxx-GM YYWWTTTTTT e4 TW es ig ns 12. Top Marking fo r Figure 12.1. Si5380 Top Marking Table 12.1. Top Marking Explanation Characters Description 1 Si5380A- Base part number for Ultra Low Phase Noise, 12-output JESD204B Clock Generator: m en de d Line Si5380A: 12-output clock generator; 64-QFN – = Dash character. 2 Rxxxxx-GM R = Product revision. (See Ordering Guide for current ordering revision). ec YYWWTTTTTT R 3 om xxxxx = Customer specific NVM sequence number. Optional NVM code assigned for custom, factory pre-programmed devices. N ot 4 Circle w/ 1.6 mm diameter Characters are not included for standard, factory default configured devices. See Ordering Guide for more information. -GM = Package (QFN) type and temperature range (–40 to +85 °C). YYWW = Characters correspond to the year (YY) and work week (WW) of package assembly. TTTTTT = Manufacturing trace code. Pin 1 indicator; left-justified e4 Pb-free symbol; Center-Justified TW TW = Taiwan; Country of Origin (ISO Abbreviation) silabs.com | Smart. Connected. Energy-friendly. Rev. 1.0 | 47 Si5380 Rev D Data Sheet Device Errata 13. Device Errata N ot R ec om m en de d fo r N ew D es ig ns Log in or register at www.silabs.com to access the device errata document. silabs.com | Smart. Connected. Energy-friendly. Rev. 1.0 | 48 Si5380 Rev D Data Sheet Document Change List 14. Document Change List 14.1 Revision 1.0 N ot R ec om m en de d fo r N ew D es ig ns July 19, 2016 • Initial release. silabs.com | Smart. Connected. Energy-friendly. Rev. 1.0 | 49 Table of Contents 1. Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 . 9 . 9 .10 .10 .10 .10 .11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 .12 .12 .13 .13 .13 .14 .15 3.5 Outputs . . . . . . . . . . . . . . . . . . . . 3.5.1 Output Crosspoint . . . . . . . . . . . . . . . . 3.5.2 Output Signal Format. . . . . . . . . . . . . . . 3.5.3 Output Terminations . . . . . . . . . . . . . . . 3.5.4 Programmable Common Mode Voltage For Differential Outputs 3.5.5 LVCMOS Output Terminations . . . . . . . . . . . 3.5.6 LVCMOS Output Impedance and Drive Strength Selection . . 3.5.7 LVCMOS Output Signal Swing . . . . . . . . . . . 3.5.8 LVCMOS Output Polarity . . . . . . . . . . . . . 3.5.9 Output Enable/Disable . . . . . . . . . . . . . . 3.5.10 Output Disable During LOL . . . . . . . . . . . . 3.5.11 Output Disable During XAXB_LOS . . . . . . . . . . 3.5.12 Output Driver State When Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 .15 .15 .16 .16 .16 .17 .17 .17 .17 .17 .17 .17 Table of Contents 50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 External Reference (XA/XB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . m en de d fo r 3.3 Inputs (IN0, IN1, IN2, IN3/FB_IN) . . . . . . . 3.3.1 Input Configuration and Terminations . . . . . 3.3.2 Manual Input Selection (IN0, IN1, IN2, IN3/FB_IN) . 3.3.3 Automatic Input Switching (IN0, IN1, IN2, IN3/FB_IN) 3.3.4 Hitless Input Switching . . . . . . . . . . 3.3.5 Ramped Input Switching. . . . . . . . . . 3.3.6 Glitchless Input Switching . . . . . . . . . 3.3.7 Zero Delay Mode . . . . . . . . . . . . N ew 3.1 Frequency Configuration . . . . . . . . . . . 3.1.1 Si5380 LTE Frequency Configuration . . . . . . 3.1.2 Si5380 Configuration for JESD204B Clock Generation 3.1.3 DSPLL Loop Bandwidth . . . . . . . . . . . 3.1.4 Fastlock . . . . . . . . . . . . . . . . 3.1.5 Modes of Operation . . . . . . . . . . . . 3.1.6 Initialization and Reset . . . . . . . . . . . 3.1.7 Freerun Mode . . . . . . . . . . . . . . 3.1.8 Lock Acquisition . . . . . . . . . . . . . 3.1.9 Locked Mode . . . . . . . . . . . . . . 3.1.10 Holdover Mode . . . . . . . . . . . . . N ot R ec om 3.4 Fault Monitoring . . . 3.4.1 Input LOS Detection . 3.4.2 XA/XB LOS Detection 3.4.3 OOF Detection . . . 3.4.4 Precision OOF Monitor 3.4.5 Fast OOF Monitor . . 3.4.6 LOL Detection . . . 3.4.7 Interrupt Pin INTRb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D . . . . . . . . . . . es ig ns 3. Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 3 4 5 5 6 6 6 6 7 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 .18 .18 3.6 Power Management . . . 3.6.1 Power Down Pin (PDNb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 .19 3.7 In-Circuit Programming . . . . . . . . . . . . . . . . . . . . . . . . . . .19 3.8 Serial Interface . . . . . . . . . . . . . . . . . 3.9 Custom Factory Preprogrammed Devices . . . . . . . . . . . . . . es ig ns 3.5.13 Synchronous Enable/Disable Feature . 3.5.14 Output Skew Control (Δt0 - Δt4) . . . 3.5.15 Output Divider (R) Synchronization. . . . . . . . . . .19 . . . . . . . . .19 3.10 Enabling Features and/or Configuration Settings Not Available in ClockBuilder Pro for Factory Preprogrammed Devices . . . . . . . . . . . . . . . . . . . . . . . . . . 19 . D 4. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 22 6. Typical Application Diagrams . . . . . . . . . . . . . . . . . . . . . . . . 36 7. Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 37 8. Typical Operating Characteristics (Phase Noise & Jitter) . . . . . . . . . . . . . . 38 9. Pin Description 40 N ew 5. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . fo r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 11. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 12. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 13. Device Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 14. Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . 49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Table of Contents 51 N ot R ec om 14.1 Revision 1.0 . m en de d 10. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . es ig ns D N ew fo r One-click access to Timing tools, documentation, software, source code libraries & more. Available for Windows and iOS (CBGo only). www.silabs.com/CBPro om Timing Portfolio www.silabs.com/timing m en de d ClockBuilder Pro SW/HW www.silabs.com/CBPro Quality www.silabs.com/quality Support and Community community.silabs.com N ot R ec Disclaimer Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. 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