SI5386A-E12144-GMR

Si5386 Data Sheet 12-Channel, Any-Frequency, Any-Output wireless Jitter Attenuator / Clock Multiplier with Ultra-Low Noise The Si5386 is an ultra high performance wireless jitter attenuator with any frequency outputs for eCPRI (ethernet-based Common Public Radio Interface) applications, which demand the highest level of integration and phase noise performance. Based on Skyworks Solutions’ 4th generation DSPLL technology, the Si5386 combines frequency synthesis and jitter attenuation in a highly integrated digital solution with a cost-effective oscillator, and without the need of any external loop filter components. The fixed frequency oscillator provides frequency stability for free-run and holdover modes. This all-digital solution provides superior performance that is highly immune to external board disturbances such as power supply noise. eCPRI-based remote radio heads and fixed wireless systems require a diverse set of clocks such as ADC/DAC, RF LOs, and Ethernet clocks. The Si5386 architecture is designed to deliver high-performance JESD204B DCLK and SYSREF clock pairs and flexible any-rate clocks for non-CPRI clocks such as Ethernet and system reference clocks all from a single IC. KEY FEATURES • Flexible timing in a single IC • Generates any combination of output frequencies from any input frequency • Input frequency range: • Differential: 7.68 MHz to 750 MHz • LVCMOS: 7.68 MHz to 250 MHz • Output frequency range (Integer): • Differential: up to 2.94912 GHz • Output frequency range (fractional): • Differential: up to 735 MHz • LVCMOS: up to 250 MHz • Ultra-low RMS jitter: • 72 fs typ (12 kHz–20 MHz) • Phase noise of 122.88MHz carrier frequency: • 118 dBc/Hz @ 100Hz offset • ITU-T G.8262 compliant Applications: • Wireless Infrastructure • eCPRI RRH (Remote Radio Head) • BBU (Baseband Unit) • Small Cell and μBTS • DOCSIS • Test and Measurement 54 MHz OSC IN_SEL IN0 ÷INT IN1 ÷INT IN2 ÷INT IN3/FB_IN ÷INT DSPLL ÷INT OUT0 ÷INT 0 OUT1 Multi Synth ÷INT OUT2 Multi Synth ÷INT OUT3 ÷INT OUT4 Multi Synth Multi Synth I2C_SEL SDA/SDIO A1/SDO SCLK Multi Synth SPI/ I2C A0/CS OUT0A ÷INT ÷INT 0 OUT5 ÷INT OUT6 ÷INT OUT7 ÷INT OUT8 NVM LOL INTR Status Monitors PDN 1 RST ÷INT 0 OUT9 ÷INT OUT9A SYNC OE Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.02 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • January 17, 2022 1 Table of Contents 1. Features List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3. Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.1 Frequency Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.2 DSPLL Loop Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.3 Fastlock Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 External Reference (XA/XB) . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.6 Inputs (IN0, IN1, IN2, IN3) . . . . . . . . 3.6.1 Manual Input Switching (IN0, IN1, IN2, IN3) . 3.6.2 Automatic Input Selection (IN0, IN1, IN2, IN3) 3.6.3 Hitless Input Switching . . . . . . . . 3.6.4 Ramped Input Switching . . . . . . . 3.6.5 Glitchless Input Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 . 9 .10 .10 .10 .10 3.7 Fault Monitoring . . . . . . . 3.7.1 Input LOS Detection. . . . . 3.7.2 Reference Clock LOS Detection. 3.7.3 OOF Detection . . . . . . 3.7.4 LOL Detection . . . . . . . 3.7.5 Interrupt Pin (INTRb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 .11 .11 .11 .12 .13 3.8 Outputs . . . . . . . . . . . . . . . . . . . 3.8.1 Output Crosspoint . . . . . . . . . . . . . . 3.8.2 Output Signal Format . . . . . . . . . . . . . 3.8.3 Output Terminations . . . . . . . . . . . . . . 3.8.4 Programmable Amplitude For Differential Outputs. . . . 3.8.5 LVCMOS Output Impedance and Drive Strength Selection . 3.8.6 LVCMOS Output Signal Swing . . . . . . . . . . 3.8.7 LVCMOS Output Polarity . . . . . . . . . . . . 3.8.8 Output Enable/Disable . . . . . . . . . . . . . 3.8.9 Output Disable During LOL . . . . . . . . . . . 3.8.10 Output Disable During Reference LOS . . . . . . . 3.8.11 Output Driver State When Disabled . . . . . . . . 3.8.12 Synchronous Output Disable Feature . . . . . . . 3.8.13 Static Output Skew Control . . . . . . . . . . . 3.8.14 Dynamic Output Skew Control . . . . . . . . . . 3.8.15 Zero Delay Mode . . . . . . . . . . . . . . 3.8.16 Output Divider (R) Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 .14 .14 .15 .15 .16 .16 .16 .16 .16 .16 .16 .17 .17 .17 .17 .18 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.02 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • January 17, 2022 2 . . 3.4 Modes of Operation . . 3.4.1 Initialization and Reset 3.4.2 Freerun Mode . . . 3.4.3 Lock Acquisition Mode 3.4.4 Locked Mode . . . 3.4.5 Holdover Mode . . 3.4.6 VCO Freeze Mode . 2 . . . . . . . . . . . . . . . . . . . . . . . . 6 7 7 7 7 8 8 3.9 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 3.10 In-Circuit Programming . . . . . . . . . . . . . . . . . . . . . . . . . . .18 3.11 Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . .18 3.12 Custom Factory Preprogrammed Parts . . . . . . . . . . . . . . . . . . . . .18 3.13 Enabling Features and/or Configuration Settings Unavailable in ClockBuilder Pro for Factory Preprogrammed Devices . . . . . . . . . . . . . . . . . . . . . . . . . .18 4. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 . . 4.1 Addressing Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 4.2 High-Level Register Map . . . . . . . . . . . . . . . . . . . . . . . . . .20 5. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6. Detailed Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7. Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . 36 8. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9. Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9.1 Si5386 9x9 mm 64-QFN Package Diagram . . .44 10. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 11. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 12. Device Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 13. Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3 . . . . . . . . . . . . . . . . . 13.1 Revision 1.02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 13.2 Revision 1.01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 13.3 Revision 1.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 13.4 Revision 0.9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.02 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • January 17, 2022 3 Si5386 Data Sheet • Features List 1. Features List The Si5386 features are listed below: • ITU-T G.8262 compliant • Flexible timing in a single IC • Generates any combination of output frequencies from any input frequency • Input frequency range: • Differential: 7.68 MHz to 750 MHz • LVCMOS: 7.68 MHz to 250 MHz • Output frequency range (Integer): • Differential: up to 2.94912 GHz with JESD204B support • Output frequency range (fractional): • Differential: up to 735 MHz • LVCMOS: up to 250 MHz • Ultra-low RMS jitter (12kHz - 20MHz): • 72 fs typ at 122.88 MHz • 88 fs typ at 156.25 MHz • 79 fs typ at 322.265625 MHz • Programmable jitter attenuation bandwidth from 1 Hz to 4 kHz • Phase noise of 122.88 MHz carrier frequency: • -118 dBc/Hz @ 100 Hz offset • -133 dBc/Hz @ 1 kHz offset • -142 dBc/Hz @ 10 kHz offset • -149 dBc/Hz @ 100 kHz offset • -154 dBc/Hz @ 1 MHz offset • Highly configurable outputs compatible with LVDS, LVPECL, LVCMOS, CML, and HCSL. CML outputs can be programmed to have 100-1600 mVpp single-ended swing. 4 • • • • • • • • • • • • • • • • Status monitoring (LOS, OOF, LOL) Pin controlled input switching DSPLL with special wireless calibration Optional zero delay mode Hitless input clock switching: automatic or manual Automatic free-run and holdover modes Fastlock feature Glitchless on the fly output frequency changes Core voltage: • VDD: 1.8 V ±5% • VDDA: 3.3 V ±5% Independent output clock supply pins: 3.3 V, 2.5 V, or 1.8 V Output-output skew: 20 ps typ Serial interface: I2C or SPI In-circuit programmable with non-volatile OTP memory ClockBuilder ProTM software simplifies device configuration Temperature range: –40 to +85 °C Pb-free, RoHS-6 compliant Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.02 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • January 17, 2022 4 Si5386 Data Sheet • Ordering Guide 2. Ordering Guide Ordering Part NumReference ber (OPN) Number of Input/Output Clocks Output Clock Frequency Range (MHz) 4/12 0.0001 to 2949.12 MHz Supported Frequency Synthesis Package Modes Temperature Range Si5386 Si5386A-E-GM1, 2 External XO Integer and 64-QFN Fractional 9×9 mm –40 to 85 °C Notes: 1. Add an R at the end of the OPN to denote tape and reel ordering options. 2. Custom, factory preprogrammed devices are available. Ordering part numbers are assigned by Skyworks and the ClockBuilder Pro software utility. Custom part number format is “Si5386A-Exxxxx-GM” where “xxxxx” is a unique numerical sequence representing the preprogrammed configuration. Figure 2.1. Ordering Part Number Fields 5 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.02 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • January 17, 2022 5 Si5386 Data Sheet • Functional Description 3. Functional Description The Si5386’s internal DSPLL provides jitter attenuation and any-frequency multiplication of the selected input frequency without the need for (external) VCXOs and loop filters. Input switching is controlled manually or automatically using an internal state machine. The external oscillator provides a frequency reference which determines output frequency stability and accuracy while the device is in free-run or holdover mode. The high-performance MultiSynthdividers (N) generate integer or fractionally related output frequencies for the output stage. A crosspoint switch connects any of the MultiSynth generated frequencies to any of the outputs. Additional integer division (R) determines the final output frequency. Further, the DSPLL is specially calibrated for ultra-low phase noise when configured for CPRI frequencies with JESD204B outputs. This integration provides a clock-tree-on-a-chip solution for applications that need a mix of 4G/CPRI, Ethernet, and general-purpose frequencies. 3.1 Frequency Configuration The frequency configuration of the DSPLL is programmable through the serial interface and can also be stored in non-volatile memory. The combination of fractional input dividers (Pn/Pd), fractional frequency multiplication (Mn/Md), fractional output MultiSynth division (Nn/ Nd), and integer output division (Rn) allows the generation of virtually any output frequency on any of the outputs with very low-phase noise suitable for wireless applications when synthesizing CPRI frequencies. All divider values for a specific frequency plan are easily determined using the ClockBuilder Pro utility. 3.2 DSPLL Loop Bandwidth The DSPLL loop bandwidth determines the amount of input clock jitter attenuation. Register configurable DSPLL loop bandwidth settings in the range of 20 Hz to 4 kHz are available for selection. Since the loop bandwidth is controlled digitally, the DSPLL will always remain stable with less than 0.1 dB of peaking regardless of the loop bandwidth selection. 3.3 Fastlock Feature Selecting a low DSPLL loop bandwidth (e.g., 20 Hz) will generally lengthen the lock acquisition time. The fastlock feature allows setting a temporary Fastlock Loop Bandwidth that is used during the lock acquisition process. Higher fastlock loop bandwidth settings will enable the DSPLLs to lock faster. Fastlock Loop Bandwidth settings of in the range of 20 Hz to 4 kHz are available for selection. The DSPLL will revert to its normal loop bandwidth once lock acquisition has completed. 3.4 Modes of Operation Once initialization is complete the DSPLL operates in one of five modes: Free-run Mode, VCO Freeze Mode, Lock Acquisition Mode, Locked Mode, or Holdover Mode. A state diagram showing the modes of operation is shown in Figure 3.1 Modes of Operation on page 7. The following sections describe each of these modes in greater detail. 6 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.02 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • January 17, 2022 6 Si5386 Data Sheet • Functional Description 3.4.1 Initialization and Reset Once power is applied, the device begins an initialization period where it downloads default register values and configuration data from NVM and performs other initialization tasks. Communicating with the device through the serial interface is possible once this initialization period is complete. No clocks are generated until the initialization is complete. There are two types of resets available. A hard reset is functionally similar to a device power-up. All registers are restored to the values stored in NVM, and all circuits including the serial interface is restored to their initial state. A hard reset is initiated using the RSTb pin or by asserting the hard reset register bit. A soft reset bypasses the NVM download. It is simply used to initiate register configuration changes. Power-Up Reset and Initialization No valid input clocks selected An input is qualified and available for selection VCO Freeze State No valid input clocks available for selection Free-run Valid input clock selected Lock Acquisition (Fast Lock) An input is qualified and available for selection Phase lock on selected input clock is achieved Locked Mode Holdover Mode Input Clock Switch Selected input clock fails Yes Yes No Holdover History Valid? Other Valid Clock Inputs No Available? Figure 3.1. Modes of Operation 3.4.2 Freerun Mode The DSPLL will automatically enter freerun mode once power is applied to the device and initialization is complete. The frequency accuracy of the generated output clocks in freerun mode is entirely dependent on the frequency accuracy of the reference clock on the XA/XB pins. For example, if the oscillator stability is ±50 ppm, then all the output clocks will be generated at their configured frequency with ±50 ppm stability in freerun mode. Any drift of the oscillator frequency is tracked at the output clock frequencies. Free run mode is maintained as long as no input clocks are valid. 3.4.3 Lock Acquisition Mode The device monitors all inputs for a valid clock. If at least one valid clock is available for synchronization, the DSPLL automatically starts the lock acquisition process. If the fast lock feature is enabled, the DSPLL acquires lock using the Fastlock Loop Bandwidth setting and then transition to the DSPLL Loop Bandwidth setting when lock acquisition is complete. During lock acquisition, the output generates a clock that follows the VCO frequency change as it pulls in to the input clock frequency. 3.4.4 Locked Mode Once locked, the DSPLL generates output clocks that are both frequency and phase locked to their selected input clocks. At this point, any oscillator frequency drift does not affect the output frequency. A loss of lock pin (LOL) and status bit indicate when lock is achieved. See 3.7.4 LOL Detection for more details on the operation of the loss-of-lock circuit. 7 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.02 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • January 17, 2022 7 Si5386 Data Sheet • Functional Description 3.4.5 Holdover Mode If holdover history is valid, the DSPLL automatically enters holdover mode when the selected input clock becomes invalid and no other valid input clocks are available for selection. The DSPLL uses an averaged input clock frequency as its final holdover frequency to minimize the disturbance of the output clock phase and frequency when an input clock suddenly fails. The holdover circuit for the DSPLL stores up to 120 seconds of historical frequency data while locked to a valid clock input. The final averaged holdover frequency value is calculated from a programmable window within the stored historical frequency data. Both the window size and the delay are programmable as shown in the figure below. The window size determines the amount of holdover frequency averaging. The delay value allows ignoring frequency data that may be corrupt just before the input clock failure. Clock Failure and Entry into Holdover Historical Frequency Data Collected time 120 seconds Programmable historical data window used to determine the final holdover value Programmable delay 0 Figure 3.2. Programmable Holdover Window When entering holdover, the DSPLL pulls its output clock frequency to the calculated averaged holdover frequency. While in holdover, the output frequency drift is entirely dependent on the external reference clock connected to the XA/XB pins. If the clock input becomes valid, the DSPLL automatically exits the holdover mode and re-acquires lock to the new input clock. This process involves pulling the output clock frequency to achieve frequency and phase lock with the input clock. This pull-in process is glitchless and its rate is controlled by the DSPLL or the Fastlock bandwidth. The DSPLL output frequency when exiting holdover can be ramped (recommended). Just before the exit is initiated, the difference between the current holdover frequency and the new desired frequency is measured. Using the calculated difference and a user-selectable ramp rate, the output is linearly ramped to the new frequency. The ramp rate can be 0.2 ppm/s, 40,000 ppm/s, or any of about 40 values in between. The DSPLL loop BW does not limit or affect ramp rate selections (and vice versa). CBPro defaults to ramped exit from holdover. The same ramp rate settings are used for both exit from holdover and ramped input switching. For more information on ramped input switching, see 3.6.4 Ramped Input Switching. Note: If ramped holdover exit is not selected, the holdover exit is governed either by (1) the DSPLL loop BW or (2) a user-selectable holdover exit BW. 3.4.6 VCO Freeze Mode If holdover history is not valid, the DSPLL automatically enters VCO Freeze mode when the selected input clock becomes invalid and no other valid input clocks are available for selection. The DSPLL uses the last measured input frequency to set the output frequencies in the VCO Freeze mode. If an input clock becomes valid, the DSPLL automatically exits the VCO Freeze mode and re-acquires lock to the new input clock. 8 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.02 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • January 17, 2022 8 Si5386 Data Sheet • Functional Description 3.5 External Reference (XA/XB) An external crystal oscillator (XO) is required to set the reference for the Si5386. Only a 54 MHz XO is used as the reference to the wireless jitter attenuator. For the jitter and phase noise performance that is specified in this data sheet, the only XO's that can be used are the 54 MHz XO's recommended for the Si5381/82/86 in the Si534x/8x Jitter Attenuators Recommended Crystal, TCXO and OCXOs Reference Manual. Place the XO as close to the XaXb pins as possible. See figure below for guidelines on how to connect the XO to the XaXb input. C1 increases the slew rate to the Xa input, which is needed to get the jitter and phase noise performance that is specifed in this data sheet. XO/Clock XO/Clock XO VDD 3.3V 2.5V 0.1 uf 0.1 uf 50 50 XB XA Note: 2.5 Vpp 0.1 uf diff max nc 2xCL Differential XO/Clock Connection Appro. Vpp @ XA Input 1.8V 1.8V nc X1 X2 2xCL OSC ÷ PREF nc XA 2xCL C1 12 pf 30 pf Note: 2.0 Vpp_se max 0.1 uf XB X2 2xCL OSC R2 0.1 uf nc X1 R2 549 Ω 732 Ω C1 R1 0.1 uf R1 453 Ω 274 Ω ÷ PREF Single-Ended XO/Clock Connection Figure 3.3. XA/XB Input 3.6 Inputs (IN0, IN1, IN2, IN3) There are four inputs that can be used to synchronize the DSPLL. The inputs accept both differential and single-ended clocks. Input selection can be manual (pin or register controlled) or automatic with user definable priorities. See the Si5386 Rev. E Family Reference Manual for details and input termination requirements. 3.6.1 Manual Input Switching (IN0, IN1, IN2, IN3) Input clock selection can be made manually using the IN_SEL[1:0] pins or through a register. A register bit determines input selection as pin selectable or register selectable. The IN_SEL pins are selected by default. If there is no clock signal on the selected input, the device automatically enters free-run or holdover mode. When the zero delay mode is enabled, IN3 becomes the feedback input (FB_IN) and is not available for selection as a clock input. Table 3.1. Manual Input Selection Using IN_SEL[1:0] Pins IN_SEL[1:0] 9 Selected Input Zero Delay Mode Disabled Zero Delay Mode Enabled 0 0 IN0 IN0 0 1 IN1 IN1 1 0 IN2 IN2 1 1 IN3 Reserved Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.02 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • January 17, 2022 9 Si5386 Data Sheet • Functional Description 3.6.2 Automatic Input Selection (IN0, IN1, IN2, IN3) An automatic input selection state machine is available in addition to the manual switching option. In automatic mode, the selection criteria is based on input clock qualification, input priority, and the revertive option. Only input clocks that are valid can be selected by the automatic clock selection state machine. If there are no valid input clocks available the DSPLL will enter the holdover mode. With revertive switching enabled, the highest priority input with a valid input clock is always selected. If an input with a higher priority becomes valid then an automatic switchover to that input is initiated. With non-revertive switching, the active input always remains selected while it is valid. If it becomes invalid an automatic switchover to a valid input with the highest priority is initiated. 3.6.3 Hitless Input Switching Hitless switching is a feature that prevents a phase offset from propagating to the output when switching between two clock inputs that have a fixed phase relationship. A hitless switch can only occur when the two input frequencies are frequency locked meaning that they have to be exactly at the same frequency, or at a fractional frequency relationship to each other. When hitless switching is enabled, the DSPLL simply absorbs the phase difference between the two input clocks during a input switch. When disabled, the phase difference between the two inputs is propagated to the output at a rate determined by the DSPLL Loop Bandwidth. The hitless switching feature supports clock frequencies down to the minimum input frequency of 7.68 MHz. 3.6.4 Ramped Input Switching When switching between two plesiochronous input clocks (i.e., the frequencies are "almost the same" but not quite), ramped input switching should be enabled to ensure a smooth transition between the two inputs. Ramped input switching avoids frequency transients and overshoot when switching between frequencies and so is the default switching mode in CBPro. The feature should be turned off when switching between input clocks that are always frequency locked (i.e., are always the same exact frequency). The same ramp rate settings are used for both holdover exit and clock switching. For more information on ramped exit from holdover see 3.4.5 Holdover Mode. 3.6.5 Glitchless Input Switching The DSPLL has the ability of switching between two input clock frequencies that are up to 40 ppm apart. The DSPLL will pull-in to the new frequency using the DSPLL Loop Bandwidth or using the Fastlock Loop Bandwidth if enabled. The loss of lock (LOL) indicator will assert while the DSPLL is pulling-in to the new clock frequency. There will be no abrupt phase change at the output during the transition. 3.7 Fault Monitoring All four input clocks (IN0, IN1, IN2, IN3/FB_IN) are monitored for loss of signal (LOS) and out-of-frequency (OOF) as shown in the figure below. The reference at the XA/XB pins is also monitored for LOS since it provides a critical reference clock for the DSPLL. There is also a Loss Of Lock (LOL) indicator which is asserted when the DSPLL loses synchronization. XA XB Si5386 IN0 IN0b IN1 IN1b IN2 IN2b IN3/FB_IN IN3/FB_INb ÷P0 LOS OOF Precision Fast ÷P1 LOS OOF Precision Fast ÷P2 LOS OOF Precision Fast ÷P3 LOS OOF Precision Fast LOS DSPLL LOL PD LPF ÷M Figure 3.4. Si5386 Fault Monitors (Grade A) 10 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.02 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • January 17, 2022 10 Si5386 Data Sheet • Functional Description 3.7.1 Input LOS Detection The loss of signal monitor measures the period of each input clock cycle to detect phase irregularities or missing clock edges. Each of the input LOS circuits has its own programmable sensitivity which allows ignoring missing edges or intermittent errors. Loss of signal sensitivity is configurable using the ClockBuilder Pro utility. The LOS status for each of the monitors is accessible by reading a status register. The live LOS register always displays the current LOS state and a sticky register always stays asserted until cleared. An option to disable any of the LOS monitors is also available. Monitor Sticky LOS LOS LOS en Live Figure 3.5. LOS Status Indicators 3.7.2 Reference Clock LOS Detection A LOS monitor is available to ensure that the external reference oscillator is valid. By default the output clocks are disabled when XAXB_LOS is detected. This feature can be disabled such that the device will continue to produce output clocks when XAXB_LOS is detected. 3.7.3 OOF Detection Each input clock is monitored for frequency accuracy with respect to a OOF reference which it considers as its “0_ppm” reference. This OOF reference can be selected as either: • The XA/XB reference • Any input clock (IN0, IN1, IN2, IN3) The final OOF status is determined by the combination of both a precise OOF monitor and a fast OOF monitor as shown in the figure below. An option to disable either monitor is also available. The live OOF register always displays the current OOF state, and its sticky register bit stays asserted until cleared. Monitor OOF Sticky en Precision LOS OOF Fast en Live Figure 3.6. OOF Status Indicator 11 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.02 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • January 17, 2022 11 Si5386 Data Sheet • Functional Description 3.7.3.1 Precision OOF Monitor The precision OOF monitor circuit measures the frequency of all input clocks to within ±1 ppm accuracy with respect to the selected OOF frequency reference. A valid input clock frequency is one that remains within the OOF frequency range which is register configurable up to 511 ppm in steps of 1/16 ppm. If the Xa input is chosen as the frequency reference, then the minimum OOF assert threshold should be 60 ppm or greater to account for the ±50 ppm error from the recommended XO at the Xa input. A configurable amount of hysteresis is also available to prevent the OOF status from toggling at the failure boundary. An example is shown in the figure below. In this case, the OOF monitor is configured with a valid frequency range of ±60 ppm and with 2 ppm of hysteresis. An option to use one of the input pins (IN0–IN3) as the 0 ppm OOF reference instead of the external XO reference is available. This option is register configurable. OOF Declared fIN Hysteresis Hysteresis OOF Cleared -60 ppm (Set) -58 ppm (Clear) +58 ppm (Clear) 0 ppm +60 ppm (Set) OOF Reference Figure 3.7. Example of Precise OOF Monitor Assertion and Deassertion Triggers 3.7.3.2 Fast OOF Monitor Because the precision OOF monitor needs to provide 1/16 ppm of frequency measurement accuracy, it must measure the monitored input clock frequencies over a relatively long period of time. This may be too slow to detect an input clock that is quickly ramping in frequency. An additional level of OOF monitoring called the Fast OOF monitor runs in parallel with the precision OOF monitors to quickly detect a ramping input frequency. The Fast OOF monitor asserts OOF on an input clock frequency that has changed by greater than ±1,000 ppm to ±16,000 ppm. This threshold can be configured in CBPro. 3.7.4 LOL Detection The Loss Of Lock (LOL) monitor asserts a LOL register bit when the DSPLL has lost synchronization with its selected input clock. There is also a dedicated loss of lock pin that reflects the loss of lock condition. The LOL monitor functions by measuring the frequency difference between the input and feedback clocks at the phase detector. There are two LOL frequency monitors, one that sets the LOL indicator (LOL Set) and another that clears the indicator (LOL Clear). An optional timer is available to delay clearing of the LOL indicator to allow additional time for the DSPLL to completely lock to the input clock. The timer is also useful to prevent the LOL indicator from toggling or chattering as the DSPLL completes lock acquisition. A block diagram of the LOL monitor is shown in the figure below. The live LOL register always displays the current LOL state and a sticky register always stays asserted until cleared. The LOL pin reflects the current state of the LOL monitor. LOL Monitor Sticky LOL Clear Timer LOL Set LOS LOL Live LOLb DSPLL fIN PD Feedback Clock LPF ÷M Si5386 Figure 3.8. LOL Status Indicators The LOL frequency monitors have an adjustable sensitivity which is register configurable from 0.1 ppm to 10,000 ppm. Having two separate frequency monitors allows for hysteresis to help prevent chattering of LOL status. 12 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.02 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • January 17, 2022 12 Si5386 Data Sheet • Functional Description An example configuration where LOCK is indicated when there is less than 0.1 ppm frequency difference at the inputs of the phase detector and LOL is indicated when there’s more than 1 ppm frequency difference is shown in the following figure. Clear LOL Threshold Set LOL Threshold Lock Acquisition LOL Hysteresis Lost Lock LOCKED 0 0.1 1 10,000 Phase Detector Frequency Difference (ppm) Figure 3.9. LOL Set and Clear Thresholds Note: In this document, the terms, LVDS and LVPECL, refer to driver formats that are compatible with these signaling standards. An optional timer is available to delay clearing of the LOL indicator to allow additional time for the DSPLL to completely lock to the input clock. The timer is also useful to prevent the LOL indicator from toggling or chattering as the DSPLL completes lock acquisition. The configurable delay value depends on frequency configuration and loop bandwidth of the DSPLL and is automatically calculated using the ClockBuilder Pro utility. 3.7.5 Interrupt Pin (INTRb) An interrupt pin (INTRb) indicates a change in state of the status indicators (LOS, OOF, LOL, HOLD). Any of the status indicators are maskable to prevent assertion of the interrupt pin. The state of the INTRb pin is reset by clearing the status register that caused the interrupt. 3.8 Outputs The Si5386 supports up to twelve differential output drivers. Each driver has a configurable voltage swing and common mode voltage covering a wide variety of differential signal formats. In addition to supporting differential signals, any of the outputs can be configured as single-ended LVCMOS (3.3 V, 2.5 V, or 1.8 V) providing up to 24 single-ended outputs, or any combination of differential and single-ended outputs. 13 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.02 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • January 17, 2022 13 Si5386 Data Sheet • Functional Description 3.8.1 Output Crosspoint A crosspoint allows any of the output drivers to connect with any of the MultiSynths as shown in the figure below. The crosspoint configuration is programmable and can be stored in NVM so that the desired output configuration is ready at power up. VDDO0 Multi N0n ÷ Synth N0d ÷R0A Multi N1n ÷ Synth N1d ÷R0 OUT0 OUT0b ÷R1 OUT1 OUT1b ÷R2 OUT2 OUT2b Multi N2n ÷ Synth N2d Multi N3n ÷ Synth N3d Multi N4n ÷ Synth N4d OUT0A OUT0Ab VDDO1 VDDO2 VDDO3 ÷R3 OUT3 OUT3b ÷R4 OUT4 OUT4b ÷R5 VDDO5 OUT5 OUT5b ÷R6 VDDO6 OUT6 OUT6b ÷R7 VDDO7 OUT7 OUT7b VDDO4 VDDO8 ÷R8 OUT8 OUT8b VDDO9 ÷R9 ÷R9A OUT9 OUT9b OUT9A OUT9Ab Figure 3.10. MultiSynth to Output Driver Crosspoint 3.8.2 Output Signal Format The differential output swing and common mode voltage are both fully programmable covering a wide variety of signal formats including LVDS and LVPECL. In addition to supporting differential signals, any of the outputs can be configured as LVCMOS (3.3 V, 2.5 V, or 1.8 V) drivers providing up to 24 single-ended outputs, or any combination of differential and single-ended outputs. 14 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.02 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • January 17, 2022 14 Si5386 Data Sheet • Functional Description 3.8.3 Output Terminations The output drivers support both ac-coupled and dc-coupled terminations as shown in the following figure. AC-coupled LVDS/LVPECL DC-coupled LVDS VDDO = 3.3 V, 2.5 V, 1.8 V VDDO = 3.3 V, 2.5 V 50 OUTx OUTx 100 OUTxb 100 OUTxb 50 50 50 Si5386 AC-coupled LVPECL / CML DC-coupled LVCMOS 3.3 V, 2.5 V, 1.8 V LVCMOS VDDO = 3.3 V, 2.5 V, 1.8 V VDD – 1.3 V VDDO = 3.3 V, 2.5 V 50 50 Rs OUTx Internally self-biased Si5386 OUTx OUTxb 50 50 OUTxb 50 50 Si5386 Si5386 Rs AC-coupled HCSL VDDRX VDDO = 3.3 V, 2.5 V, 1.8 V R1 OUTx R1 50 OUTxb Standard HCSL Receiver 50 Si5386 R2 R2 For VCM = 0.35 V VDDRX R1 R2 3.3 V 442 Ω 56.2 Ω 2.5 V 332 Ω 59 Ω 1.8 V 243 Ω 63.4 Ω Figure 3.11. Supported Output Terminations 3.8.4 Programmable Amplitude For Differential Outputs See the Si5386 Rev. E Reference Manual Appendix for programming the outputs to variable amplitudes when AC coupled. 15 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.02 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • January 17, 2022 15 Si5386 Data Sheet • Functional Description 3.8.5 LVCMOS Output Impedance and Drive Strength Selection Each LVCMOS driver has a configurable output impedance to accommodate different trace impedances and drive strengths. A source termination resistor is recommended to help match the selected output impedance to the trace impedance. There are three programmable output impedance selections for each VDDO options as shown in the table below. Table 3.2. LVCMOS Output Impedance and Drive Strength Selections VDDO OUTx_CMOS_DRV Source Impedance (Zs) Drive Strength (Iol/Ioh) 3.3 V 0x01 38 Ω 10 mA 0x02 30 Ω 12 mA 0x03* 22 Ω 17 mA 0x01 43 Ω 6 mA 0x02 35 Ω 8 mA 0x03* 24 Ω 11 mA 0x03* 31 Ω 5 mA 2.5 V 1.8 V Note: Use of the lowest impedance setting is recommended for all supply voltages for best edge rates. 3.8.6 LVCMOS Output Signal Swing The signal swing (VOL/VOH) of the LVCMOS output drivers is set by the voltage on the VDDO pins. Each output driver has its own VDDO pin allowing a unique output voltage swing for each of the LVCMOS drivers. 3.8.7 LVCMOS Output Polarity When a driver is configured as an LVCMOS output, it generates a clock signal on both pins (OUTx and OUTxb). By default, the clock on the OUTx pin is generated with the same polarity (in phase) as the clock on the OUTxb pin. The polarity of these clocks is configurable, enabling complementary clock generation and/or inverted polarity with respect to other output drivers. 3.8.8 Output Enable/Disable The OEb pin provides a convenient method of disabling or enabling all of the output drivers at the same time. When the OEb pin is held high all outputs will be disabled. When held low, the outputs will all be enabled. Outputs in the enabled state can still be individually disabled through register control. 3.8.9 Output Disable During LOL By default, a DSPLL that is out of lock will generate either free-running clocks or generate clocks in holdover mode. There is an option to disable the outputs when a DSPLL is LOL. This option can be useful to force a downstream PLL into holdover. 3.8.10 Output Disable During Reference LOS The external XA/XB reference provides a critical function for the operation of the DSPLLs. In the event of the XO failure, the device will assert an XAXB_LOS alarm. By default, all outputs will be disabled during assertion of the XAXB_LOS alarm. There is an option to leave the outputs enabled during an XAXB_LOS alarm, but the frequency accuracy and stability is indeterminate during this fault condition. 3.8.11 Output Driver State When Disabled The disabled state of an output driver is configurable as disable low or disable high. 16 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.02 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • January 17, 2022 16 Si5386 Data Sheet • Functional Description 3.8.12 Synchronous Output Disable Feature The output drivers provide a selectable synchronous disable feature. Output drivers with this feature turned on will wait until a clock period has completed before the driver is disabled. This prevents unwanted runt pulses from occurring when disabling an output. When this feature is turned off, the output clock will disable immediately without waiting for the period to complete. 3.8.13 Static Output Skew Control The static phase adjust will allow a programmable phase offset between outputs on different N dividers. The resolution of the static phase adjustment is 68 ps with up to ±1 ms of total range. This feature is intended for use in JESD204B subclass 1 applications to adjust the phase of SYSREF signals with respect to DCLK. See the family Reference Manual and Application Note AN1165: Configuring Si538x Devices for JESD204B/C Wireless Applications for more details. 3.8.14 Dynamic Output Skew Control The dynamic phase adjust will allow the device to dynamically and glitchlessly change the outputs phase using register writes while the device remains locked. The resolution of the dynamic phase adjustment is 68 ps step size with up to ±1 ms of total range. See the family Reference Manual for more details. 3.8.15 Zero Delay Mode Zero delay mode is configured by opening the internal feedback loop through software configuration and closing the loop externally around as shown in the figure below. This helps to cancel out the internal delay introduced by the dividers, the crosspoint, the input, and the output drivers. Any output can be fed back to the IN3/FB_IN pins, although using the output driver that achieves the shortest trace length will help to minimize the input-to-output delay. The OUT9A and IN3/FB_IN pins are recommended for the external feedback connection. The FB_IN input pins must be terminated and ac-coupled when zero delay mode is used. A differential external feedback path connection is necessary for best performance. The order of the OUT9A and FB_IN polarities is such that they may be routed on the device side of the PCB without requiring vias or needing to cross each other. IN0 ÷P0 IN0b IN1 DSPLL ÷P1 IN1b IN2 PD ÷P2 IN2b LPF ÷M IN3/FB_IN ÷5 100 ÷P3 VDDO0 ÷R0A IN3/FB_INb OUT0A OUT0Ab ÷R0 OUT0 OUT0b ÷R1 VDDO1 OUT1 OUT1b ÷R2 VDDO2 OUT2 OUT2b ÷N0 t0 ÷N1 t1 ÷N2 t2 ÷N3 t3 ÷R7 VDDO7 OUT7 OUT7b ÷N4 t4 ÷R8 VDDO8 OUT8 OUT8b ÷R9 OUT9 OUT9b ÷R9A OUT9A OUT9Ab VDDO9 External Feedback Path Figure 3.12. Si5386 Zero Delay Mode Setup 17 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.02 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • January 17, 2022 17 Si5386 Data Sheet • Functional Description 3.8.16 Output Divider (R) Synchronization All the output R dividers are reset to a known state during the power-up initialization period. This ensures consistent and repeatable phase alignment across all output drivers. Resetting the device using the RSTb pin or asserting the hard reset bit will have the same result. 3.9 Power Management Unused inputs and output drivers can be powered down when unused. Consult the Reference Manual and ClockBuilder Pro configuration utility for details. 3.10 In-Circuit Programming The Si5386 is fully configurable using the serial interface (I2C or SPI). At power-up the device downloads its default register values from internal non-volatile memory (NVM). Application specific default configurations can be written into NVM allowing the device to generate specific clock frequencies at power-up. Writing default values to NVM is in-circuit programmable with normal operating power supply voltages applied to its VDD and VDDA pins. The NVM is two time writable. Once a new configuration has been written to NVM, the old configuration is no longer accessible. Refer to the Reference Manual for a detailed procedure for writing registers to NVM. 3.11 Serial Interface Configuration and operation of the Si5386 is controlled by reading and writing registers using the I2C or SPI interface. The I2C_SEL pin selects I2C or SPI operation. Communication with both 3.3 V and 1.8 V host is supported. The SPI mode operates in either 4-wire or 3-wire. The SCLK in SPI mode does not need to be present when CSb is high. See the timing diagram for SPI and the Reference Manual for details. 3.12 Custom Factory Preprogrammed Parts For applications where a serial interface is not available for programming the device, custom pre-programmed parts can be ordered with a specific configuration written into NVM. A factory preprogrammed part will generate clocks at power-up. Custom, factory-preprogrammed devices are available. The ClockBuilder Pro custom part number wizard can be used to quickly and easily generate a custom part number for your configuration. In less than three minutes, you will be able to generate a custom part number with a detailed data sheet addendum matching your design’s configuration. Once you receive the confirmation email with the data sheet addendum, simply place an order with your local Skyworks sales representative. Samples of your preprogrammed device will typically ship in about two weeks. 3.13 Enabling Features and/or Configuration Settings Unavailable in ClockBuilder Pro for Factory Preprogrammed Devices As with essentially all modern software utilities, ClockBuilder Pro is continually being updated and enhanced. This update process will ultimately enable ClockBuilder Pro users to access all features and register setting values documented in this data sheet and the Reference Manual. However, if you must enable or access a feature or register setting value so that the device starts up with this feature or a register setting, but the feature or register setting is not yet available in CBPro, you must contact a Skyworks applications engineer for assistance. One example of this type of feature or custom setting is the customizable output amplitude and common voltages for the clock outputs. After careful review of your project file and requirements, the Skyworks applications engineer will email back your CBPro project file with your specific features and register settings enabled using what's referred to as the manual "settings override" feature of CBPro. "Override" settings to match your request(s) will be listed in your design report file. Examples of setting "overrides" in a CBPro design report are shown in the following table. Table 3.3. Setting Overrides 18 Location Name Type Target Dec Value Hex Value 0x0435[0] FORCE_HOLD_PLLA No NVM N/A 1 0x1 0x0B48[0:4] OOF_DIV_CLK_DIS User OPN and EVB 0 0x00 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.02 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • January 17, 2022 18 Si5386 Data Sheet • Functional Description Once you receive the updated design file, simply open it in CBPro. The device will begin operation after startup with the values in the NVM file. The flowchart for this process is shown in the following figure. End: Place sample order Start Do I need a pre-programmed device with a feature or setting which is unavailable in ClockBuilder Pro? No Configure device using CBPro Generate Custom OPN in CBPro Yes Contact Skyworks Technical Support to submit & review your non-standard configuration request & CBPro project file Receive updated CBPro project file from Skyworks with “Settings Override” Yes Load project file into CBPro and test Does the updated CBPro Project file match your requirements? Figure 3.13. Process for Requesting Non-Standard CBPro Features Note: Contact Skyworks Technical Support at https://www.skyworksinc.com/support-ia. 19 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.02 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • January 17, 2022 19 Si5386 Data Sheet • Register Map 4. Register Map The register map is divided into multiple pages where each page has 256 addressable registers. Page 0 contains frequently accessible registers, such as alarm status, resets, device identification, etc. Other pages contain registers that need less frequent access such as frequency configuration, and general device settings. A high level map of the registers is shown in “6.2. High-Level Register Map” . Refer to the Reference Manual for a complete list of register descriptions and settings. Skyworks strongly recommends using ClockBuilder Pro to create and manage register settings. 4.1 Addressing Scheme The device registers are accessible using a 16-bit address that consists of an 8-bit page address plus an 8-bit register address. By default, the page address is set to 0x00. Changing to another page is accomplished by writing to the "Set Page Address" byte located at address 0x01 of each page. 4.2 High-Level Register Map Table 4.1. High-Level Register Map 16-Bit Address 8-bit Page Address 00 01 02 20 8-bit Register Address Range Content 00 Revision IDs 01 Set Page Address 02–0A Device IDs 0B–15 Alarm Status 17–1B INTR Masks 1C Reset controls 1D FINC, FDEC Control Bits 2B SPI (3-Wire vs 4-Wire) 2C–E1 Alarm Configuration E2–E4 NVM Controls FE Device Ready Status 01 Set Page Address 08–3A Output Driver Controls 41–42 Output Driver Disable Masks FE Device Ready Status 01 Set Page Address 02–05 Reference Clock Frequency Adjust 08–2F Input Divider (P) Settings 30 Input Divider (P) Update Bits 47–6A Output Divider (R) Settings 6B–72 User Scratch Pad Memory FE Device Ready Status Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.02 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • January 17, 2022 20 Si5386 Data Sheet • Register Map 16-Bit Address 8-bit Page Address Content 01 Set Page Address 02–37 MultiSynth Divider (N0–N4) Settings 0C MultiSynth Divider (N0) Update Bit 17 MultiSynth Divider (N1) Update Bit 22 MultiSynth Divider (N2) Update Bit 2D MultiSynth Divider (N3) Update Bit 38 MultiSynth Divider (N4) Update Bit 39–58 FINC/FDEC Settings N0–N4 59–62 Output Delay (Δt) Settings FE Device Ready Status 87 Zero Delay Mode Set Up 0E–14 Fast Lock Loop Bandwidth 15–1F Feedback Divider (M) Settings 2A Input Select Control 2B Fast Lock Control 2C–35 Holdover Settings 36 Input Clock Switching Mode Select 38–39 Input Priority Settings 3F Holdover History Valid Data 06–08 00–FF Reserved 09 01 Set Page Address 1C Zero Delay Mode Settings 43 Control I/O Voltage Select 49 Input Settings 00–FF Reserved 03 04 05 10–FF 21 8-bit Register Address Range Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.02 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • January 17, 2022 21 Si5386 Data Sheet • Electrical Specifications 5. Electrical Specifications Table 5.1. Recommended Operating Conditions (VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, TA = –40 to 85 °C) Parameter Ambient Temperature Maximum Junction Temperature Core Supply Voltage Output Driver Supply Voltage Symbol Min Typ Max Unit TA –40 25 85 °C TJMAX — — 125 °C VDD 1.71 1.80 1.89 V VDDA 3.14 3.30 3.47 V VDDO 3.14 3.30 3.47 2.38 2.50 2.62 V 1.71 1.80 1.89 V V Note: 1. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted. Table 5.2. DC Characteristics (VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, VDDO = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA = –40 to 85 °C) Parameter Core Supply Current Symbol Test Condition Min Typ Max Unit IDD Notes 1, 2 — 210 375 mA — 125 140 mA — 22 26 mA — 15 18 mA — 22 30 mA — 18 23 mA — 12 16 mA — 1150 1520 mW IDDA Output Buffer Supply Current IDDO LVPECL Output3 @ 156.25 MHz LVDS Output3 @ 156.25 MHz 3.3 V LVCMOS4 Output @ 156.25 MHz 2.5 V LVCMOS4 Output @ 156.25 MHz 1.8 V LVCMOS4 Output @ 156.25 MHz Total Power Dissipation 22 Pd Note 1,5 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.02 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • January 17, 2022 22 Si5386 Data Sheet • Electrical Specifications (VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, VDDO = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA = –40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit Note: 1. Si5386 test configuration: 10 clock outputs enabled (10 MHz and 30.72 MHz 3.3V CMOS Complementary, 125 MHz LVDS 3.3V, all other outputs are 1.8V Sub-LVDS, 3 x 122.88 MHz, 2 x 960 kHz, 1 x 49.152 MHz, 1 x 307.2 MHz). Excludes power in termination resistors. 2. VDDO0 supplies power to both OUT0 and OUT0A buffers. Similarly, VDDO9 supplies power to both OUT9 and OUT9A buffers. 3. Differential outputs terminated into an AC coupled 100 Ω load. 4. LVCMOS outputs measured into a 5-inch 50 Ω PCB trace with 5 pF load. The LVCMOS outputs were set to OUTx_CMOS_DRV = 3, which is the strongest driver setting. 5. Detailed power consumption for any configuration can be estimated using ClockBuilder Pro when an evaluation board (EVB) is not available. All EVBs support detailed current measurements for any configuration. LVCMOS Output Test Configuration Differential Output Test Configuration IDDO OUT 50 Trace length 5 inches 0.1 uF IDDO 100 OUTb 50 499 Ω 50 OUT OUTb 0.1 uF 4.7 pF 50 Ω Scope Input 56 Ω 499 Ω 50 4.7 pF 50 Ω Scope Input 56 Ω Table 5.3. Input Clock Specifications (VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, TA = –40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit MHz Standard Differential or Single-Ended — AC-coupled (IN0, IN1, IN2, IN3) Input Frequency Range Input Voltage Amplitude Single-Ended Input Amplitude fIN_DIFF Differential 7.68 — 750 fIN_SE Single-ended 7.68 — 250 VIN_DIFF fIN_DIFF < 250 MHz 100 — 1800 mVpp_se 250 MHz < fIN_DIFF< 750 MHz 225 — 1800 mVpp_se fIN_SE< 250 MHz 100 — 3600 mVpp_se VIN_SE Slew Rate2, 3 SR 400 — — V/µs Duty Cycle DC 40 — 60 % Capacitance CIN — 2.4 — pF Standard CMOS & Non-standard CMOS 0.008 — 250 MHz Pulsed CMOS 0.008 — 1 MHz LVCMOS / Pulsed CMOS DC-Coupled Input Buffer (IN0, IN1, IN2, IN3/FB_IN)4 Input Frequency 23 fIN_CMOS Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.02 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • January 17, 2022 23 Si5386 Data Sheet • Electrical Specifications (VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, TA = –40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit VIL Standard CMOS — — 0.5 V Non-standard CMOS & Pulsed CMOS — — 0.4 V Standard CMOS 1.3 — — V Non-standard CMOS & Pulsed CMOS 0.8 — — V 400 — — V/µs Standard CMOS & Non-standard CMOS 40 — 60 % Pulsed CMOS 5 Standard CMOS & 1.6 — — 50 — — RIN — 8 — kΩ Frequency fIN_REF — 54 — MHz Total Frequency Tolerance7 fRANGE -50 — +50 ppm Input Voltage Amplitude VIN_SE Single-ended Input 365 — 2000 mVpp_se VIN_DIFF Differential Input 365 — 2500 mVpp_diff SR Single-ended Input 1500 — — V/µs SRIN_DIFF Differential Input 400 — — V/µs 40 — 60 % 2 ppm/C Input Voltage VIH Slew Rate2, 3 SR Duty Cycle DC Minimum Pulse Width PW 95 ns Non-standard CMOS (250 MHz @ 40% Duty Cycle) Pulsed CMOS (1 MHz @ 5% Duty Cycle) Input Resistance XO (applied to XA/XB)4 Slew Rate2, 3 Input Duty Cycle Activity Dip8 24 DC Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.02 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • January 17, 2022 24 Si5386 Data Sheet • Electrical Specifications (VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, TA = –40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit Note: 1. Voltage swing is specified as single-ended mVpp. OUTx Vcm Vpp_se Vcm Vpp_se Vpp_diff = 2*Vpp_se OUTxb 2. Recommended for specified jitter performance. Slew rate can go lower, but jitter performance could degrade if the minimum slew rate specification is not met (see the Si5386 Reference Manual). 3. Rise and fall times can be estimated using the following simplified equation: tr/tf80-20 = ((0.8 – 0.2) x VIN_Vpp_se) / SR. 4. Standard, Non-standard and Pulsed CMOS refer to different formats of CMOS each with a voltage swing of 1.8V, 2.5V or 3.3V +/-5%. • Standard CMOS refers to the industry standard LVCMOS signal. • Non-standard CMOS refers to a signal that has been attenuated/level-shifted in order to comply with the specified non-standard VIL and VIH specifications. • Pulsed CMOS refers to a signal that has been attenuated/level-shifted and has a low/high duty cycle and must be dc coupled. A typical application example is a low-frequency video frame sync pulse. Refer to the Si5386 Reference Manual for the recommended connections/termination for the different modes. 5. CMOS signals that exceed 3.3 V + 5% can be used as inputs as long as a resistive attenuation network is used to guarantee that the input voltage at the pin does not violate the device's input ratings. Please refer to the Si5386 Reference Manual for the recommended connections/termination for this mode. 6. Refer to the Si534x/8x Jitter Attenuators Recommended Crystal, TCXO and OCXOs Reference Manual for recommended 54 MHz XOs. 7. Includes aging and temperature affects. 8. Activity dip is also called frequency perturbation. Table 5.4. Serial and Control Input Pin Specifications (VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, VDDS = 3.3 V ±5%, 1.8 V ±5%, TA = –40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit Serial and Control Input Pins (IN_SEL[1:0], RSTb, OEb, PDNb, A1/SDO, SCLK, A0/CSb, SDA/SDIO) Input Voltage Thresholds Input Capacitance Input Resistance Minimum Pulse Width VIL — — 0.3 x VDDIO1 V VIH 0.7 x VDDIO1 — — V CIN — 2 — pF IL — 20 — kΩ 100 — — ns PW RSTb, PDNb Note: 1. VDDIO is determined by the IO_VDD_SEL bit. It is selectable as VDDA or VDD. See the Si5386 Reference Manual for more details on the register settings. 25 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.02 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • January 17, 2022 25 Si5386 Data Sheet • Electrical Specifications Table 5.5. Differential Clock Output Specifications (VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, VDDO = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA = –40 to 85 °C) Parameter Output Frequency5 Duty Cycle Output-Output Skew6 Symbol Test Condition Min Typ Max Unit fOUT N >= 10, R >= 2 0.0001 — 737.28 MHz N = 9, R = 2 — 819.2 — MHz N = 8, R = 2 — 921.6 — MHz N = 7.5, R = 2 — 983.04 — MHz N = 7, R = 2 — 14745.6/ 14 — MHz N = 6, R = 2 — 1228.8 — MHz N = 5, R = 2 — 1474.56 — MHz N = 9, R = 1 — 1638.4 — MHz N = 8, R = 1 — 1843.2 — MHz N = 7, R = 1 — 2106.53 — MHz N = 6, R = 1 — 2457.6 — MHz N = 5, R = 1 — 2949.12 — MHz fOUT < 400 MHz 48 — 52 % 400 MHz < fOUT < 800 MHz 45 — 55 % 800 MHz < fOUT < 1474.56 MHz 40 — 60 % f > 1474.56 MHz 25 — 75 % Differential output — 0 75 ps -150 0 150 ps Tdelay_step — 68 — ps Tdelay_range — ±1 — ms — 0 50 ps mVpp_se DC TSK Specified for outputs using the same MultiSynth Differential output Specified for outputs using different MultiSynths Output Dynamic/Static Delay Adjustment OUT-OUTb Skew Output Voltage Amplitude1 Common Mode Voltage 1,2 Rise and Fall Times TSK_OUT VOUT VCM tR/tF Measured from the positive to negative output pins VDDO = 3.3 V, 2.5 V, or 1.8 V LVDS 350 450 530 VDDO = 3.3 V, 2.5 V LVPECL 610 780 950 VDDO = 3.3 V LVDS 1.1 1.2 1.3 LVPECL 1.9 2.0 2.1 VDDO = 2.5 V LVPECL, LVDS 1.1 1.2 1.3 VDDO = 1.8 V sub-LVDS 0.8 0.9 1.0 — 100 200 LVPECL and LVDS outputs V ps (20% to 80%) 26 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.02 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • January 17, 2022 26 Si5386 Data Sheet • Electrical Specifications (VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, VDDO = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA = –40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit ZO LVPECL and LVDS outputs — 100 — Ω PSRR 10 kHz sinusoidal noise — –101 — dBc 100 kHz sinusoidal noise — –96 — 500 kHz sinusoidal noise — –99 — 1 MHz sinusoidal noise — –97 — Differential — –72 — Differential Output Impedance2 Power Supply Noise Rejection3 XTALK Output-output Crosstalk4 dB Note: 1. Output amplitude and common mode voltage are programmable through register settings and can be stored in NVM. Each output driver can be programmed independently. The typical normal mode (or low power mode) LVDS maximum is 100 mV (or 80 mV) higher than the TIA/EIA-644 maximum. Refer to the Si5386 Reference Manual for recommended output settings. 2. Not all combinations of voltage amplitude and common mode voltages settings are possible. 3. Measured for 156.25 MHz carrier frequency. Sinewave noise added to VDDO (1.8 V = 50 mVpp, 2.5 V/3.3 V = 100 mVpp) and noise spur amplitude measured. 4. Measured across two adjacent outputs, both in LVDS mode, with the victim running at 122.88 MHz and the aggressor at 156.25 MHz. Refer to application note, "AN862: Optimizing Si534x Jitter Performance in Next Generation Internet Infrastructure Systems”, guidance on crosstalk minimization. Note that all active outputs must be terminated when measuring crosstalk. 5. VDDO = 2.5 V or 3.3 V required for fOUT > 1474.56 MHz 6. For any R divider settings that differ by a power of 2. OUTx Vcm Vpp_se Vcm Vpp_se Vpp_diff = 2*Vpp_se OUTxb Differential Output Test Configuration 0.1 uF IDDO OUT 50 100 Ω OUTb 50 0.1 uF Table 5.6. LVCMOS Clock Output Specifications (VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, VDDO = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA = –40 to 85 °C) Parameter Symbol Output Frequency fOUT Duty Cycle DC 27 Test Condition Min Typ Max Unit 0.0001 — 250 MHz fOUT