Si5391 Data Sheet
Ultra Low-Jitter, 12-Output, Any-Frequency, Any-Output Clock
Generator
The any-frequency, any-output Si5391 clock generators combine a wide-band PLL with
proprietary MultiSynth™ fractional synthesizer technology to offer a versatile and high
performance clock generator platform. This highly flexible architecture is capable of
synthesizing a wide range of integer and non-integer related frequencies up to 1 GHz
on 12 differential clock outputs while delivering sub-100 fs rms phase jitter performance optimized for 100G/200G/400G applications. Each of the clock outputs can be
assigned its own format and output voltage enabling the Si5391 to replace multiple
clock ICs and oscillators with a single device making it a true "clock tree on a chip."
The Si5391 can be quickly and easily configured using ClockBuilderPro software. Custom part numbers are automatically assigned using ClockBuilder™ Pro for fast, free,
and easy factory pre-programming or the Si5391 can be programmed via I2C and SPI
serial interfaces.
KEY FEATURES
• Generates any combination of output
frequencies from any input frequency
• Ultra-low jitter performance
• 69fs RMS (Precision Calibration)
• 75fs RMS (integer mode)
• 115fs RMS (fractional mode)
• Input frequency range:
• External crystal: 25 to 54 MHz
• Differential clock: 10 to 750 MHz
• LVCMOS clock: 10 to 250 MHz
• Output frequency range:
• Differential: 100 Hz to 1028 MHz
• LVCMOS: 100 Hz to 250 MHz
Applications:
• 100/200/400G switches
• 56G/112G PAM4 SerDes reference clocks
• Clock tree generation replacing XOs, buffers, signal format translators
• Clocking for FPGAs, processors, memory
• Ethernet switches/routers
• OTN framers/mappers/processors
• Highly configurable outputs compatible with
LVDS, LVPECL, LVCMOS, CML, and HCSL
with programmable signal amplitude
• Si5391: 4 input, 12 output, 64-QFN 9x9mm
25-54 MHz XTAL
XA
XB
OSC
IN0
÷INT
IN1
÷INT
IN2
÷INT
PLL
Zero Delay
FB_IN
Status Flags
I2C / SPI
1
÷INT
Status Monitor
Control
NVM
MultiSynth
÷INT
MultiSynth
÷INT
OUT0A
MultiSynth
÷INT
OUT1
MultiSynth
÷INT
OUT2
MultiSynth
÷INT
OUT3
÷INT
OUT4
÷INT
OUT5
÷INT
OUT6
÷INT
OUT7
÷INT
OUT8
÷INT
OUT9
÷INT
OUT9A
OUT0
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Si5391 Data Sheet • Features List
1. Features List
The Si5391 features are listed below:
• Generates any combination of output frequencies from any
input frequency
• Ultra-low phase jitter performance
• 69fs RMS (Precision Calibration)
• 75fs RMS (integer mode)
• 115fs RMS (fractional mode)
• Input frequency range:
• External crystal: 25 to 54 MHz
• Differential clock: 10 to 750 MHz
• LVCMOS clock: 10 to 250 MHz
• Output frequency range:
• Differential: 100 Hz to 1028 MHz
• LVCMOS: 100 Hz to 250 MHz
• Highly configurable outputs compatible with LVDS, LVPECL,
LVCMOS, CML, and HCSL with programmable signal amplitude
• Optional zero delay mode
• Glitchless on the fly output frequency changes
2
• DCO mode: as low as 0.001 ppb steps
• Core voltage
• VDD: 1.8 V ±5%
• VDDA: 3.3 V ±5%
• Independent output clock supply pins
• 3.3 V, 2.5 V, or 1.8 V
• Serial interface: I2C or SPI
• In-circuit programmable with non-volatile OTP memory
• ClockBuilder Pro software simplifies device configuration
• 64-QFN 9x9mm
• Temperature range: –40 to +85 °C
• Pb-free, RoHS-6 compliant
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Si5391 Data Sheet • Related Documents
2. Related Documents
3
Document/Resource
Description/URL
Si5391 Family Reference Manual
https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/reference-manuals/si5391-reference-manual.pdf
Crystal Reference Manual
https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/reference-manuals/si534x-8x-9x-recommended-crystals-rm.pdf
Si5391A-A-EVB User Guide
https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/user-guides/
ug352-si5391a-a-evb.pdf
Quality and Reliability
https://www.skyworksinc.com/Quality
Development Kits
https://www.skyworksinc.com/en/Products/Timing
ClockBuilder Pro (CBPro) Software
https://www.skyworksinc.com/en/Application-Pages/Clockbuilder-Pro-Software
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Si5391 Data Sheet • Ordering Guide
3. Ordering Guide
Table 3.1. Si5391 Ordering Guide
Ordering Part
Number (OPN)
Number of Input/Output Clocks
Output Clock Frequency Range
(MHz)
Frequency Synthesis
Mode
Package
Temperature
Range
Si5391A-A-GM1, 2
4/12
0.001 to 1028
Integer and Fractional
64-QFN 9x9mm
-40 to 85C
Si5391B-A-GM1, 2
0.001 to 350
Si5391C-A-GM1, 2
0.001 to 1028
Si5391D-A-GM1, 2
0.001 to 350
Si5391P-A-GM
Crystal / 12
Si5391A-A-EVB
4 / 12
Si5391P-A-EVB
Crystal /12
Up to 3 domains
(see 4.5.2 Grade P)
Integer Only
Precision Calibration
Any-Frequency, Any Integer and Fractional
Output
Ultra low jitter
clocks for 56G/112G
SerDes
Precision Calibration
Evaluation Board
(A/B/C/D Grades)
Evaluation Board (P
Grade)
Note:
1. Add an R at the end of the OPN to denote tape and reel ordering options.
2. Custom, factory pre-programmed devices are available. Ordering part numbers are assigned by Skyworks and the ClockBuilder
Pro software utility. Custom part number format is: e.g., Si5391A-Axxxxx-GM, where "xxxxx" is a unique numerical sequence
representing the preprogrammed configuration.
Si5391g-Rxxxxx-GM
Timing product family
f = Multi-PLL clock family member (7, 6)
g = Device grade (A, B, C, D, P)
Product Revision (A)*
Custom ordering part number (OPN) sequence ID**
Package, ambient temperature range (QFN, -40 °C to +85°C)
*See Ordering Guide table for current product revision
** 5 digits; assigned by ClockBuilder Pro
Figure 3.1. Ordering Part Number Fields
4
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Table of Contents
1. Features List
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3. Ordering Guide
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.1 Power-up and Initialization .
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4.2 Frequency Configuration
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4.3 Inputs . . . . . . . . . . . . .
4.3.1 XA/XB Clock and Crystal Input . . .
4.3.2 Input Clocks (IN0, IN1, IN2) . . . .
4.3.3 Input Selection (IN0, IN1, IN2, XA/XB)
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.10
4.4 Fault Monitoring . . .
4.4.1 Status Indicators . .
4.4.2 Interrupt Pin (INTRb)
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.10
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4.5 Outputs . . . . . . . . . . . . . . . . . . . .
4.5.1 Grade A/B/C/D . . . . . . . . . . . . . . . .
4.5.2 Grade P . . . . . . . . . . . . . . . . . . .
4.5.3 Output Signal Format . . . . . . . . . . . . . .
4.5.4 Differential Output Terminations . . . . . . . . . . .
4.5.5 Programmable Common Mode Voltage for Differential Outputs
4.5.6 LVCMOS Output Terminations . . . . . . . . . . .
4.5.7 LVCMOS Output Impedance and Drive Strength Selection . .
4.5.8 LVCMOS Output Signal Swing . . . . . . . . . . .
4.5.9 LVCMOS Output Polarity . . . . . . . . . . . . .
4.5.10 Output Enable/Disable . . . . . . . . . . . . .
4.5.11 Output Driver State When Disabled . . . . . . . . .
4.5.12 Synchronous/Asynchronous Output Disable Feature . . .
4.5.13 Zero Delay Mode (Grade A/B/C/D) . . . . . . . . .
4.5.14 Output Crosspoint . . . . . . . . . . . . . . .
4.5.15 Digitally Controlled Oscillator (DCO) Modes . . . . . .
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.11
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.12
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.14
.14
.14
4.6 Power Management .
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.15
4.7 In-Circuit Programming .
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.15
4.8 Serial Interface .
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.15
4.9 Custom Factory Preprogrammed Devices .
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.15
4.10 Enabling Features and/or Configuration Settings Not Available in ClockBuilder Pro for Factory
Pre-Programmed Devices . . . . . . . . . . . . . . . . . . . . . . . .
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.15
5. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17
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5.1 Addressing Scheme .
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.17
6. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . .
18
7. Detailed Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . .
32
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8. Typical Operating Characteristics
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33
9. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
34
10. Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . .
39
10.1 Si5391 9x9 mm 64-QFN Package Diagram .
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.39
11. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . .
40
12. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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13. Device Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
43
14. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
44
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Si5391 Data Sheet • Functional Description
4. Functional Description
The Si5391 combines a wide band PLL with next generation MultiSynth technology to offer the industry's most versatile and high
performance clock generator. The PLL locks to either an external crystal between XA/XB or to an external clock connected to XA/XB
or IN0, 1, 2. A fractional or integer multiplier takes the selected input clock or cystal frequency up to a very high frequency that is
then divided by the MultiSynth output stage to any frequency in the range of 100 Hz to 1 GHz on each output. The MultiSynth stage
can divide by both integer and fractional values. The high-resolution fractional MultiSynth dividers enable true any-frequency input to
any-frequency on any of the outputs. The output drivers offer flexible output formats which are independently configurable on each of
the outputs. This clock generator is fully configurable via its serial interface (I2C/SPI) and includes in-circuit programmable non-volatile
memory.
4.1 Power-up and Initialization
Once power is applied, the device begins an initialization period where it downloads default register values and configuration data
from NVM and performs other initialization tasks. Communicating with the device through the serial interface is possible once this
initialization period is complete. No clocks will be generated until the initialization is done. There are two types of resets available. A
hard reset is functionally similar to a device power-up. All registers will be restored to the values stored in NVM, and all circuits will be
restored to their initial state including the serial interface. A hard reset is initiated using the RSTb pin or by asserting the hard reset bit.
A soft reset bypasses the NVM download. It is simply used to initiate register configuration changes.
Power-Up
Hard Reset
bit asserted
RSTb
pin asserted
NVM download
Soft Reset
bit asserted
Initialization
Serial interface
ready
Figure 4.1. Si5391 Power-Up and Initialization
4.2 Frequency Configuration
The phase-locked loop is fully contained and does not require external loop filter components to operate. Its function is to phase lock to
the selected input and provide a common reference to the MultiSynth high-performance fractional dividers.
A crosspoint mux connects any of the MultiSynth divided frequencies to any of the outputs drivers. Additional output integer dividers
provide further frequency division by an even integer from 2 to (2^25)-2. The frequency configuration of the device is programmed by
setting the input dividers (P), the PLL feedback fractional divider (Mn/Md), the MultiSynth fractional dividers (Nn/Nd), and the output
integer dividers (R). Skyworks's ClockBuilder Pro configuration utility determines the optimum divider values for any desired input and
output frequency plan.
4.3 Inputs
The Si5391 requires either an external crystal at its XA/XB pins or an external clock at XA/XB or IN0, 1, 2.
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Si5391 Data Sheet • Functional Description
4.3.1 XA/XB Clock and Crystal Input
An internal crystal oscillator exists between pin XA and XB. When this oscillator is enabled, an external crystal connected across
these pins will oscillate and provide a clock input to the PLL. A crystal frequency of 25 MHz can be used although crystals in the
frequency range of 48 MHz to 54 MHz are recommended for best jitter performance. The Si5391 Family Reference Manual provides
additional information on PCB layout recommendations for the crystal to ensure optimum jitter performance. Refer to Table 6.12 Crystal
Specifications on page 30 for crystal specifications. Si5391P must use a 48 MHz crystal input.
To achieve optimal jitter performance and minimize BOM cost, a crystal is recommended on the XA/XB reference input. A clock (e.g.,
XO) may be used in lieu of the crystal, but it will result in higher output jitter. See the Si5391 Family Reference Manual for more
information.
Selection between the external XTAL or input clock is controlled by register configuration. The internal crystal load capacitors (CL)
are disabled in the input clock mode. Refer to Table 6.3 Input Clock Specifications (A/B/C/D Grades) on page 20 for the input clock
requirements at XAXB. Both a single-ended or a differential input clock can be connected to the XA/XB pins as shown in the figure
below. A PXAXB divider is available to accommodate external clock frequencies higher than 54 MHz.
Differential Connection
Single-ended XO Connection
nc X1
nc X1
nc X2
nc X2
Note: 2.0 Vpp_se max
0.1 µf
50
2xCL
0.1 µf
XA
50
OSC
2xCL
XA
OSC
XB
2xCL
XO with Clipped Sine
Wave Output
Si5391
0.1 µf
0.1 µf
XB
2xCL
Si5391
Note: 2.5 Vpp diff max
Crystal Connection
Single-ended Connection
nc X1
nc X2
Note: 2.0 Vpp_se max
CMOS/XO Output
R1
0.1 µf
X1
2xCL
XA
XTA
L
OSC
XO VDD
R1
R2
3.3 V
523 Ohms 422 Ohms
2.5 V
475 Ohms 649 Ohms
158 Ohms 866 Ohms
1.8 V
R2
0.1 µf
0.1 µf
2xCL
XA
OSC
XB
XB
2xCL
Si5391
X2
2xCL
Si5391
Figure 4.2. XAXB External Crystal and Clock Connections
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Si5391 Data Sheet • Functional Description
4.3.2 Input Clocks (IN0, IN1, IN2)
Three different formats are supported: Standard Differential/Single-Ended, Standard LVCMOS or Pulsed CMOS (See Family Reference
Manual for more details). The recommended input termination schemes are shown in the figure below. Input clock support is not
available on Precision Calibration Si5391P.
Standard AC Coupled Differential LVDS
Si5391
50
INx
Standard
100
3.3V, 2.5V
LVDS or
CML
INxb
50
Pulsed CMOS
Standard AC Coupled Differential LVPECL
Si5391
50
INx
Standard
100
INxb
50
3.3V, 2.5V
LVPECL
Pulsed CMOS
Standard AC Coupled Single Ended
Si5391
50
INx
3.3V, 2.5V, 1.8V
LVCMOS
Standard
INxb
Pulsed CMOS
Pulsed CMOS DC Coupled Single Ended
R1
Si5391
50
3.3V, 2.5V, 1.8V
LVCMOS
VDD
1.8 V
2.5 V
3.3 V
R1 (Ohm) R2 (Ohm)
324
665
511
475
634
365
INx
R2
Standard
INxb
Pulsed CMOS
Figure 4.3. Termination of Differential and LVCMOS Input Signals
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Si5391 Data Sheet • Functional Description
4.3.3 Input Selection (IN0, IN1, IN2, XA/XB)
The active clock input is selected using the IN_SEL[1:0] pins or by register control. A register bit determines input selection as pin or
register selectable. There are internal pull ups on the IN_SEL pins.
Table 4.1. Manual Input Selection Using IN_SEL[1:0] Pins
IN_SEL[1:0]
Selected Input
0
0
IN0
0
1
IN1
1
0
IN2
1
1
XA/XB
4.4 Fault Monitoring
The Si5391 provides fault indicators which monitor loss of signal (LOS) of the inputs (IN0, IN1, IN2, XA/XB, FB_IN) and loss of lock
(LOL) for the PLL as shown in the figure below.
IN0
÷P0
IN0b
Si5391
LOS0
LOL
IN1
IN1b
IN2
IN2b
÷P1
LOS1
÷P2
LOS2
PLL
PD
LPF
÷
Mn
Md
LOSXAB
XB
FB_IN
÷Pfb
LOSFB
LOLb
FB _INb
OSC
INTRb
XA
Figure 4.4. LOS and LOL Fault Monitors
4.4.1 Status Indicators
The state of the status monitors are accessible by reading registers through the serial interface or with a dedicated pin (LOLb). Each
of the status indicator register bits has a corresponding sticky bit in a separate register location. Once a status bit is asserted its
corresponding sticky bit (_FLG) will remain asserted until cleared. Writing a logic zero to a sticky register bit clears its state.
4.4.2 Interrupt Pin (INTRb)
An interrupt pin (INTRb) indicates a change in state with any of the status registers. All status registers are maskable to prevent
assertion of the interrupt pin. The state of the INTRb pin is reset by clearing the status registers.
10
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Si5391 Data Sheet • Functional Description
4.5 Outputs
The Si5391 supports 12 differential output drivers which can be independently configured as differential or LVCMOS.
Each driver has a configurable voltage swing and common mode voltage covering a wide variety of differential signal formats. In
addition to supporting differential signals, any of the outputs can be configured as single-ended LVCMOS (3.3 V, 2.5 V, or 1.8 V)
providing up to 24 single-ended outputs, or any combination of differential and single-ended outputs.
4.5.1 Grade A/B/C/D
The Si539x grades A/B/C/D can generate any output frequency in any format. These devices are available as a preprogrammed option
or can be written to the device via I2C. The input/output frequency plan determines whether the output divider operates in integer or
fractional mode. In the fractional mode, the device can generate any output frequency or any format from any input frequency with
best-in-class jitter. Some frequency plans allow the user to use an integer mode that delivers even lower jitter. See the family reference
manual for more details.
4.5.2 Grade P
Applications using 56G/112G PAM4 SerDes require ultra-low jitter reference clocks, with RMS phase jitter performance below 100 fs
RMS. The Precision Calibration Grade P option calibrates out linearity errors to deliver the world's best jitter performance over a wide
range of frequency plans.
Si5391P supports up to 3 clock domains, featuring RMS phase jitter performance of 95 fs MAX on 156.25 MHz and 312.5 MHz
frequencies. The frequencies supported by the 3 domains are as follows:
• Domain#1: 156.25/312.5/625 MHz
• Domain#2: 25/50/100/125/200/156.25/312.5/625 MHz
• Domain#3: 25/50/100/125/200/156.25/312.5/625/322.265625/644.53125 MHz
The following examples provide an overview of the 3 domains:
The external reference used on the XA/XB pins of the P grade is restricted to a 48 MHz crystal. No other values of crystal or other
reference sources are allowed (XO, VCXO, clock input). Designs that require alternative crystal frequencies must use Si5391A/B/C/D
options instead.
Additional design rules must be followed to achieve the 95fs MAX phase jitter performance on the 156.25MHz and/or 312.5MHz output
clocks. The Si5391 Family Reference Manual outlines the details of these design rules.
4.5.3 Output Signal Format
The differential output amplitude and common mode voltage are both fully programmable and compatible with a wide variety of signal
formats including LVDS and LVPECL. In addition to supporting differential signals, any of the outputs can be configured as LVCMOS
(3.3 V, 2.5 V, or 1.8 V) drivers providing up to 24 single-ended outputs, or any combination of differential and single-ended outputs.
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Si5391 Data Sheet • Functional Description
4.5.4 Differential Output Terminations
The differential output drivers support both ac-coupled and dc-coupled terminations as shown in the figure below.
DC Coupled LVDS
AC Coupled LVDS/LVPECL
VDDO = 3.3V , 2.5V , 1.8V
VDDO = 3.3V , 2.5V , 1.8V
OUTx
50
OUTx
100
OUTxb
100
OUTxb
50
50
50
AC Coupled LVPECL/CML
AC Coupled HCSL
VDD– 1.3V
VDDRX
VDDO = 3.3V, 2.5V, 1.8V
VDDO = 3.3V , 2.5V
R1
OUTx
Internally
self-biased
Si 5391
Si 5391
50
R1
50
50
Si5391
OUTx
Standard
HCSL
Receiver
OUTxb
R2
50
50
OUTxb
50
Si 5391
R2
Option
For VCM
= 0.137 V
VDDRX
3. 3 V
2. 5 V
1. 8 V
R1
R2
442 ohms 56.2 ohms
332 ohms 59 ohms
243 ohms 63.4 ohms
Figure 4.5. Supported Differential Output Terminations
4.5.5 Programmable Common Mode Voltage for Differential Outputs
The common mode voltage (VCM) for the differential modes are programmable so that LVDS specifications can be met and for the best
signal integrity with different supply voltages. When dc coupling the output driver it is essential that the receiver should have a relatively
high common mode impedance so that the common mode current from the output driver is very small.
4.5.6 LVCMOS Output Terminations
LVCMOS outputs are typically dc-coupled, as shown in the figure below.
DC Coupled LVCMOS
3.3V , 2.5V , 1.8 V
LVCMOS
VDDO = 3.3V , 2.5V , 1.8V
50
OUTx
Rs
OUTxb
Si5391
50
Rs
Figure 4.6. LVCMOS Output Terminations
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Si5391 Data Sheet • Functional Description
4.5.7 LVCMOS Output Impedance and Drive Strength Selection
Each LVCMOS driver has a configurable output impedance. It is highly recommended that the minimum output impedance (strongest
drive setting) is selected and a suitable series resistor (Rs) is chosen to match the trace impedance.
Table 4.2. Nominal Output Impedance vs. OUTx_CMOS_DRV (register)
VDDO
CMOS_DRIVE_Selection
OUTx_CMOS_DRV=1
OUTx_CMOS_DRV=2
OUTx_CMOS_DRV=3
3.3 V
38 Ω
30 Ω
22 Ω
2.5 V
43 Ω
35 Ω
24 Ω
1.8 V
—
46 Ω
31 Ω
Note: Refer to the Si5391 Family Reference Manual for more information on register settings.
4.5.8 LVCMOS Output Signal Swing
The signal swing (VOL/VOH) of the LVCMOS output drivers is set by the voltage on the VDDO pins. Each output driver has its own
VDDO pin allowing a unique output voltage swing for each of the LVCMOS drivers.
4.5.9 LVCMOS Output Polarity
When a driver is configured as an LVCMOS output it generates a clock signal on both pins (OUTx and OUTxb). By default the clock on
the OUTxb pin is generated with complementary polarity with the clock on the OUTx pin. The LVCMOS OUTx and OUTxb outputs can
also be generated in phase.
4.5.10 Output Enable/Disable
The OEb pin provides a convenient method of disabling or enabling the output drivers. When the OEb pin is held high all outputs will be
disabled. When held low, the outputs will be enabled. Outputs in the enabled state can be individually disabled through register control.
4.5.11 Output Driver State When Disabled
The disabled state of an output driver is configurable as: disable low or disable high.
4.5.12 Synchronous/Asynchronous Output Disable Feature
Outputs can be configured to disable synchronously or asynchronously. The default state is synchronous output disable. In synchronous disable mode the output will wait until a clock period has completed before the driver is disabled. This prevents unwanted runt
pulses from occurring when disabling an output. In asynchronous disable mode the output clock will disable immediately without waiting
for the period to complete.
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Si5391 Data Sheet • Functional Description
4.5.13 Zero Delay Mode (Grade A/B/C/D)
A zero delay mode is available for applications that require fixed and consistent minimum delay between the selected input and outputs.
The zero delay mode is configured by opening the internal feedback loop through software configuration and closing the loop externally
as shown in the figure below. This helps to cancel out the internal delay introduced by the dividers, the crosspoint, the input, and the
output drivers. Any one of the outputs can be fed back to the FB_IN pins, although using the output driver that achieves the shortest
trace length will help to minimize the input-to-output delay. It is recommended to connect OUT9A to FB_IN for external feedback. The
FB_IN input pins must be terminated and ac-coupled when zero delay mode is used. A differential external feedback path connection is
necessary for best performance.
VDDO0
OUT0
OUT0b
IN0
fIN
IN0b
IN1
IN1b
IN2
IN2b
÷ P0
OUT 0A
OUT 0Ab
÷ P1
VDDO1
OUT1
OUT1b
÷ P2
VDDO2
OUT2
OUT2b
IN_ SEL[1:0]
IN3/FB_IN
100
fFB = fIN
Zero Delay
Mode
MultiSynth
& Dividers
PLL
PD
LPF
÷Pfb
÷
IN3b/FB_INb
VDDO8
OUT8
OUT9b
Mn
Md
VDDO 9
OUT 9
OUT 9b
÷
N9n
N9d
÷R11
OUT 9A
OUT 9Ab
External Feedback Path
Figure 4.7. Si5391 Zero Delay Mode Setup
4.5.14 Output Crosspoint
The output crosspoint allows any of the N dividers to connect to any of the clock outputs.
4.5.15 Digitally Controlled Oscillator (DCO) Modes
Each MultiSynth can be digitally controlled so that all outputs connected to the MultiSynth change frequency in real time without any
transition glitches. There are two ways to control the MultiSynth to accomplish this task:
• Use the Frequency Increment/Decrement Pins or register bits.
• Write directly to the numerator of the MultiSynth divider.
An output that is controlled as a DCO is useful for simple tasks such as frequency margining or CPU speed control. The output can also
be used for more sophisticated tasks such as FIFO management by adjusting the frequency of the read or write clock to the FIFO or
using the output as a variable Local Oscillator in a radio application.
4.5.15.1 DCO with Frequency Increment/Decrement Pins/Bits
Each of the MultiSynth fractional dividers can be independently stepped up or down in predefined steps with a resolution as low as
0.001 ppb. Setting of the step size and control of the frequency increment or decrement is accomplished by setting the step size with
the 44 bit Frequency Step Word (FSTEPW). When the FINC or FDEC pin or register bit is asserted the output frequency will increment
or decrement respectively by the amount specified in the FSTEPW.
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Si5391 Data Sheet • Functional Description
4.5.15.2 DCO with Direct Register Writes
When a MultiSynth numerator and its corresponding update bit is written, the new numerator value will take effect and the output
frequency will change without any glitches. The MultiSynth numerator and denominator terms can be left and right shifted so that the
least significant bit of the numerator word represents the exact step resolution that is needed for your application.
4.6 Power Management
Several unused functions can be powered down to minimize power consumption. Consult the Si5391 Family Reference Manual and
ClockBuilder Pro configuration utility for details.
4.7 In-Circuit Programming
The Si5391 is fully configurable using the serial interface (I2C or SPI). At power-up the device downloads its default register values from
internal non-volatile memory (NVM). Application specific default configurations can be written into NVM allowing the device to generate
specific clock frequencies at power-up. Writing default values to NVM is in-circuit programmable with normal operating power supply
voltages applied to its VDD and VDDA pins. The NVM is two time writable. Once a new configuration has been written to NVM, the old
configuration is no longer accessible. Refer to the Si5391 Family Reference Manual for a detailed procedure for writing registers to
NVM.
4.8 Serial Interface
Configuration and operation of the Si5391 is controlled by reading and writing registers using the I2C or SPI interface. The I2C_SEL pin
selects I2C or SPI operation. Communication with both 3.3 V and 1.8 V host is supported. The SPI mode operates in either 4-wire or
3-wire. See the Si5391 Family Reference Manual for details.
4.9 Custom Factory Preprogrammed Devices
For applications where a serial interface is not available for programming the device, custom pre-programmed parts can be ordered
with a specific configuration written into NVM. A factory pre-programmed device will generate clocks at power-up. Use the ClockBuilder
Pro custom part number wizard (https://www.skyworksinc.com/en/Application-Pages/Clockbuilder-Pro-Software) to quickly and easily
request and generate a custom part number for your configuration. In less than three minutes, you will be able to generate a custom
part number with a detailed data sheet addendum matching your design’s configuration. Once you receive the confirmation email with
the data sheet addendum, simply place an order with your local Skyworks sales representative. Samples of your pre-programmed
device will ship to you typically within two weeks.
4.10 Enabling Features and/or Configuration Settings Not Available in ClockBuilder Pro for Factory Pre-Programmed Devices
As with essentially all software utilities, ClockBuilder Pro is continuously updated and enhanced. By registering at http://www.skyworksinc.com and opting in for updates to software, you will be notified whenever changes are made and what the impact of those changes
are. This update process will ultimately enable ClockBuilder Pro users to access all features and register setting values documented
in this data sheet and the Si5391 Family Reference Manual. However, if you must enable or access a feature or register setting value
so that the device starts up with this feature or a register setting, but the feature or register setting is NOT yet available in CBPro, you
must contact a Skyworks applications engineer for assistance. An example of this type of feature or custom setting is the customizable
amplitudes for the clock outputs. After careful review of your project file and custom requirements, a Skyworks applications engineer
will email back your CBPro project file with your specific features and register settings enabled, using what is referred to as the manual
"settings override" feature of CBPro. "Override" settings to match your request(s) will be listed in your design report file. Examples of
setting "overrides" in a CBPro design report are shown below:
Table 4.3. Setting Overrides
Location
Name
Type
Target
Dec Value
Hex Value
0128[6:4]
OUT6_AMPL
User
OPN & EVB
5
5
Once you receive the updated design file, simply open it in CBPro. After you create a custom OPN, the device will begin operation after
startup with the values in the NVM file, including the Skyworks-supplied override settings.
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Si5391 Data Sheet • Functional Description
End: Place
sample order
Start
Do I need a
pre-programmed device with
a feature or setting which is
unavailable in ClockBuilder
Pro?
No
Configure device
using CBPro
Generate
Custom OPN
in CBPro
Yes
Contact Skyworks
Technical Support
to submit & review
your
non-standard
configuration
request & CBPro
project file
Receive
updated CBPro
project file
from
Skyworks
with “Settings
Override”
Yes
Load project file
into CBPro and test
Does the updated
CBPro Project file
match your
requirements?
Figure 4.8. Flowchart to Order Custom Parts with Features not Available in CBPro
Note: Contact Skyworks Technical Support at www.skyworksinc.com/support-ia.
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Si5391 Data Sheet • Register Map
5. Register Map
The register map is divided into multiple pages where each page has 256 addressable registers. Page 0 contains frequently accessible
registers such as alarm status, resets, device identification, etc. Other pages contain registers that need less frequent access such
as frequency configuration, and general device settings. Refer to the Si5391 Family Reference Manual for a complete list of register
descriptions and settings.
Note: It is strongly recommended that ClockBuilder Pro be used to create and manage register settings.
5.1 Addressing Scheme
The device registers are accessible using a 16-bit address which consists of an 8-bit page address + 8-bit register address. By default
the page address is set to 0x00. Changing to another page is accomplished by writing to the ‘Set Page Address’ byte located at
address 0x01 of each page.
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Si5391 Data Sheet • Electrical Specifications
6. Electrical Specifications
Table 6.1. Recommended Operating Conditions1
Parameter
Symbol
Min
Typ
Max
Units
Ambient Temperature
TA
–40
25
85
°C
Junction Temperature
TJMAX
—
—
125
°C
Core Supply Voltage
VDD
1.71
1.80
1.89
V
VDDA
3.14
3.30
3.47
V
VDDO
3.14
3.30
3.47
V
2.37
2.50
2.62
V
1.71
1.80
1.89
V
Output Driver Supply Voltage
Note:
1. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical
values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted.
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Si5391 Data Sheet • Electrical Specifications
Table 6.2. DC Characteristics
(VDD=1.8V ± 5%, VDDA=3.3V ± 5%, VDDO=1.8V ± 5%, 2.5V ± 5%, or 3.3V ± 5%, TA= -40 to 85°C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Core Supply Current1
IDD
Si5391
—
130
260
mA
IDDA
Si5391
—
125
140
mA
IDDOx
LVPECL Output2
—
22
26
mA
—
15
18
mA
—
22
30
mA
—
18
23
mA
—
12
16
mA
—
950
1350
mW
Output Buffer Supply Current
@ 156.25 MHz
LVDS Output2
@ 156.25 MHz
3.3 V LVCMOS3 output
@ 156.25 MHz
2.5 V LVCMOS3 output
@ 156.25 MHz
1.8 V LVCMOS3 output
@ 156.25 MHz
Total Power Dissipation1, 4
Pd
Si5391
Note:
1. Si5391 test configuration: 7 x 2.5 V LVDS outputs enabled @ 156.25 MHz. Excludes power in termination resistors.
2. Differential outputs terminated into an ac-coupled 100 Ω load.
3. LVCMOS outputs measured into a 6-inch 50 Ω PCB trace with 4.7 pF load. The LVCMOS outputs were set to
OUTx_CMOS_DRV=3, which is the strongest driver setting. Refer to the Si5391 Family Reference Manual for more details
on register settings.
Differential Output Test Configuration
I DDO
OUT
50
I DDO
0. 1 uF
100
OUTb
50
LVCMOS Output Test Configuration
6 inch
OUTa
OUTb
50
5 pF
0. 1 uF
4. Detailed power consumption for any configuration can be estimated using ClockBuilderPro when an evaluation board (EVB) is not
available. All EVBs support detailed current measurements for any configuration.
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Si5391 Data Sheet • Electrical Specifications
Table 6.3. Input Clock Specifications (A/B/C/D Grades)
(VDD =1.8 V ± 5%, VDDA = 3.3 V ± 5%, TA= –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Standard Input Buffer with Differential or Single-Ended - AC-Coupled (IN0/IN0b, IN1/IN1b, IN2/IN2b, FB_IN/FB_INb)
Input Frequency Range
fIN
Differential
10
—
750
MHz
All Single-ended Signals
10
—
250
MHz
100
—
1800
mVpp_se
225
—
1800
mVpp_se
100
—
3600
mVpp_se
(including LVCMOS)
Input Voltage Swing1
VIN
Differential AC-coupled
fIN < 250 MHz
Differential AC-coupled
250 MHz < fIN < 750 MHz
Single-ended AC-coupled
fIN < 250 MHz
Slew Rate2,
SR
400
—
—
V/μs
Duty Cycle
DC
40
—
60
%
Input Capacitance
CIN
—
2.4
—
pF
RIN_DIFF
—
16
—
kΩ
RIN_SE
—
8
—
kΩ
0.008
—
250
MHz
—
—
0.4
V
0.8
—
—
V
—
—
0.8
V
1
—
—
V
Input Resistance Differential
Input Resistance Single-Ended
CMOS Input Buffer - DC Coupled (IN0, IN1, IN2,IN4)3
Input Frequency
Input Voltage (See Family Reference Manual for details)
fIN_CMOS
VIL
VIH
VIL
VIH
CMOS_HI_THR = 0
CMOS_HI_THR = 1
Slew Rate2,
SR
400
—
—
V/μs
Duty Cycle
DC
40
—
60
%
Minimum Pulse Width
PW
1.6
—
—
ns
Input Resistance
RIN
—
8
—
kΩ
Full operating range. Jitter performance may be
reduced.
10
—
200
MHz
Range for best jitter.
48
—
54
MHz
VIN_SE
365
—
2000
mVpp_se
VIN_DIFF
365
—
2500
mVpp_diff
Pulse Input
REFCLK (Applied to XA/XB)4
Input Frequency Range
Input Single-ended Voltage
Swing
Input Differential Voltage Swing
20
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Si5391 Data Sheet • Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Slew Rate2,
SR
Imposed for best jitter performance
400
—
—
V/μs
Duty Cycle
DC
40
—
60
%
Note:
Vcm
Vpp_se
Vcm
Vpp_se
Vpp_diff = 2*Vpp_se
1. Voltage swing is specified as single-ended mVpp.
2. Imposed for jitter performance.
3. DC-coupled CMOS Input Buffer selection is not supported in ClockBuilder Pro for new designs. For single-ended LVCMOS inputs
to IN0,1,2 it is required to ac-couple into the differential input buffer.
4. Clock input is not supported on Si5391P, Precision Calibration mode.
Table 6.4. Control Input Pin Specifications
(VDD =1.8 V ± 5%, VDDA = 3.3 V ± 5%, VDDS= 3.3 V ± 5%, 1.8 V ± 5%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Si5391 Control Input Pins (I2C_SEL, IN_SEL[1:0], RSTb, OEb, SYNCb, A1/SDO, SCLK, A0/CSb, FINC, FDEC, SDA/SDIO)
Input Voltage
VIL
—
—
0.3xVDDIO1
V
VIH
0.7xVDDIO1
—
—
V
Input Capacitance
CIN
—
2
—
pF
Input Resistance
RIN
—
20
—
kΩ
Minimum Pulse Width
TPW
RSTb, SYNCb, FINC, and
FDEC
100
—
—
ns
Frequency Update Rate
FUR
FINC and FDEC
—
—
1
MHz
Note:
1. VDDIO is determined by the IO_VDD_SEL bit. It is selectable as VDDA or VDD. Refer to the Si5391 Family Reference Manual for
more details on register settings.
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Si5391 Data Sheet • Electrical Specifications
Table 6.5. Differential Clock Output Specifications
(VDD=1.8 V ± 5%, VDDA= 3.3 V ± 5%, VDDO= 1.8 V ± 5%, 2.5 V ± 5%, or 3.3 V ± 5%, TA= –40 to 85 °C)
Parameter
Output Frequency
Duty Cycle
Symbol
Test Condition
Min
Typ
Max
Units
fOUT
MultiSynth not used
0.0001
—
720
MHz
733.33
—
800.00
825
—
1028
MultiSynth used
0.0001
—
720
MHz
fOUT < 400 MHz
48
—
52
%
400 MHz < fOUT < 1028 MHz
45
—
55
%
Outputs on same MultiSynth
—
0
75
ps
DC
Output-Output Skew
TSKS
Using Same MultiSynth
OUT-OUTb Skew
Output Voltage Swing1
Common Mode Voltage1
(Measured at 712.5 MHz)
TSK_OUT
Measured from the positive
to negative output pins
—
0
50
ps
VOUT
LVDS
350
450
530
mVpp_se
LVPECL
630
780
950
LVDS
1.10
1.2
1.3
LVPECL
1.90
2.0
2.1
LVPECL
1.1
1.2
1.3
0.8
0.9
1.0
—
100
200
ps
—
100
—
Ω
10 kHz sinusoidal noise
—
–101
—
dBc
100 kHz sinusoidal noise
—
–96
—
500 kHz sinusoidal noise
—
–99
—
1 MHz sinusoidal noise
—
–97
—
—
–72
—
VCM
VDDO = 3.3 V
VDDO = 2.5 V
V
LVDS
VDDO = 1.8 V
Rise and Fall Times
tR/tF
Sub-LVDS
fOUT>100 MHz
(20% to 80%)
Differential Output Impedance
Power Supply Noise Rejection2
Output-Output Crosstalk3
ZO
PSRR
XTALK
dBc
Notes:
1. Output amplitude and common-mode settings are programmable through register settings and can be stored in
NVM. Each output driver can be programmed independently. The maximum LVDS single-ended amplitude can be
up to 110 mV higher than the TIA/EIA-644 maximum. Refer to the Si5391 Family Reference Manual for more suggested output settings. Not all combinations of voltage amplitude and common mode voltages settings are possible.
OUTx
Vcm
Vpp_se
Vcm
Vpp_se
Vpp_ diff = 2* Vpp_se
OUTxb
2. Measured for 156.25 MHz carrier frequency. 100 mVpp sinewave noise added to VDDO = 3.3 V and noise spur amplitude
measured.
3. Measured across two adjacent outputs, both in LVDS mode, with the victim running at 155.52 MHz and the aggressor at 156.25
MHz.
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Si5391 Data Sheet • Electrical Specifications
Table 6.6. LVCMOS Clock Output Specifications
(VDD =1.8 V ± 5%, VDDA= 3.3 V ± 5%, VDDO= 1.8 V ± 5%, 2.5 V ± 5%, or 3.3 V ± 5%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
0.0001
—
250
MHz
fOUT < 100 MHz
48
—
52
%
100 MHz < fOUT < 250 MHz
44
—
56
VDDO x 0.85
—
—
Output Frequency
Duty Cycle
Output Voltage High1, 2, 3
DC
VOH
VDDO = 3.3 V
OUTx_CMOS_DRV=1
IOH = -10 mA
OUTx_CMOS_DRV=2
IOH = -12 mA
—
—
OUTx_CMOS_DRV=3
IOH = -17 mA
—
—
—
—
V
VDDO = 2.5 V
OUTx_CMOS_DRV=1
IOH = -6 mA
VDDO x 0.85
V
OUTx_CMOS_DRV=2
IOH = -8 mA
—
—
OUTx_CMOS_DRV=3
IOH = -11 mA
—
—
—
—
—
—
VDDO x 0.15
V
VDDO x 0.15
V
VDDO x 0.15
V
VDDO = 1.8 V
Output Voltage Low1, 2, 3
VOL
OUTx_CMOS_DRV=2
IOH = -4 mA
OUTx_CMOS_DRV=3
IOH = -5 mA
VDDO x 0.85
V
VDDO = 3.3 V
OUTx_CMOS_DRV=1
IOL = 10 mA
—
—
OUTx_CMOS_DRV=2
IOL = 12 mA
—
—
OUTx_CMOS_DRV=3
IOL = 17 mA
—
—
OUTx_CMOS_DRV=1
IOL = 6 mA
—
—
OUTx_CMOS_DRV=2
IOL = 8 mA
—
—
OUTx_CMOS_DRV=3
IOL = 11 mA
—
—
OUTx_CMOS_DRV=2
IOL = 4 mA
—
—
OUTx_CMOS_DRV=3
IOL = 5 mA
—
—
VDDO = 3.3 V, 156.25 MHz
—
400
600
ps
VDDO = 2.5 V, 156.25 MHz
—
450
600
ps
VDDO = 1.8 V, 156.25 MHz
—
550
750
ps
VDDO = 2.5 V
VDDO = 1.8 V
LVCMOS Rise and Fall
Times3
(20% to 80%)
23
tr/tf
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Si5391 Data Sheet • Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Notes:
1. Driver strength is a register programmable setting and stored in NVM. Options are OUTx_CMOS_DRV = 1, 2, 3. Refer to the
Si5391 Family Reference Manual for more details on register settings.
2. IOL/IOH is measured at VOL/VOH as shown in the dc test configuration.
3. A series termination resistor (Rs) is recommended to help match the source impedance to a 50 Ω PCB
trace. A 5 pF capacitive load is assumed. The LVCMOS outputs were set to OUTx_CMOS_DRV = 3.
AC Test Configuration
DC Test Configuration
Trace length 5 inches
IOL/IOH
IDDO
50
OUT
Zs
VOL/VOH
499
4.7 pF
DC Block
OUTb
499
DC Block
50 probe, scope
50
4.7 pF
24
50 probe, scope
56
56
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Si5391 Data Sheet • Electrical Specifications
Table 6.7. Output Status Pin Specifications
(VDD =1.8 V ± 5%, VDDA= 3.3 V ± 5%, VDDS= 3.3 V ± 5%, 1.8 V ± 5%, TA = –40 to 85°C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
VOH
IOH = -2 mA
VDDIO2 x
0.85
—
—
V
VOL
IOL = 2 mA
—
—
VDDIO2x
0.15
V
VOH
IOH = -2 mA
VDDIO2 x
0.85
—
—
V
VOL
IOL = 2 mA
—
—
VDDIO2 x
0.15
V
Si5391 Status Output Pins (INTRb, SDA/SDIO)1
Output Voltage
Si5391 Status Output Pins (LOLb)
Output Voltage
Notes:
1. The VOH specification does not apply to the open-drain SDA/SDIO output when the serial interface is in I2C mode or is unused
with I2C_SEL pulled high. VOL remains valid in all cases.
2. VDDIO is determined by the IO_VDD_SEL bit. It is selectable as VDDA or VDD. Refer to the Si5391 Family Reference Manual for
more details on register settings.
Table 6.8. Performance Characteristics
(VDD= 1.8 V ± 5%, VDDA= 3.3 V ± 5%, TA= –40 to 85 °C)
Parameter
Symbol
PLL Loop Bandwidth
fBW
Initial Start-Up Time
tSTART
PLL Lock Time1
tACQ
POR2 to Serial Interface
Ready
tRDY
RMS Phase Jitter5 (Grade
P)
JGEN
RMS Phase Jitter6 (Grade
A/B/C/D)
25
JGEN
Test Condition
Min
Typ
Max
Units
—
1.0
—
MHz
Time from power-up to when the device generates clocks (Input Frequency >48 MHz)
A/B/C/D grades
—
30
45
Time from power-up to when the device generates free-running clocks in P-Grade
—
460
625
fIN = 19.44 MHz
15
—
150
ms
—
—
15
ms
fOUT = 156.25 MHz
69
90
fs
fOUT = 312.5 MHz
69
95
fs
fOUT = 100 MHz
150
200
fs
fOUT = 50/25 MHz
200
300
fs
Output divider Integer
Mode3
75
115
fs
Output divider Fractional Mode4
115
145
fs
fIN = 48 MHz crystal
fIN = 48 MHz crystal
ms
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Si5391 Data Sheet • Electrical Specifications
Parameter
Symbol
RMS Phase Jitter6 (Grade
A/B/C/D)
JGEN
Test Condition
fIN = 100 MHz clock
Min
Typ
Max
Units
Output divider Integer
Mode3
145
195
fs
Output divider Fractional Mode4
165
215
fs
Notes:
1. PLL lock time is measured by first letting the PLL lock, then turning off the input clock, and then turning on the input clock. The
time from the first edge of the input clock being re-applied until LOL de-asserts is the PLL lock time.
2. Measured as time from valid VDD and VDD33 rails (90% of their value) to when the serial interface is ready to respond to
commands. Measured in SPI 4-wire mode, with SCLK @ 10 MHz.
3. Integer mode assumes that the output dividers (Nn/Nd) are configured with an integer value.
4. Fractional and DCO modes assume that the output dividers (Nn/Nd) are configured with a fractional value and the feedback
divider is integer.
5. Grade P is calibrated for optimum performance in 56G/112G SerDes applications at frequencies of 312.5 MHz or 156.25 MHz.
Specific layout rules must be followed to achieve optimum performance. For mroe details refer to 4.5.2 Grade P.
6. Grade A/B/C/D are targeted for applications that require more flexibility and set the output divider to Integer or Fractional modes.
Integer mode test conditions: fin = 100 MHz, fout = 156.25 MHz (MultiSynth in integer mode). Fractional mode test conditions: fin
= 100 MHz, fout = 156.25 MHz (Multisynth in fractional mode). Outputs are assumed to be LVPECL. For more details, refer to
4.5.1 Grade A/B/C/D.
Table 6.9. I2C Timing Specifications (SCL,SDA)
Parameter
Symbol
Test Condition
Standard Mode
Fast Mode
100 kbps
400 kbps
Min
Max
Min
Max
Units
SCL Clock Frequency
fSCL
—
100
—
400
kHz
Hold Time (Repeated)
START Condition
tHD:STA
4.0
—
0.6
—
μs
Low Period of the SCL Clock
tLOW
4.7
—
1.3
—
μs
HIGH Period of the SCL
Clock
tHIGH
4.0
—
0.6
—
μs
Set-up Time for a Repeated
START Condition
tSU:STA
4.7
—
0.6
—
μs
Data Hold Time
tHD:DAT
100
—
100
—
ns
Data Set-up Time
tSU:DAT
250
—
100
—
ns
Rise Time of Both SDA and
SCL Signals
tr
—
1000
20
300
ns
Fall Time of Both SDA and
SCL Signals
tf
—
300
—
300
ns
Set-up Time for STOP Condition
tSU:STO
4.0
—
0.6
—
μs
Bus Free Time between a
STOP and START Condition
tBUF
4.7
—
1.3
—
μs
Data Valid Time
tVD:DAT
—
3.45
—
0.9
μs
Data Valid Acknowledge
Time
tVD:ACK
—
3.45
—
0.9
μs
26
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Si5391 Data Sheet • Electrical Specifications
Figure 6.1. I2C Serial Port Timing Standard and Fast Modes
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Si5391 Data Sheet • Electrical Specifications
Table 6.10. SPI Timing Specifications (4-Wire)
(VDD=1.8 V ± 5%, VDDA=3.3 V ± 5%, TA= –40 to 85 °C)
Parameter
Symbol
Min
Typ
Max
Units
SCLK Frequency
fSPI
—
—
20
MHz
SCLK Duty Cycle
TDC
40
—
60
%
SCLK Period
TC
50
—
—
ns
Delay Time, SCLK Fall to SDO Active
TD1
—
—
18
ns
Delay Time, SCLK Fall to SDO
TD2
—
—
15
ns
Delay Time, CSb Rise to SDO Tri-State
TD3
—
—
15
ns
Setup Time, CSb to SCLK
TSU1
5
—
—
ns
Hold Time, SCLK Fall to CSb
TH1
5
—
—
ns
Setup Time, SDI to SCLK Rise
TSU2
5
—
—
ns
Hold Time, SDI to SCLK Rise
TH2
5
—
—
ns
Delay Time Between Chip Selects (CSb)
TCS
2
—
—
TC
TSU1
TD1
TC
SCLK
TH1
CSb
TSU2
TH2
TCS
SDI
TD2
TD3
SDO
Figure 6.2. 4-Wire SPI Serial Interface Timing
28
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Si5391 Data Sheet • Electrical Specifications
Table 6.11. SPI Timing Specifications (3-Wire)
(VDD=1.8 V ± 5%, VDDA= 3.3 V ± 5%, TA= –40 to 85 °C)
Parameter
Symbol
Min
Typ
Max
Units
SCLK Frequency
fSPI
—
—
20
MHz
SCLK Duty Cycle
TDC
40
—
60
%
SCLK Period
TC
50
—
—
ns
Delay Time, SCLK Fall to SDO Turn-on
TD1
—
—
20
ns
Delay Time, SCLK Fall to SDO Next-bit
TD2
—
—
15
ns
Delay Time, CSb Rise to SDO Tri-State
TD3
—
—
15
ns
Setup Time, CSb to SCLK
TSU1
5
—
—
ns
Hold Time, CSb to SCLK Rise
TH1
5
—
—
ns
Setup Time, SDI to SCLK Rise
TSU2
5
—
—
ns
Hold Time, SDI to SCLK Rise
TH2
5
—
—
ns
Delay Time Between Chip Selects (CSb)
TCS
2
—
—
TC
TSU1
TC
SCLK
TD1
CSb
TSU2
TH1
TD2
TH2
TCS
SDIO
TD3
Figure 6.3. 3-Wire SPI Serial Interface Timing
29
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Si5391 Data Sheet • Electrical Specifications
Table 6.12. Crystal Specifications
Parameter
Crystal Frequency Range
Symbol
Test Condition
Min
Typ
Max
Units
fXTAL
Full operating range. Jitter performance may be reduced.
24.97
—
54.06
MHz
Range for best jitter.
48
—
54
MHz
Si5391P requires 48 MHz
XTAL
Load Capacitance
CL
—
8
—
pF
Crystal Drive Level
dL
—
—
200
μW
Equivalent Series Resistance
Shunt Capacitance
rESR
CO
Refer to the Si5391 Family Reference Manual to determine ESR and shunt capacitance.
Note:
1. Refer to the Si534x/8x Recommended Crystal, TCXO and OCXOs Reference Manual for recommended 48 to 54 MHz crystals.
The Si5391 is designed to work with crystals that meet these specifications.
Table 6.13. Thermal Characteristics
Parameter
Symbol
Test Condition1
Value
Units
ϴJA
Still Air
22
°C/W
Air Flow 1 m/s
19.4
Air Flow 2 m/s
18.3
Si5391 - 64QFN
Thermal Resistance
Junction to Ambient
Thermal Resistance
ϴJC
9.5
Thermal Resistance
ϴJB
9.4
Junction to Board
ΨJB
9.3
Thermal Resistance
ΨJT
0.2
Junction to Case
Junction to Top Center
Note:
1. Based on PCB Dimension: 3 x 4.5 mm, PCB Land/Via under GND pad: 36, Number of Cu Layers: 4
30
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Si5391 Data Sheet • Electrical Specifications
Table 6.14. Absolute Maximum Ratings1, 2, 3
Parameter
Symbol
Test Condition
Value
Units
Storage Temperature Range
TSTG
-55 to +150
°C
DC Supply Voltage
VDD
-0.5 to 3.8
V
VDDA
-0.5 to 3.8
V
VDDO
-0.5 to 3.8
V
Input Voltage Range
Latch-up Tolerance
VI1
IN0-IN2, FB_IN
-1.0 to 3.8
V
VI2
IN_SEL[1:0], RSTb, OEb,
SYNCb, I2C_SEL, SDI, SCLK,
A0/CSb, A1, SDA/SDIO, FINC/
FDEC
-0.5 to 3.8
V
VI3
XA/XB
-0.5 to 2.7
V
LU
ESD Tolerance
HBM
Maximum Junction Temperature in Operation
Soldering Temperature (Pb-free profile)3
Soldering Temperature Time at TPEAK
JESD78 Compliant
100 pF, 1.5 kΩ
2.0
kV
TJCT
125
°C
TPEAK
260
°C
TP
20 to 40
sec
(Pb-free profile)3
Notes:
1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be restricted
to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
2. 64-QFN packages are RoHS-6 compliant.
3. The device is compliant with JEDEC J-STD-020.
31
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Si5391 Data Sheet • Detailed Block Diagrams
VDD
VDDA
7. Detailed Block Diagrams
3
Si5391
IN_ SEL[1:0]
Clock
Generator
IN0
÷P0
IN0b
IN1
IN2
PLL
PD
÷P2
IN2b
LPF
÷
÷ PXAXB
÷
OSC
Si5391P requires 48 MHz XTAL
XA
÷
N1n
N1d
t1
÷
N2n
N2d
t2
÷
N3n
N3d
t3
÷
N4n
N4d
t4
Zero Delay
Mode
FB_IN
÷Pfb
FB_ INb
Mn
Md
MultiSynth
N0n
t0
N0d
XB
25-54 MHz
XTAL
VDDO0
OUT0
OUT0b
÷R0
÷P1
IN1b
Dividers/
Drivers
OUT0A
OUT0Ab
÷R0A
÷R1
VDDO1
OUT1
OUT1b
÷R2
VDDO2
OUT2
OUT2b
÷R3
VDDO3
OUT3
OUT3b
÷R4
VDDO4
OUT4
OUT4b
÷R5
VDDO5
OUT5
OUT5b
÷R6
VDDO6
OUT6
OUT6b
÷R7
VDDO7
OUT7
OUT7b
÷R8
VDDO8
OUT8
OUT8b
÷R9
VDDO9
OUT9
OUT9b
÷R9A
OUT9A
OUT9Ab
I2C_ SEL
OEb
Frequency
Control
SYNCb
Status
Monitors
FINC
RSTb
A0/CSb
NVM
FDEC
SCLK
SPI /
I2 C
INTRb
A1/ SDO
LO Lb
SDA/ SDIO
Figure 7.1. Si5391 Block Diagram
32
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Si5391 Data Sheet • Typical Operating Characteristics
8. Typical Operating Characteristics
Figure 8.1. 156.25MHz Ouput (3.3V LVPECL) in Precision Calibration Mode (Grade P)
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Si5391 Data Sheet • Pin Descriptions
9. Pin Descriptions
34
VDDO8
OUT7
OUT7b
VDDO7
50
49
53
51
OUT8b
54
52
OUT9b
OUT8
55
VDDO9
OUT9
OUT9
56
57
OUT9A
OUT9A
OUT9Ab
OUT9Ab
60
58
FB_IN
VDD
61
59
IN0
FB_INb
FB_INb
62
IN0b
63
64
Si 5391 64QFN
Top View
IN1
1
48
IN1b
2
47
LOLb
IN_ SEL0
3
46
VDD
IN_ SEL1
4
45
OUT 6
SYNCb
5
44
OUT6b
RSTb
6
43
VDDO6
X1
7
42
OUT5
XA
8
41
OUT5b
XB
9
40
VDDO 5
X2
10
39
I2C_SEL
OEb
11
38
OUT4
INTRb
12
37
OUT4b
VDDA
13
36
VDDO4
IN2
14
35
OUT3
IN2b
15
34
OUT3b
SCLK
16
33
VDDO 3
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
A1/SDO
SDA/SDIO
A0/CSb
OUT0Ab
OUT0A
VDDO0
OUT0b
OUT0
FDEC
VDDO1
OUT1b
OUT1
VDDO2
OUT2b
OUT2
VDD
GND
Pad
FINC
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Si5391 Data Sheet • Pin Descriptions
Table 9.1. Pin Descriptions
Pin
Name
Pin Number
Pin Type1
Function
Crystal and External Clock Input.
These pins are used to connect an external crystal or an external clock. See
4.3.1 XA/XB Clock and Crystal Input
and Figure 4.2 XAXB External Crystal
and Clock Connections on page 8 for
connection information. If IN_SEL[1:0]
= 11b, then the XAXB input is selected. If the XAXB input is not used and
powered down, then both inputs can
be left unconnected. ClockBuilder Pro
will power down an input that is set as
"Unused".
Si5391
Inputs
XA
8
I
XB
9
I
X1
7
I
X2
10
I
IN0
63
I
IN0b
64
I
IN1
1
I
IN1b
2
I
IN2
14
I
IN2b
15
I
FB_IN
61
I
FB_INb
62
I
35
XTAL Shield. Connect these pins directly to the XTAL ground pins. X1, X2,
and the XTAL ground pins must not be
connected to the PCB ground plane.
DO NOT GROUND THE CRYSTAL
GROUND PINS. Refer to the Si5391
Family Reference Manual for layout
guidelines. These pins should be left
disconnected when connecting XA/XB
pins to an external reference clock.
Clock Inputs. These pins accept both
differential and single-ended clock signals. Refer 4.3.2 Input Clocks (IN0,
IN1, IN2) for input termination options.
These pins are high-impedance and
must be terminated externally. If both
the INx and INxb inputs are un-used
and powered down, then both inputs
can be left floating. ClockBuilder Pro
will power down an input that is set as
"Unused".
External Feedback Input. These pins
are used as the external feedback input (FB_IN/FB_INb) for the optional
zero delay mode. See 4.5.13 Zero Delay Mode (Grade A/B/C/D) for details
on the optional zero delay mode. If
FB_IN and FB_INb are un-used and
powered down, then both inputs can
be left floating. ClockBuilder Pro will
power down an input that is set as
"Unused".
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35
Si5391 Data Sheet • Pin Descriptions
Pin Name
Pin Number
Pin Type1
Function
Output Clocks. These output clocks support a programmable
signal amplitude when configured as a differential output. Desired
output signal format is configurable using register control. Termination recommendations are provided in 4.5.4 Differential Output
Terminations and 4.5.6 LVCMOS Output Terminations. Unused
outputs should be left unconnected.
Si5391
Outputs
OUT0
24
O
OUT0b
23
O
OUT0A
21
O
OUT0Ab
20
O
OUT1
28
O
OUT1b
27
O
OUT2
31
O
OUT2b
30
O
OUT3
35
O
OUT3b
34
O
OUT4
38
O
OUT4b
37
O
OUT5
42
O
OUT5b
41
O
OUT6
45
O
OUT6b
44
O
OUT7
51
O
OUT7b
50
O
OUT8
54
O
OUT8b
53
O
OUT9
56
O
OUT9b
55
O
OUT9A
59
O
OUT9Ab
58
O
I2C_SEL
39
I
SDA/SDIO
18
I/O
Serial Data Interface.2 This is the bidirectional data pin (SDA) for
the I2C mode, or the bidirectional data pin (SDIO) in the 3-wire
SPI mode, or the input data pin (SDI) in 4-wire SPI mode. When
in I2C mode, this pin must be pulled-up using an external resistor
of at least 1 kΩ. No pull-up resistor is needed when in SPI mode.
A1/SDO
17
I/O
Address Select 1/Serial Data Output.2 In I2C mode, this pin
functions as the A1 address input pin and does not have an
internal pull up or pull down resistor. In 4-wire SPI mode this is
the serial data output (SDO) pin (SDO) pin and drives high to the
voltage selected by the IO_VDD_SEL pin.
Serial Interface
36
I2C Select.2 This pin selects the serial interface mode as I2C
(I2C_SEL = 1) or SPI (I2C_SEL = 0). This pin is internally
pulled up by a ~ 20 kΩ resistor to the voltage selected by the
IO_VDD_SEL register bit.
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Si5391 Data Sheet • Pin Descriptions
Pin Name
Pin Number
Pin Type1
Function
Si5391
SCLK
16
I
Serial Clock Input.2 This pin functions as the serial clock input for
both I2C and SPI modes.This pin is internally pulled up by a ~20
kΩ resistor to the voltage selected by the IO_VDD_SEL register
bit. In I2C mode this pin should have an external pull up of at least
1 kΩ. No pull-up resistor is needed when in SPI mode.
A0/CSb
19
I
Address Select 0/Chip Select.2 This pin functions as the hardware controlled address A0 in I2C mode. In SPI mode, this pin
functions as the chip select input (active low). This pin is internally
pulled up by a ~20 kΩ resistor to the voltage selected by the
IO_VDD_SEL register bit.
INTRb
12
O
Interrupt. 2 This pin is asserted low when a change in device
status has occurred. This interrupt has a push pull output and
should be left unconnected when not in use.
RSTb
6
I
Device Reset. 2 Active low input that performs power-on reset
(POR) of the device. Resets all internal logic to a known state and
forces the device registers to their default values. Clock outputs
are disabled during reset. This pin is internally pulled up with a
~20 kΩ resistor to the voltage selected by the IO_VDD_SEL bit.
OEb
11
I
Output Enable.2 This pin disables all outputs when held high.
This pin is internally pulled low and can be left unconnected when
not in use.
LOLb
47
O
Loss Of Lock.2 This output pin indicates when the DSPLL™ is
locked (high) or out-of-lock (low). An external pull up or pull down
is not needed.
SYNCb
5
I
Output Clock Synchronization.2 An active low signal on this pin
resets the output dividers for the purpose of re-aligning the output
clocks. For a tighter alignment of the clocks, a soft reset should
be applied. This pin is internally pulled up with a ~20 kΩ resistor
to the voltage selected by the IO_VDD_SEL bit and can be left
unconnected when not in use.
FDEC
25
I
Frequency Decrement Pin.2 This pin is used to step-down the
output frequency of a selected output. The affected output driver
and its frequency change step size is register configurable. This
pin is internally pulled low with a ~20 kΩ resistor and can be left
unconnected when not in use.
FINC
48
I
Frequency Increment Pin.2 This pin is used to step-up the output frequency of a selected output. The affected output and its
frequency change step size is register configurable. This pin is
internally pulled low with a ~20 kΩ resistor and can be left unconnected when not in use.
IN_SEL0
3
I
IN_SEL1
4
I
Input Reference Select.2 The IN_SEL[1:0] pins are used in the
manual pin controlled mode to select the active clock input. These
pins are internally pulled up with a ~20 kΩ resistor to the voltage
selected by the IO_VDD_SEL bit and can be left unconnected
when not in use.
32
P
Control/Status
Power
VDD
46
Core Supply Voltage. The device core operates from a 1.8 V
supply. A 1.0 µf bypass capacitor is recommended.
60
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Si5391 Data Sheet • Pin Descriptions
Pin Name
Pin Number
Pin Type1
Function
Si5391
VDDA
13
P
Core Supply Voltage 3.3 V. This core supply pin requires a 3.3 V
power source. A 1.0 µf bypass capacitor is recommended.
VDDO0
22
P
VDDO1
26
P
VDDO2
29
P
VDDO3
33
P
Output Clock Supply Voltage 0–9. Supply voltage (3.3 V, 2.5 V,
1.8 V) for OUTx, OUTx outputs. See the Si5391 Family Reference
Manual for power supply filtering recommendations. Leave VDDO
pins of unused output drivers unconnected. An alternate option is
to connect the VDDO pin to a power supply and disable the output
driver to minimize current consumption.
VDDO4
36
P
VDDO5
40
P
VDDO6
43
P
VDDO7
49
P
VDDO8
52
P
VDDO9
57
P
GND PAD
P
Ground Pad This pad provides electrical and thermal connection
to ground and must be connected for proper operation. Use as
many vias as practical and keep the via length to an internal
ground plan as short as possible.
Note:
1. I = Input, O = Output, P = Power.
2. The IO_VDD_SEL control bit (0x0943 bit 0) selects 3.3 V or 1.8 V operation.
38
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Si5391 Data Sheet • Package Outlines
10. Package Outlines
10.1 Si5391 9x9 mm 64-QFN Package Diagram
The figure below illustrates the package details for the Si5391. The table below lists the values for the dimensions shown in the
illustration.
Figure 10.1. 64-Pin Quad Flat No-Lead (QFN)
Table 10.1. Package Dimensions
Dimension
Min
Nom
Max
A
0.80
0.85
0.90
A1
0.00
0.02
0.05
b
0.18
0.25
0.30
D
D2
9.00 BSC
5.10
5.20
e
0.50 BSC
E
9.00 BSC
5.30
E2
5.10
5.20
5.30
L
0.30
0.40
0.50
aaa
—
—
0.15
bbb
—
—
0.10
ccc
—
—
0.08
ddd
—
—
0.10
eee
—
—
0.05
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-220.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
39
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Si5391 Data Sheet • PCB Land Pattern
11. PCB Land Pattern
The figure below illlustrates the PCB land pattern details for the devices. The table below lists the values for the dimensions shown in
the illustration.
Si5391
Figure 11.1. PCB Land Pattern
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Si5391 Data Sheet • PCB Land Pattern
Table 11.1. PCB Land Pattern Dimensions
Dimension
Si5391 (Max)
C1
8.90
C2
8.90
E
0.50
X1
0.30
Y1
0.85
X2
5.30
Y2
5.30
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
3. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition is calculated based on a fabrication
Allowance of 0.05 mm.
Solder Mask Design
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm
minimum, all the way around the pad.
Stencil Design
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
4. A 3×3 array of 1.25 mm square openings on 1.80 mm pitch should be used for the center ground pad.
Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
41
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Si5391 Data Sheet • Top Marking
12. Top Marking
Figure 12.1. Si5391 Top Marking
Table 12.1. Si5391 Top Marking Explanation
Line
Characters
1
Si5391g-
Description
Base part number and Device Grade for Low Jitter, Any-Frequency, 12-output Clock
Generator.
Si5391: 10-output, 64-QFN
g = Device Grade (A, B, C, D, P). See 3. Ordering Guide for more information.
– = Dash character.
2
Rxxxxx-GM
R = Product revision. (See ordering guide for current revision).
xxxxx = Customer specific NVM sequence number. Optional NVM code assigned for
custom, factory pre-programmed devices.
Characters are not included for standard, factory default configured devices. See
Ordering Guide for more information.
–GM = Package (QFN) and temperature range (–40 to +85 °C)
3
YYWWTTTTTT
YYWW = Characters correspond to the year (YY) and work week (WW) of package
assembly.
TTTTTT = Manufacturing trace code.
4
Circle w/ 1.6 mm (64-QFN) diam- Pin 1 indicator; left-justified
eter
TW
42
TW = Taiwan; Country of Origin (ISO Abbreviation)
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Si5391 Data Sheet • Device Errata
13. Device Errata
See www.skyworksinc.com to access the device errata document.
43
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Si5391 Data Sheet • Revision History
14. Revision History
Revision 1.0
May, 2019
• Expanded rules and layout guidelines for P-grade operation.
Revision 0.8
March, 2019
• Corrected Ordering Guide OPN from Si5391P-A-EGM to Si5391P-A-GM.
• Updated CMOS input buffer specifications.
• Adjusted core supply current and power dissipation.
• Adjusted typical input capacitance.
• Adjusted LVCMOS DC-Coupled Input voltage threshold.
• Expanded operation of the Si5392P/94P/95P grade options to support 1, 2 or 3 output clock domains.
Revision 0.7
June, 2018
• Initial release.
44
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