SI5397L-A12203-GM

Si5397/96 Data Sheet Dual/Quad DSPLL™ Any-Frequency, Any-Output Jitter Attenuators The Si5397 is a high-performance, 8-output jitter-attenuating clock multiplier which integrates four any-frequency DSPLLs for applications that require maximum integration and independent timing paths. The Si5396 is a dual DSPLL version with either 4 outputs or 12 outputs. Each DSPLL has access to any of the four inputs and can provide low jitter clocks on any of the device outputs. Device grades J/K/L/M have an integrated reference to save board space, improve system reliability and reduces the effect of acoustic emissions noise caused by temperature ramps. Grades A/B/C/D use an external crystal (XTAL) or crystal oscillator (XO) reference. Based on 4th generation DSPLL technology, these devices provide any-frequency conversion with typical jitter performance of 95 fs. Each DSPLL supports independent free-run, holdover modes of operation, as well as automatic and hitless input clock switching. The Si5397/96 is programmable via a serial interface with in-circuit programmable non-volatile memory so that it always powers up in a known configuration. Programming the Si5397/96 is easy with Skyworks' ClockBuilder Pro software. Factory pre-programmed devices are also available. • Each DSPLL generates any output frequency from any input frequency • Four or two DSPLLs to synchronize to multiple time domains • Ultra-low phase jitter of 95 fs rms • Enhanced hitless switching minimizes output phase transients • Input frequency range: • Differential: 8 kHz to 750 MHz • LVCMOS: 8 kHz to 250 MHz • Output frequency range: • Differential: 100 Hz to 720 MHz • LVCMOS: 100 Hz 250 MHz • Status Monitoring • Si5397: 4-PLL, 8/4 output, 64-QFN/LGA • Si5396: 2-PLL, 4 output, 44-QFN/LGA and 12 output, 64-QFN/LGA Applications • OTN Muxponders and Transponders • 10/40/100/400GbE • Synchronous Ethernet (ITU-T G.8262) • 10/25/100G Carrier Ethernet switches • Broadcast video • External reference: Grades A/B/C/D • Integrated reference: Grades J/K/L/M • Drop-in compatible with Si5347/46 Si5397 Si5396 ÷R0A Integrated Reference* Integrated Reference* OUT0A OUT1 ÷R2 OUT2 ÷R3 OUT3 ÷R4 OUT4 ÷R5 OUT5 ÷R6 OUT6 ÷R7 OUT7 NVM ÷R8 OUT8 I C/SPI I2C/SPI ÷R9 OUT9 Control/ Status Control/ Status ÷R9A OUT9A ÷P0 IN1 IN2 ÷P1 DSPLL B ÷P2 DSPLL C ÷P3 NVM 2 DSPLL D ÷R1 OUT1 ÷R2 ÷R3 ÷R4 ÷R5 OUT2 IN0 ÷P0 IN1 ÷P1 DSPLL A IN2 ÷P2 DSPLL B OUT3 OUT4 OUT5 ÷R6 OUT6 ÷R7 OUT7 Si5397A/B/J/K IN3 DSPLL A OUT0 IN3 ÷P3 Si5396C/D/L/M ÷R1 ÷R0 Si5396A/B/J/K OUT0 Si5397C/D/L/M ÷R0 IN0 1 KEY FEATURES Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • December 4, 2021 1 Si5397/96 Data Sheet • Feature List 1. Feature List The Si5397/96 features are listed below: • Generates any output frequency in any format from any input frequency • External XTAL or XO reference (A/B/C/D) • Integrated reference (J/K/L/M) • Ultra-low phase jitter of 95 fs rms • Four or two DSPLLs to synchronize to multiple inputs • Input frequency range: • Differential: 8 kHz to 750 MHz • LVCMOS: 8 kHz to 250 MHz • Output frequency range: • Differential: up to 720 MHz • LVCMOS: up to 250 MHz • Flexible crosspoints route any input to any output clock • Programmable jitter attenuation bandwidth per DSPLL: 0.1 Hz to 4 kHz • Highly configurable outputs compatible with LVDS, LVPECL, LVCMOS, CML, and HCSL with programmable signal amplitude • Status monitoring (LOS, OOF, LOL) • Enhanced hitless switching minimizes output phase transients for 8 kHz, 19.44 MHz, 25 MHz, and other input frequencies • Drop-in compatible with Si5347/46 2 • • • • • • Locks to gapped clock inputs Automatic free-run and holdover modes Fastlock feature for low nominal bandwidths Independent Frequency-on-the-fly for each DSPLL DCO mode: as low as 0.01 ppb steps per DSPLL Core voltage: • VDD: 1.8 V ±5% • VDDA: 3.3 V ±5% • Independent output clock supply pins: 3.3, 2.5, or 1.8 V • Serial interface: I2C or SPI • In-circuit programmable with non-volatile OTP memory • ClockBuilder™ Pro software tool simplifies device configuration • Si5397 (4-PLL): 4 input, 8 output • Grade A/B: 64-QFN 9×9 mm • Grade J/K: 64-LGA 9x9 mm • Si5397 (4-PLL): 4 input, 4 output • Grade C/D: 64-QFN 9×9 mm • Grade L/M: 64-LGA 9x9 mm • Si5396 (2-PLL): 4 input, 4 output • Grade A/B: 44-QFN 7×7 mm • Grade J/K: 44-LGA 7x7 mm • Si5396 (2-PLL): 4 input, 12 output • Grade C/D: 64-QFN 9×9 mm • Grade L/M: 64-LGA 9x9 mm • Temperature range: –40 to +85 °C • Pb-free, RoHS-6 compliant Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • December 4, 2021 2 Si5397/96 Data Sheet • Related Documents 2. Related Documents Table 2.1. Related Documentation and Software Document/Resource Description/URL Si5397/96 Family Reference Manual Si5397/96 Family Reference Manual The reference manual is intended to be used in conjunction with this data sheet, which contains more detailed explanations about the operation of the device. Crystal Reference Manual (Grades A/B/C/D only) https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/reference-manuals/si534x-8x-9x-recommendedcrystals-rm.pdf UG336: Si5396 Evaluation Board User's Guide UG353: Si5397 Evaluation Board User's Guide AN1151: Using the Si539x in 56G SerDes Applications AN1155: Differences between Si5342-47 and Si5392-97 https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/user-guides/ug336-si5396-evb.pdf https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/user-guides/ug353-si5397evb.pdf https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/application-notes/an1151-using-si539x.pdf https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/application-notes/an1155-differences-betweensi5342-47-and-si5392-97.pdf AN1178: Frequency-On-the-Fly for Skyworks Jitter Attenuators and Clock Generators https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/application-notes/an1178-frequency-otf-jitter-attenclock-gen.pdf Quality and Reliability https://www.skyworksinc.com/Quality Development Kits https://www.skyworksinc.com/en/Products/Timing ClockBuilder Pro (CBPro) Software https://www.skyworksinc.com/en/Application-Pages/ClockbuilderPro-Software 3 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • December 4, 2021 3 Si5397/96 Data Sheet • Ordering Guide 3. Ordering Guide Table 3.1. Si5397/96 A/B/C/D Ordering Guide (External Reference) Ordering Part Number Number Of DSPLLs Number of Input/Output Clocks Output Clock Package Reference 64-QFN 9x9 mm External Frequency Range Si5397 Si5397A-A-GM1,2 Si5397B-A-GM1,2 Si5397C-A-GM1,2 4/8 4 4/4 Si5397D-A-GM1,2 Si5397A-A-EVB — 8-output 2 4/4 0.0001 to 720 MHz 0.0001 to 350 MHz 0.0001 to 720 MHz 0.0001 to 350 MHz — Evaluation Board Si5396 Si5396A-A-GM1,2 Si5396B-A-GM1,2 Si5396C-A-GM1,2 Si5396D-A-GM1,2 Si5396C-A-EVB 0.0001 to 720 MHz 0.0001 to 350 MHz 44-QFN 7x7 mm External 0.0001 to 720 MHz 2 4/12 — 4/12 0.0001 to 350 MHz — 64-QFN 9x9 mm Evaluation Board Notes: 1. Add an R at the end of the device part number to denote tape and reel ordering options. 2. Custom, factory pre-programmed devices are available. Ordering part numbers are assigned by the ClockBuilder Pro software. Part number format is: Si5397A-Axxxxx-GM or Si5396A-Axxxxx-GM, where “xxxxx” is a unique numerical sequence representing the pre-programmed configuration. 4 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • December 4, 2021 4 Si5397/96 Data Sheet • Ordering Guide Table 3.2. Si5397/6 J/K/L/M Ordering Guide (Integrated Reference) Ordering Part Number Number Of DSPLLs Number of Input/Output Clocks Output Clock Package Reference 64-LGA 9x9 mm Internal Frequency Range Si5397 Si5397J-A-GM1,2 Si5397K-A-GM1,2 Si5397L-A-GM1,2 4/8 4 4/4 Si5397M-A-GM1,2 Si5397J-A-EVB — 8-output 2 4/4 — 4/4 0.0001 to 720 MHz 0.0001 to 350 MHz 0.0001 to 720 MHz 0.0001 to 350 MHz — Evaluation Board Si5396 Si5396J-A-GM1,2 Si5396K-A-GM1,2 Si5396J-A-EVB Si5396L-A-GM1,2 Si5396M-A-GM1,2 Si5396L-A-EVB 0.0001 to 720 MHz 0.0001 to 350 MHz — 44-LGA 7x7 mm Evaluation Board 0.0001 to 720 MHz 2 4/12 — 4/12 0.0001 to 350 MHz — Internal 64-LGA 9x9 mm Evaluation Board Notes: 1. Add an R at the end of the device part number to denote tape and reel ordering options. 2. Custom, factory pre-programmed devices are available. Ordering part numbers are assigned by the ClockBuilder Pro software. Part number format is: Si5397A-Axxxxx-GM or Si5396A-Axxxxx-GM, where “xxxxx” is a unique numerical sequence representing the pre-programmed configuration. Figure 3.1. Ordering Part Number Fields 5 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • December 4, 2021 5 Table of Contents 1. Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2. Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4. Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.1 Frequency Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.2 DSPLL Loop Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.3 Fastlock Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.4 Modes of Operation . . . . . 4.4.1 Initialization and Reset . . . 4.4.2 Free-run Mode . . . . . 4.4.3 Lock Acquisition Mode . . . 4.4.4 Locked Mode . . . . . . 4.4.5 Holdover Mode . . . . . 4.4.6 Frequency-on-the-Fly (FOTF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 . 9 . 9 .10 .10 .10 .10 4.5 Digitally-Controlled Oscillator (DCO) Mode . . . . . . . . . . . . . . . . . . . .11 4.6 External Reference (Grade A/B/C/D Only) . . . . . . . . . . . . . . . . . . . . .11 4.7 Inputs (IN0, IN1, IN2, IN3) . . . . . . 4.7.1 Input Selection . . . . . . . . 4.7.2 Manual Input Selection . . . . . . 4.7.3 Automatic Input Selection . . . . . 4.7.4 Hitless Input Switching . . . . . . 4.7.5 Frequency Ramped Input Switching . 4.7.6 Glitchless Input Switching . . . . . 4.7.7 Typical Hitless Switching Scenarios . 4.7.8 Synchronizing to Gapped Input Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 .12 .12 .12 .12 .12 .12 .13 .14 4.8 Fault Monitoring . . . 4.8.1 Input LOS Detection. 4.8.2 XA/XB LOS Detection 4.8.3 OOF Detection . . 4.8.4 LOL Detection . . . 4.8.5 Interrupt Pin (INTRb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 .15 .15 .16 .17 .18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 .18 .18 .18 .18 .18 .18 .19 .19 .19 .19 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • December 4, 2021 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.9 Outputs . . . . . . . . . . . . . . . . . . . . 4.9.1 Output Crosspoint . . . . . . . . . . . . . . . 4.9.2 Output Signal Format . . . . . . . . . . . . . . 4.9.3 Programmable Common Mode Voltage For Differential Outputs 4.9.4 LVCMOS Output Impedance Selection . . . . . . . . 4.9.5 LVCMOS Output Signal Swing . . . . . . . . . . . 4.9.6 LVCMOS Output Polarity . . . . . . . . . . . . . 4.9.7 Output Enable/Disable . . . . . . . . . . . . . . 4.9.8 Output Disable During LOL . . . . . . . . . . . . 4.9.9 Output Disable During XAXB_LOS . . . . . . . . . . 4.9.10 Output Driver State When Disabled . . . . . . . . . 6 4.9.11 Synchronous/Asynchronous Output Disable . 4.9.12 Output Divider (R) Synchronization . . . . 4.10 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 .19 . . . . . . . . . . . . . . . . . . . . . . . . . . .19 4.11 In-Circuit Programming . . . . . . . . . . . . . . . . . . . . . . . . . . .19 4.12 Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . .19 4.13 Custom Factory Preprogrammed Parts . . . . . . . . . . . . . . . . . . . . .20 4.14 Register Map . . . . . . . . . . . . . . . . . . . . .20 5. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . 38 7. Detailed Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8. Typical Operating Characteristics (Jitter and Phase Noise) . . . . . . . . . . . . . 41 9. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 10. Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 . . . . . . . . . . . . 10.1 Si5397 A/B/C/D and Si5396C/D (External Reference) 9x9 mm 64-QFN Package Diagram . . . .50 10.2 Si5397 J/K/L/M and Si5396L/M (Internal Reference) 9x9 mm 64-LGA Package Diagram . . . .51 10.3 Si5396 A/B (External Reference) 7x7 mm 44-QFN Package Diagram . . . . . . . . . . .52 10.4 Si5396 J/K (Internal Reference) 7x7 mm 44-LGA Package Diagram . . . . . . . . . .53 11. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 12. Top Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 13. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • December 4, 2021 7 7 . Si5397/96 Data Sheet • Functional Description 4. Functional Description The Si5397/96 multi-PLL Jitter attenuators take advantage of Skyworks’ 4th generation DSPLL technology to offer the industry’s most integrated and flexible jitter attenuating clock generator solution. Each of the DSPLLs operate independently from each other and are controlled through a common serial interface. Each DSPLL has access to any of the four inputs (IN0 to IN3) with manual or automatic input selection. The Si5397 has 4-DSPLLs and has either 4 or 8 outputs while the Si5396 has 2-DSPLLs and comes with either 4 or 12 outputs. Any of the output clocks can be configured to any of the DSPLLs using a flexible crosspoint connection. 4.1 Frequency Configuration The frequency configuration for each of the DSPLLs is programmable through the serial interface and can also be stored in non-volatile memory. The combination of fractional input dividers (Pn/Pd), fractional frequency multiplication (Mn/Md), and integer output division (Rn) allows each of the DSPLLs to lock to any input frequency and generate virtually any output frequency. All divider values for a specific frequency plan are easily determined using the ClockBuilder Pro utility. 4.2 DSPLL Loop Bandwidth The DSPLL loop bandwidth determines the amount of input clock jitter attenuation. Register-configurable DSPLL loop bandwidth settings in the range of 0.1 Hz to 4 kHz are available for selection for each of the DSPLLs. Since the loop bandwidth is controlled digitally, each of the DSPLLs will always remain stable with less than 0.1 dB of peaking regardless of the loop bandwidth selection. 4.3 Fastlock Feature Selecting a low DSPLL loop bandwidth (e.g. 0.1 Hz) will generally lengthen the lock acquisition time. The fastlock feature allows setting a temporary Fastlock Loop Bandwidth that is used during the lock acquisition process. Higher fastlock loop bandwidth settings will enable the DSPLLs to lock faster. Fastlock Loop Bandwidth settings in the range of 100 Hz to 4 kHz are available for selection. The DSPLL will revert to its normal loop bandwidth once lock acquisition has completed. 8 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • December 4, 2021 8 Si5397/96 Data Sheet • Functional Description 4.4 Modes of Operation Once initialization is complete, each of the DSPLLs operates independently in one of four modes: Free-run Mode, Lock Acquisition Mode, Locked Mode, or Holdover Mode. A state diagram showing the modes of operation is shown in the figure below. The following sections describe each of these modes in greater detail. Power-Up Reset and Initialization No valid input clocks selected Free-run Valid input clock selected Lock Acquisition (Fast Lock) An input is qualified and available for selection No valid input clocks available for selection Phase lock on selected input clock is achieved Locked Mode Holdover Mode Input Clock Switch Selected input clock fails Yes Yes No Holdover History Valid? Other Valid Clock Inputs No Available? Figure 4.1. Modes of Operation 4.4.1 Initialization and Reset Once power is applied, the device begins an initialization period where it downloads default register values and configuration data from NVM and performs other initialization tasks. Communicating with the device through the serial interface is possible once this initialization period is complete. No clocks will be generated until the initialization is complete. Clocks that feature the integrated crystal may require a slightly longer settling time compared to the external crystal device. See the Reference Manual for more details. There are two types of resets available. A hard reset is functionally similar to a device power-up. All registers will be restored to the values stored in NVM, and all circuits including the serial interface will be restored to their initial state. A hard reset is initiated using the RSTb pin or by asserting the hard reset register bit. A soft reset bypasses the NVM download. It is simply used to initiate register configuration changes. 4.4.2 Free-run Mode All four DSPLLs will automatically enter freerun mode once power is applied to the device and initialization is complete. The frequency accuracy of the generated output clocks in Free-run Mode is entirely dependent on the frequency accuracy of the external crystal or reference clock on the XA/XB pins. For example, if the crystal frequency is ±100 ppm, then all the output clocks will be generated at their configured frequency ±100 ppm in Free-run Mode. Any drift of the crystal frequency will be tracked at the output clock frequencies. A TCXO or OCXO is recommended for applications that need better frequency accuracy and stability while in Free-run Mode or Holdover Mode. 9 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • December 4, 2021 9 Si5397/96 Data Sheet • Functional Description 4.4.3 Lock Acquisition Mode Each of the DSPLLs independently monitors its configured inputs for a valid clock. If at least one valid clock is available for synchronization, a DSPLL will automatically start the lock acquisition process. If the fast lock feature is enabled, a DSPLL will acquire lock using the Fastlock Loop Bandwidth setting and then transition to the DSPLL Loop Bandwidth setting when lock acquisition is complete. During lock acquisition the outputs will generate a clock that follows the VCO frequency change as it pulls-in to the input clock frequency. 4.4.4 Locked Mode Once locked, a DSPLL will generate output clocks that are both frequency and phase locked to their selected input clocks. At this point, any XTAL frequency drift will not affect the output frequency. Each DSPLL has its own LOLb pin and status bit to indicate when lock is achieved. See 4.8.4 LOL Detection for more details on the operation of the loss of lock circuit. 4.4.5 Holdover Mode Any of the DSPLLs will automatically enter Holdover Mode when the selected input clock becomes invalid and no other valid input clocks are available for selection. Each DSPLL uses an averaged input clock frequency as its final holdover frequency to minimize the disturbance of the output clock phase and frequency when an input clock suddenly fails. The holdover circuit for each DSPLL stores up to 120 seconds of historical frequency data while locked to a valid clock input. The final averaged holdover frequency value is calculated from a programmable window within the stored historical frequency data. Both the window size and delay are programmable, as shown in the figure below. The window size determines the amount of holdover frequency averaging. The delay value allows ignoring frequency data that may be corrupt just before the input clock failure. Clock Failure and Entry into Holdover Historical Frequency Data Collected time 120 seconds Programmable historical data window used to determine the final holdover value Programmable delay Figure 4.2. Programmable Holdover Window When entering Holdover Mode, a DSPLL will pull its output clock frequency to the calculated averaged holdover frequency. While in Holdover Mode, the output frequency drift is entirely dependent on the external crystal or external reference clock connected to the XA/XB pins. If the clock input becomes valid, a DSPLL will automatically exit the Holdover Mode and reacquire lock to the new input clock. This process involves pulling the output clock frequencies to achieve frequency and phase lock with the input clock. This pull-in process is glitchless, and its rate is controlled by the DSPLL bandwidth or the fastlock bandwidth. These options are register programmable. The DSPLL output frequency when exiting holdover can be ramped (recommended). Just before the exit is initiated, the difference between the current holdover frequency and the new desired frequency is measured. Using the calculated difference and a user-selectable ramp rate, the output is linearly ramped to the new frequency. The ramp rate can be 0.2 ppm/s, 40,000 ppm/s, or any of about 40 values in between. The DSPLL loop BW does not limit or affect ramp rate selections (and vice versa). CBPro defaults to ramped exit from holdover. The same ramp rate settings are used for both exit from holdover and ramped input switching. For more information on ramped input switching, see 4.7.5 Frequency Ramped Input Switching. Note: If ramped holdover exit is not selected, the holdover exit is governed either by (1) the DSPLL loop BW or (2) a user-selectable holdover exit BW. 4.4.6 Frequency-on-the-Fly (FOTF) The Si5397/96 uses register writes to support configuration on the fly to allow certain characteristics to be changed on one DSPLL without affecting the clocks generated from other DSPLLs. These characteristics include Input/Output Frequencies, PLL bandwidth, LOL, and OOF settings. See the Si5397/96 Family Reference Manual and AN1178: Frequency-On-the-Fly for Skyworks Jitter Attenuators and Clock Generators for more details. 10 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • December 4, 2021 10 Si5397/96 Data Sheet • Functional Description 4.5 Digitally-Controlled Oscillator (DCO) Mode The DSPLLs support a DCO mode where their output frequencies are adjustable in predefined steps defined by frequency step words (FSW).The frequency adjustments are controlled through the serial interface or by pin control using frequency increment (FINC) or decrement (FDEC). A FINC will add the frequency step word to the DSPLL output frequency, while a FDEC will decrement it. 4.6 External Reference (Grade A/B/C/D Only) An external crystal (XTAL) is used in combination with the internal oscillator (OSC) to produce an ultra-low jitter reference clock for the DSPLLs and for providing a stable reference for the Free-run and Holdover Modes. A simplified diagram is shown in the figure below. The device includes internal XTAL loading capacitors, which eliminates the need for external capacitors and also has the benefit of reduced noise coupling from external sources. Refer to Table 5.12 External Crystal Specifications for Grades A/B/C/D1 on page 35 for crystal specifications. A crystal in the range of 48 MHz to 54 MHz is recommended for best jitter performance. The Si5397/96 Family Reference Manual provides additional information on PCB layout recommendations for the crystal to ensure optimum jitter performance. To achieve optimal jitter performance and minimize BOM cost, a crystal is recommended on the XA/XB reference input. For SyncE line card PLL applications (e.g. loop bandwidth set to 0.1 Hz), a TCXO is required on the XA/XB reference to minimize wander and to provide a stable holdover reference. See the Si5397/96 Family Reference Manual for more information. Selection between the external XTAL or REFCLK is controlled by register configuration. The internal crystal loading capacitors (CL) are disabled in the REFCLK mode. Refer to Table 5.3 Input Clock Specifications on page 24 for REFCLK requirements when using this mode. The Si5397/96 Family Reference Manual provides additional information on PCB layout recommendations for the crystal to ensure optimum jitter performance. A PREF divider is available to accommodate external clock frequencies higher than 54 MHz. Although the REFCLK frequency range of 25 MHz to 54 MHz is supported, frequencies in the range of 48 MHz to 54 MHz will achieve the best output jitter performance. 25-54 MHz XO/Clock LVCMOS 25-54 MHz XO/Clock C1 is recommended to increase the slew rate at Xa 25-54 MHz XTAL X2 XB XA 2xCL C1 R1 See the Reference Manual for the recommended R1, R2, C1 values R2 Note: See Pin Descriptions for X1/X2 connections nc X1 XB 2xCL 2xCL OSC nc X1 XA 2xCL OSC ÷ PXAXB Crystal Resonator Connection nc XB X2 2xCL nc X1 XA X2 2xCL OSC ÷ PXAXB Differential XO/Clock Connection ÷ PXAXB LVCMOS XO/Clock Connection Note: XA and XB must not exceed the maximum input voltage listed in Table 5.3 Input Clock Specifications on page 24 Figure 4.3. Crystal Resonator and External Reference Clock Connection Options Note: Connecting an external reference to a device that already has an integrated reference (grades J/K/L/M) is not allowed. Doing so could lead to internal damage to the circuits. 11 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • December 4, 2021 11 Si5397/96 Data Sheet • Functional Description 4.7 Inputs (IN0, IN1, IN2, IN3) The Si5397 has four inputs that can be synchronized with four DSPLLs. The Si5396 has four inputs that can be synchronized with two DSPLLs. The inputs accept both differential and single-ended clocks. A crosspoint between the inputs and the DSPLLs allows any of the inputs to connect to any of the DSPLLs. 4.7.1 Input Selection Input selection for each of the DSPLLs can be made manually through register control or automatically using an internal state machine. 4.7.2 Manual Input Selection In Manual Mode, the input selection is made by writing to a register. If there is no clock signal on the selected input, the DSPLL will automatically enter Holdover Mode. 4.7.3 Automatic Input Selection When configured in this mode, the DSPLL automatically selects a valid input that has the highest configured priority. The priority scheme is independently configurable for each DSPLL and supports revertive or non-revertive selection. All inputs are continuously monitored for loss of signal (LOS) and/or invalid frequency range (OOF). Only inputs that do not assert both the LOS and OOF monitors can be selected for synchronization by the automatic state machine. The DSPLL(s) will enter the Holdover mode if there are no valid inputs available. 4.7.4 Hitless Input Switching Hitless switching is a feature that prevents a phase offset from propagating to the output when switching between two clock inputs that have a fixed phase relationship. A hitless switch can only occur when the two input frequencies are frequency locked, meaning that they have to be exactly at the same frequency, or at an integer frequency relationship to each other. When hitless switching is enabled, the DSPLL simply absorbs the phase difference between the two input clocks during an input switch. When disabled, the phase difference between the two inputs is propagated to the output at a rate determined by the DSPLL Loop Bandwidth. The hitless switching feature supports clock frequencies down to the minimum input frequency of 8 kHz; however, for optimum hitless switching performance, higher input frequencies are recommended. Hitless switching can be enabled on a per DSPLL basis. 4.7.5 Frequency Ramped Input Switching The ramped input switching feature is enabled/disabled depending on both the frequency of the Phase-Frequency detector (Fpfd) and the difference in input frequencies (Zero-PPM vs non-zero PPM). The table below shows the selection criteria to enable ramped input switching. The same ramp rate settings are used for both holdover exit and clock switching. For more information on ramped exit from holdover, see 4.4.5 Holdover Mode and the Si5397/96 Family Reference Manual. Table 4.1. Recommended Ramped Input Switching Settings for Internal Clock Switches Maximum Input Frequency Difference 0 ppm Frequency Locked ≤ 10 ppm > 10 ppm Fpfd < 500 kHz Fpfd ≥ 500 kHz Ramped Exit from Holdover Ramped Input Switching and Ramped Exit from Holdover Ramped Exit from Holdover Ramped Input Switching and Ramped Exit from Holdover Note: 1. The Fpfd value is determined by various requirements of the frequency plan and is displayed in the CBPro project file. Always enable hitless switching and enable phase buildout on holdover exit. In CBPro these selections are in Step 14 of 18 DSPLL configure. 4.7.6 Glitchless Input Switching The DSPLLs have the ability of switching between two input clock frequencies that are up to ±500 ppm apart. The DSPLL will pull-in to the new frequency using the DSPLL Loop Bandwidth or using the Fastlock Loop Bandwidth if it is enabled. The loss of lock (LOL) indicator will assert while the DSPLL is pulling-in to the new clock frequency. There will be no output runt pulses generated at the output during the transition. 12 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • December 4, 2021 12 Si5397/96 Data Sheet • Functional Description 4.7.7 Typical Hitless Switching Scenarios Figure 4.4. Output Frequency Transient—Ramped Switching between Two 8 kHz Inputs (±4.6 ppm Offset) Figure 4.5. Output Phase Transient—Hitless Switching between Two 25 MHz Inputs (0 ppm, 180 Degree Phase Shift) 13 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • December 4, 2021 13 Si5397/96 Data Sheet • Functional Description 4.7.8 Synchronizing to Gapped Input Clocks Each of the DSPLLs support locking to an input clock that has missing periods. This is also referred to as a gapped clock. The purpose of gapped clocking is to modulate the frequency of a periodic clock by selectively removing some of its cycles. Gapping a clock severely increases its jitter, so a phase-locked loop with high jitter tolerance and low loop bandwidth is required to produce a low-jitter periodic clock. The resulting output will be a periodic non-gapped clock with an average frequency of the input with its missing cycles. For example, an input clock of 100 MHz with one cycle removed every 10 cycles will result in a 90 MHz periodic non-gapped output clock. This is shown in the figure below. Gapped Input Clock Periodic Output Clock 100 MHz clock 1 missing period every 10 90 MHz non-gapped clock 100 ns 100 ns DSPLL 1 2 10 ns 3 4 5 6 7 8 9 Period Removed 10 1 2 3 4 5 6 7 8 9 11.11111... ns Figure 4.6. Generating an Averaged Clock Output Frequency from a Gapped Clock Input A valid gapped clock input must have a minimum frequency of 10 MHz with a maximum of two missing cycles out of every 8. Locking to a gapped clock will not trigger the LOS, OOF, and LOL fault monitors. Clock switching between gapped clocks may violate the hitless switching specification in Table 5.8 Performance Characteristics on page 31 when the switch occurs during a gap in either input clock. 14 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • December 4, 2021 14 Si5397/96 Data Sheet • Functional Description 4.8 Fault Monitoring All four input clocks (IN0, IN1, IN2, IN3) are monitored for LOS and OOF, as shown in the figure below. The reference at the XA/XB pins is also monitored for LOS since it provides a critical reference clock for the DSPLLs. Each of the DSPLLs also has an LOL indicator, which is asserted when synchronization is lost with their selected input clock. XA XB Si5397 OSC LOS DSPLL A LOL PD VCO LPF NA MA IN0 IN0b IN1 IN1b IN2 IN2b ÷ P0n P0d LOS ÷ P1n P1d LOS ÷ P2n P2d LOS OOF OOF OOF Precision Fast DSPLL B LOL VCO PD Precision Fast LPF MB Precision Fast DSPLL C LOL VCO PD IN3 IN3b ÷ P3n P3d LOS OOF NB Precision Fast LPF NC MC DSPLL D LOL VCO PD LPF ND MD Figure 4.7. Si5397 Fault Monitors 4.8.1 Input LOS Detection The loss of signal monitor measures the period of each input clock cycle to detect phase irregularities or missing clock edges. Each of the input LOS circuits has its own programmable sensitivity which allows ignoring missing edges or intermittent errors. Loss of signal sensitivity is configurable using the ClockBuilder Pro utility. The LOS status for each of the monitors is accessible by reading a status register. The live LOS register always displays the current LOS state and a sticky register always stays asserted until cleared. An option to disable any of the LOS monitors is also available. Monitor Sticky LOS LOS LOS en Live Figure 4.8. LOS Status Indicators 4.8.2 XA/XB LOS Detection A LOS monitor is available to ensure that the external crystal or reference clock is valid. By default the output clocks are disabled when XAXB_LOS is detected. This feature can be disabled such that the device will continue to produce output clocks when XAXB_LOS is detected. 15 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • December 4, 2021 15 Si5397/96 Data Sheet • Functional Description 4.8.3 OOF Detection Each input clock is monitored for frequency accuracy with respect to an OOF reference, which it considers as its “0_ppm” reference. This OOF reference can be selected as either: • XA/XB pins • Any input clock (IN0, IN1, IN2, IN3) The final OOF status is determined by the combination of both a precise OOF monitor and a fast OOF monitor, as shown in the figure below. An option to disable either monitor is also available. The live OOF register always displays the current OOF state and its sticky register bit stays asserted until cleared. Monitor Sticky en Precision OOF LOS OOF Fast Live en Figure 4.9. OOF Status Indicator 4.8.3.1 Precision OOF Monitor The precision OOF monitor circuit measures the frequency of all input clocks to within 1/16 ppm accuracy with respect to the selected OOF frequency reference. A valid input clock frequency is one that remains within the OOF frequency range, which is register configurable up to ±512 ppm in steps of 1/16 ppm. A configurable amount of hysteresis is also available to prevent the OOF status from toggling at the failure boundary. An example is shown in the figure below. In this case, the OOF monitor is configured with a valid frequency range of ±6 ppm and with 2 ppm of hysteresis. An option to use one of the input pins (IN0 – IN3) as the 0 ppm OOF reference instead of the XA/XB pins is available. This option is register-configurable. OOF Declared fIN Hysteresis Hysteresis OOF Cleared -6 ppm (Set) -4 ppm (Clear) 0 ppm OOF Reference +4 ppm (Clear) +6 ppm (Set) Figure 4.10. Example of Precise OOF Monitor Assertion and De-assertion Triggers 4.8.3.2 Fast OOF Monitor Because the precision OOF monitor needs to provide 1/16 ppm of frequency measurement accuracy, it must measure the monitored input clock frequencies over a relatively long period of time. This may be too slow to detect an input clock that is quickly ramping in frequency. An additional level of OOF monitoring called the Fast OOF monitor runs in parallel with the precision OOF monitors to quickly detect a ramping input frequency. The Fast OOF monitor asserts OOF on an input clock frequency that has changed by greater than ±4000 ppm. 16 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • December 4, 2021 16 Si5397/96 Data Sheet • Functional Description 4.8.4 LOL Detection There is an LOL monitor for each of the DSPLLs. The LOL monitor asserts an LOL register bit when a DSPLL has lost synchronization with its selected input clock. There is also a dedicated loss of lock pin that reflects the loss of lock condition for each of the DSPLLs (LOL_Ab, LOL_Bb, LOL_Cb, LOL_Db). The LOL monitor functions by measuring the frequency difference between the input and feedback clocks at the phase detector. There are two LOL frequency monitors, one that sets the LOL indicator (LOL Set) and another that clears the indicator (LOL Clear). An optional timer is available to delay clearing of the LOL indicator to allow additional time for the DSPLL to completely lock to the input clock. The timer is also useful to prevent the LOL indicator from toggling or chattering as the DSPLL completes lock acquisition. A block diagram of the LOL monitor is shown in the figure below. The live LOL register always displays the current LOL state and a sticky register always stays asserted until cleared. The LOLb pin reflects the current state of the LOL monitor. LOL Monitor LOL Clear Sticky Timer LOS LOL LOL Set Live LOLb VCO fIN PD Feedback Clock DSPLL LPF NA/B/C/D MA/B/C/D Si5397/96 Figure 4.11. LOL Status Indicators Each of the LOL frequency monitors has adjustable sensitivity, which is register-configurable from 0.1 ppm to 10,000 ppm. Having two separate frequency monitors allows for hysteresis to help prevent chattering of LOL status. An example configuration where LOCK is indicated when there is less than 0.1 ppm frequency difference at the inputs of the phase detector and LOL is indicated when there is more than 1 ppm frequency difference is shown in the figure below. Clear LOL Threshold Set LOL Threshold Lock Acquisition LOL Hysteresis Lost Lock LOCKED 0 0.1 1 10,000 Phase Detector Frequency Difference (ppm) Figure 4.12. LOL Set and Clear Thresholds An optional timer is available to delay clearing of the LOL indicator to allow additional time for the DSPLL to completely lock to the input clock. The timer is also useful to prevent the LOL indicator from toggling or chattering as the DSPLL completes lock acquisition. The configurable delay value depends on frequency configuration and loop bandwidth of the DSPLL and is automatically calculated using the ClockBuilderPro utility. 17 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • December 4, 2021 17 Si5397/96 Data Sheet • Functional Description 4.8.5 Interrupt Pin (INTRb) An interrupt pin (INTRb) indicates a change in state of the status indicators (LOS, OOF, LOL, HOLD). Any of the status indicators are maskable to prevent assertion of the interrupt pin. The state of the INTRb pin is reset by clearing the status register that caused the interrupt. 4.9 Outputs The Si5397 supports up to eight differential output drivers and the Si5396 supports up to 12 outputs. Each driver has a configurable voltage amplitude and common mode voltage covering a wide variety of differential signal formats including LVPECL, LVDS, HCSL, and CML. In addition to supporting differential signals, any of the outputs can be configured as single-ended LVCMOS (3.3 V, 2.5 V, or 1.8 V) providing up to 24 single-ended outputs, or any combination of differential and single-ended outputs. 4.9.1 Output Crosspoint A crosspoint allows any of the output drivers to connect with any of the DSPLLs, as shown in the figure below. The crosspoint configuration is programmable and can be stored in NVM so that the desired output configuration is ready at power-up. 4.9.2 Output Signal Format The differential output amplitude and common mode voltage are both fully programmable and compatible with a wide variety of signal formats, including LVDS and LVPECL. In addition to supporting differential signals, any of the outputs can be configured as LVCMOS (3.3 V, 2.5 V, or 1.8 V) drivers providing up to 24 single-ended outputs or any combination of differential and single-ended outputs. 4.9.3 Programmable Common Mode Voltage For Differential Outputs The common mode voltage (VCM) for the differential modes is programmable and depends on the voltage available at the output’s VDDO pin. Setting the common mode voltage is useful when dc-coupling the output drivers. 4.9.4 LVCMOS Output Impedance Selection Each LVCMOS driver has a configurable output impedance to accommodate different trace impedances and drive strengths. A source termination resistor is recommended to help match the selected output impedance to the trace impedance. There are three programmable output impedance selections for each VDDO option, as shown in the table below. Note that selecting a lower source impedance may result in higher output power consumption. Table 4.2. Typical Output Impedance (ZS) VDDO CMOS_DRIVE_Selection OUTx_CMOS_DRV = 1 OUTx_CMOS_DRV = 2 OUTx_CMOS_DRV = 3 3.3 V 38 Ω 30 Ω 22 Ω 2.5 V 43 Ω 35 Ω 24 Ω 1.8 V — 46 Ω 31 Ω 4.9.5 LVCMOS Output Signal Swing The signal swing (VOL/VOH) of the LVCMOS output drivers is set by the voltage on the VDDO pins. Each output driver has its own VDDO pin allowing a unique output voltage swing for each of the LVCMOS drivers. 4.9.6 LVCMOS Output Polarity When a driver is configured as an LVCMOS output, it generates a clock signal on both pins (OUTx and OUTxb). By default the clock on the OUTxb pin is generated with the same polarity (in phase) with the clock on the OUTx pin. The polarity of these clocks is configurable, which enables complementary clock generation and/or inverted polarity with respect to other output drivers. 18 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • December 4, 2021 18 Si5397/96 Data Sheet • Functional Description 4.9.7 Output Enable/Disable The Si5397/96 allows enabling/disabling outputs by pin or register control, or a combination of both. Two output enable pins are available (OE0b, OE1b). The output enable pins can be mapped to any of the outputs (OUTx) through register configuration. By default OE0b controls all of the outputs while OE1b remains unmapped and has no effect until configured. The figure below shows an example of an output enable mapping scheme that is register configurable and can be stored in NVM as the default at power-up. Enabling and disabling outputs can also be controlled by register control. This allows disabling one or more output when the OEb pin(s) has them enabled. By default the output enable register settings are configured to allow the OEb pins to have full control. 4.9.8 Output Disable During LOL By default a DSPLL that is out of lock will generate either free-running clocks or generate clocks in holdover mode. There is an option to disable the outputs when a DSPLL is LOL. This option can be useful to force a downstream PLL into holdover. 4.9.9 Output Disable During XAXB_LOS The internal oscillator circuit (OSC) in combination with the external crystal (XTAL) provides a critical function for the operation of the DSPLLs. In the event of a crystal failure the device will assert an XAXB_LOS alarm. By default all outputs will be disabled during assertion of the XAXB_LOS alarm. There is an option to leave the outputs enabled during an XAXB_LOS alarm, but the frequency accuracy and stability will be indeterminate during this fault condition. 4.9.10 Output Driver State When Disabled The disabled state of an output driver is register configurable as disable low or disable high. 4.9.11 Synchronous/Asynchronous Output Disable Outputs can be configured to disable synchronously or asynchronously. In synchronous disable mode the output will wait until a clock period has completed before the driver is disabled. This prevents unwanted runt pulses from occurring when disabling an output. In asynchronous disable mode, the output clock will disable immediately without waiting for the period to complete. 4.9.12 Output Divider (R) Synchronization All the output R dividers are reset to a known state during the power-up initialization period. This ensures consistent and repeatable phase alignment across all output drivers. Resetting the device using the RSTb pin or asserting the hard reset bit will have the same result. 4.10 Power Management Unused inputs, output drivers, and DSPLLs can be powered down when unused. Consult the Si5397/96 Family Reference Manual and ClockBuilder Pro configuration utility for details. 4.11 In-Circuit Programming The Si5397/96 is fully configurable using the serial interface (I2C or SPI). At power-up the device downloads its default register values from internal non-volatile memory (NVM). Application specific default configurations can be written into NVM allowing the device to generate specific clock frequencies at power-up. Writing default values to NVM is in-circuit programmable with normal operating power supply voltages applied to its VDD and VDDA pins. The NVM is two time writable. Once a new configuration has been written to NVM, the old configuration is no longer accessible. Refer to the Si5397/96 Family Reference Manual for a detailed procedure for writing registers to NVM. 4.12 Serial Interface Configuration and operation of the Si5397/96 is controlled by reading and writing registers using the I2C or SPI interface. The I2C_SEL pin selects I2C or SPI operation. Communication with both 3.3 V and 1.8 V host is supported. The SPI mode operates in either 4-wire or 3-wire mode. See the Si5397/96 Family Reference Manual for details. 19 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • December 4, 2021 19 Si5397/96 Data Sheet • Functional Description 4.13 Custom Factory Preprogrammed Parts For applications where a serial interface is not available for programming the device, custom pre-programmed parts can be ordered with a specific configuration written into NVM. A factory pre-programmed part will generate clocks at power-up. Custom, factory-preprogrammed devices are available. Use the ClockBuilder Pro custom part number wizard (https://www.skyworksinc.com/en/applicationpages/clockbuilder-pro-software) to quickly and easily request and generate a custom part number for your configuration. In less than three minutes, you will be able to generate a custom part number with a detailed data sheet addendum matching your design’s configuration. Once you receive the confirmation email with the data sheet addendum, simply place an order with your local Skyworks sales representative. Samples of your pre-programmed device will typically ship in about two weeks. 4.14 Register Map The register map is divided into multiple pages where each page has 256 addressable registers. Page 0 contains frequently accessible registers, such as alarm status, resets, device identification, etc. Other pages contain registers that need less frequent access, such as frequency configuration and general device settings. Refer to the Si5397/96 Family Reference Manual for a complete list of register descriptions and settings. It is strongly recommended that ClockBuilder Pro be used to create and manage register settings. 20 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • December 4, 2021 20 Si5397/96 Data Sheet • Electrical Specifications 5. Electrical Specifications Table 5.1. Recommended Operating Conditions Parameter Symbol Min Typ Max Unit Ambient Temperature TA –40 25 85 °C Junction Temperature TJM1AX — — 125 °C VDD 1.71 1.80 1.89 V VDDA 3.14 3.30 3.47 V 3.14 3.30 3.47 V 2.37 2.50 2.62 V 1.71 1.80 1.89 V 3.14 3.30 3.47 V 1.71 1.80 1.89 V Core Supply Voltage Output Driver Supply Voltage Status Pin Supply Voltage VDDO VDDS Note: 1. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted. 21 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • December 4, 2021 21 Si5397/96 Data Sheet • Electrical Specifications Table 5.2. DC Characteristics (VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, VDDIO/VDDS = 3.3 V ±5%, 1.8 V ±5%, VDDO = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA = –40 to 85 °C) Parameter Symbol IDD Core Supply Current1, 2, 4 IDDA Output Buffer Supply Current Total Power Dissipation6 22 IDDO Pd Test Condition Min Typ Max Unit Si5397, 4 DSPLLs — 320 520 mA S5397, 1 DSPLL — 200 360 mA Si5396, 2 DSPLLs — 180 290 mA Si5397, 4 DSPLLs — 155 195 mA Si5397, 1 DSPLL — 125 140 mA Si5396, 2 DSPLLs — 120 150 mA 2.5 V LVPECL Output4 — 22 26 mA 2.5 V LVDS Output4 — 15 18 mA 3.3 V LVCMOS Output5 — 22 30 mA 2.5 V LVCMOS Output5 — 18 23 mA 1.8 V LVCMOS Output5 — 12 16 mA Si5397, 4 DSPLLs1 — 1400 1950 mW Si5397, 2 DSPLLs1 — 1100 1550 mW Si5396 A/B/J/K, 2 DSPLLs2 — 870 1200 mW Si5396 C/D/L/M, 2 DSPLLs3 — 1100 1850 mW Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • December 4, 2021 22 Si5397/96 Data Sheet • Electrical Specifications Parameter Symbol Test Condition Min Typ Max Unit Notes: 1. Si5397 test configuration: 7×2.5 V LVDS outputs enabled @156.25 MHz. Excludes power in termination resistors. 2. Si5396A/B/J/K test configuration: 4×2.5 V LVDS outputs enabled @ 156.25 MHz. Excludes power in termination resistors. 3. Si5396C/D/L/M test configuration: 12 x 2.5 V LVPECL outputs enabled @ 156.25 MHz. Excludes power in termination resistors. 4. Differential outputs terminated into an ac-coupled 100 Ω load. Differential Output Test Configuration IDDO 0.1 µF 50 OUT 100 OUTb 50 0.1 µF 5. LVCMOS outputs measured into a 5-inch 50 Ω PCB trace with 5 pF load. The LVCMOS outputs were set to OUTx_CMOS_DRV = 3, which is the strongest driver setting. Refer to the Si5397/96 Family Reference Manual for more details on register settings. LVCMOS Output Test Configuration Trace length 5 inches 499 50 Scope Input 50 IDDO OUTx 4.7pF 56 OUTxb 499 50 Scope Input 50 4.7pF 56 6. Detailed power consumption for any configuration can be estimated using ClockBuilder Pro when an evaluation board (EVB) is not available. All EVBs support detailed current measurements for any configuration. 23 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • December 4, 2021 23 Si5397/96 Data Sheet • Electrical Specifications Table 5.3. Input Clock Specifications VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, TA = –40 to 85 °C Parameter Symbol Test Condition Min Typ Max Unit Standard Differential or Single-Ended - AC Coupled Input Buffer (IN0/IN0b, IN1/IN1b, IN2/IN2b, IN3/IN3b) Input Frequency Range Voltage Swing1 fIN VIN Differential 0.008 — 750 MHz All Single-ended signals (including LVCMOS) 0.008 — 250 MHz Differential ac-coupled fIN < 250 MHz 100 — 1800 mVpp_se Differential ac-coupled 250 MHz < fIN < 750 MHz 225 — 1800 mVpp_se Single-ended ac-coupled fIN< 250 MHz 100 — 3600 mVpp_se Slew Rate2,3 SR 400 — — V/µs Duty Cycle DC 40 — 60 % Input Capacitance CIN — 2.4 — pF RIN_DIFF — 16 — kΩ RIN_SE — 8 — kΩ Standard CMOS & Non-standard CMOS 0.008 — 250 MHz Pulsed CMOS 0.008 — 1 MHz Standard CMOS — — 0.5 V Non-standard CMOS & Pulsed CMOS — — 0.4 V Standard CMOS 1.3 — — V Non-standard CMOS & Pulsed CMOS 0.8 — — V 400 — — V/µs Standard CMOS & Non-standard CMOS 40 — 60 Pulsed CMOS 5 Input Resistance Differential Input Resistance Single-ended LVCMOS / Pulsed CMOS DC-Coupled Input Buffer (IN0, IN1, IN2, IN3)4 Input Frequency fIN_CMOS VIL Input Voltage5 VIH Slew Rate2,3 SR Duty Cycle DC % 95 Standard CMOS & Non-standard CMOS Minimum Pulse Width PW 24 RIN — — (250 MHz @ 40% Duty Cycle) Pulsed CMOS (1 MHz @ 40% Duty Cycle) Input Resistance 1.6 ns 50 — — — 8 — kΩ Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • December 4, 2021 24 Si5397/96 Data Sheet • Electrical Specifications Parameter Symbol Test Condition Min Typ Max Unit fIN_REF Full operating range. Jitter performance may be reduced. 24.97 — 54.06 MHz Range for best jitter. 48 — 54 MHz VIN_DIFF 365 — 2500 mVpp_diff VIN_SE 365 — 2000 mVpp_se Slew rate2,3 SR 400 — — V/µs Input Duty Cycle DC 40 — 60 % REFCLK (Applied to XA/XB) REFCLK Frequency Input Voltage Swing Notes: 1. Voltage swing is specified as single-ended mVpp. OUTx Vcm Vpp_se Vcm Vpp_se Vpp_diff = 2*Vpp_se OUTxb 2. Recommended for specified jitter performance. Slew rate can go lower, but jitter performance could degrade if the minimum slew rate specification is not met (See the Si5397/96 Family Reference Manual). 3. Rise and fall times can be estimated using the following simplified equation: tr/tf80-20 = ((0.8 - 0.2) x VIN_Vpp_se) / SR. 4. Standard, Non-standard and Pulsed CMOS refer to different formats of CMOS each with a voltage swing of 1.8V, 2.5V or 3.3V +/-5%. • Standard CMOS refers to the industry standard LVCMOS signal. • Non-standard CMOS refers to a signal that has been attenuated/level-shifted in order to comply with the specified non-standard VIL and VIH specifications. • Pulsed CMOS refers to a signal that has been attenuated/level-shifted and has a low/high duty cycle and must be dc coupled. A typical application example is a low-frequency video frame sync pulse. Refer to the Si5397/96 Reference Manual for the recommended connections/termination for the different modes. 5. CMOS signals that exceed 3.3 V + 5% can be used as inputs as long as a resistive attenuation network is used to guarantee that the input voltage at the pin does not violate the device's input ratings. Please refer to the Si5397/96 Reference Manual for the recommended connections/termination for this mode. 25 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • December 4, 2021 25 Si5397/96 Data Sheet • Electrical Specifications Table 5.4. Serial and Control Input Pin Specifications VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, VDDIO/VDDS = 3.3 V ±5%, 1.8 V ±5%, TA = –40 to 85 °C Parameter Symbol Test Condition Min Typ Max Unit Si5397 Serial and Control Input Pins (I2C_SEL, RSTb, OE0b, A1/SDO, SCLK, A0/CSb, FINC, A0/CSb, SDA/SDIO, DSPLL_SEL[1:0]) VIL — — 0.3 x VDDIO1 V VIH 0.7 x VDDIO1 — — V Input Capacitance CIN — 2 — pF Input Resistance RL — 20 — kΩ Minimum Pulse Width PW RSTb, FINC 100 — — ns Update Rate FUR FINC — — 1 MHz VIL — — 0.3 x VDDS V VIH 0.7 x VDDS — — V Input Capacitance CIN — 2 — pF Minimum Pulse Width PW FDEC 100 — — ns Update Rate FUR FDEC — — 1 MHz Input Voltage Si5397 Control Input Pins (FDEC, OE1b) Input Voltage Si5396 Serial and Control Input Pins (I2C_SEL, RSTb, OE0b, OE1b, A1/SDO, SCLK, A0/CSb, SDA/SDIO) VIL — — 0.3 x VDDIO1 V VIH 0.7 x VDDIO1 — — V Input Capacitance CIN — 2 — pF Input Resistance RL — 20 — kΩ Minimum Pulse Width PW 100 — — ns Input Voltage RSTb Note: 1. VDDIO is determined by the IO_VDD_SEL bit. It is selectable as VDDA or VDD. 26 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • December 4, 2021 26 Si5397/96 Data Sheet • Electrical Specifications Table 5.5. Differential Clock Output Specifications (VDD = 1.8 V ±5%, VDDA = 3.3V ±5%, VDDO = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA = –40 to 85 °C) Parameter Symbol Output Frequency fOUT Duty Cycle DC Output Voltage Amplitude1 VOUT Test Condition Min Typ Max Unit 0.0001 — 720 MHz fOUT < 400 MHz 48 — 52 % 400 MHz < fOUT < 720 MHz 45 — 55 % VDDO = 3.3 V, 2.5 V, or 1.8 V LVDS 350 450 530 mVpp_se VDDO = 3.3 V, 2.5 V LVPECL 630 750 950 mVpp_se LVDS 1.10 1.20 1.30 V LVPECL 1.90 2.00 2.10 V VDDO = 2.5 V LVPECL, LVDS 1.10 1.20 1.30 V VDDO = 1.8 V sub-LVDS 0.80 0.90 1.00 V VDDO = 3.3 V Common Mode Voltage1,2 VCM Output-to-Output Skew (Same DSPLL,Different Outputs) TSKS fOUT = 720 MHz (LVDS differential) — 0 75 ps OUT-OUTb Skew (Same Output) TSK_OUT Measured from positive to negative output pins — 0 50 ps Rise and Fall Times tr/tf fOUT> 100 MHz (20% to 80%) — 100 200 ps Differential Output Impedance ZO — 100 — Ω 10 kHz sinusoidal noise — –101 — dBc 100 kHz sinusoidal noise — –96 — dBc 500 kHz sinusoidal noise — –99 — dBc 1 MHz sinusoidal noise — –97 — dBc Si5397 — –72 — dB Si5396 — –88 — dB Power Supply Noise Rejection2 Output-output Crosstalk3 27 PSRR XTALK Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • December 4, 2021 27 Si5397/96 Data Sheet • Electrical Specifications Parameter Symbol Test Condition Min Typ Max Unit Notes: 1. Output amplitude and common-mode settings are programmable through register settings and can be stored in NVM. Each output driver can be programmed independently. Note that the maximum LVDS single-ended amplitude can be up to 110 mV higher than the TIA/EIA-644 maximum. Refer to the Si5397/96 Reference Manual for more suggested output settings. Not all combinations of voltage amplitude and common mode voltages settings are possible. OUTx Vcm Vpp_se Vcm Vpp_se Vpp_diff = 2*Vpp_se OUTxb Differential Output Test Configuration IDDO OUT 50 0.1 µF 100 OUTb 50 0.1 µF 2. Measured for 156.25 MHz carrier frequency. 100 mVpp sinewave noise added to VDDO = 3.3 V and noise spur amplitude measured. 3. Measured across two adjacent outputs, both in LVDS mode, with the victim running at 155.52 MHz and the aggressor at 156.25 MHz. Refer to “AN862: Optimizing Si534x Jitter Performance in Next Generation Internet Infrastructure Systems” for guidance on crosstalk optimization. Note that all active outputs must be terminated when measuring crosstalk. 28 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • December 4, 2021 28 Si5397/96 Data Sheet • Electrical Specifications Table 5.6. LVCMOS Clock Output Specifications (VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, VDDO = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA = –40 to 85 °C) Parameter Symbol Output Frequency fOUT Duty Cycle DC Test Condition Min Typ Max Unit 0.0001 — 250 MHz fOUT