SI8232AD-B-ISR

Si823x 0 . 5 AND 4 . 0 A MP I S O D R I V E R S (2.5 AND 5 K V RMS ) Features       Two completely isolated drivers  60 ns propagation delay (max) in one package  Independent HS and LS inputs or Up to 5 kVRMS input-to-output PWM input versions isolation  Transient immunity >45 kV/µs Up to 1500 VDC peak driver-to Overlap protection and driver differential voltage programmable dead time HS/LS and dual driver versions  AEC-Q100 qualification Up to 8 MHz switching frequency  Wide operating range 0.5 A peak output (Si8230/1/2/7) –40 to +125 °C  RoHS-compliant packages 4.0 A peak output (Si8233/4/5/6/8) SOIC-16 wide body SOIC-16 High electromagnetic immunity narrow body LGA-14 Applications     Power delivery systems Motor control systems  Isolated dc-dc power supplies Lighting control systems Plasma displays  Solar and industrial inverters Safety Approval  UL 1577 recognized Up   to 5000 Vrms for 1 minute IEC 60747-5-5 (VDE 0884 Part 5) 60950-1 (reinforced insulation) CSA component notice 5A approval IEC 60950-1, 61010-1, 60601-1 (reinforced insulation) VDE certification conformity EN  CQC certification approval GB4943.1 Ordering Information: See page 39. Description The Si823x isolated driver family combines two independent, isolated drivers into a single package. The Si8230/1/3/4 are high-side/low-side drivers, and the Si8232/5/6/7/8 are dual drivers. Versions with peak output currents of 0.5 A (Si8230/1/2/7) and 4.0 A (Si8233/4/5/6/8) are available. All drivers operate with a maximum supply voltage of 24 V. The Si823x drivers utilize Silicon Labs' proprietary silicon isolation technology, which provides up to 5 kVRMS withstand voltage per UL1577 and fast 60 ns propagation times. Driver outputs can be grounded to the same or separate grounds or connected to a positive or negative voltage. The TTL level compatible inputs with >400 mV hysteresis are available in individual control input (Si8230/2/3/5/6/7/8) or PWM input (Si8231/4) configurations. High integration, low propagation delay, small installed size, flexibility, and cost-effectiveness make the Si823x family ideal for a wide range of isolated MOSFET/IGBT gate drive applications. Rev. 1.5 3/14 Copyright © 2014 by Silicon Laboratories Si823x Si823x 2 Rev. 1.5 Si823x TABLE O F C ONTENTS Section Page 1. Top-Level Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 2.1. Test Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1. Typical Operating Characteristics (0.5 Amp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.2. Typical Operating Characteristics (4.0 Amp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.3. Family Overview and Logic Operation During Startup . . . . . . . . . . . . . . . . . . . . . . . 21 3.4. Power Supply Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.5. Power Dissipation Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 3.6. Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.7. Undervoltage Lockout Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.8. Programmable Dead Time and Overlap Protection . . . . . . . . . . . . . . . . . . . . . . . . . 28 4. Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.1. High-Side/Low-Side Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.2. Dual Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.3. Dual Driver with Thermally Enhanced Package (Si8236) . . . . . . . . . . . . . . . . . . . . .31 5. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7. Package Outline: 16-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8. Land Pattern: 16-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9. Package Outline: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 10. Land Pattern: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 11. Package Outline: 14 LD LGA (5 x 5 mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 12. Land Pattern: 14 LD LGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 13. Package Outline: 14 LD LGA with Thermal Pad (5 x 5 mm) . . . . . . . . . . . . . . . . . . . . .50 14. Land Pattern: 14 LD LGA with Thermal Pad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 15. Top Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 15.1. Si823x Top Marking (16-Pin Wide Body SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 15.2. Top Marking Explanation (16-Pin Wide Body SOIC) . . . . . . . . . . . . . . . . . . . . . . . 52 15.3. Si823x Top Marking (16-Pin Narrow Body SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . . 53 15.4. Top Marking Explanation (16-Pin Narrow Body SOIC) . . . . . . . . . . . . . . . . . . . . . . 53 15.5. Si823x Top Marking (14 LD LGA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 15.6. Top Marking Explanation (14 LD LGA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Rev. 1.5 3 Si823x 1. Top-Level Block Diagrams VDDI VDDA ISOLATION VIA VOA UVLO GNDA DT CONTROL & OVERLAP PROTECTION DT VDDI VDDI VDDB ISOLATION VDDI UVLO VOB UVLO DISABLE GNDB VIB GNDI Si8230/3 Figure 1. Si8230/3 Two-Input High-Side/Low-Side Isolated Drivers VDDI VDDA ISOLATION PWM LPWM VOA UVLO GNDA DT CONTROL & OVERLAP PROTECTION DT VDDI VDDI VDDB ISOLATION VDDI UVLO VOB UVLO DISABLE GNDB LPWM GNDI Si8231/4 Figure 2. Si8231/4 Single-Input High-Side/Low-Side Isolated Drivers 4 Rev. 1.5 Si823x VDDI ISOLATION VDDA VIA VOA UVLO GNDA VDDI VDDI UVLO VDDI ISOLATION VDDB DISABLE VOB UVLO GNDB VIB GNDI Si8232/5/6/7/8 Figure 3. Si8232/5/6/7/8 Dual Isolated Drivers Rev. 1.5 5 Si823x 2. Electrical Specifications Table 1. Electrical Characteristics1 2.7 V < VDDI < 5.5 V, VDDA = VDDB = 12 V or 15 V. TA = –40 to +125 °C. Typical specs at 25 °C Parameter Symbol Test Condition Min Typ Max Unit VDDI Si8230/1/2/3/4/5/6 Si8237/8 4.5 2.7 — — 5.5 5.5 V 6.5 — 24 V Si8230/2/3/5/6/7/8 — 2 3 mA Si8231/4 — 3.5 5 mA IDDA(Q), IDDB(Q) Current per channel — — 3.0 mA Input Supply Active Current IDDI Input freq = 500 kHz, no load — 3.5 — mA Output Supply Active Current IDDA IDDB Current per channel with Input freq = 500 kHz, no load — 6 — mA DC Specifications Input-side Power Supply Voltage Driver Supply Voltage Input Supply Quiescent Current Output Supply Quiescent Current Voltage between VDDA and VDDA, VDDB GNDA, and VDDB and GNDB (See “6. Ordering Guide” ) IDDI(Q) Input Pin Leakage Current IVIA, IVIB, IPWM –10 — +10 µA dc Input Pin Leakage Current IDISABLE –10 — +10 µA dc Logic High Input Threshold VIH 2.0 — — V Logic Low Input Threshold VIL — — 0.8 V Input Hysteresis VIHYST Si8230/1/2/3/4/5/6/7/8 400 450 — mV Logic High Output Voltage VOAH, VOBH IOA, IOB = –1 mA (VDDA /VDDB) — 0.04 — — V Logic Low Output Voltage VOAL, VOBL IOA, IOB = 1 mA — — 0.04 V Output Short-Circuit Pulsed Sink Current IOA(SCL), IOB(SCL) Si8230/1/2/7, Figure 4 — 0.5 — A Si8233/4/5/6/8, Figure 4 — 4.0 — A Output Short-Circuit Pulsed Source Current IOA(SCH), IOB(SCH) Si8230/1/2/7, Figure 5 — 0.25 — A Si8233/4/5/6/8, Figure 5 — 2.0 — A Si8230/1/2/7 — 5.0 —  Output Sink Resistance RON(SINK) Si8233/4/5/6/8 — 1.0 —  Notes: 1. VDDA = VDDB = 12 V for 5, 8, and 10 V UVLO devices; VDDA = VDDB = 15 V for 12.5 V UVLO devices. 2. TDD is the minimum overlap time without triggering overlap protection (Si8230/1/3/4 only). 3. The largest RDT resistor that can be used is 220 k.. 6 Rev. 1.5 Si823x Table 1. Electrical Characteristics1 (Continued) 2.7 V < VDDI < 5.5 V, VDDA = VDDB = 12 V or 15 V. TA = –40 to +125 °C. Typical specs at 25 °C Parameter Output Source Resistance Symbol RON(SOURCE) Test Condition Min Typ Max Unit Si8230/1/2/7 — 15 —  Si8233/4/5/6/8 — 2.7 —  VDDI Undervoltage Threshold VDDIUV+ VDDI rising (Si8230/1/2/3/4/5/6) 3.60 4.0 4.45 V VDDI Undervoltage Threshold VDDIUV– VDDI falling (Si8230/1/2/3/4/5/6) 3.30 3.70 4.15 V VDDI Lockout Hysteresis VDDIHYS (Si8230/1/2/3/4/5/6) — 250 — mV VDDI Undervoltage Threshold VDDIUV+ VDDI rising (Si8237/8) 2.15 2.3 2.5 V VDDI Undervoltage Threshold VDDIUV– VDDI falling (Si8237/8) 2.10 2.22 2.40 V VDDI Lockout Hysteresis VDDIHYS (Si8237/8) — 75 — mV VDDAUV+, VDDBUV+ VDDA, VDDB rising VDDA, VDDB Undervoltage Threshold 5 V Threshold See Figure 37 on page 27. 5.20 5.80 6.30 V 8 V Threshold See Figure 38 on page 27. 7.50 8.60 9.40 V 10 V Threshold See Figure 39 on page 27. 9.60 11.1 12.2 V 12.5 V Threshold See Figure 40 on page 27. 12.4 13.8 14.8 V VDDA, VDDB Undervoltage Threshold VDDAUV–, VDDBUV– VDDA, VDDB falling 5 V Threshold See Figure 37 on page 27. 4.90 5.52 6.0 V 8 V Threshold See Figure 38 on page 27. 7.20 8.10 8.70 V 10 V Threshold See Figure 39 on page 27. 9.40 10.1 10.9 V 12.5 V Threshold See Figure 40 on page 27. 11.6 12.8 13.8 V VDDA, VDDB Lockout Hysteresis VDDAHYS, VDDBHYS UVLO voltage = 5 V — 280 — mV VDDA, VDDB Lockout Hysteresis VDDAHYS, VDDBHYS UVLO voltage = 8 V — 600 — mV VDDA, VDDB Lockout Hysteresis VDDAHYS, VDDBHYS UVLO voltage = 10 V or 12.5 V — 1000 — mV Notes: 1. VDDA = VDDB = 12 V for 5, 8, and 10 V UVLO devices; VDDA = VDDB = 15 V for 12.5 V UVLO devices. 2. TDD is the minimum overlap time without triggering overlap protection (Si8230/1/3/4 only). 3. The largest RDT resistor that can be used is 220 k.. Rev. 1.5 7 Si823x Table 1. Electrical Characteristics1 (Continued) 2.7 V < VDDI < 5.5 V, VDDA = VDDB = 12 V or 15 V. TA = –40 to +125 °C. Typical specs at 25 °C Parameter Symbol Test Condition Min Typ Max Unit — 10 — ns — 30 60 ns — — 5.60 ns DT = VDDI, No-Connect — 0.4 — ns Figure 42, RDT = 100 k — 900 — ns Figure 42, RDT = 6 k — 70 — ns CL = 200 pF (Si8230/1/2/7) — — 20 ns CL = 200 pF (Si8233/4/5/6/8) — — 12 ns tSD — — 60 ns tRESTART — — 60 ns AC Specifications Minimum Pulse Width Propagation Delay tPHL, tPLH Pulse Width Distortion |tPLH - tPHL| PWD Minimum Overlap Time2 TDD Programmed Dead Time3 Output Rise and Fall Time Shutdown Time from Disable True Restart Time from Disable False CL = 200 pF DT tR,tF Device Start-up Time tSTART Time from VDD_ = VDD_UV+ to VOA, VOB = VIA, VIB — — 40 µs Common Mode Transient Immunity CMTI VIA, VIB, PWM = VDDI or 0 V VCM = 1500 V (see Figure 6) 20 45 — kV/µs Notes: 1. VDDA = VDDB = 12 V for 5, 8, and 10 V UVLO devices; VDDA = VDDB = 15 V for 12.5 V UVLO devices. 2. TDD is the minimum overlap time without triggering overlap protection (Si8230/1/3/4 only). 3. The largest RDT resistor that can be used is 220 k.. 8 Rev. 1.5 Si823x 2.1. Test Circuits Figures 4, 5, and 6 depict sink current, source current, and common-mode transient immunity test circuits, respectively. VDDA = VDDB = 15 V VDDI VDD IN INPUT 10 OUT Si823x SCHOTTKY VSS 1 µF 1 µF CER Measure 100 µF 8V + _ 5.5 V + _ 10 µF EL RSNS 0.1 50 ns VDDI GND 200 ns INPUT WAVEFORM Figure 4. IOL Sink Current Test Circuit VDDA = VDDB = 15 V VDDI IN INPUT VDD Si823x 10 OUT SCHOTTKY VSS 1 µF 1 µF CER Measure 100 µF 10 µF EL RSNS 0.1 50 ns VDDI GND 200 ns INPUT WAVEFORM Figure 5. IOH Source Current Test Circuit Rev. 1.5 9 Si823x 12 V Supply Si823x Input Signal Switch 5V Isolated  Supply VDDI VDDA INPUT VOA DISABLE DT GNDA VDDB Oscilloscope VOB 100k GNDI GNDB Isolated  Ground Input High Voltage Differential Probe Output Vcm Surge Output High Voltage Surge Generator Figure 6. Common Mode Transient Immunity Test Circuit 10 Rev. 1.5 Si823x Table 2. Regulatory Information1,2,3,4 CSA The Si823x is certified under CSA Component Acceptance Notice 5A. For more details, see File 232873. 61010-1: Up to 600 VRMS reinforced insulation working voltage; up to 600 VRMS basic insulation working voltage. 60950-1: Up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage. 60601-1: Up to 125 VRMS reinforced insulation working voltage; up to 380 VRMS basic insulation working voltage. VDE The Si823x is certified according to IEC 60747-5-5. For more details, see File 5006301-4880-0001. 60747-5-5: Up to 891 Vpeak for basic insulation working voltage. 60950-1: Up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage. UL The Si823x is certified under UL1577 component recognition program. For more details, see File E257455. Rated up to 5000 VRMS isolation voltage for basic protection. CQC The Si823x is certified under GB4943.1-2011. For more details, see File V2012CQC001041. Rated up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage. Notes: 1. Regulatory Certifications apply to 2.5 kVRMS rated devices which are production tested to 3.0 kVRMS for 1 sec. 2. Regulatory Certifications apply to 3.75 kVRMS rated devices which are production tested to 4.5 kVRMS for 1 sec. 3. Regulatory Certifications apply to 5.0 kVRMS rated devices which are production tested to 6.0 kVRMS for 1 sec. 4. For more information, see "6. Ordering Guide" on page 39. Rev. 1.5 11 Si823x Table 3. Insulation and Safety-Related Specifications Value Parameter Symbol Test Condition 14 LD WBSOIC-16 14 LD WBSOIC-16 LGA with NBSOIC-16 LGA 5 kVRMS Pad 2.5 kVRMS 2.5 kVRMS 1.0 kVRMS Unit Nominal Air Gap (Clearance)1 L(1O1) 8.0 8.0/4.01 3.5 1.75 mm Nominal External Tracking (Creepage)1 L(1O2) 8.0 8.0/4.01 3.5 1.75 mm 0.014 0.014 0.014 0.014 mm 600 600 600 600 V Minimum Internal Gap (Internal Clearance) Tracking Resistance (Proof Tracking Index) PTI Erosion Depth ED 0.040 0.019 0.021 0.021 mm Resistance (Input-Output)2 RIO 1012 1012 1012 1012  Capacitance (Input-Output)2 CIO 1.4 1.4 1.4 1.4 pF 4.0 4.0 4.0 4.0 pF Input Capacitance3 IEC60112 f = 1 MHz CI Notes: 1. The values in this table correspond to the nominal creepage and clearance values as detailed in “7. Package Outline: 16-Pin Wide Body SOIC” , “9. Package Outline: 16-Pin Narrow Body SOIC” , “11. Package Outline: 14 LD LGA (5 x 5 mm)” , and “13. Package Outline: 14 LD LGA with Thermal Pad (5 x 5 mm)” . VDE certifies the clearance and creepage limits as 4.7 mm minimum for the NB SOIC-16 and 8.5 mm minimum for the WB SOIC-16 package. UL does not impose a clearance and creepage minimum for component level certifications. CSA certifies the clearance and creepage limits as 3.9 mm minimum for the NB SOIC 16 and 7.6 mm minimum for the WB SOIC-16 package. 2. To determine resistance and capacitance, the Si823x is converted into a 2-terminal device. Pins 1–8 (1-7, 14 LD LGA) are shorted together to form the first terminal and pins 9–16 (8-14, 14 LD LGA) are shorted together to form the second terminal. The parameters are then measured between these two terminals. 3. Measured from input pin to ground. Table 4. IEC 60664-1 (VDE 0884 Part 5) Ratings Specification Parameter Basic Isolation Group Installation Classification 12 WB SOIC-16 NB SOIC-16 14 LD LGA 14 LD LGA with Pad I I I I Rated Mains Voltages < 150 VRMS I-IV I-IV I-IV I-IV Rated Mains Voltages < 300 VRMS I-IV I-III I-III I-III Rated Mains Voltages < 400 VRMS I-III I-II I-II I-II Rated Mains Voltages < 600 VRMS I-III I-II I-II I-I Test Condition Material Group Rev. 1.5 Si823x Table 5. IEC 60747-5-5 Insulation Characteristics* Characteristic Parameter Symbol Maximum Working Insulation Voltage VIORM Input to Output Test Voltage Transient Overvoltage Test Condition WB SOIC-16 891 560 373 V peak VPR Method b1 (VIORM x 1.875 = VPR, 100% Production Test, tm = 1 sec, Partial Discharge < 5 pC) 1375 1050 700 V peak VIOTM t = 60 sec 6000 4000 2650 V peak 2 2 2 >109 >109 >109 Pollution Degree (DIN VDE 0110, Table 1) Insulation Resistance at TS, VIO = 500 V Unit NB SOIC-16 14 LD LGA 14 LD LGA with Pad RS  *Note: Maintenance of the safety data is ensured by protective circuits. The Si823x provides a climate classification of 40/125/21. Table 6. IEC Safety Limiting Values1 Parameter Case Temperature Symbol WB NB SOIC-16 SOIC-16 Test Condition TS Safety Input Current IS Device Power Dissipation2 PD JA = 100 °C/W (WB SOIC-16), 105 °C/W (NB SOIC-16, 14 LD LGA), 50 °C/W (14 LD LGA with Pad) VDDI = 5.5 V, VDDA = VDDB = 24 V, TJ = 150 °C, TA = 25 °C 14 LD 14 LD LGA with LGA Pad Unit 150 150 150 150 °C 50 50 50 100 mA 1.2 1.2 1.2 1.2 W Notes: 1. Maximum value allowed in the event of a failure. Refer to the thermal derating curve in Figures 7 and 8. 2. The Si82xx is tested with VDDI = 5.5 V, VDDA = VDDB = 24 V, TJ = 150 ºC, CL = 100 pF, input 2 MHz 50% duty cycle square wave. Rev. 1.5 13 Si823x Table 7. Thermal Characteristics Parameter IC Junction-to-Air Thermal Resistance Symbol WB SOIC-16 NB SOIC-16 14 LD LGA 14 LD LGA with Pad Unit JA 100 105 105 50 °C/W Table 8. Absolute Maximum Ratings1 Parameter Symbol Min Typ Max Unit TSTG –65 — +150 °C Ambient Temperature under Bias TA –40 — +125 °C Junction Temperature TJ — — +150 °C Input-side Supply Voltage VDDI –0.6 — 6.0 V Driver-side Supply Voltage VDDA, VDDB –0.6 — 30 V VIN –0.5 — VDD + 0.5 V IO — — 10 mA Lead Solder Temperature (10 sec.) — — 260 °C Maximum Isolation (Input to Output) (1 sec) WB SOIC-16 — — 6500 VRMS Maximum Isolation (Output to Output) (1 sec) WB SOIC-16 — — 2500 VRMS Maximum Isolation (Input to Output) (1 sec) NB SOIC-16 — — 4250 VRMS Maximum Isolation (Output to Output) (1 sec) NB SOIC-16 — — 2500 VRMS Maximum Isolation (Input to Output) (1 sec) 14 LD LGA without Thermal Pad — — 3850 VRMS Maximum Isolation (Output to Output) (1 sec) 14 LD LGA without Thermal Pad — — 650 VRMS Maximum Isolation (Input to Output) (1 sec) 14 LD LGA with Thermal Pad — — 1850 VRMS Maximum Isolation (Output to Output) (1 sec) 14 LD LGA with Thermal Pad — — 0 VRMS Storage Temperature2 Voltage on any Pin with respect to Ground Output Drive Current per Channel Notes: 1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. VDE certifies storage temperature from –40 to 150 °C. 14 Rev. 1.5 Safety-Limiting Current (mA) Si823x 60 50 VDDI = 5.5 V VDDA, VDDB = 24 V 40 30 20 10 0 0 50 100 150 Case Temperature (ºC) 200 Safety-Limiting Current (mA) Figure 7. WB SOIC-16, NB SOIC-16, 14 LD LGA Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per DIN EN 60747-5-5 120 VDDI = 5.5 V VDDA, VDDB = 24 V 100 80 60 40 20 0 0 50 100 150 Case Temperature (ºC) 200 Figure 8. 14 LD LGA with Pad Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per DIN EN 60747-5-5 Rev. 1.5 15 Si823x 3. Functional Description The operation of an Si823x channel is analogous to that of an optocoupler and gate driver, except an RF carrier is modulated instead of light. This simple architecture provides a robust isolated data path and requires no special considerations or initialization at start-up. A simplified block diagram for a single Si823x channel is shown in Figure 9. Transmitter Receiver Driver RF OSCILLATOR VDD A Dead time control MODULATOR SemiconductorBased Isolation Barrier B DEMODULATOR 0.5 to 4 A peak Gnd Figure 9. Simplified Channel Diagram A channel consists of an RF Transmitter and RF Receiver separated by a semiconductor-based isolation barrier. Referring to the Transmitter, input A modulates the carrier provided by an RF oscillator using on/off keying. The Receiver contains a demodulator that decodes the input state according to its RF energy content and applies the result to output B via the output driver. This RF on/off keying scheme is superior to pulse code schemes as it provides best-in-class noise immunity, low power consumption, and better immunity to magnetic fields. See Figure 10 for more details. Input Signal Modulation Signal Output Signal Figure 10. Modulation Scheme 16 Rev. 1.5 Si823x 3.1. Typical Operating Characteristics (0.5 Amp) The typical performance characteristics depicted in Figures 11 through 22 are for information purposes only. Refer to Table 1 on page 6 for actual specification limits. VDDA Supply Current (mA) 10 Rise/Fall Time (ns) 8 Tfall 6 4 Trise 2 VDD=12V, 25°C CL = 100 pF 7 5 12 15 18 500kHz 3 100kHz 2 1 50 kHz 0 9 21 1MHz 4 0 9 Duty Cycle = 50% CL = 100 pF 1 Channel Switching 6 14 19 24 VDDA Supply Voltage (V) 24 VDDA Supply (V) Figure 11. Rise/Fall Time vs. Supply Voltage Figure 14. Supply Current vs. Supply Voltage 30 25 Supply Current (mA) Propagation Delay (ns) 5 H-L 20 L-H 15 VDD=12V, 25°C CL = 100 pF 4 3 VDDA = 15V, f = 250kHz, CL = 0 pF Duty Cycle = 50% 2 Channels Switching 2 1 10 -50 9 12 15 18 21 0 24 50 100 Temperature (°C) VDDA Supply (V) Figure 15. Supply Current vs. Temperature Figure 12. Propagation Delay vs. Supply Voltage 40 35 Duty Cycle = 50% CL = 0 pF 1 Channel Switching 3.5 Rise/Fall Time (ns) VDDA Supply Current (mA) 4 1MHz 3 500kHz 2.5 2 100kHz Trise 30 25 20 Tfall 15 10 5 1.5 VDD=12V, 25°C 0 50 kHz 1 0.0 9 14 19 24 VDDA Supply Voltage (V) Figure 13. Supply Current vs. Supply Voltage Rev. 1.5 0.5 1.0 1.5 2.0 Load (nF) Figure 16. Rise/Fall Time vs. Load 17 50 4ϳϱ 45 ϰϱϬ 6RXUFH&XUUHQWP$ Propagation Delay (ns) Si823x 40 35 L-H 30 H-L 25 20 15 ϰϮϱ ϰϬϬ ϯϳϱ ϯϱϬ ϯϮϱ ϯϬϬ VDD=12V, Vout=VDD-5V VDD=12V, 25°C 10 Ϯϳϱ 0.0 0.5 1.0 1.5 2.0 10 15 Load (nF) 20 25 6XSSO\9ROWDJH9 Figure 20. Output Source Current vs. Supply Voltage Figure 17. Propagation Delay vs. Load Propagation Delay (ns) 30 25 20 6LQN&XUUHQWP$ L-H H-L 15 VDD=12V, Load = 200pF 10 -40 -20 0 20 40 60 80 100 120 ϴϱϬ ϴϮϱ ϴϬϬ ϳϳϱ ϳϱϬ 7Ϯϱ ϳϬϬ ϲϳϱ ϲϱϬ ϲϮϱ ϲϬϬ ϱϳϱ ϱϱϬ -40 Temperature (°C) VDD=12V, Vout=5V -10 20 50 80 110 7HPSHUDWXUH°& Figure 18. Propagation Delay vs. Temperature Figure 21. Output Sink Current vs. Temperature ϭϭϮϱ ϰϮ5 6RXUFH&XUUHQWP$ 6LQN&XUUHQWP$ ϭϬϬϬ ϴϳϱ ϳϱϬ ϲϮϱ VDD=12V, Vout=5V 12 14 16 18 20 22 24 ϯϱϬ ϯϮ5 Ϯϳϱ -40 6XSSO\9ROWDJH9 VDD=12V, Vout=VDD-5V -10 20 50 80 110 7HPSHUDWXUH°& Figure 19. Output Sink Current vs. Supply Voltage 18 3ϳϱ ϯϬϬ ϱϬϬ 10 ϰϬϬ Figure 22. Output Source Current vs. Temperature Rev. 1.5 Si823x 3.2. Typical Operating Characteristics (4.0 Amp) The typical performance characteristics depicted in Figures 23 through 34 are for information purposes only. Refer to Table 1 on page 6 for actual specification limits. VDDA Supply Current (mA) 10 Rise/Fall Time (ns) 8 Tfall 6 Trise 4 2 14 15 18 500kHz 8 6 100kHz 4 2 50 kHz 0 9 14 19 24 VDDA Supply Voltage (V) 0 12 1MHz 10 VDD=12V, 25°C CL = 100 pF 9 Duty Cycle = 50% CL = 100 pF 1 Channel Switching 12 21 24 Figure 26. Supply Current vs. Supply Voltage VDDA Supply (V) Propagation Delay (ns) 30 25 L-H 10 Supply Current (mA) Figure 23. Rise/Fall Time vs. Supply Voltage 6 VDDA = 15V, f = 250kHz, CL = 0 pF Duty Cycle = 50% 2 Channels Switching 4 2 0 20 -50 0 50 15 Figure 27. Supply Current vs. Temperature 10 9 12 15 18 21 40 24 35 Rise/Fall Time (ns) VDDA Supply (V) Figure 24. Propagation Delay vs. Supply Voltage 14 Duty Cycle = 50% CL = 0 pF 1 Channel Switching 12 1MHz 19 15 10 VDD=12V, 25°C 1 2 3 4 5 6 7 8 9 10 Figure 28. Rise/Fall Time vs. Load 50 kHz 14 Tfall Load (nF) 100kHz 2 9 20 0 6 0 25 0 500kHz 4 Trise 30 5 10 8 100 Temperature (°C) H-L VDD=12V, 25°C CL = 100 pF VDDA Supply Current (mA) 8 24 VDDA Supply Voltage (V) Figure 25. Supply Current vs. Supply Voltage Rev. 1.5 19 Si823x 50 4 3.75 H-L 40 35 Source Current (A) Propagation Delay (ns) 45 L-H 30 25 20 3.25 3 2.75 2.5 2.25 15 0 1 2 3 4 5 6 7 10 8 9 30 Sink Current (A) H-L L-H 20 15 VDD=12V, Load = 200pF -40 -20 0 20 40 60 80 100 120 7 6.75 6.5 6.25 6 5.75 5.5 5.25 5 4.75 4.5 4.25 4 -40 -10 20 50 80 110 Temperature (°C) Figure 30. Propagation Delay vs. Temperature Figure 33. Output Sink Current vs. Temperature 3.5 9 3.25 Source Current (A) 8 Sink Current (A) 25 VDD=12V, Vout=5V Temperature (°C) 7 6 5 3 2.75 2.5 2.25 VDD=12V, Vout=5V VDD=12V, Vout=VDD-5V 2 4 10 12 14 16 18 20 22 24 -40 Supply Voltage (V) -10 20 50 80 110 Temperature (°C) Figure 31. Output Sink Current vs. Supply Voltage 20 20 Supply Voltage (V) Figure 32. Output Source Current vs. Supply Voltage Figure 29. Propagation Delay vs. Load 10 15 10 Load (nF) 25 VDD=12V, Vout=VDD-5V 2 VDD=12V, 25°C 10 Propagation Delay (ns) 3.5 Figure 34. Output Source Current vs. Temperature Rev. 1.5 Si823x 3.3. Family Overview and Logic Operation During Startup The Si823x family of isolated drivers consists of high-side, low-side, and dual driver configurations. 3.3.1. Products Table 9 shows the configuration and functional overview for each product in this family. Table 9. Si823x Family Overview Part Number Configuration Overlap Protection Programmable Dead Time Inputs Peak Output Current (A) Si8230 High-Side/Low-Side   VIA, VIB 0.5 Si8231 High-Side/Low-Side   PWM 0.5 Si8232/7 Dual Driver — — VIA, VIB 0.5 Si8233 High-Side/Low-Side   VIA, VIB 4.0 Si8234 High-Side/Low-Side   PWM 4.0 Si8235/6/8 Dual Driver — — VIA, VIB 4.0 3.3.2. Device Behavior Table 10 consists of truth tables for the Si8230/3, Si8231/4, and Si8232/5/6 families. Table 10. Si823x Family Truth Table1 Si8230/3 (High-Side/Low-Side) Truth Table Inputs VDDI State Disable VIA VIB L L Powered L H H Output Notes VOA VOB L L L Output transition occurs after internal dead time expires. Powered L L H Output transition occurs after internal dead time expires. L Powered L H L Output transition occurs after internal dead time expires. H H Powered L L L Invalid state. Output transition occurs after internal dead time expires. X2 X2 Unpowered X L L Output returns to input state within 7 µs of VDDI power restoration. X X Powered H L L Device is disabled. Si8231/4 (PWM Input High-Side/Low-Side) Truth Table PWM Input VDDI State Disable Output VOA VOB Notes H Powered L H L Output transition occurs after internal dead time expires. L Powered L L H Output transition occurs after internal dead time expires. X2 Unpowered X L L Output returns to input state within 7 µs of VDDI power restoration. X Powered H L L Device is disabled. Notes: 1. This truth table assumes VDDA and VDDB are powered. If VDDA and VDDB are below UVLO, see "3.7.2. Undervoltage Lockout" on page 26 for more information. 2. Note that an input can power the input die through an internal diode if its source has adequate current. Rev. 1.5 21 Si823x Table 10. Si823x Family Truth Table1 (Continued) Si8232/5/6/7/8 (Dual Driver) Truth Table Inputs VDDI State Disable VIA VIB L L Powered L H H Output Notes VOA VOB L L L Output transition occurs immediately (no internal dead time). Powered L L H Output transition occurs immediately (no internal dead time). L Powered L H L Output transition occurs immediately (no internal dead time). H H Powered L H H Output transition occurs immediately (no internal dead time). X2 X2 Unpowered X L L Output returns to input state within 7 µs of VDDI power restoration. X X Powered H L L Device is disabled. Notes: 1. This truth table assumes VDDA and VDDB are powered. If VDDA and VDDB are below UVLO, see "3.7.2. Undervoltage Lockout" on page 26 for more information. 2. Note that an input can power the input die through an internal diode if its source has adequate current. 22 Rev. 1.5 Si823x 3.4. Power Supply Connections Isolation requirements mandate individual supplies for VDDI, VDDA, and VDDB. The decoupling caps for these supplies must be placed as close to the VDD and GND pins of the Si823x as possible. The optimum values for these capacitors depend on load current and the distance between the chip and the regulator that powers it. Low effective series resistance (ESR) capacitors, such as Tantalum, are recommended. 3.5. Power Dissipation Considerations Proper system design must assure that the Si823x operates within safe thermal limits across the entire load range.The Si823x total power dissipation is the sum of the power dissipated by bias supply current, internal parasitic switching losses, and power dissipated by the series gate resistor and load. Equation 1 shows total Si823x power dissipation. Rp Rn 2 P D =  V DDI   I DDI  + 2  I DD2   V DD2  +  f   Q TL   V DD2  -------------------- +  f   Q TL   V DD2  -------------------- + 2fCintV DD2 Rp + Rg Rn + Rg where: P D is the total Si823x device power dissipation (W) I DDI is the input-side maximum bias current (3 mA) I DD2 is the driver die maximum bias current (2.5 mA) C int is the internal parasitic capacitance (75 pF for the 0.5 A driver and 370 pF for the 4.0 A driver) V DDI is the input-side VDD supply voltage (2.7 to 5.5 V) V DD2 is the driver-side supply voltage (10 to 24 V) f is the switching frequency (Hz) Q TL is the total highside bootstrap charge (see Section 2.2 of AN486) R G is the external gate resistor R P is the R DS  ON  of the driver pull-up switch: (Rp=15 for the 0.5A driver; Rp=2.7 for the 4.0A driver) R n is the R DS  ON  of the driver pull-down switch: (Rn=5 for the 0.5A driver and 1 for the 4.0A driver) Equation 1. Power dissipation example for 0.5 A driver using Equation 1 with the following givens: VDDI = 5.0 V VDD2 = 12 V f = 350 kHz RG = 22  QG = 25 nC 3 –9 3 – 12 15 5 Pd = 0.015 + 0.060 +  350  10   25  10   12  ------------------- +  f   Q TL   V DD2  ---------------- + 2   350  10   75  10   144   15 + 22 5 + 22 = 140 mW From which the driver junction temperature is calculated using Equation 2, where: Pd is the total Si823x device power dissipation (W)  ja is the thermal resistance from junction to air (105 °C/W in this example) T A is the ambient temperature Rev. 1.5 23 Si823x T j = P d   ja + T A = (0.145)(105) + 20 = 35.2 °C The maximum power dissipation allowable for the Si823x is a function of the package thermal resistance, ambient temperature, and maximum allowable junction temperature, as shown in Equation 2: T jmax – T A P Dmax  --------------------------ja where: P Dmax = Maximum Si823x power dissipation (W) T jmax = Si823x maximum junction temperature (150 °C) T A = Ambient temperature (°C) ja = Si823x junction-to-air thermal resistance (105 °C/W) f = Si823x switching frequency (Hz) Equation 2. Substituting values for PDmax Tjmax, TA, and ja into Equation 2 results in a maximum allowable total power dissipation of 1.19 W. Maximum allowable load is found by substituting this limit and the appropriate data sheet values from Table 1 on page 6 into Equation 1 and simplifying. The result is Equation 3 (0.5 A driver) and Equation 4 (4.0 A driver), both of which assume VDDI = 5 V and VDDA = VDDB = 18 V. –3  10 - – 7.5  10 – 11 C L(MAX) = 1.4 ------------------------f Equation 3. –3  10 - – 3.7  10 – 10 C L(MAX) = 1.4 ------------------------f Equation 4. Equation 1 and Equation 2 are graphed in Figure 35 where the points along the load line represent the package dissipation-limited value of CL for the corresponding switching frequency. 24 Rev. 1.5 Si823x 1 6 ,0 0 0 0 .5 A D r i ve r ( p F ) 4 A D r i ve r ( p F ) 1 4 ,0 0 0 1 2 ,0 0 0 Max Load (pF) 1 0 ,0 0 0 8 ,0 0 0 6 ,0 0 0 4 ,0 0 0 2 ,0 0 0 0 700 650 600 550 500 450 400 350 300 250 200 150 100 F re q u e n c y (K h z ) Figure 35. Max Load vs. Switching Frequency Rev. 1.5 25 Si823x 3.6. Layout Considerations It is most important to minimize ringing in the drive path and noise on the Si823x VDD lines. Care must be taken to minimize parasitic inductance in these paths by locating the Si823x as close to the device it is driving as possible. In addition, the VDD supply and ground trace paths must be kept short. For this reason, the use of power and ground planes is highly recommended. A split ground plane system having separate ground and VDD planes for power devices and small signal components provides the best overall noise performance. 3.7. Undervoltage Lockout Operation Device behavior during start-up, normal operation and shutdown is shown in Figure 36, where UVLO+ and UVLOare the positive-going and negative-going thresholds respectively. Note that outputs VOA and VOB default low when input side power supply (VDDI) is not present. 3.7.1. Device Startup Outputs VOA and VOB are held low during power-up until VDD is above the UVLO threshold for time period tSTART. Following this, the outputs follow the states of inputs VIA and VIB. 3.7.2. Undervoltage Lockout Undervoltage Lockout (UVLO) is provided to prevent erroneous operation during device startup and shutdown or when VDD is below its specified operating circuits range. The input (control) side, Driver A and Driver B, each have their own undervoltage lockout monitors. The Si823x input side enters UVLO when VDDI < VDDIUV–, and exits UVLO when VDDI > VDDIUV+. The driver outputs, VOA and VOB, remain low when the input side of the Si823x is in UVLO and their respective VDD supply (VDDA, VDDB) is within tolerance. Each driver output can enter or exit UVLO independently. For example, VOA unconditionally enters UVLO when VDDA falls below VDDAUV– and exits UVLO when VDDA rises above VDDAUV+. UVLO+ UVLO- VDD HYS VDDI UVLO+ UVLO- VDD HYS VDDA VIA DISABLE tSTART tSD tSTART tSTART tSD tRESTART tPHL tPLH VOA Figure 36. Device Behavior during Normal Operation and Shutdown 26 Rev. 1.5 Si823x 3.7.3. Undervoltage Lockout (UVLO) The UVLO circuit unconditionally drives VO low when VDD is below the lockout threshold. Referring to Figures 37 through 40, upon power up, the Si823x is maintained in UVLO until VDD rises above VDDUV+. During power down, the Si823x enters UVLO when VDD falls below the UVLO threshold plus hysteresis (i.e., VDD < VDDUV+ – VDDHYS). V DDUV+ (Typ) 3.5 Output Voltage (VO) 10.5 Output Voltage (VO) 10.5 V DDUV+ (Typ) 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.5 Supply Voltage (V DD - V SS) (V) 9.0 Figure 37. Si823x UVLO Response (5 V) 10.0 10.5 11.0 11.5 12.0 12.5 Figure 39. Si823x UVLO Response (10 V) V DDUV+ (Typ) Output Voltage (VO) 10.5 Output Voltage (VO) 10.5 V DDUV+ (Typ) 6.0 9.5 Supply Voltage (V DD - V SS) (V) 6.5 7.0 7.5 8.0 8.5 9.0 11.3 9.5 10.0 11.8 12.3 12.8 13.3 13.8 14.3 14.8 15.3 Supply Voltage (V DD - V SS) (V) Supply Voltage (V DD - V SS) (V) Figure 40. Si823x UVLO Response (12.5 V) Figure 38. Si823x UVLO Response (8 V) Rev. 1.5 27 Si823x 3.7.4. Control Inputs VIA, VIB, and PWM inputs are high-true, TTL level-compatible logic inputs. A logic high signal on VIA or VIB causes the corresponding output to go high. For PWM input versions (Si8231/4), VOA is high and VOB is low when the PWM input is high, and VOA is low and VOB is high when the PWM input is low. 3.7.5. Disable Input When brought high, the DISABLE input unconditionally drives VOA and VOB low regardless of the states of VIA and VIB. Device operation terminates within tSD after DISABLE = VIH and resumes within tRESTART after DISABLE = VIL. The DISABLE input has no effect if VDDI is below its UVLO level (i.e., VOA, VOB remain low). 3.8. Programmable Dead Time and Overlap Protection All high-side/low-side drivers (Si8230/1/3/4) include programmable overlap protection to prevent outputs VOA and VOB from being high at the same time. These devices also include programmable dead time, which adds a userprogrammable delay between transitions of VOA and VOB. When enabled, dead time is present on all transitions, even after overlap recovery. The amount of dead time delay (DT) is programmed by a single resistor (RDT) connected from the DT input to ground per Equation 5. Note that the dead time pin can be tied to VDDI or left floating to provide a nominal dead time at approximately 400 ps. DT  10  RDT where: DT = dead time (ns) and RDT = dead time programming resistor (k  Equation 5. The device driving VIA and VIB should provide a minimum dead time of TDD to avoid activating overlap protection. Input/output timing waveforms for the two-input drivers are shown in Figure 41, and dead time waveforms are shown in Figure 42. Ref VIA/ PWM VIB VOA VOB A B C D E F G H I Description A Normal operation: VIA high, VIB low. B Normal operation: VIB high, VIA low. C Contention: VIA = VIB = high. D Recovery from contention: VIA transitions low. E Normal operation: VIA = VIB = low. F Normal operation: VIA high, VIB low. G Contention: VIA = VIB = high. H Recovery from contention: VIB transitions low. I Normal operation: VIB transitions high. Figure 41. Input / Output Waveforms for High-Side / Low-Side Two-Input Drivers 28 Rev. 1.5 Si823x OVERLAP OVERLAP VOB VIA/ PWM VIA/ PWM VIB 50% VIB DT DT DT DT 90% VOA VOA 10% DT DT 90% VOB VOB 10% A. Typical Dead Time Operation B. Dead Time Operation During Overlap Figure 42. Dead Time Waveforms for High-Side/Low-Side Two-Input Drivers Rev. 1.5 29 Si823x 4. Applications The following examples illustrate typical circuit configurations using the Si823x. 4.1. High-Side/Low-Side Driver Figure 43A shows the Si8230/3 controlled using the VIA and VIB input signals, and Figure 43B shows the Si8231/4 controlled by a single PWM signal. VDD2 VDDI D1 VDDI C1 1uF 1500 V max 1500 V max VDDA VDDA GNDI CB OUT1 VIA OUT2 VIB RDT PWMOUT PWM GNDA DT CONTROLLER CB Q1 VOA GNDA DT Si8230/3 CONTROLLER RDT Si8231/4 VDDB VDDB VDDB C3 10uF DISABLE I/O C3 10uF DISABLE GNDB VOB Q1 VOA VDDB I/O D1 C2 1 µF VDDI C1 1uF GNDI VDD2 VDDI C2 1 µF GNDB Q2 A VOB Q2 B Figure 43. Si823x in Half-Bridge Application For both cases, D1 and CB form a conventional bootstrap circuit that allows VOA to operate as a high-side driver for Q1, which has a maximum drain voltage of 1500 V. VOB is connected as a conventional low-side driver. Note that the input side of the Si823x requires VDD in the range of 4.5 to 5.5 V (2.7 to 5.5 V for Si8237/8), while the VDDA and VDDB output side supplies must be between 6.5 and 24 V with respect to their respective grounds. The boot-strap start up time will depend on the CB cap chosen. VDD2 is usually the same as VDDB. Also note that the bypass capacitors on the Si823x should be located as close to the chip as possible. Moreover, it is recommended that 0.1 and 10 µF bypass capacitors be used to reduce high frequency noise and maximize performance. 30 Rev. 1.5 Si823x 4.2. Dual Driver Figure 44 shows the Si823x configured as a dual driver. Note that the drain voltages of Q1 and Q2 can be referenced to a common ground or to different grounds with as much as 1500 V dc between them. VDDI VDDI C1 10 µF Q1 VOA GNDI VDDA PH1 VIA PH2 VIB VDDA C2 10 µF GNDA CONTROLLER Si8232/5/7/8 VDDB VDDB I/O DISABLE C3 10 µF GNDB VOB Q2 Figure 44. Si8232/5/7/8 in a Dual Driver Application Because each output driver resides on its own die, the relative voltage polarities of VOA and VOB can reverse without damaging the driver. That is, the voltage at VOA can be higher or lower than that of VOB by VDD without damaging the driver. Therefore, a dual driver in a low-side high side/low side drive application can use either VOA or VOB as the high side driver. Similarly, a dual driver can operate as a dual low-side or dual high-side driver and is unaffected by static or dynamic voltage polarity changes. 4.3. Dual Driver with Thermally Enhanced Package (Si8236) The thermal pad of the Si8236 must be connected to a heat spreader to lower thermal resistance. Generally, the larger the thermal shield’s area, the lower the thermal resistance. It is recommended that thermal vias also be used to add mass to the shield. Vias generally have much more mass than the shield alone and consume less space, thus reducing thermal resistance more effectively. While the heat spreader is not generally a circuit ground, it is a good reference plane for the Si8236 and is also useful as a shield layer for EMI reduction. With a 10mm2 thermal plane on the outer layers (including 20 thermal vias), the thermal impedance of the Si8236 was measured at 50 °C/W. This is a significant improvement over the Si8235 which does not include a thermal pad. The Si8235’s thermal resistance was measured at 105 °C /W. In addition, note that the GNDA and GNDB pins for the Si8236 are connected together through the thermal pad. Rev. 1.5 31 Si823x 5. Pin Descriptions SOIC-16 (Narrow) SOIC-16 (Wide) VIA 1 16 VDDA VIA 1 16 VDDA VIB 2 15 VOA VIB 2 15 VOA VDDI 3 14 GNDA VDDI 3 14 GNDA GNDI 4 13 NC GNDI 4 DISABLE 5 12 NC DISABLE 5 Si8230 13 Si8233 12 DT 6 11 VDDB DT 6 11 VDDB NC 7 10 VOB NC 7 10 VOB VDDI 8 9 VDDI 8 9 Si8230 Si8233 GNDB NC NC GNDB Table 11. Si8230/3 Two-Input HS/LS Isolated Driver (SOIC-16) Pin Name 1 VIA Non-inverting logic input terminal for Driver A. 2 VIB Non-inverting logic input terminal for Driver B. 3 VDDI Input-side power supply terminal; connect to a source of 4.5 to 5.5 V. 4 GNDI Input-side ground terminal. 5 32 Description DISABLE Device Disable. When high, this input unconditionally drives outputs VOA, VOB LOW. It is strongly recommended that this input be connected to external logic level to avoid erroneous operation due to capacitive noise coupling. 6 DT Dead time programming input. The value of the resistor connected from DT to ground sets the dead time between output transitions of VOA and VOB. Defaults to 400 ps dead time when connected to VDDI or left open (see "3.8. Programmable Dead Time and Overlap Protection" on page 28). 7 NC No connection. 8 VDDI Input-side power supply terminal; connect to a source of 4.5 to 5.5 V. 9 GNDB Ground terminal for Driver B. 10 VOB 11 VDDB 12 NC No connection. 13 NC No connection. 14 GNDA 15 VOA 16 VDDA Driver B output (low-side driver). Driver B power supply voltage terminal; connect to a source of 6.5 to 24 V. Ground terminal for Driver A. Driver A output (high-side driver). Driver A power supply voltage terminal; connect to a source of 6.5 to 24 V. Rev. 1.5 Si823x SOIC-16 (Narrow) SOIC-16 (Wide) PWM 1 16 VDDA NC 2 15 VOA VDDI 3 14 GNDI 4 DISABLE 5 DT PWM 1 16 VDDA NC 2 15 VOA GNDA VDDI 3 14 GNDA 13 NC GNDI 4 12 NC DISABLE 5 Si8231 13 Si8234 12 6 11 VDDB DT 6 11 VDDB NC 7 10 VOB NC 7 10 VOB VDDI 8 9 VDDI 8 9 Si8231 Si8234 GNDB NC NC GNDB Table 12. Si8231/4 PWM Input HS/LS Isolated Driver (SOIC-16) Pin Name 1 PWM 2 NC 3 VDDI Input-side power supply terminal; connect to a source of 4.5 to 5.5 V. 4 GNDI Input-side ground terminal. 5 Description PWM input. No connection. DISABLE Device Disable. When high, this input unconditionally drives outputs VOA, VOB LOW. It is strongly recommended that this input be connected to external logic level to avoid erroneous operation due to capacitive noise coupling. 6 DT Dead time programming input. The value of the resistor connected from DT to ground sets the dead time between output transitions of VOA and VOB. Defaults to 400 ps dead time when connected to VDDI or left open (see "3.8. Programmable Dead Time and Overlap Protection" on page 28). 7 NC No connection. 8 VDDI Input-side power supply terminal; connect to a source of 4.5 to 5.5 V. 9 GNDB Ground terminal for Driver B. 10 VOB 11 VDDB 12 NC No connection. 13 NC No connection. 14 GNDA 15 VOA 16 VDDA Driver B output (low-side driver). Driver B power supply voltage terminal; connect to a source of 6.5 to 24 V. Ground terminal for Driver A. Driver A output (high-side driver). Driver A power supply voltage terminal; connect to a source of 6.5 to 24 V. Rev. 1.5 33 Si823x SOIC-16 (Narrow) SOIC-16 (Wide) VIA 1 16 VDDA VIA 1 16 VDDA VIB 2 15 VOA VIB 2 15 VOA VDDI 3 14 GNDA VDDI 3 GNDA GNDI 4 13 NC GNDI 4 DISABLE 5 12 NC DISABLE 5 Si8232 14 Si8235 13 Si8237 Si8238 12 NC 6 11 VDDB NC 6 11 VDDB NC 7 10 VOB NC 7 10 VOB VDDI 8 9 VDDI 8 9 Si8232 Si8235 Si8237 Si8238 GNDB NC NC GNDB Table 13. Si8232/5/7/8 Dual Isolated Driver (SOIC-16) Pin Name 1 VIA Non-inverting logic input terminal for Driver A. 2 VIB Non-inverting logic input terminal for Driver B. 3 VDDI Input-side power supply terminal; connect to a source of 4.5 to 5.5 V, (2.7 to 5.5 V for Si8237/8). 4 GNDI Input-side ground terminal. 5 34 Description DISABLE Device Disable. When high, this input unconditionally drives outputs VOA, VOB LOW. It is strongly recommended that this input be connected to external logic level to avoid erroneous operation due to capacitive noise coupling. 6 NC No connection. 7 NC No connection. 8 VDDI Input-side power supply terminal; connect to a source of 4.5 to 5.5 V, (2.7 to 5.5 V for Si8237/8). 9 GNDB Ground terminal for Driver B. 10 VOB 11 VDDB 12 NC No connection. 13 NC No connection. 14 GNDA 15 VOA 16 VDDA Driver B output. Driver B power supply voltage terminal; connect to a source of 6.5 to 24 V. Ground terminal for Driver A. Driver A output. Driver A power supply voltage terminal; connect to a source of 6.5 to 24 V. Rev. 1.5 Si823x LGA-14 (5 x 5 mm) GNDI 1 14 VDDA VIA 2 13 VOA VIB 3 12 GNDA VDDI 4 11 NC DISABLE 5 10 VDDB DT 6 7 VOB VDDI 7 8 GNDB Si8233 Table 14. Si8233 Two-Input HS/LS Isolated Driver (14 LD LGA) Pin Name Description GNDI 1 Input-side ground terminal. VIA 2 Non-inverting logic input terminal for Driver A. VIB 3 Non-inverting logic input terminal for Driver B. VDDI 4 Input-side power supply terminal; connect to a source of 4.5 to 5.5 V. DISABLE 5 Device Disable. When high, this input unconditionally drives outputs VOA, VOB LOW. It is strongly recommended that this input be connected to external logic level to avoid erroneous operation due to capacitive noise coupling. DT 6 Dead time programming input. The value of the resistor connected from DT to ground sets the dead time between output transitions of VOA and VOB. Defaults to 400 ps dead time when connected to VDDI or left open (see"3.8. Programmable Dead Time and Overlap Protection" on page 28). VDDI 7 Input-side power supply terminal; connect to a source of 4.5 to 5.5 V. GNDB 8 Ground terminal for Driver B. VOB 9 Driver B output (low-side driver). VDDB 10 Driver B power supply voltage terminal; connect to a source of 6.5 to 24 V. NC 11 No connection. GNDA 12 Ground terminal for Driver A. VOA 13 Driver A output (high-side driver). VDDA 14 Driver A power supply voltage terminal; connect to a source of 6.5 to 24 V. Rev. 1.5 35 Si823x LGA-14 (5 x 5 mm) GNDI 1 14 VDDA PWM 2 13 VOA NC 3 12 GNDA VDDI 4 11 NC DISABLE 5 10 VDDB DT 6 7 VOB VDDI 7 8 GNDB Si8234 Table 15. Si8234 PWM Input HS/LS Isolated Driver (14 LD LGA) 36 Pin Name Description GNDI 1 Input-side ground terminal. PWM 2 PWM input. NC 3 No connection. VDDI 4 Input-side power supply terminal; connect to a source of 4.5 to 5.5 V. DISABLE 5 Device Disable. When high, this input unconditionally drives outputs VOA, VOB LOW. It is strongly recommended that this input be connected to external logic level to avoid erroneous operation due to capacitive noise coupling. DT 6 Dead time programming input. The value of the resistor connected from DT to ground sets the dead time between output transitions of VOA and VOB. Defaults to 400 ps dead time when connected to VDDI or left open (see "3.8. Programmable Dead Time and Overlap Protection" on page 28). VDDI 7 Input-side power supply terminal; connect to a source of 4.5 to 5.5 V. GNDB 8 Ground terminal for Driver B. VOB 9 Driver B output (low-side driver). VDDB 10 Driver B power supply voltage terminal; connect to a source of 6.5 to 24 V. NC 11 No connection. GNDA 12 Ground terminal for Driver A. VOA 13 Driver A output (high-side driver). VDDA 14 Driver A power supply voltage terminal; connect to a source of 6.5 to 24 V. Rev. 1.5 Si823x LGA-14 (5 x 5 mm) GNDI 1 14 VDDA VIA 2 13 VOA VIB 3 12 GNDA VDDI 4 11 NC DISABLE 5 10 VDDB NC 6 7 VOB VDDI 7 8 GNDB Si8235 Table 16. Si8235 Dual Isolated Driver (14 LD LGA) Pin Name Description GNDI 1 Input-side ground terminal. VIA 2 Non-inverting logic input terminal for Driver A. VIB 3 Non-inverting logic input terminal for Driver B. VDDI 4 Input-side power supply terminal; connect to a source of 4.5 to 5.5 V. DISABLE 5 Device Disable. When high, this input unconditionally drives outputs VOA, VOB LOW. It is strongly recommended that this input be connected to external logic level to avoid erroneous operation due to capacitive noise coupling. NC 6 No connection. VDDI 7 Input-side power supply terminal; connect to a source of 4.5 to 5.5 V. GNDB 8 Ground terminal for Driver B. VOB 9 Driver B output (low-side driver). VDDB 10 Driver B power supply voltage terminal; connect to a source of 6.5 to 24 V. NC 11 No connection. GNDA 12 Ground terminal for Driver A. VOA 13 Driver A output (high-side driver). VDDA 14 Driver A power supply voltage terminal; connect to a source of 6.5 to 24 V. Rev. 1.5 37 Si823x LGA-14 (5 x 5 mm) GNDI 1 14 VDDA VIA 2 13 VOA VIB 3 12 GNDA VDDI 4 11 NC DISABLE 5 10 VDDB NC 6 7 VOB VDDI 7 8 GNDB Si8236 Table 17. Si8236 Dual Isolated Driver (14 LD LGA) Pin Name Description GNDI 1 Input-side ground terminal. VIA 2 Non-inverting logic input terminal for Driver A. VIB 3 Non-inverting logic input terminal for Driver B. VDDI 4 Input-side power supply terminal; connect to a source of 4.5 to 5.5 V. DISABLE 5 Device Disable. When high, this input unconditionally drives outputs VOA, VOB LOW. It is strongly recommended that this input be connected to external logic level to avoid erroneous operation due to capacitive noise coupling. NC 6 No connection. VDDI 7 Input-side power supply terminal; connect to a source of 4.5 to 5.5 V. GNDB 8 Ground terminal for Driver B. GNDA and GNDB pins for the Si8236 are connected together through the thermal pad. VOB 9 Driver B output (low-side driver). VDDB 10 Driver B power supply voltage terminal; connect to a source of 6.5 to 24 V. NC 11 No connection. GNDA 12 Ground terminal for Driver A.GNDA and GNDB pins for the Si8236 are connected together through the thermal pad. 38 VOA 13 Driver A output (high-side driver). VDDA 14 Driver A power supply voltage terminal; connect to a source of 6.5 to 24 V. Rev. 1.5 Si823x 6. Ordering Guide Table 18. Ordering Part Numbers1,2,3 Ordering Part Number (OPN) Inputs Peak UVLO Configuration Current Voltage Isolation Rating Temperature Range Package Type Legacy Ordering Part Number (OPN) 2.5 kV Only Wide Body (WB) Package Options Si8230BB-B-IS VIA, VIB High Side/ Low Side Si8231BB-B-IS PWM High Side/ Low Side Si8232BB-B-IS VIA,VIB Dual Driver Si8234CB-C-IS PWM High Side/ Low Side Si8233BB-C-IS VIA,VIB High Side/ Low Side Si8230-A-IS 0.5 A 8V Si8231-A-IS Si8232-A-IS 10 V 2.5 kVrms –40 to +125 °C SOIC-16 Wide Body N/A Si8233-B-IS 4.0 A Si8234BB-C-IS PWM High Side/ Low Side 8V Si8235BB-C-IS VIA,VIB Dual Driver Si8235-B-IS Si8230AB-B-IS VIA, VIB N/A Si8231AB-B-IS PWM High Side/ Low Side Si8232AB-B-IS VIA,VIB Dual Driver 0.5 A Si8234-B-IS 5V N/A 2.5 kVrms Si8233AB-C-IS VIA,VIB Si8234AB-C-IS PWM High Side/ Low Side Si8235AB-C-IS VIA,VIB Dual Driver 4.0 A 5V –40 to +125 °C SOIC-16 Wide Body N/A N/A N/A N/A Notes: 1. All packages are RoHS-compliant with peak reflow temperatures of 260 °C according to the JEDEC industry standard classifications and peak solder temperatures. 2. All devices >1 kVRMS are AEC-Q100 qualified. 3. “Si” and “SI” are used interchangeably. Rev. 1.5 39 Si823x Table 18. Ordering Part Numbers1,2,3 (Continued) Ordering Part Number (OPN) Inputs Peak UVLO Configuration Current Voltage Isolation Rating Temperature Range Package Type Legacy Ordering Part Number (OPN) 2.5 kV Only –40 to +125 °C SOIC-16 Narrow Body N/A Narrow Body (NB) Package Options Si8230BB-B-IS1 VIA,VIB High Side/ Low Side Si8231BB-B-IS1 PWM High Side/ Low Side Si8232BB-B-IS1 VIA,VIB Dual Driver Si8233BB-C-IS1 VIA,VIB High Side/ Low Side Si8234BB-C-IS1 PWM High Side/ Low Side Si8235BB-C-IS1 VIA,VIB Dual Driver Si8235BA-C-IS1 VIA,VIB Dual Driver Si8230AB-B-IS1 VIA,VIB Si8231AB-B-IS1 PWM High Side/ Low Side Si8232AB-B-IS1 VIA,VIB Dual Driver 0.5 A 8V 2.5 kVrms 4.0 A 8V 1.0 kVrms N/A 0.5 A 5V N/A 2.5 kVrms Si8233AB-C-IS1 VIA,VIB Si8234AB-C-IS1 PWM High Side/ Low Side Si8235AB-C-IS1 VIA,VIB Dual Driver 4.0 A 5V –40 to +125 °C SOIC-16 Narrow Body N/A N/A N/A N/A Notes: 1. All packages are RoHS-compliant with peak reflow temperatures of 260 °C according to the JEDEC industry standard classifications and peak solder temperatures. 2. All devices >1 kVRMS are AEC-Q100 qualified. 3. “Si” and “SI” are used interchangeably. 40 Rev. 1.5 Si823x Table 18. Ordering Part Numbers1,2,3 (Continued) Ordering Part Number (OPN) Inputs Peak UVLO Configuration Current Voltage Isolation Rating Temperature Range Package Type Legacy Ordering Part Number (OPN) 2.5 kV Only LGA Package Options Si8233CB-C-IM Si8233BB-C-IM VIA,VIB High Side/ Low Side Si8233AB-C-IM 10 V N/A 8V Si8233-B-IM 5V Si8234BB-C-IM 8V N/A LGA-14 5x5 mm 2.5 kVrms PWM Si8234AB-C-IM 5V 4.0 A Si8235BB-C-IM Si8235AB-C-IM Si8236BA-C-IM N/A –40 to +125 °C 8V Si8235-B-IM 5V VIA,VIB N/A 8V Dual Driver 5V Si8234-B-IM LGA-14 5x5 mm with Thermal Pad 1.0 kVrms Si8236AA-C-IM Si8236-B-IM N/A 5 kV Ordering Options Si8230BD-B-IS VIA, VIB High Side/ Low Side Si8231BD-B-IS PWM High Side/ Low Side Si8232BD-B-IS VIA, VIB Dual Driver 0.5 A 8V Si8233BD-C-IS VIA, VIB High Side/ Low Side Si8234BD-C-IS PWM High Side/ Low Side Si8235BD-C-IS VIA, VIB Dual Driver Si8230AD-B-IS VIA, VIB Si8231AD-B-IS PWM High Side/ Low Side Si8232AD-B-IS VIA, VIB Dual Driver 5.0 kVrms VIA, VIB Si8234AD-C-IS PWM High Side/ Low Side Si8235AD-C-IS VIA, VIB Dual Driver SOIC-16 Wide Body N/A 4.0 A N/A 0.5 A 5V N/A 5.0 kVrms Si8233AD-C-IS –40 to +125 °C 4.0 A 5V –40 to +125 °C SOIC-16 Wide Body N/A N/A N/A N/A Notes: 1. All packages are RoHS-compliant with peak reflow temperatures of 260 °C according to the JEDEC industry standard classifications and peak solder temperatures. 2. All devices >1 kVRMS are AEC-Q100 qualified. 3. “Si” and “SI” are used interchangeably. Rev. 1.5 41 Si823x Table 18. Ordering Part Numbers1,2,3 (Continued) Ordering Part Number (OPN) Inputs Peak UVLO Configuration Current Voltage Isolation Rating Temperature Range Package Type Legacy Ordering Part Number (OPN) 2.5 kV Only 3 V VDDI Ordering Options Si8237AB‐B‐IS1 VIA, VIB Dual Driver Si8237BB‐B‐IS1 VIA, VIB Dual Driver Si8238AB‐C‐IS1 VIA, VIB Dual Driver Si8238BB‐C‐IS1 VIA, VIB Dual Driver 8V Si8237AD‐B‐IS VIA, VIB Dual Driver 5V Si8237BD‐B‐IS VIA, VIB Dual Driver Si8238AD‐C‐IS VIA, VIB Si8238BD‐C‐IS VIA, VIB 0.5 A 8V 4.0 A 0.5 A 4.0 A SOIC-16 Narrow Body 2.5 kVrms 5V 8V Dual Driver Dual Driver 5V 5V 40 to +125 °C 5.0 kVrms N/A SOIC-16 Wide Body 8V Notes: 1. All packages are RoHS-compliant with peak reflow temperatures of 260 °C according to the JEDEC industry standard classifications and peak solder temperatures. 2. All devices >1 kVRMS are AEC-Q100 qualified. 3. “Si” and “SI” are used interchangeably. 42 Rev. 1.5 Si823x 7. Package Outline: 16-Pin Wide Body SOIC Figure 45 illustrates the package details for the Si823x in a 16-Pin Wide Body SOIC. Table 19 lists the values for the dimensions shown in the illustration. Figure 45. 16-Pin Wide Body SOIC Rev. 1.5 43 Si823x Table 19. Package Diagram Dimensions Dimension Min Max A — 2.65 A1 0.10 0.30 A2 2.05 — b 0.31 0.51 c 0.20 0.33 D 10.30 BSC E 10.30 BSC E1 7.50 BSC e 1.27 BSC L 0.40 1.27 h 0.25 0.75  0° 8° aaa — 0.10 bbb — 0.33 ccc — 0.10 ddd — 0.25 eee — 0.10 fff — 0.20 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to JEDEC Outline MS-013, Variation AA. 4. Recommended reflow profile per JEDEC J-STD-020 specification for small body, lead-free components. 44 Rev. 1.5 Si823x 8. Land Pattern: 16-Pin Wide Body SOIC Figure 46 illustrates the recommended land pattern details for the Si823x in a 16-pin wide-body SOIC. Table 20 lists the values for the dimensions shown in the illustration. Figure 46. 16-Pin SOIC Land Pattern Table 20. 16-Pin Wide Body SOIC Land Pattern Dimensions Dimension Feature (mm) C1 Pad Column Spacing 9.40 E Pad Row Pitch 1.27 X1 Pad Width 0.60 Y1 Pad Length 1.90 Notes: 1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P1032X265-16AN for Density Level B (Median Land Protrusion). 2. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0.05 mm is assumed. Rev. 1.5 45 Si823x 9. Package Outline: 16-Pin Narrow Body SOIC Figure 47 illustrates the package details for the Si823x in a 16-pin narrow-body SOIC (SO-16). Table 21 lists the values for the dimensions shown in the illustration. Figure 47. 16-pin Small Outline Integrated Circuit (SOIC) Package Table 21. Package Diagram Dimensions Dimension Min Max Dimension Min Max A — 1.75 L 0.40 1.27 A1 0.10 0.25 L2 A2 1.25 — h 0.25 0.50 b 0.31 0.51 θ 0° 8° c 0.17 0.25 aaa 0.10 0.25 BSC D 9.90 BSC bbb 0.20 E 6.00 BSC ccc 0.10 E1 3.90 BSC ddd 0.25 e 1.27 BSC Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to the JEDEC Solid State Outline MS-012, Variation AC. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 46 Rev. 1.5 Si823x 10. Land Pattern: 16-Pin Narrow Body SOIC Figure 48 illustrates the recommended land pattern details for the Si823x in a 16-pin narrow-body SOIC. Table 22 lists the values for the dimensions shown in the illustration. Figure 48. 16-Pin Narrow Body SOIC PCB Land Pattern Table 22. 16-Pin Narrow Body SOIC Land Pattern Dimensions Dimension Feature (mm) C1 Pad Column Spacing 5.40 E Pad Row Pitch 1.27 X1 Pad Width 0.60 Y1 Pad Length 1.55 Notes: 1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P600X165-16N for Density Level B (Median Land Protrusion). 2. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0.05 mm is assumed. Rev. 1.5 47 Si823x 11. Package Outline: 14 LD LGA (5 x 5 mm) Figure 49 illustrates the package details for the Si823x in an LGA outline. Table 23 lists the values for the dimensions shown in the illustration. Figure 49. Si823x LGA Outline Table 23. Package Diagram Dimensions Dimension MIN NOM MAX A 0.74 0.84 0.94 b 0.25 0.30 0.35 D 5.00 BSC D1 4.15 BSC e 0.65 BSC E 5.00 BSC E1 3.90 BSC L 0.70 0.75 0.80 L1 0.05 0.10 0.15 aaa — — 0.10 bbb — — 0.10 ccc — — 0.08 ddd — — 0.15 eee — — 0.08 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 48 Rev. 1.5 Si823x 12. Land Pattern: 14 LD LGA Figure 50 illustrates the recommended land pattern details for the Si823x in a 14-pin LGA. Table 24 lists the values for the dimensions shown in the illustration. Figure 50. 14-Pin LGA Land Pattern Table 24. 14-Pin LGA Land Pattern Dimensions Dimension C1 E X1 Y1 (mm) 4.20 0.65 0.80 0.40 Notes: General 1. All dimensions shown are in millimeters (mm). 2. This Land Pattern Design is based on the IPC-7351 guidelines. 3. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm. Solder Mask Design 4. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad. Stencil Design 5. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 6. The stencil thickness should be 0.125 mm (5 mils). 7. The ratio of stencil aperture to land pad size should be 1:1. Card Assembly 8. A No-Clean, Type-3 solder paste is recommended. 9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. Rev. 1.5 49 Si823x 13. Package Outline: 14 LD LGA with Thermal Pad (5 x 5 mm) Figure 51 illustrates the package details for the Si8236 ISOdriver in an LGA outline. Table 25 lists the values for the dimensions shown in the illustration. Figure 51. Si823x LGA Outline with Thermal Pad Table 25. Package Diagram Dimensions Dimension MIN NOM MAX A 0.74 0.84 0.94 b 0.25 0.30 0.35 D 5.00 BSC D1 4.15 BSC e 0.65 BSC E 5.00 BSC E1 3.90 BSC L 0.70 0.75 0.80 L1 0.05 0.10 0.15 P1 1.40 1.45 1.50 P2 4.15 4.20 4.25 aaa — — 0.10 bbb — — 0.10 ccc — — 0.08 ddd — — 0.15 eee — — 0.08 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 50 Rev. 1.5 Si823x 14. Land Pattern: 14 LD LGA with Thermal Pad Figure 52 illustrates the recommended land pattern details for the Si8236 in a 14-pin LGA with thermal pad. Table 26 lists the values for the dimensions shown in the illustration. Figure 52. 14-Pin LGA with Thermal Pad Land Pattern Table 26. 14-Pin LGA with Thermal Pad Land Pattern Dimensions Dimension C1 C2 D2 E X1 Y1 (mm) 4.20 1.50 4.25 0.65 0.80 0.40 Notes: General: 1. All dimensions shown are in millimeters (mm). 2. This Land Pattern Design is based on the IPC-7351 guidelines. 3. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm. Solder Mask Design: 4. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad. Stencil Design: 5. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 6. The stencil thickness should be 0.125 mm (5 mils). 7. The ratio of stencil aperture to land pad size should be 1:1. Card Assembly: 8. A No-Clean, Type-3 solder paste is recommended. 9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. Rev. 1.5 51 Si823x 15. Top Markings 15.1. Si823x Top Marking (16-Pin Wide Body SOIC) Si823YUV YYWWTTTTTT e4 TW 15.2. Top Marking Explanation (16-Pin Wide Body SOIC) Line 1 Marking: Line 2 Marking: Line 3 Marking: 52 Si823 = ISOdriver product series Y = Peak output current Base Part Number  0, 1, 2, 7 = 0.5 A Ordering Options  3, 4, 5, 8 = 4.0 A U = UVLO level See Ordering Guide for more  A = 5 V; B = 8 V; C = 10 V; D = 12.5 V information. V = Isolation rating  B = 2.5 kV; C = 3.75 kV; D = 5.0 kV YY = Year WW = Workweek Assigned by the Assembly House. Corresponds to the year and workweek of the mold date. TTTTTT = Mfg Code Manufacturing Code from Assembly Purchase Order form. Circle = 1.5 mm Diameter (Center Justified) “e4” Pb-Free Symbol Country of Origin ISO Code Abbreviation TW = Taiwan Rev. 1.5 Si823x 15.3. Si823x Top Marking (16-Pin Narrow Body SOIC) e4 Si823YUV YYWWTTTTTT 15.4. Top Marking Explanation (16-Pin Narrow Body SOIC) Base Part Number Ordering Options Line 1 Marking: See Ordering Guide for more information. Line 2 Marking: Si823 = ISOdriver product series Y = Peak output current  0, 1, 2, 7 = 0.5 A  3, 4, 5, 8 = 4.0 A U = UVLO level  A = 5 V; B = 8 V; C = 10 V; D = 12.5 V V = Isolation rating  B = 2.5 kV; C = 3.75 kV; D = 5.0 kV YY = Year WW = Workweek Assigned by the Assembly House. Corresponds to the year and workweek of the mold date. TTTTTT = Mfg Code Manufacturing Code from Assembly Purchase Order form. Rev. 1.5 53 Si823x 15.5. Si823x Top Marking (14 LD LGA) Si823Y UV-IM TTTTTT YYWW 15.6. Top Marking Explanation (14 LD LGA) Line 1 Marking: Base Part Number Ordering Options See Ordering Guide for more information. Line 2 Marking: Ordering options Si823 = ISOdriver product series Y = Peak output current  0, 1, 2 = 0.5 A  3, 4, 5, 6 = 4.0 A U = UVLO level A = 5 V; B = 8 V; C = 10 V; D = 12.5 V V = Isolation rating  A = 1.0 kV; B = 2.5 kV; C = 3.75 kV; D = 5.0 kV I = –40 to +125 °C ambient temperature range M = LGA package type  Line 3 Marking: TTTTTT Manufacturing Code from Assembly Line 4 Marking: Circle = 1.5 mm diameter Pin 1 identifier YYWW Manufacturing date code 54 Rev. 1.5 Si823x DOCUMENT CHANGE LIST  Revision 0.11 to Revision 0.2         Added Updated all specs to reflect latest silicon revision. Updated Table 1 on page 6 to include new UVLO options. Updated Table 8 on page 14 to reflect new maximum package isolation ratings Added Figures 34, 35, and 36. Updated Ordering Guide to reflect new package offerings. Added "3.7.3. Undervoltage Lockout (UVLO)" on page 27 to describe UVLO operation.       Revision 0.2 to Revision 0.3  Moved Sections 2, 3, and 4 to after Section 5.  Updated Tables 14, 15, and 17. Removed  Si8230, Si8231, and Si8232 from pinout and from title.  Updated and added Ordering Guide footnotes.  Updated UVLO specifications in Table 1 on page 6.  Added PWD and Output Supply Active Current specifications in Table 1.  Updated and added typical operating condition graphs in "3.1. Typical Operating Characteristics (0.5 Amp)" on page 17 and "3.2. Typical Operating Characteristics (4.0 Amp)" on page 19.         Added Device Marking sections.  Updated "6. Ordering Guide" on page 39. “ 3 V VDDI Ordering Options” . Revision 1.4 to Revision 1.5 Updated Table 1 on page 6. CMTI specification.  Updated Table 1, input and output supply current. Added references to AEC-Q100 qualified throughout.  Changed all 60747-5-2 references to 60747-5-5.  Added references to CQC throughout.  Updated pin descriptions throughout. Updated Table 5, “IEC 60747-5-5 Insulation Characteristics*,” on page 13.  Updated "4.2. Dual Driver" on page 31.  Updated "6. Ordering Guide" on page 39.  Replaced pin descriptions on page 1 with chip graphics.  Corrected Revision 1.1 to Revision 1.2  dead time default to 400 ps from 1 ns. Updated Table 18, Ordering Part Numbers. Removed Updated "6. Ordering Guide" on page 39. Updated Si8235-BA-C-IS1 ordering part number. table note. Updated CMTI specification.   references to Figures 26A and 26B. Updated Table 18 on page 39. Revision 1.3 to Revision 1.4 Updated " Features" on page 1. Updated Notes 1 and 2. Updated "3.8. Programmable Dead Time and Overlap Protection" on page 28. Added Revision 1.0 to Revision 1.1  Added Si8237/8 throughout. Updated Table 1 on page 6. Updated Figure 4 on page 9. UpdatedFigure 5 on page 9. Added Figure 6 on page 10. Updated Table 10 on page 21. Added 5 V UVLO ordering options Updated Updated "3.5. Power Dissipation Considerations" on page 23. Removed Updated Tables 2, 3, 4, and 5.  Updated “6. Ordering Guide” .  Updated Table 2 on page 11 with new notes. Added Table 17 and pinout. Updated Figures 19, 20, 21, and 22 to reflect correct y-axis scaling. Updated Figure 44 on page 31. Updated "4.3. Dual Driver with Thermally Enhanced Package (Si8236)" on page 31. Updated "7. Package Outline: 16-Pin Wide Body SOIC" on page 43. Updated Table 19, “Package Diagram Dimensions,” on page 44. Change references to 1.5 kVRMS rated devices to 1.0 kVRMS throughout. Created   junction temperature spec. Revision 1.2 to Revision 1.3 Revision 0.3 to Revision 1.0 Added Updated Table 8 on page 14. moisture sensitivity level table notes. moisture sensitivity level (MSL) for all package types. Rev. 1.5 55 Si823x CONTACT INFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Please visit the Silicon Labs Technical Support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. Patent Notice Silicon Labs invests in research and development to help our customers differentiate in the market with innovative low-power, small size, analogintensive mixed-signal solutions. Silicon Labs' extensive patent portfolio is a testament to our unique approach and world-class engineering team. The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. 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