Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
L O W - P OWER, S INGLE AND D U A L - C HANNEL
D IGITA L I S O L A T O R S
Features
High-speed operation
DC to 150 Mbps
No start-up initialization required
Wide Operating Supply Voltage:
2.6–5.5 V
Up to 5000 VRMS isolation
High electromagnetic immunity
Ultra low power (typical)
5 V Operation:
< 2.6 mA/channel at 1 Mbps
< 6.8 mA/channel at 100 Mbps
2.70 V Operation:
< 2.3 mA/channel at 1 Mbps
< 4.6 mA/channel at 100 Mbps
Schmitt trigger inputs
Selectable fail-safe mode
Default high or low output
Precise timing (typical)
11 ns propagation delay max
1.5 ns pulse width distortion
0.5 ns channel-channel skew
2 ns propagation delay skew
5 ns minimum pulse width
Transient immunity 45 kV/µs
Wide temperature range
–40 to 125 °C at 150 Mbps
RoHS compliant packages
SOIC-16 wide body
SOIC-8 narrow body
Applications
Industrial automation systems
Medical electronics
Hybrid electric vehicles
Isolated switch mode supplies
Isolated ADC, DAC
Motor control
Power inverters
Communication systems
Safety Regulatory Approvals
UL 1577 recognized
Up to 5000 VRMS for 1 minute
CSA component notice 5A approval
IEC 60950-1, 61010-1, 60601-1
(reinforced insulation)
VDE certification conformity
IEC 60747-5-2
(VDE0884 Part 2)
EN60950-1 (reinforced insulation)
Ordering Information:
See page 29.
Description
Silicon Lab's family of ultra-low-power digital isolators are CMOS devices offering
substantial data rate, propagation delay, power, size, reliability, and external BOM
advantages when compared to legacy isolation technologies. The operating
parameters of these products remain stable across wide temperature ranges and
throughout device service life for ease of design and highly uniform performance.
All device versions have Schmitt trigger inputs for high noise immunity and only
require VDD bypass capacitors.
Data rates up to 150 Mbps are supported, and all devices achieve worst-case
propagation delays of less than 10 ns. Ordering options include a choice of
isolation ratings (up to 5 kV) and a selectable fail-safe operating mode to control
the default output state during power loss. All products are safety certified by UL,
CSA, and VDE, and products in wide-body packages support reinforced insulation
withstanding up to 5 kVRMS.
Rev. 1.2 3/12
Copyright © 2012 by Silicon Laboratories
Si8410/20/21 / Si8422/23
Si8410/20/21 (5 kV)
Si8 422/23 ( 2. 5 & 5 k V)
2
Rev. 1.2
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
TABLE O F C ONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.1. Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.2. Eye Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3. Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.1. Device Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
3.2. Under Voltage Lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.3. Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.4. Fail-Safe Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.5. Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4. Pin Descriptions (Wide-Body SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5. Pin Descriptions (Narrow-Body SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7. Package Outline: 16-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
8. Land Pattern: 16-Pin Wide-Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
9. Package Outline: 8-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
10. Land Pattern: 8-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
11. Top Marking: 16-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
12. Top Marking: 8-Pin Narrow-Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Rev. 1.2
3
Si8410/20/21 (5 kV)
Si8 422/23 ( 2. 5 & 5 k V)
1. Electrical Specifications
Table 1. Electrical Characteristics
(VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA = –40 to 125 ºC)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
VDD Undervoltage Threshold
VDD Negative-Going Lockout
Hysteresis
Positive-Going Input Threshold
Negative-Going Input Threshold
Input Hysteresis
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Input Leakage Current
Output Impedance1
VDDUV+
VDDHYS
VDD1, VDD2 rising
2.15
45
2.3
75
2.5
95
V
mV
—
—
0.45
—
—
4.8
0.2
—
50
1.9
1.4
0.50
—
0.8
—
0.4
±10
—
V
V
V
V
V
V
V
µA
Si8410Ax, Bx
VDD1
VDD2
VDD1
VDD2
Si8420Ax, Bx
VDD1
VDD2
VDD1
VDD2
Si8421Ax, Bx
VDD1
VDD2
VDD1
VDD2
Si8422Ax, Bx
VDD1
VDD2
VDD1
VDD2
Si8423Ax, Bx
VDD1
VDD2
VDD1
VDD2
VT+
All inputs rising
1.6
VT–
All inputs falling
1.1
0.40
VHYS
2.0
VIH
—
VIL
loh = –4 mA
VDD1,VDD2 – 0.4
VOH
lol = 4 mA
—
VOL
—
IL
ZO
—
DC Supply Current (All inputs 0 V or at Supply)
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1.0
1.0
3.0
1.0
1.5
1.5
4.5
1.5
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1.3
1.7
5.8
1.7
2.0
2.6
8.7
2.6
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1.7
1.7
3.7
3.7
2.6
2.6
5.6
5.6
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
3.7
3.7
1.7
1.7
5.6
5.6
2.6
2.6
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
5.4
1.7
1.3
1.7
8.1
2.6
2.0
2.6
mA
mA
mA
mA
mA
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of
the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
4
Rev. 1.2
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
Table 1. Electrical Characteristics (Continued)
(VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA = –40 to 125 ºC)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
1 Mbps Supply Current (All inputs = 500 kHz square wave, CL = 15 pF on all outputs)
Si8410Ax, Bx
VDD1
—
2.0
3.0
VDD2
—
1.1
1.7
Si8420Ax, Bx
VDD1
—
3.5
5.3
VDD2
—
1.9
2.9
Si8421Ax, Bx
—
2.8
4.2
VDD1
VDD2
—
2.8
4.2
Si8422Ax, Bx
VDD1
—
2.8
4.2
VDD2
—
2.8
4.2
Si8423Ax, Bx
VDD1
—
3.4
5.1
VDD2
—
1.9
2.9
10 Mbps Supply Current (All inputs = 5 MHz square wave, CL = 15 pF on all outputs)
Si8410Bx
VDD1
VDD2
Si8420Bx
VDD1
VDD2
Si8421Bx
VDD1
VDD2
Si8422Bx
VDD1
VDD2
Si8423Bx
VDD1
VDD2
mA
mA
mA
mA
mA
—
—
2.1
1.5
3.1
2.1
mA
—
—
3.6
2.6
5.4
3.6
mA
—
—
3.2
3.2
4.5
4.5
mA
—
—
3.2
3.2
4.5
4.5
mA
—
—
3.4
2.5
5.1
3.5
mA
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of
the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
Rev. 1.2
5
Si8410/20/21 (5 kV)
Si8 422/23 ( 2. 5 & 5 k V)
Table 1. Electrical Characteristics (Continued)
(VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA = –40 to 125 ºC)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
100 Mbps Supply Current (All inputs = 50 MHz square wave, CL = 15 pF on all outputs)
Si8410Bx
VDD1
VDD2
Si8420Bx
VDD1
VDD2
Si8421Bx
VDD1
VDD2
Si8422Bx
VDD1
VDD2
Si8423Bx
VDD1
VDD2
—
—
2.1
5.0
3.1
6.3
mA
—
—
3.7
9.8
5.4
12.3
mA
—
—
6.8
6.8
8.5
8.5
mA
—
—
6.8
6.8
8.5
8.5
mA
—
—
3.4
9.2
5.1
11.5
mA
—
—
—
1.0
250
35
Mbps
ns
ns
Timing Characteristics
Si841xAx, Si842xAx
Maximum Data Rate
Minimum Pulse Width
Propagation Delay
Pulse Width Distortion
|tPLH - tPHL|
Propagation Delay Skew2
Channel-Channel Skew
Si841xBx, Si842xBx
Maximum Data Rate
Minimum Pulse Width
Propagation Delay
Pulse Width Distortion
|tPLH - tPHL|
Propagation Delay Skew2
Channel-Channel Skew
All Models
Output Rise Time
Output Fall Time
Peak Eye Diagram Jitter
Common Mode Transient
Immunity
Start-up Time3
tPHL, tPLH
See Figure 1
0
—
—
PWD
See Figure 1
—
—
25
ns
tPSK(P-P)
tPSK
—
—
—
—
40
35
ns
ns
tPHL, tPLH
See Figure 1
0
—
4.0
—
—
8.0
150
6.0
11
Mbps
ns
ns
PWD
See Figure 1
—
1.5
3.0
ns
—
—
2.0
0.5
3.0
1.5
ns
ns
tJIT(PK)
CL = 15 pF
CL = 15 pF
See Figure 6
—
—
—
2.0
2.0
350
4.0
4.0
—
ns
ns
ps
CMTI
VI = VDD or 0 V
20
45
—
kV/µs
—
15
40
µs
tPSK(P-P)
tPSK
tr
tf
tSU
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of
the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
6
Rev. 1.2
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
1.4 V
Typical
Input
tPLH
tPHL
90%
90%
10%
10%
1.4 V
Typical
Output
tr
tf
Figure 1. Propagation Delay Timing
Rev. 1.2
7
Si8410/20/21 (5 kV)
Si8 422/23 ( 2. 5 & 5 k V)
Table 2. Electrical Characteristics
(VDD1 = 3.3 V ±10%, VDD2 = 3.3 V ±10%, TA = –40 to 125 °C)
Parameter
Symbol
Test Condition
VDD Undervoltage Threshold
VDDUV+ VDD1, VDD2 rising
VDD Negative-Going Lockout
Hysteresis
VDDHYS
Min
Typ
Max
Unit
2.15
2.3
2.5
V
45
75
95
mV
Positive-Going Input Threshold
VT+
All inputs rising
1.6
—
1.9
V
Negative-Going Input Threshold
VT–
All inputs falling
1.1
—
1.4
V
Input Hysteresis
VHYS
0.40
0.45
0.50
V
High Level Input Voltage
VIH
2.0
—
—
V
Low Level Input Voltage
VIL
—
—
0.8
V
High Level Output Voltage
VOH
loh = –4 mA
VDD1,VDD2 – 0.4
3.1
—
V
Low Level Output Voltage
VOL
lol = 4 mA
—
0.2
0.4
V
IL
—
—
±10
µA
ZO
—
50
—
Input Leakage Current
Output Impedance
(Si8410/20)1
DC Supply Current (All inputs 0 V or at supply)
Si8410Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1.0
1.0
3.0
1.0
1.5
1.5
4.5
1.5
Si8420Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1.3
1.7
5.8
1.7
2.0
2.6
8.7
2.6
Si8421Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1.7
1.7
3.7
3.7
2.6
2.6
5.6
5.6
Si8422Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
3.7
3.7
1.7
1.7
5.6
5.6
2.6
2.6
Si8423Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
5.4
1.7
1.3
1.7
8.1
2.6
2.0
2.6
mA
mA
mA
mA
mA
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
8
Rev. 1.2
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
Table 2. Electrical Characteristics (Continued)
(VDD1 = 3.3 V ±10%, VDD2 = 3.3 V ±10%, TA = –40 to 125 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
1 Mbps Supply Current (All inputs = 500 kHz square wave, CL = 15 pF on all outputs)
Si8410Ax, Bx
VDD1
VDD2
—
—
2.0
1.1
3.0
1.7
mA
Si8420Ax, Bx
VDD1
VDD2
—
—
3.5
1.9
5.3
2.9
mA
Si8421Ax, Bx
VDD1
VDD2
—
—
2.8
2.8
4.2
4.2
mA
Si8422Ax, Bx
VDD1
VDD2
—
—
2.8
2.8
4.2
4.2
mA
Si8423Ax, Bx
VDD1
VDD2
—
—
3.4
1.9
5.1
2.9
mA
10 Mbps Supply Current (All inputs = 5 MHz square wave, CL = 15 pF on all outputs)
Si8410Bx
VDD1
VDD2
—
—
2.0
1.3
3.0
1.8
mA
Si8420Bx
VDD1
VDD2
—
—
3.5
2.3
5.3
3.2
mA
Si8421Bx
VDD1
VDD2
—
—
3.0
3.0
4.4
4.4
mA
Si8422Bx
VDD1
VDD2
—
—
3.0
3.0
4.4
4.4
mA
Si8423Bx
VDD1
VDD2
—
—
3.4
2.2
5.1
3.1
mA
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
Rev. 1.2
9
Si8410/20/21 (5 kV)
Si8 422/23 ( 2. 5 & 5 k V)
Table 2. Electrical Characteristics (Continued)
(VDD1 = 3.3 V ±10%, VDD2 = 3.3 V ±10%, TA = –40 to 125 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
100 Mbps Supply Current (All inputs = 50 MHz square wave, CL = 15 pF on all outputs)
Si8410Bx
VDD1
VDD2
—
—
2.0
3.6
3.0
4.5
mA
Si8420Bx
VDD1
VDD2
—
—
4.5
7.0
5.3
8.8
mA
Si8421Bx
VDD1
VDD2
—
—
5.3
5.3
6.6
6.6
mA
Si8422Bx
VDD1
VDD2
—
—
5.3
5.3
6.6
6.6
mA
Si8423Bx
VDD1
VDD2
—
—
3.4
6.6
5.1
8.3
mA
Maximum Data Rate
0
—
1.0
Mbps
Minimum Pulse Width
—
—
250
ns
Timing Characteristics
Si841xAx, Si842xAx
Propagation Delay
tPHL, tPLH
See Figure 1
—
—
35
ns
PWD
See Figure 1
—
—
25
ns
tPSK(P-P)
—
—
40
ns
tPSK
—
—
35
ns
Maximum Data Rate
0
—
150
Mbps
Minimum Pulse Width
—
—
6.0
ns
Pulse Width Distortion
|tPLH – tPHL|
Propagation Delay Skew2
Channel-Channel Skew
Si841xBx, Si842xBx
Propagation Delay
Pulse Width Distortion
|tPLH – tPHL|
Propagation Delay Skew2
Channel-Channel Skew
tPHL, tPLH
See Figure 1
4.0
8.0
11
ns
PWD
See Figure 1
—
1.5
3.0
ns
tPSK(P-P)
—
2.0
3.0
ns
tPSK
—
0.5
1.5
ns
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
10
Rev. 1.2
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
Table 2. Electrical Characteristics (Continued)
(VDD1 = 3.3 V ±10%, VDD2 = 3.3 V ±10%, TA = –40 to 125 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Output Rise Time
tr
CL = 15 pF
—
2.0
4.0
ns
Output Fall Time
tf
CL = 15 pF
—
2.0
4.0
ns
Peak Eye Diagram Jitter
tJIT(PK)
See Figure 6
—
350
—
ps
Common Mode Transient
Immunity
Start-up Time3
CMTI
VI = VDD or 0 V
20
45
—
kV/µs
—
15
40
µs
All Models
tSU
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
Rev. 1.2
11
Si8410/20/21 (5 kV)
Si8 422/23 ( 2. 5 & 5 k V)
Table 3. Electrical Characteristics1
(VDD1 = 2.70 V, VDD2 = 2.70 V, TA = –40 to 125 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
VDD Undervoltage Threshold
VDD Negative-Going Lockout
Hysteresis
Positive-Going Input Threshold
Negative-Going Input Threshold
Input Hysteresis
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
VDDUV+
VDDHYS
VDD1, VDD2 rising
2.15
45
2.3
75
2.5
95
V
mV
VT+
VT–
VHYS
VIH
VIL
VOH
All inputs rising
All inputs falling
—
—
0.45
—
—
2.3
1.9
1.4
0.50
—
0.8
—
V
V
V
V
V
V
0.2
—
50
0.4
±10
—
V
µA
Low Level Output Voltage
Input Leakage Current
Output Impedance2
Si8410Ax, Bx
VDD1
VDD2
VDD1
VDD2
Si8420Ax, Bx
VDD1
VDD2
VDD1
VDD2
Si8421Ax, Bx
VDD1
VDD2
VDD1
VDD2
Si8422Ax, Bx
VDD1
VDD2
VDD1
VDD2
1.6
1.1
0.40
2.0
—
loh = –4 mA
VDD1,VDD2 – 0.
4
VOL
lol = 4 mA
—
—
IL
ZO
—
DC Supply Current (All inputs 0 V or at supply)
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1.0
1.0
3.0
1.0
1.5
1.5
4.5
1.5
mA
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1.3
1.7
5.8
1.7
2.0
2.6
8.7
2.6
mA
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1.7
1.7
3.7
3.7
2.6
2.6
5.6
5.6
mA
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
3.7
3.7
1.7
1.7
5.6
5.6
2.6
2.6
mA
Notes:
1. Specifications in this table are also valid at VDD1 = 2.6 V and VDD2 = 2.6 V when the operating temperature range is
constrained to TA = 0 to 85 °C.
2. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
3. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
4. Start-up time is the time period from the application of power to valid data at the output.
12
Rev. 1.2
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
Table 3. Electrical Characteristics1 (Continued)
(VDD1 = 2.70 V, VDD2 = 2.70 V, TA = –40 to 125 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Si8423Ax, Bx
All inputs 0 DC
—
5.4
8.1
VDD1
VDD2
All inputs 0 DC
—
1.7
2.6
VDD1
All inputs 1 DC
—
1.3
2.0
VDD2
All inputs 1 DC
—
1.7
2.6
1 Mbps Supply Current (All inputs = 500 kHz square wave, CL = 15 pF on all outputs)
Si8410Ax, Bx
VDD1
—
2.0
3.0
VDD2
—
1.1
1.7
Si8420Ax, Bx
—
3.5
5.3
VDD1
VDD2
—
1.9
2.9
Si8421Ax, Bx
VDD1
—
2.8
4.2
VDD2
—
2.8
4.2
Si8422Ax, Bx
VDD1
—
2.8
4.2
VDD2
—
2.8
4.2
Si8423Ax, Bx
—
3.3
5.0
VDD1
VDD2
—
1.8
2.8
10 Mbps Supply Current (All inputs = 5 MHz square wave, CL = 15 pF on all outputs)
Si8410Bx
VDD1
VDD2
Si8420Bx
VDD1
VDD2
Si8421Bx
VDD1
VDD2
Unit
mA
mA
mA
mA
mA
mA
—
—
2.0
1.1
3.0
1.7
mA
—
—
3.5
2.1
5.3
3.0
mA
—
—
2.9
2.9
4.3
4.3
mA
Notes:
1. Specifications in this table are also valid at VDD1 = 2.6 V and VDD2 = 2.6 V when the operating temperature range is
constrained to TA = 0 to 85 °C.
2. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
3. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
4. Start-up time is the time period from the application of power to valid data at the output.
Rev. 1.2
13
Si8410/20/21 (5 kV)
Si8 422/23 ( 2. 5 & 5 k V)
Table 3. Electrical Characteristics1 (Continued)
(VDD1 = 2.70 V, VDD2 = 2.70 V, TA = –40 to 125 °C)
Min
Typ
Max
Unit
—
—
2.9
2.9
4.3
4.3
mA
—
3.4
5.1
—
2.0
2.9
100 Mbps Supply Current (All inputs = 50 MHz square wave, CL = 15 pF on all outputs)
mA
Parameter
Si8422Bx
VDD1
VDD2
Si8423Bx
VDD1
VDD2
Symbol
Test Condition
Si8410Bx
VDD1
VDD2
Si8420Bx
VDD1
VDD2
Si8421Bx
VDD1
VDD2
Si8422Bx
VDD1
VDD2
Si8423Bx
VDD1
VDD2
—
—
2.0
2.0
3.0
3.0
mA
—
—
3.5
5.5
5.3
6.9
mA
—
—
4.6
4.6
5.8
5.8
mA
—
—
4.6
4.6
5.8
5.8
mA
—
—
3.4
5.2
5.1
6.5
mA
0
—
—
—
—
—
—
—
1.0
250
35
25
Mbps
ns
ns
ns
—
—
—
—
40
35
ns
ns
0
—
150
Mbps
Timing Characteristics
Si841xAx, Si842xAx
Maximum Data Rate
Minimum Pulse Width
Propagation Delay
Pulse Width Distortion
|tPLH - tPHL|
Propagation Delay Skew3
Channel-Channel Skew
Si841xBx, Si842xBx
Maximum Data Rate
tPHL, tPLH
PWD
See Figure 1
See Figure 1
tPSK(P-P)
tPSK
Notes:
1. Specifications in this table are also valid at VDD1 = 2.6 V and VDD2 = 2.6 V when the operating temperature range is
constrained to TA = 0 to 85 °C.
2. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
3. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
4. Start-up time is the time period from the application of power to valid data at the output.
14
Rev. 1.2
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
Table 3. Electrical Characteristics1 (Continued)
(VDD1 = 2.70 V, VDD2 = 2.70 V, TA = –40 to 125 °C)
Parameter
Minimum Pulse Width
Propagation Delay
Pulse Width Distortion
|tPLH - tPHL|
Propagation Delay Skew3
Channel-Channel Skew
All Models
Output Rise Time
Output Fall Time
Symbol
Test Condition
Min
Typ
Max
Unit
tPHL, tPLH
PWD
See Figure 1
See Figure 1
—
4.0
—
—
8.0
1.5
6.0
11
3.0
ns
ns
ns
—
—
2.0
0.5
3.0
1.5
ns
ns
tPSK(P-P)
tPSK
tr
tf
CL = 15 pF
CL = 15 pF
—
—
2.0
2.0
4.0
4.0
ns
ns
Peak Eye Diagram Jitter
tJIT(PK)
See Figure 6
—
350
—
ps
Common Mode Transient
Immunity
Start-up Time4
CMTI
VI = VDD or 0 V
20
45
—
kV/µs
—
15
40
µs
tSU
Notes:
1. Specifications in this table are also valid at VDD1 = 2.6 V and VDD2 = 2.6 V when the operating temperature range is
constrained to TA = 0 to 85 °C.
2. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
3. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
4. Start-up time is the time period from the application of power to valid data at the output.
Table 4. Absolute Maximum Ratings1
Parameter
Symbol
Min
Typ
Max
Unit
TSTG
–65
—
150
C°
TA
–40
—
125
C°
VDD1, VDD2
–0.5
—
6.0
V
Input Voltage
VI
–0.5
—
VDD + 0.5
V
Output Voltage
VO
–0.5
—
VDD + 0.5
V
Output Current Drive Channel
IO
—
—
10
mA
Lead Solder Temperature (10 s)
—
—
260
C°
Maximum Isolation Voltage (1 s) NB SOIC-8
—
—
4500
VRMS
Maximum Isolation Voltage (1 s) WB SOIC-16
—
—
6500
VRMS
Storage Temperature
2
Operating Temperature
Supply Voltage
Notes:
1. Permanent device damage may occur if the above absolute maximum ratings are exceeded. Functional operation
should be restricted to conditions as specified in the operational sections of this data sheet.
2. VDE certifies storage temperature from –40 to 150 °C.
Rev. 1.2
15
Si8410/20/21 (5 kV)
Si8 422/23 ( 2. 5 & 5 k V)
Table 5. Recommended Operating Conditions
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Ambient Operating Temperature*
TA
150 Mbps, 15 pF, 5 V
–40
25
125
C°
VDD1
2.70
—
5.5
V
VDD2
2.70
—
5.5
V
Supply Voltage
*Note: The maximum ambient temperature is dependent upon data frequency, output loading, the number of operating
channels, and supply voltage.
Table 6. Regulatory Information*
CSA
The Si84xx is certified under CSA Component Acceptance Notice 5A. For more details, see File 232873.
61010-1: Up to 600 VRMS reinforced insulation working voltage; up to 600 VRMS basic insulation working voltage.
60950-1: Up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage.
60601-1: Up to 125 VRMS reinforced insulation working voltage; up to 380 VRMS basic insulation working voltage.
VDE
The Si84xx is certified according to IEC 60747-5-2. For more details, see File 5006301-4880-0001.
60747-5-2: Up to 891 Vpeak for basic insulation working voltage.
60950-1: Up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage.
UL
The Si84xx is certified under UL1577 component recognition program. For more details, see File E257455.
Rated up to 5000 VRMS isolation voltage for basic insulation.
*Note: Regulatory Certifications apply to 2.5 kVRMS rated devices which are production tested to 3.0 kVRMS for 1 sec.
Regulatory Certifications apply to 5.0 kVRMS rated devices which are production tested to 6.0 kVRMS for 1 sec.
For more information, see "6. Ordering Guide" on page 29.
16
Rev. 1.2
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
Table 7. Insulation and Safety-Related Specifications
Value
Parameter
Symbol
Test Condition
WB
SOIC-16
NB
SOIC-8
Unit
Nominal Air Gap (Clearance)1
L(IO1)
8.0 min
4.9 min
mm
Nominal External Tracking (Creepage)1
L(IO2)
8.0 min
4.01 min
mm
0.014
0.008
mm
600
600
VRMS
ED
0.019
0.040
mm
RIO
101,2
101,2
2.0
1.0
pF
4.0
4.0
pF
Minimum Internal Gap (Internal Clearance)
Tracking Resistance
(Proof Tracking Index)
PTI
Erosion Depth
Resistance (Input-Output)
2
Capacitance (Input-Output)2
Input Capacitance
CIO
3
IEC60112
f = 1 MHz
CI
Notes:
1. The values in this table correspond to the nominal creepage and clearance values as detailed in “7. Package Outline:
16-Pin Wide Body SOIC”, “9. Package Outline: 8-Pin Narrow Body SOIC”. VDE certifies the clearance and creepage
limits as 8.5 mm minimum for the WB SOIC-16 package and 4.7 mm minimum for the NB SOIC-8 package. UL does
not impose a clearance and creepage minimum for component level certifications. CSA certifies the clearance and
creepage limits as 3.9 mm minimum for the NB SOIC-8 and 7.6 mm minimum for the WB SOIC-16 package.
2. To determine resistance and capacitance, the Si84xx is converted into a 2-terminal device. Pins 1–8 (1–4, NB SOIC-8)
are shorted together to form the first terminal and pins 9–16 (5–8, NB SOIC-8) are shorted together to form the second
terminal. The parameters are then measured between these two terminals.
3. Measured from input pin to ground.
Table 8. IEC 60664-1 (VDE 0844 Part 2) Ratings
Parameter
Basic Isolation Group
Installation Classification
Test Conditions
Specification
NB SOIC8
WB SOIC 16
I
I
Rated Mains Voltages < 150 VRMS
I-IV
I-IV
Rated Mains Voltages < 300 VRMS
I-III
I-IV
Rated Mains Voltages < 400 VRMS
I-II
I-III
Rated Mains Voltages < 600 VRMS
I-II
I-III
Material Group
Rev. 1.2
17
Si8410/20/21 (5 kV)
Si8 422/23 ( 2. 5 & 5 k V)
Table 9. IEC 60747-5-2 Insulation Characteristics for Si84xxxx*
Characteristic
Symbol
Parameter
Maximum Working Insulation
Voltage
Test Condition
WB
SOIC-16
NB SOIC-8
891
560
Method b1
(VIORM x 1.875 = VPR, 100%
Production Test, tm = 1 sec,
Partial Discharge < 5 pC)
1671
1050
t = 60 sec
6000
4000
2
2
>109
>109
VIORM
Input to Output Test Voltage
VIOTM
Transient Overvoltage
Pollution Degree
(DIN VDE 0110, Table 1)
Insulation Resistance at TS,
VIO = 500 V
RS
Unit
Vpeak
Vpeak
*Note: Maintenance of the safety data is ensured by protective circuits. The Si84xx provides a climate classification of
40/125/21.
Table 10. IEC Safety Limiting Values1
Max
Parameter
Symbol
Case Temperature
TS
Safety Input, Output, or
Supply Current
IS
Device Power
Dissipation2
PD
Test Condition
JA = 140 °C/W (NB SOIC-8),
100 °C (WB SOIC-16),
VI = 5.5 V, TJ = 150 °C, TA = 25 °C
Min Typ
WB
SOIC-16
NB
SOIC-8
Unit
—
—
150
150
°C
—
—
220
160
mA
—
—
150
150
mW
Notes:
1. Maximum value allowed in the event of a failure; also see the thermal derating curve in Figures 2 and 3.
2. The Si84xx is tested with VDD1 = VDD2 = 5.5 V, TJ = 150 ºC, CL = 15 pF, input a 150 Mbps 50% duty cycle square
wave.
18
Rev. 1.2
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
Table 11. Thermal Characteristics
Parameter
Safety-Limiting Values (mA)
IC Junction-to-Air Thermal Resistance
Symbol
WB SOIC-16
NB SOIC-8
Unit
JA
100
140
ºC/W
500
460
VDD1, VDD2 = 2.70 V
375 360
250
VDD1, VDD2 = 3.3 V
220
VDD1, VDD2 = 5.5 V
125
0
0
50
100
150
Case Temperature (ºC)
200
Safety-Limiting Values (mA)
Figure 2. (WB SOIC-16) Thermal Derating Curve, Dependence of Safety Limiting Values
with Case Temperature per DIN EN 60747-5-2
400
320
VDD1, VDD2 = 2.70 V
300 270
200
VDD1, VDD2 = 3.3 V
160
VDD1, VDD2 = 5.5 V
100
0
0
50
100
150
Case Temperature (ºC)
200
Figure 3. (NB SOIC-8) Thermal Derating Curve, Dependence of Safety Limiting Values
with Case Temperature per DIN EN 60747-5-2
Rev. 1.2
19
Si8410/20/21 (5 kV)
Si8 422/23 ( 2. 5 & 5 k V)
2. Functional Description
2.1. Theory of Operation
The operation of an Si84xx channel is analogous to that of an opto coupler, except an RF carrier is modulated
instead of light. This simple architecture provides a robust isolated data path and requires no special
considerations or initialization at start-up. A simplified block diagram for a single Si84xx channel is shown in
Figure 4.
Transmitter
Receiver
RF
OSCILLATOR
A
MODULATOR
SemiconductorBased Isolation
Barrier
DEMODULATOR
B
Figure 4. Simplified Channel Diagram
A channel consists of an RF Transmitter and RF Receiver separated by a semiconductor-based isolation barrier.
Referring to the Transmitter, input A modulates the carrier provided by an RF oscillator using on/off keying. The
Receiver contains a demodulator that decodes the input state according to its RF energy content and applies the
result to output B via the output driver. This RF on/off keying scheme is superior to pulse code schemes as it
provides best-in-class noise immunity, low power consumption, and better immunity to magnetic fields. See
Figure 5 for more details.
Input Signal
Modulation Signal
Output Signal
Figure 5. Modulation Scheme
20
Rev. 1.2
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
2.2. Eye Diagram
Figure 6 illustrates an eye-diagram taken on an Si8422. For the data source, the test used an Anritsu (MP1763C)
Pulse Pattern Generator set to 1000 ns/div. The output of the generator's clock and data from an Si8422 were
captured on an oscilloscope. The results illustrate that data integrity was maintained even at the high data rate of
150 Mbps. The results also show that 2 ns pulse width distortion and 250 ps peak jitter were exhibited.
Figure 6. Eye Diagram
Rev. 1.2
21
Si8410/20/21 (5 kV)
Si8 422/23 ( 2. 5 & 5 k V)
3. Device Operation
Device behavior during start-up, normal operation, and shutdown is shown in Figure 7, where UVLO+ and UVLOare the positive-going and negative-going thresholds respectively. Refer to Table 12 to determine outputs when
power supply (VDD) is not present.
Table 12. Si84xx Logic Operation Table
VI Input1,4 VDDI State1,2,3 VDDO State1,2,3
VO Output1,4
H
P
P
H
L
P
P
L
X5
UP
P
Comments
Normal operation.
H6 (Si8422/23) Upon transition of VDDI from unpowered to
(Si8410/20/21) powered, VO returns to the same state as VI in
less than 1 µs.
L6
X5
P
UP
Undetermined
Upon transition of VDDO from unpowered to
powered, VO returns to the same state as VI
within 1 µs.
Notes:
1. VDDI and VDDO are the input and output power supplies. VI and VO are the respective input and output terminals.
2. Powered (P) state is defined as 2.70 V < VDD < 5.5 V.
3. Unpowered (UP) state is defined as VDD = 0 V.
4. X = not applicable; H = Logic High; L = Logic Low.
5. Note that an I/O can power the die for a given side through an internal diode if its source has adequate current.
6. See "6. Ordering Guide" on page 29 for details. This is the selectable fail-safe operating mode (ordering option). Some
devices have default output state = H, and some have default output state = L, depending on the ordering part number
(OPN).
22
Rev. 1.2
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
3.1. Device Startup
Outputs are held low during powerup until VDD is above the UVLO threshold for time period tSTART. Following this,
the outputs follow the states of inputs.
3.2. Under Voltage Lockout
Under Voltage Lockout (UVLO) is provided to prevent erroneous operation during device startup and shutdown or
when VDD is below its specified operating circuits range. Both Side A and Side B each have their own undervoltage
lockout monitors. Each side can enter or exit UVLO independently. For example, Side A unconditionally enters
UVLO when VDD1 falls below VDD1(UVLO–) and exits UVLO when VDD1 rises above VDD1(UVLO+). Side B operates
the same as Side A with respect to its VDD2 supply.
UVLO+
UVLO-
VDD1
UVLO+
UVLO-
VDD2
INPUT
tSTART
tSD
tSTART
tSTART
tPHL
tPLH
OUTPUT
Figure 7. Device Behavior during Normal Operation
Rev. 1.2
23
Si8410/20/21 (5 kV)
Si8 422/23 ( 2. 5 & 5 k V)
3.3. Layout Recommendations
To ensure safety in the end user application, high voltage circuits (i.e., circuits with >30 VAC) must be physically
separated from the safety extra-low voltage circuits (SELV is a circuit with
工商网监
湘ICP备2023018690号
