Si8630/31/35 Data Sheet
Low-Power Triple-Channel Digital Isolators
KEY FEATURES
Skyworks' family of ultra-low-power digital isolators are CMOS devices offering substantial data rate, propagation delay, power, size, reliability, and external BOM advantages
over legacy isolation technologies. The operating parameters of these products remain
stable across wide temperature ranges and throughout device service life for ease of
design and highly uniform performance. All device versions have Schmitt trigger inputs
for high noise immunity and only require VDD bypass capacitors.
• High-speed operation
• DC to 150 Mbps
• No start-up initialization required
• Wide Operating Supply Voltage
• 2.5–5.5 V
Data rates up to 150 Mbps are supported, and all devices achieve propagation delays
of less than 10 ns. Ordering options include a choice of isolation ratings (2.5, 3.75 and
5 kV) and a selectable fail-safe operating mode to control the default output state during
power loss. All products are safety certified by UL, CSA, VDE, and CQC, and products
in wide-body packages support reinforced insulation withstanding up to 5 kVRMS.
• Up to 5000 VRMS isolation
Automotive Grade is available for certain part numbers. These products are built using
automotive-specific flows at all steps in the manufacturing process to ensure the robustness and low defectivity required for automotive applications.
• Ultra low power (typical)
Industrial Applications
• Industrial automation systems
• Medical electronics
• Isolated switch mode supplies
• Isolated ADC, DAC
• Motor control
• Power inverters
• Communications systems
Safety Regulatory Approvals
• UL 1577 recognized
• Up to 5000 VRMS for 1 minute
• CSA component notice 5A approval
• IEC 60950-1, 61010-1, 60601-1 (reinforced insulation)
• VDE certification conformity
• Si862xxT options certified to reinforced VDE 0884-10
• All other options certified to IEC
60747-5-5 and reinforced 60950-1
• CQC certification approval
• GB4943.1
Automotive Applications
• On-board chargers
• Battery management systems
• Charging stations
• Traction inverters
• Hybrid Electric Vehicles
• Battery Electric Vehicles
• Reinforced VDE 0884-10, 10 kV surgecapable (Si862xxT)
• 60-year life at rated working voltage
• High electromagnetic immunity
5 V Operation
• 1.6 mA per channel at 1 Mbps
• 5.5 mA per channel at 100 Mbps
2.5 V Operation
• 1.5 mA per channel at 1 Mbps
• 3.5 mA per channel at 100 Mbps
• Schmitt trigger inputs
• Selectable fail-safe mode
• Default high or low output (ordering
option)
• Precise timing (typical)
• 10 ns propagation delay
• 1.5 ns pulse width distortion
• 0.5 ns channel-channel skew
• 2 ns propagation delay skew
• 5 ns minimum pulse width
• Transient Immunity 50 kV/µs
• AEC-Q100 qualification
• Wide temperature range
• –40 to 125 °C
• RoHS-compliant packages
• SOIC-16 wide body
• SOIC-16 narrow body
• Automotive-grade OPNs available
• AIAG compliant PPAP documentation
support
• IMDS and CAMDS listing support
1
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Si8630/31/35 Data Sheet • Ordering Guide
1. Ordering Guide
Industrial and Automotive Grade OPNs
Industrial-grade devices (part numbers having an “-I” in their suffix) are built using well-controlled, high-quality manufacturing flows to
ensure robustness and reliability. Qualifications are compliant with JEDEC, and defect reduction methodologies are used throughout
definition, design, evaluation, qualification, and mass production steps.
Automotive-grade devices (part numbers having an “-A” in their suffix) are built using automotive-specific flows at all steps in the
manufacturing process to ensure robustness and low defectivity. These devices are supported with AIAG-compliant Production Part
Approval Process (PPAP) documentation, and feature International Material Data System (IMDS) and China Automotive Material
Data System (CAMDS) listing. Qualifications are compliant with AEC-Q100, and a zero-defect methodology is maintained throughout
definition, design, evaluation, qualification, and mass production steps.
Table 1.1. Ordering Guide for Valid OPNs1, 2, 4
Ordering Part Number
(OPN)
Automotive OPNs5, 6
Number Number Max Data
of Inputs of Inputs
Rate
VDD1
VDD2
(Mbps)
Side
Side
Default
Output
State
Isolation
Rating
(kVrms)
Package
Si8630BB-B-IS
Si8630BB-AS
3
0
150
Low
2.5
WB SOIC-16
Si8630BB-B-IS1
Si8630BB-AS1
3
0
150
Low
2.5
NB SOIC-16
Si8630BC-B-IS1
Si8630BC-AS1
3
0
150
Low
3.75
NB SOIC-16
Si8630EC-B-IS1
Si8630EC-AS1
3
0
150
High
3.75
NB SOIC-16
Si8630BD-B-IS
Si8630BD-AS
3
0
150
Low
5.0
WB SOIC-16
Si8630ED-B-IS
Si8630ED-AS
3
0
150
High
5.0
WB SOIC-16
Si8631BB-B-IS
Si8631BB-AS
2
1
150
Low
2.5
WB SOIC-16
Si8631BB-B-IS1
Si8631BB-AS1
2
1
150
Low
2.5
NB SOIC-16
Si8631BC-B-IS1
Si8631BC-AS1
2
1
150
Low
3.75
NB SOIC-16
Si8631EC-B-IS1
Si8631EC-AS1
2
1
150
High
3.75
NB SOIC-16
Si8631BD-B-IS
Si8631BD-AS
2
1
150
Low
5.0
WB SOIC-16
Si8631ED-B-IS
Si8631ED-AS
2
1
150
High
5.0
WB SOIC-16
Si8635BB-B-IS
Si8635BB-AS
3
0
150
Low
2.5
WB SOIC-16
Si8635BC-B-IS1
Si8635BC-AS1
3
0
150
Low
3.75
NB SOIC-16
Si8635BD-B-IS
Si8635BD-AS
3
0
150
Low
5.0
WB SOIC-16
Product Options with Reinforced VDE 0884-10 Rating with 10 kV Surge Capability
2
Si8630BT-IS
Si8630BT-AS
3
0
150
Low
5.0
WB SOIC-16
Si8630ET-IS
Si8630ET-AS
3
0
150
High
5.0
WB SOIC-16
Si8631BT-IS
Si8631BT-AS
2
1
150
Low
5.0
WB SOIC-16
Si8631ET-IS
Si8631ET-AS
2
1
150
High
5.0
WB SOIC-16
Si8635BT-IS
Si8635BT-AS
3
0
150
Low
5.0
WB SOIC-16
Si8635ET-IS
Si8635ET-AS
3
0
150
High
5.0
WB SOIC-16
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Si8630/31/35 Data Sheet • Ordering Guide
Ordering Part Number
(OPN)
Automotive OPNs5, 6
Number Number Max Data
of Inputs of Inputs
Rate
VDD1
VDD2
(Mbps)
Side
Side
Default
Output
State
Isolation
Rating
(kVrms)
Package
Note:
1. All packages are RoHS-compliant with peak reflow temperatures of 260 °C according to the JEDEC industry standard classifications and peak solder temperatures.
2. “Si” and “SI” are used interchangeably.
3. An "R" at the end of the part number denotes tape and reel packaging option.
4. The temperature ranges is –40 to +125 °C.
5. Automotive-Grade devices (with an "–A" suffix) are identical in construction materials, topside marking, and electrical parameters
to their Industrial-Grade (with an "–I" suffix) version counterparts. Automotive-Grade products are produced utilizing full automotive process flows and additional statistical process controls throughout the manufacturing flow. The Automotive-Grade part
number is included on shipping labels.
6. In the top markings of each device, the Manufacturing Code represented by either “RTTTTT” or “TTTTTT” contains as its first
character a letter in the range N through Z to indicate Automotive-Grade.
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Table of Contents
1. Ordering Guide
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2. System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1 Theory of Operation .
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2.2 Eye Diagram.
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3. Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1 Device Startup .
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3.2 Undervoltage Lockout
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3.3 Layout Recommendations .
3.3.1 Supply Bypass . . .
3.3.2 Output Pin Termination .
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3.4 Fail-Safe Operating Mode .
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3.5 Typical Performance Characteristis .
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.10
4. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .11
5. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
26
6. Package Outline: 16-Pin Wide Body SOIC. . . . . . . . . . . . . . . . . . . .
27
7. Land Pattern: 16-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . . . .
29
8. Package Outline: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . .
30
9. Land Pattern: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . .
32
10. Top Marking: 16-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . . . .
33
11. Top Marking: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . .
34
12. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
35
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Si8630/31/35 Data Sheet • System Overview
2. System Overview
2.1 Theory of Operation
The operation of an Si863x channel is analogous to that of an opto coupler, except an RF carrier is modulated instead of light. This
simple architecture provides a robust isolated data path and requires no special considerations or initialization at start-up. A simplified
block diagram for a single Si863x channel is shown in the figure below.
Figure 2.1. Simplified Channel Diagram
A channel consists of an RF Transmitter and RF Receiver separated by a semiconductor-based isolation barrier. Referring to the
transmitter, input A modulates the carrier provided by an RF oscillator using on/off keying. The Receiver contains a demodulator that
decodes the input state according to its RF energy content and applies the result to output B via the output driver. This RF on/off keying
scheme is superior to pulse code schemes as it provides best-in-class noise immunity, low power consumption, and improved immunity
to magnetic fields. See the following figure for more details.
Figure 2.2. Modulation Scheme
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Si8630/31/35 Data Sheet • System Overview
2.2 Eye Diagram
The figure below illustrates an eye diagram taken on an Si8630. For the data source, the test used an Anritsu (MP1763C) Pulse Pattern
Generator set to 1000 ns/div. The output of the generator's clock and data from an Si8630 were captured on an oscilloscope set to 1.0
ns/div. The results illustrate that data integrity was maintained even at the high data rate of 150 Mbps. The results also show that 2 ns
pulse width distortion and 350 ps peak jitter were exhibited.
Figure 2.3. Eye Diagram
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Si8630/31/35 Data Sheet • Device Operation
3. Device Operation
Device behavior during start-up, normal operation, and shutdown is shown in Figure 3.1 Device Behavior during Normal Operation on
page 9, where UVLO+ and UVLO– are the respective positive-going and negative-going thresholds. Refer to the following tables to
determine outputs when power supply (VDD) is not present and for logic conditions when enable pins are used.
Table 3.1. Si86xx Logic Operation
VI Input1, 2 EN Input1, 2, 3, 4
VDDI State1, 5, 6
VDDO State1, 5, 6
VO Output1, 2
Comments
H
H or NC
P
P
H
L
H or NC
P
P
L
X7
L
P
P
Hi-Z8
NC
H or NC
P
P
L9
Output L for default low product options.
H9
Output H for default high product options.
L9
Upon transition of VDDI from unpowered to
powered, VO returns to the same state as VI
in less than 1 µs.
X7
H or NC
UP
P
H9
X7
L
UP
P
X7
X7
P
UP
Hi-Z8
Enabled, normal operation.
Disabled.
Disabled.
Undetermined Upon transition of VDDO from unpowered to
powered, VO returns to the same state as VI
within 1 µs, if EN is in either the H or NC
state. Upon transition of VDDO from unpowered to powered, VO returns to Hi-Z within 1
µs if EN is L.
Note:
1. VDDI and VDDO are the input and output power supplies. VI and VO are the respective input and output terminals. EN is the
enable control input located on the same output side.
2. X = not applicable; H = Logic High; L = Logic Low; Hi-Z = High Impedance.
3. It is recommended that the enable inputs be connected to an external logic high or low level when the Si86xx is operating in noisy
environments.
4. No Connect (NC) replaces EN1 on Si86x0/x5. No Connect replaces EN2 on the Si86x5. No Connects are not internally connected and can be left floating, tied to VDD, or tied to GND.
5. “Powered” state (P) is defined as 2.5 V < VDD < 5.5 V.
6. “Unpowered” state (UP) is defined as VDD = 0 V.
7. Note that an I/O can power the die for a given side through an internal diode if its source has adequate current.
8. When using the enable pin (EN) function, the output pin state is driven into a high-impedance state when the EN pin is disabled
(EN = 0).
9. See Section 1. Ordering Guide for details. This is the selectable fail-safe operating mode (ordering option). Some devices have
default output state = H, and some have default output state = L, depending on the ordering part number (OPN). For default high
devices, the data channels have 2 μA (Si86xxxA/B/C/D) or 10 μA (Si86xxxT) pull-ups on inputs/outputs. For default low devices,
the data channels have 2 μA (Si86xxxA/B/C/D) or 10 μA (Si86xxxT) pull-downs on inputs/outputs.
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Si8630/31/35 Data Sheet • Device Operation
Table 3.2. Enable Input Truth
Part Number
EN11, 2
EN21, 2
Si8630
—
H
Outputs B1, B2, B3 are enabled and follow input state.
—
L
Outputs B1, B2, B3 are disabled and in high impedance state.3
H
X
Output A3 enabled and follows the input state.
L
X
Output A3 disabled and in high impedance state.3
X
H
Outputs B1, B2 are enabled and follow the input state.
X
L
Outputs B1, B2 are disabled and in high impedance state.3
—
—
Outputs B1, B2, B3 are enabled and follow the input state.
Si8631
Si8635
Operation
Note:
1. Enable inputs EN1 and EN2 can be used for multiplexing, for clock sync, or other output control. These inputs are internally
pulled-up to local VDD allowing them to be connected to an external logic level (high or low) or left floating. To minimize noise
coupling, do not connect circuit traces to EN1 or EN2 if they are left floating. If EN1, EN2 are unused, it is recommended they be
connected to an external logic level, especially if the Si86xx is operating in a noisy environment.
2. X = not applicable; H = Logic High; L = Logic Low.
3. When using the enable pin (EN) function, the output pin state is driven into a high-impedance state when the EN pin is disabled
(EN = 0).
8
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Si8630/31/35 Data Sheet • Device Operation
3.1 Device Startup
Outputs are held low during powerup until VDD is above the UVLO threshold for time period tSTART. Following this, the outputs follow
the states of inputs.
3.2 Undervoltage Lockout
Undervoltage Lockout (UVLO) is provided to prevent erroneous operation during device startup and shutdown or when VDD is below its
specified operating circuits range. Both Side A and Side B each have their own undervoltage lockout monitors. Each side can enter or
exit UVLO independently. For example, Side A unconditionally enters UVLO when VDD1 falls below VDD1(UVLO–) and exits UVLO when
VDD1 rises above VDD1(UVLO+). Side B operates the same as Side A with respect to its VDD2 supply.
Figure 3.1. Device Behavior during Normal Operation
3.3 Layout Recommendations
To ensure safety in the end-user application, high-voltage circuits (i.e., circuits with >30 VAC) must be physically separated from the
safety extra-low-voltage circuits (SELV is a circuit with 109
>109
>109
VIORM
Method b1
Input to Output Test Voltage
(VIORM x 1.875 = VPR, 100%
VPR
Production Test, tm = 1 sec,
Partial Discharge < 5 pC)
Transient Overvoltage
(Si86xxxA/B/C/D)
Transient Overvoltage
(Si86xxxT)
VIOTM
t = 60 sec
Vpeak
Tested per IEC 60065 with surge
voltage of 1.2 µs/50 µs
VIOSM
Surge Voltage
Vpeak
Pollution Degree
(DIN VDE 0110, Table 1)
Insulation Resistance at TS, VIO
= 500 V
RS
Ω
Note:
1. Maintenance of the safety data is ensured by protective circuits. The Si86xx provides a climate classification of 40/125/21.
Table 4.9. IEC Safety Limiting Values 1
Parameter
Symbol
Case Temperature
TS
Safety Input, Output, or Supply Current
IS
Test Condition
θJA = 100 °C/W (WB SOIC-16)
Max
Unit
WB SOIC-16
NB SOIC-16
150
150
°C
220
210
mA
275
275
mW
105 °C/W (NB SOIC-16)
VI = 5.5 V, TJ = 150 °C, TA = 25 °C
Device Power Dissipation 2
PD
Note:
1. Maximum value allowed in the event of a failure; also see the thermal derating curve in Figure 4.4 (WB SOIC-16) Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per DIN EN 60747-5-5/VDE 0884-10, as Applies on
page 24 and Figure 4.5 (NB SOIC-16) Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature
per DIN EN 60747-5-5/VDE 0884-10, as Applies on page 24.
2. The Si86xx is tested with VDD1 = VDD2 = 5.5 V; TJ = 150 ºC; CL = 15 pF, input a 150 Mbps 50% duty cycle square wave.
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Si8630/31/35 Data Sheet • Electrical Specifications
Table 4.10. Thermal Characteristics
Parameter
IC Junction-to-Air Thermal Resistance
Symbol
WB SOIC-16
NB SOIC-16
Unit
θJA
100
105
°C/W
Figure 4.4. (WB SOIC-16) Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per DIN EN
60747-5-5/VDE 0884-10, as Applies
Figure 4.5. (NB SOIC-16) Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per DIN EN
60747-5-5/VDE 0884-10, as Applies
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Si8630/31/35 Data Sheet • Electrical Specifications
Table 4.11. Absolute Maximum Ratings 1
Parameter
Symbol
Min
Max
Unit
Storage Temperature 2
TSTG
–65
150
°C
Operating Temperature
TA
–40
125
°C
Junction Temperature
TJ
—
150
°C
VDD1, VDD2
–0.5
7.0
V
Input Voltage
VI
–0.5
VDD + 0.5
V
Output Voltage
VO
–0.5
VDD + 0.5
V
Output Current Drive Channel
IO
—
10
mA
Lead Solder Temperature (10 s)
—
260
°C
Maximum Isolation (Input to Output) (1 sec)
—
4500
VRMS
—
6500
VRMS
Supply Voltage
NB SOIC-16
Maximum Isolation (Input to Output) (1 sec)
WB SOIC-16
Note:
1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be restricted
to conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum ratings for exteneded
periods may degrade performance.
2. VDE certifies storage temperature from –40 to 150 °C.
25
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Si8630/31/35 Data Sheet • Pin Descriptions
5. Pin Descriptions
VDD1
GND2
GND1
A1
RF
XMITR
A2
RF
XMITR
A3
RF
XMITR
NC
I
s
o
l
a
t
i
o
n
VDD2
GND2
GND1
RF
RCVR
B1
A1
RF
XMITR
RF
RCVR
B2
A2
RF
XMITR
RF
RCVR
B3
A3
RF
RCVR
NC
NC
EN2/NC
NC
GND1
VDD1
VDD2
RF
RCVR
B1
RF
RCVR
B2
RF
XMITR
B3
NC
EN2
EN1
GND2
Si8630/35
I
s
o
l
a
t
i
o
n
GND1
GND2
Si8631
Name
SOIC-16 Pin#
Type
Description
VDD1
1
Supply
Side 1 power supply.
GND1
21
Ground
Side 1 ground.
A1
3
Digital Input
Side 1 digital input.
A2
4
Digital Input
Side 1 digital input.
A3
5
Digital I/O
NC
6
NA
EN1/NC2
7
Digital Input
GND1
81
Ground
Side 1 ground.
GND2
91
Ground
Side 2 ground.
EN2/NC2
10
Digital Input
NC
11
NA
B3
12
Digital I/O
B2
13
Digital Output
Side 2 digital output.
B1
14
Digital Output
Side 2 digital output.
GND2
151
Ground
Side 2 ground.
VDD2
16
Supply
Side 2 power supply.
Side 1 digital input or output.
No Connect.
Side 1 active high enable. NC on Si8630/35
Side 2 active high enable. NC on Si8635.
No Connect.
Side 2 digital input or output.
Note:
1. For narrow-body devices, Pin 2 and Pin 8 GND must be externally connected to respective ground. Pin 9 and Pin 15 must also be
connected to external ground.
2. No Connect. These pins are not internally connected. They can be left floating, tied to VDD or tied to GND.
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Si8630/31/35 Data Sheet • Package Outline: 16-Pin Wide Body SOIC
6. Package Outline: 16-Pin Wide Body SOIC
The figure below illustrates the package details for the Triple-Channel Digital Isolator. The table lists the values for the dimensions
shown in the illustration.
Figure 6.1. 16-Pin Wide Body SOIC
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Si8630/31/35 Data Sheet • Package Outline: 16-Pin Wide Body SOIC
Table 6.1. 16-Pin Wide Body SOIC Package Diagram Dimensions1, 2, 3, 4
Dimension
Min
Max
A
—
2.65
A1
0.10
0.30
A2
2.05
—
b
0.31
0.51
c
0.20
0.33
D
10.30 BSC
E
10.30 BSC
E1
7.50 BSC
e
1.27 BSC
L
0.40
1.27
h
0.25
0.75
θ
0°
8°
aaa
—
0.10
bbb
—
0.33
ccc
—
0.10
ddd
—
0.25
eee
—
0.10
fff
—
0.20
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC Outline MS-013, Variation AA.
4. Recommended reflow profile per JEDEC J-STD-020 specification for small body, lead-free components.
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Si8630/31/35 Data Sheet • Land Pattern: 16-Pin Wide Body SOIC
7. Land Pattern: 16-Pin Wide Body SOIC
The figure below illustrates the recommended land pattern details for the Si863x in a 16-pin wide-body SOIC package. The table lists
the values for the dimensions shown in the illustration.
Figure 7.1. PCB Land Pattern: 16-Pin Wide Body SOIC
Table 7.1. 16-Pin Wide Body SOIC Land Pattern Dimensions1, 2
Dimension
Feature
(mm)
C1
Pad Column Spacing
9.40
E
Pad Row Pitch
1.27
X1
Pad Width
0.60
Y1
Pad Length
1.90
Note:
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P1032X265-16AN for Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0.05 mm is assumed.
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Si8630/31/35 Data Sheet • Package Outline: 16-Pin Narrow Body SOIC
8. Package Outline: 16-Pin Narrow Body SOIC
The figure below illustrates the package details for the Si863x in a 16-pin narrow-body SOIC (SO-16). The table lists the values for the
dimensions shown in the illustration.
Figure 8.1. 16-Pin Narrow Body SOIC
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Si8630/31/35 Data Sheet • Package Outline: 16-Pin Narrow Body SOIC
Table 8.1. 16-Pin Narrow Body SOIC Package Diagram Dimensions1, 2, 3, 4
Dimension
Min
Max
A
—
1.75
A1
0.10
0.25
A2
1.25
—
b
0.31
0.51
c
0.17
0.25
D
9.90 BSC
E
6.00 BSC
E1
3.90 BSC
e
1.27 BSC
L
0.40
L2
1.27
0.25 BSC
h
0.25
0.50
θ
0°
8°
aaa
0.10
bbb
0.20
ccc
0.10
ddd
0.25
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MS-012, Variation AC.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
31
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Si8630/31/35 Data Sheet • Land Pattern: 16-Pin Narrow Body SOIC
9. Land Pattern: 16-Pin Narrow Body SOIC
The figure below illustrates the recommended land pattern details for the Si863x in a 16-pin narrow-body SOIC package. The table lists
the values for the dimensions shown in the illustration.
Figure 9.1. PCB Land Pattern: 16-Pin Narrow Body SOIC
Table 9.1. 16-Pin Narrow Body SOIC Land Pattern Dimensions1, 2
Dimension
Feature
(mm)
C1
Pad Column Spacing
5.40
E
Pad Row Pitch
1.27
X1
Pad Width
0.60
Y1
Pad Length
1.55
Note:
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P600X165-16N for Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0.05 mm is assumed.
32
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Si8630/31/35 Data Sheet • Top Marking: 16-Pin Wide Body SOIC
10. Top Marking: 16-Pin Wide Body SOIC
Si86XYSV
YYWWRTTTTT
e4
CC
Figure 10.1. 16-Pin Wide Body SOIC Top Marking
Table 10.1. 16-Pin Wide Body SOIC Top Marking Explanation
Line 1 Marking:
Base Part Number
Si86 = Isolator product series
Ordering Options
X = # of data channels (3)
(See 1. Ordering Guide for more
information.)
Y = # of reverse channels (5, 1, 0)1
S = Speed Grade (max data rate) and operating mode:
B = 150 Mbps (default output = low)
E = 150 Mbps (default output = high)
V = Insulation rating
B = 2.5 kV; C = 3.75 kV; D = 5.0 kV; T = 5.0 kV with 10 kV surge
capability.
Line 2 Marking:
YY = Year
WW = Workweek
RTTTTT = Mfg Code
Assigned by assembly subcontractor. Corresponds to the year
and workweek of the mold date.
Manufacturing code from assembly house
“R” indicates revision
Line 3 Marking:
Circle = 1.7 mm Diameter
“e4” Pb-Free Symbol
(Center-Justified)
Country of Origin ISO Code Ab- CC = Country of Origin ISO Code Abbreviation
breviation
• TW = Taiwan
• TH = Thailand
Note:
1. Si8635 has 0 reverse channels.
33
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Si8630/31/35 Data Sheet • Top Marking: 16-Pin Narrow Body SOIC
11. Top Marking: 16-Pin Narrow Body SOIC
e3
Si86XYSV
YYWWRTTTTT
Figure 11.1. 16-Pin Narrow Body SOIC Top Marking
Table 11.1. 16-Pin Narrow Body SOIC Top Marking Explanation
Line 1 Marking:
Base Part Number
Si86 = Isolator product series
Ordering Options
XY = Channel Configuration
X = # of data channels (3)
(See 1. Ordering Guide for more
information.)
Y = # of reverse channels (5, 1, 0)1
S = Speed Grade (max data rate) and operating mode:
B = 150 Mbps (default output = low)
E = 150 Mbps (default output = high)
V = Insulation rating
B = 2.5 kV; C = 3.75 kV
Line 2 Marking:
Circle = 1.2 mm Diameter
“e3” Pb-Free Symbol
YY = Year
Assigned by the Assembly House. Corresponds to the year and
work week of the mold date.
WW = Work Week
RTTTTT = Mfg Code
Manufacturing code from assembly house
“R” indicates revision
Note:
1. Si8635 has 0 reverse channels.
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Si8630/31/35 Data Sheet • Revision History
12. Revision History
Revision 1.84
June 2021
• Increased IDD1 max spec for Si8630xT/35xT from 3.9 mA to 4.9 mA for > 10 Mbps operation, based on production data.
• A row was added to the Table 3.1 Si86xx Logic Operation on page 7 to define the condition when both VDDs are powered up but
input is left not connected.
• Specified that 2 μA pull-ups/downs are integrated to enable the default high/low functions in Note 9, Table 3.1 Si86xx Logic
Operation on page 7
• A separate row was added to the VIOTM spec in Table 4.8 VDE 0884-10 Insulation Characteristics for Si86xx 1 on page 23 for all
Si86xxxT devices, value = 8000 V
Revision 1.83
September 2019
• Updated Ordering Guide.
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Si8630/31/35 Data Sheet • Revision History
Revision 1.82
March 2019
• Corrected document title.
Revision 1.81
January 2018
• Added new table to Ordering Guide for Automotive-Grade OPN options.
Revision 1.8
November 30th, 2016
• Added note to Ordering Guide table for denoting tape and reel marking.
Revision 1.7
July 19, 2016
• Added "R" part to the Ordering Guide.
Revision 1.6
October 29, 2015
• Added product options Si863xxT in 1. Ordering Guide.
• Added spec line items for Input and Enable Leakage Currents pertaining to Si863xxT in 4. Electrical Specifications.
• Added new spec for tSD in Electrical Specifications
• Updated IEC 60747-5-2 to IEC 60747-5-5 in all instances in document
Revision 1.5
June 6, 2015
• Updated Table 5 on page 14.
• Added CQC certificate numbers.
• Updated "4. Ordering Guide" on page 10.
• Removed references to moisture sensitivity levels.
• Removed Note 2.
Revision 1.4
September 25, 2013
• Added Figure 3, “Common-Mode Transient Immunity Test Circuit,” on page 8.
• Added references to CQC throughout.
• Added references to 2.5 kVRMS devices throughout.
• Updated "4. Ordering Guide" on page 10.
• Updated "9.1. Si863x Top Marking (16-Pin Wide Body SOIC)" on page 17.
Revision 1.3
June 26, 2012
• Updated Table 11 on page 20.
• Added junction temperature spec.
• Updated "2.3.1. Supply Bypass" on page 7.
• Removed “3.3.2. Pin Connections” on page 23.
• Updated "3. Pin Descriptions" on page 9.
• Updated table notes.
• Updated "4. Ordering Guide" on page 10.
• Removed Rev A devices.
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Si8630/31/35 Data Sheet • Revision History
• Updated "6. Land Pattern: 16-Pin Wide-Body SOIC" on page 13.
• Updated Top Marks.
• Added revision description.
Revision 1.2
March 21, 2012
• Updated "4. Ordering Guide" on page 10 to include MSL2A.
Revision 1.1
September 14, 2011
• Updated High Level Output Voltage VOH to 3.1 V in Table 3, “Electrical Characteristics,” on page 9.
• Updated High Level Output Voltage VOH to 2.3 V in Table 4, “Electrical Characteristics,” on page 12.
Revision 1.0
July 14, 2011
• Reordered spec tables to conform to new convention.
• Removed “pending” throughout document.
Revision 0.2
March 31, 2011
• Added chip graphics on page 1.
• Moved Tables 1 and 11 to page 20.
• Updated Table 6, “Insulation and Safety-Related Specifications,” on page 17.
• Updated Table 8, “IEC 60747-5-5 Insulation Characteristics for Si86xxxx*,” on page 18.
• Moved Table 1 to page 4.
• Moved Table 2 to page 5.
• Moved “Typical Performance Characteristics” to page 8.
• Updated "3. Pin Descriptions" on page 9.
• Updated "4. Ordering Guide" on page 10.
• Removed references to QSOP-16 package.
Revision 0.1
September 15, 2010
• Initial release.
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