Si8650/51/52/55
L O W P O W E R F I V E - C HANNEL D IGITAL I SOLATOR
Features
High-speed operation
DC to 150 Mbps
No start-up initialization required
Wide Operating Supply Voltage
2.5–5.5 V
Up to 5000 VRMS isolation
60-year life at rated working voltage
High electromagnetic immunity
Ultra low power (typical)
5 V Operation
1.6 mA per channel at 1 Mbps
5.5 mA per channel at 100 Mbps
2.5 V Operation
1.5 mA per channel at 1 Mbps
3.5 mA per channel at 100 Mbps
Tri-state outputs with ENABLE
Schmitt trigger inputs
Selectable fail-safe mode
Default high or low output
(ordering option)
Precise timing (typical)
10 ns propagation delay
1.5 ns pulse width distortion
0.5 ns channel-channel skew
2 ns propagation delay skew
5 ns minimum pulse width
Transient Immunity 50 kV/µs
AEC-Q100 qualification
Wide temperature range
–40 to 125 °C
RoHS-compliant packages
SOIC-16 wide body
SOIC-16 narrow body
QSOP-16
Applications
Industrial automation systems
Medical electronics
Hybrid electric vehicles
Isolated switch mode supplies
Isolated ADC, DAC
Motor control
Power inverters
Communication systems
Safety Regulatory Approvals
UL 1577 recognized
Up to 5000 VRMS for 1 minute
CSA component notice 5A approval
IEC 60950-1, 61010-1, 60601-1
(reinforced insulation)
VDE certification conformity
IEC 60747-5-2
(VDE0884 Part 2)
EN60950-1
(reinforced insulation)
Ordering Information:
See page 28.
Description
Silicon Lab's family of ultra-low-power digital isolators are CMOS devices
offering substantial data rate, propagation delay, power, size, reliability, and
external BOM advantages over legacy isolation technologies. The operating
parameters of these products remain stable across wide temperature ranges
and throughout device service life for ease of design and highly uniform
performance. All device versions have Schmitt trigger inputs for high noise
immunity and only require VDD bypass capacitors.
Data rates up to 150 Mbps are supported, and all devices achieve propagation
delays of less than 10 ns. Enable inputs provide a single point control for
enabling and disabling output drive. Ordering options include a choice of
isolation ratings (3.75 and 5 kV) and a selectable fail-safe operating mode to
control the default output state during power loss. All products >1 kVRMS are
safety certified by UL, CSA, and VDE, and products in wide-body packages
support reinforced insulation withstanding up to 5 kVRMS.
Rev. 1.6 6/12
Copyright © 2012 by Silicon Laboratories
Si8650/51/52/55
Si8650/51/52/55
2
Rev. 1.6
Si8650/51/52/55
TABLE O F C ONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.1. Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.2. Eye Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3. Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.1. Device Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
3.2. Undervoltage Lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.3. Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.4. Fail-Safe Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.5. Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4. Pin Descriptions (Si8650/51/52) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5. Pin Descriptions (Si8655) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7. Package Outline: 16-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8. Land Pattern: 16-Pin Wide-Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
9. Package Outline: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
10. Land Pattern: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
11. Package Outline: 16-Pin QSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
12. Land Pattern: 16-Pin QSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
13. Top Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
13.1. Top Marking (16-Pin Wide Body SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
13.2. Top Marking Explanation (16-Pin Wide Body SOIC) . . . . . . . . . . . . . . . . . . . . . . . 38
13.3. Top Marking (16-Pin Narrow Body SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
13.4. Top Marking Explanation (16-Pin Narrow Body SOIC) . . . . . . . . . . . . . . . . . . . . . . 39
13.5. Top Marking (16-Pin QSOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
13.6. Top Marking Explanation (16-Pin QSOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Rev. 1.6
3
Si8650/51/52/55
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
TA
150 Mbps, 15 pF, 5 V
–40
25
125
ºC
VDD1
2.5
—
5.5
V
VDD2
2.5
—
5.5
V
Ambient Operating Temperature*
Supply Voltage
*Note: The maximum ambient temperature is dependent on data frequency, output loading, number of operating channels,
and supply voltage.
Table 2. Electrical Characteristics
(VDD1 = 5 V±10%, VDD2 = 5 V±10%, TA = –40 to 125 ºC)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
VDD Undervoltage Threshold
VDDUV+
VDD1, VDD2 rising
1.95
2.24
2.375
V
VDD Undervoltage Threshold
VDDUV–
VDD1, VDD2 falling
1.88
2.16
2.325
V
VDD Negative-Going
Lockout Hysteresis
VDDHYS
50
70
95
mV
Positive-Going Input Threshold
VT+
All inputs rising
1.4
1.67
1.9
V
Negative-Going
Input Threshold
VT–
All inputs falling
1.0
1.23
1.4
V
Input Hysteresis
VHYS
0.38
0.44
0.50
V
High Level Input Voltage
VIH
2.0
—
—
V
Low Level input voltage
VIL
—
—
0.8
V
High Level Output Voltage
VOH
loh = –4 mA
VDD1,VDD2 – 0.4
4.8
—
V
Low Level Output Voltage
VOL
lol = 4 mA
—
0.2
0.4
V
IL
—
—
±10
µA
ZO
—
50
—
Input Leakage Current
1
Output Impedance
Enable Input High Current
IENH
VENx = VIH
—
2.0
—
µA
Enable Input Low Current
IENL
VENx = VIL
—
2.0
—
µA
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of
the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
4
Rev. 1.6
Si8650/51/52/55
Table 2. Electrical Characteristics (Continued)
(VDD1 = 5 V±10%, VDD2 = 5 V±10%, TA = –40 to 125 ºC)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
DC Supply Current (All inputs 0 V or at Supply)
Si8650Bx, Ex, Si8655Bx
VDD1
VDD2
VDD1
VDD2
VI = 0(Bx), 1(Ex)
VI = 0(Bx), 1(Ex)
VI = 1(Bx), 0(Ex)
VI = 1(Bx), 0(Ex)
—
—
—
—
1.1
3.1
7.0
3.3
1.8
4.7
9.8
5.0
Si8651Bx, Ex
VDD1
VDD2
VDD1
VDD2
VI = 0(Bx), 1(Ex)
VI = 0(Bx), 1(Ex)
VI = 1(Bx), 0(Ex)
VI = 1(Bx), 0(Ex)
—
—
—
—
1.5
2.7
6.6
4.0
2.4
4.1
9.2
6.0
Si8652Bx, Ex
VDD1
VDD2
VDD1
VDD2
VI = 0(Bx), 1(Ex)
VI = 0(Bx), 1(Ex)
VI = 1(Bx), 0(Ex)
VI = 1(Bx), 0(Ex)
—
—
—
—
2.0
2.4
5.6
5.0
3.0
3.6
7.8
7.5
mA
mA
mA
1 Mbps Supply Current (All inputs = 500 kHz square wave, CI = 15 pF on all outputs)
Si8650Bx, Ex, Si8655Bx
VDD1
VDD2
—
—
4.1
3.7
5.7
5.2
mA
Si8651Bx, Ex
VDD1
VDD2
—
—
4.2
3.8
5.8
5.3
mA
Si8652Bx, Ex
VDD1
VDD2
—
—
4.0
4.0
5.6
5.6
mA
10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs)
Si8650Bx, Ex, Si8655Bx
VDD1
VDD2
—
—
4.1
5.2
5.7
7.2
mA
Si8651Bx, Ex
VDD1
VDD2
—
—
4.4
4.9
6.2
6.9
mA
Si8652Bx, Ex
VDD1
VDD2
—
—
4.6
4.9
6.4
6.8
mA
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of
the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
Rev. 1.6
5
Si8650/51/52/55
Table 2. Electrical Characteristics (Continued)
(VDD1 = 5 V±10%, VDD2 = 5 V±10%, TA = –40 to 125 ºC)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs)
Si8650Bx, Ex, Si8655Bx
VDD1
VDD2
—
—
4.1
22.1
5.7
28.7
mA
Si8651Bx, Ex
VDD1
VDD2
—
—
8.0
18.4
10.8
24
mA
Si8652Bx, Ex
VDD1
VDD2
—
—
11.7
15
15.2
19.5
mA
Maximum Data Rate
0
—
150
Mbps
Minimum Pulse Width
—
—
5.0
ns
Timing Characteristics
Si865xBx, Ex
Propagation Delay
Pulse Width Distortion
|tPLH – tPHL|
Propagation Delay Skew2
Channel-Channel Skew
tPHL, tPLH
See Figure 2
5.0
8.0
13
ns
PWD
See Figure 2
—
0.2
4.5
ns
tPSK(P-P)
—
2.0
4.5
ns
tPSK
—
0.4
2.5
ns
2.5
4.0
2.5
4.0
All Models
Output Rise Time
tr
CL = 15 pF
See Figure 2
—
Output Fall Time
tf
CL = 15 pF
See Figure 2
—
Peak eye diagram jitter
tJIT(PK)
See Figure 7
—
350
—
ps
Common Mode
Transient Immunity
Enable to Data Valid
CMTI
VI = VDD or 0 V
35
50
—
kV/µs
ten1
See Figure 1
—
6.0
11
ns
ten2
See Figure 1
—
8.0
12
ns
—
15
40
µs
Enable to Data Tri-State
3
Start-up Time
tSU
ns
ns
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of
the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
6
Rev. 1.6
Si8650/51/52/55
ENABLE
OUTPUTS
ten1
ten2
Figure 1. ENABLE Timing Diagram
1.4 V
Typical
Input
tPLH
tPHL
90%
90%
10%
10%
1.4 V
Typical
Output
tr
tf
Figure 2. Propagation Delay Timing
Rev. 1.6
7
Si8650/51/52/55
Table 3. Electrical Characteristics
(VDD1 = 3.3 V±10%, VDD2 = 3.3 V±10%, TA = –40 to 125 ºC)
Parameter
Symbol
VDD Undervoltage Threshold
VDDUV+ VDD1, VDD2 rising
VDDUV– VDD1, VDD2 falling
VDD Undervoltage Threshold
VDD Negative-Going Lockout
Hysteresis
Test Condition
VDDHYS
Min
Typ
Max
Unit
1.95
2.24
2.375
V
1.88
2.16
2.325
V
50
70
95
mV
Positive-Going Input Threshold
VT+
All inputs rising
1.4
1.67
1.9
V
Negative-Going Input Threshold
VT–
All inputs falling
1.0
1.23
1.4
V
Input Hysteresis
VHYS
0.38
0.44
0.50
V
High Level Input Voltage
VIH
2.0
—
—
V
Low Level Input Voltage
VIL
—
—
0.8
V
High Level Output Voltage
VOH
loh = –4 mA
VDD1,VDD2 – 0.4
3.1
—
V
Low Level Output Voltage
VOL
lol = 4 mA
—
0.2
0.4
V
IL
—
—
±10
µA
ZO
—
50
—
Input Leakage Current
1
Output Impedance
Enable Input High Current
IENH
VENx = VIH
—
2.0
—
µA
Enable Input Low Current
IENL
VENx = VIL
—
2.0
—
µA
DC Supply Current (All inputs 0 V or at supply)
Si8650Bx, Ex, Si8655Bx
VDD1
VDD2
VDD1
VDD2
VI = 0(Bx), 1(Ex)
VI = 0(Bx), 1(Ex)
VI = 1(Bx), 0(Ex)
VI = 1(Bx), 0(Ex)
—
—
—
—
1.1
3.1
7.0
3.3
1.8
4.7
9.8
5.0
Si8651Bx, Ex
VDD1
VDD2
VDD1
VDD2
VI = 0(Bx), 1(Ex)
VI = 0(Bx), 1(Ex)
VI = 1(Bx), 0(Ex)
VI = 1(Bx), 0(Ex)
—
—
—
—
1.5
2.7
6.6
4.0
2.4
4.1
9.2
6.0
Si8652Bx, Ex
VDD1
VDD2
VDD1
VDD2
VI = 0(Bx), 1(Ex)
VI = 0(Bx), 1(Ex)
VI = 1(Bx), 0(Ex)
VI = 1(Bx), 0(Ex)
—
—
—
—
2.0
2.4
5.6
5.0
3.0
3.6
7.8
7.5
mA
mA
mA
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
8
Rev. 1.6
Si8650/51/52/55
Table 3. Electrical Characteristics (Continued)
(VDD1 = 3.3 V±10%, VDD2 = 3.3 V±10%, TA = –40 to 125 ºC)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
1 Mbps Supply Current (All inputs = 500 kHz square wave, CI = 15 pF on all outputs)
Si8650Bx, Ex, Si8655Bx
VDD1
VDD2
—
—
4.1
3.7
5.7
5.2
mA
Si8651Bx, Ex
VDD1
VDD2
—
—
4.2
3.8
5.8
5.3
mA
Si8652Bx, Ex
VDD1
VDD2
—
—
4.0
4.0
5.6
5.6
mA
10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs)
Si8650Bx, Ex, Si8655Bx
VDD1
VDD2
—
—
4.1
4.4
5.7
6.1
mA
Si8651Bx, Ex
VDD1
VDD2
—
—
4.3
4.3
6.0
6.0
mA
Si8652Bx, Ex
VDD1
VDD2
—
—
4.3
4.4
6.0
6.1
mA
100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs)
Si8650Bx, Ex, Si8655Bx
VDD1
VDD2
—
—
4.1
15.5
5.7
20.1
mA
Si8651Bx, Ex
VDD1
VDD2
—
—
6.6
13.2
8.9
17.1
mA
Si8652Bx, Ex
VDD1
VDD2
—
—
8.9
11.1
11.6
14.4
mA
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
Rev. 1.6
9
Si8650/51/52/55
Table 3. Electrical Characteristics (Continued)
(VDD1 = 3.3 V±10%, VDD2 = 3.3 V±10%, TA = –40 to 125 ºC)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Maximum Data Rate
0
—
150
Mbps
Minimum Pulse Width
—
—
5.0
ns
Timing Characteristics
Si865xBx, Ex
Propagation Delay
Pulse Width Distortion
|tPLH – tPHL|
Propagation Delay Skew2
Channel-Channel Skew
tPHL, tPLH
See Figure 2
5.0
8.0
13
ns
PWD
See Figure 2
—
0.2
4.5
ns
tPSK(P-P)
—
2.0
4.5
ns
tPSK
—
0.4
2.5
ns
2.5
4.0
2.5
4.0
All Models
Output Rise Time
tr
CL = 15 pF
See Figure 2
—
Output Fall Time
tf
CL = 15 pF
See Figure 2
—
Peak eye diagram jitter
tJIT(PK)
See Figure 7
—
350
—
ps
Common Mode Transient
Immunity at Logic Low Output
Enable to Data Valid
CMTI
VI = VDD or 0 V
35
50
—
kV/µs
ten1
See Figure 1
—
6.0
11
ns
ten2
See Figure 1
—
8.0
12
ns
—
15
40
µs
Enable to Data Tri-State
Start-Up Time
3
tSU
ns
ns
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
10
Rev. 1.6
Si8650/51/52/55
Table 4. Electrical Characteristics
(VDD1 = 2.5 V ±5%, VDD2 = 2.5 V ±5%, TA = –40 to 125 ºC)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
VDD Undervoltage Threshold
VDDUV+
VDD1, VDD2 rising
1.95
2.24
2.375
V
VDD Undervoltage Threshold
VDDUV–
VDD1, VDD2 falling
1.88
2.16
2.325
V
VDD Negative-Going
Lockout Hysteresis
VDDHYS
50
70
95
mV
Positive-Going Input Threshold
VT+
All inputs rising
1.4
1.67
1.9
V
Negative-Going Input Threshold
VT–
All inputs falling
1.0
1.23
1.4
V
Input Hysteresis
VHYS
0.38
0.44
0.50
V
High Level Input Voltage
VIH
2.0
—
—
V
Low Level Input Voltage
VIL
—
—
0.8
V
High Level Output Voltage
VOH
loh = –4 mA
VDD1,VDD2 – 0.4
2.3
—
V
Low Level Output Voltage
VOL
lol = 4 mA
—
0.2
0.4
V
IL
—
—
±10
µA
ZO
—
50
—
Input Leakage Current
Output Impedance
1
Enable Input High Current
IENH
VENx = VIH
—
2.0
—
µA
Enable Input Low Current
IENL
VENx = VIL
—
2.0
—
µA
DC Supply Current (All inputs 0 V or at supply)
Si8650Bx, Ex, Si8655Bx
VDD1
VDD2
VDD1
VDD2
VI = 0(Bx), 1(Ex)
VI = 0(Bx), 1(Ex)
VI = 1(Bx), 0(Ex)
VI = 1(Bx), 0(Ex)
—
—
—
—
1.1
3.1
7.0
3.3
1.8
4.7
9.8
5.0
Si8651Bx, Ex
VDD1
VDD2
VDD1
VDD2
VI = 0(Bx), 1(Ex)
VI = 0(Bx), 1(Ex)
VI = 1(Bx), 0(Ex)
VI = 1(Bx), 0(Ex)
—
—
—
—
1.5
2.7
6.6
4.0
2.4
4.1
9.2
6.0
Si8652Bx, Ex
VDD1
VDD2
VDD1
VDD2
VI = 0(Bx), 1(Ex)
VI = 0(Bx), 1(Ex)
VI = 1(Bx), 0(Ex)
VI = 1(Bx), 0(Ex)
—
—
—
—
2.0
2.4
5.6
5.0
3.0
3.6
7.8
7.5
mA
mA
mA
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the
same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
Rev. 1.6
11
Si8650/51/52/55
Table 4. Electrical Characteristics (Continued)
(VDD1 = 2.5 V ±5%, VDD2 = 2.5 V ±5%, TA = –40 to 125 ºC)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
1 Mbps Supply Current (All inputs = 500 kHz square wave, CI = 15 pF on all outputs)
Si8650Bx, Ex, Si8655Bx
VDD1
VDD2
—
—
4.1
3.7
5.7
5.2
mA
Si8651Bx, Ex
VDD1
VDD2
—
—
4.2
3.8
5.8
5.3
mA
Si8652Bx, Ex
VDD1
VDD2
—
—
4.0
4.0
5.6
5.6
mA
10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs)
Si8650Bx, Ex, Si8655Bx
VDD1
VDD2
—
—
4.1
4.0
5.7
5.6
mA
Si8651Bx, Ex
VDD1
VDD2
—
—
4.2
4.0
5.9
5.6
mA
Si8652Bx, Ex
VDD1
VDD2
—
—
4.1
4.2
5.8
5.9
mA
100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs)
Si8650Bx, Ex, Si8655Bx
VDD1
VDD2
—
—
4.1
12.5
5.7
16.2
mA
Si8651Bx, Ex
VDD1
VDD2
—
—
6.0
10.8
8.1
14
mA
Si8652Bx, Ex
VDD1
VDD2
—
—
7.6
9.3
9.9
12.0
mA
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the
same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
12
Rev. 1.6
Si8650/51/52/55
Table 4. Electrical Characteristics (Continued)
(VDD1 = 2.5 V ±5%, VDD2 = 2.5 V ±5%, TA = –40 to 125 ºC)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Maximum Data Rate
0
—
150
Mbps
Minimum Pulse Width
—
—
5.0
ns
Timing Characteristics
Si865xBx, Ex
Propagation Delay
Pulse Width Distortion
|tPLH - tPHL|
Propagation Delay Skew2
Channel-Channel Skew
tPHL, tPLH
See Figure 2
5.0
8.0
14
ns
PWD
See Figure 2
—
0.2
5.0
ns
tPSK(P-P)
—
2.0
5.0
ns
tPSK
—
0.4
2.5
ns
2.5
4.0
2.5
4.0
All Models
Output Rise Time
tr
CL = 15 pF
See Figure 2
—
Output Fall Time
tf
CL = 15 pF
See Figure 2
—
Peak Eye Diagram Jitter
tJIT(PK)
See Figure 7
—
350
—
ps
Common Mode Transient
Immunity at Logic Low Output
CMTI
VI = VDD or 0 V
35
50
—
kV/µs
Enable to Data Valid
ten1
See Figure 1
—
6.0
11
ns
Enable to Data Tri-State
ten2
See Figure 1
—
8.0
12
ns
—
15
40
µs
Startup Time
3
tSU
ns
ns
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the
same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
Rev. 1.6
13
Si8650/51/52/55
Table 5. Regulatory Information*
CSA
The Si865x is certified under CSA Component Acceptance Notice 5A. For more details, see File 232873.
61010-1: Up to 600 VRMS reinforced insulation working voltage; up to 600 VRMS basic insulation working voltage.
60950-1: Up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage.
60601-1: Up to 125 VRMS reinforced insulation working voltage; up to 380 VRMS basic insulation working voltage.
VDE
The Si865x is certified according to IEC 60747-5-2. For more details, see File 5006301-4880-0001.
60747-5-2: Up to 1200 Vpeak for basic insulation working voltage.
60950-1: Up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage.
UL
The Si865x is certified under UL1577 component recognition program. For more details, see File E257455.
Rated up to 5000 VRMS isolation voltage for basic protection.
*Note: Regulatory Certifications apply to 3.75 kVRMS rated devices which are production tested to 4.5 kVRMS for 1 sec.
Regulatory Certifications apply to 5.0 kVRMS rated devices which are production tested to 6.0 kVRMS for 1 sec.
For more information, see "6. Ordering Guide" on page 28.
Table 6. Insulation and Safety-Related Specifications
Value
Parameter
Symbol
Test Condition
WB
SOIC-16
NB
QSOP-16
SOIC-16
Unit
Nominal Air Gap (Clearance)1
L(IO1)
8.0
4.9
3.6
mm
Nominal External Tracking
(Creepage)1
L(IO2)
8.0
4.01
3.6
mm
0.014
0.011
0.008
600
600
600
VRMS
Minimum Internal Gap
(Internal Clearance)
mm
Tracking Resistance
(Proof Tracking Index)
PTI
Erosion Depth
ED
0.019
0.019
0.031
mm
RIO
1012
1012
1012
2.0
2.0
2.0
pF
4.0
4.0
4.0
pF
Resistance
(Input-Output)2
2
Capacitance (Input-Output)
Input Capacitance
3
CIO
IEC60112
f = 1 MHz
CI
Notes:
1. The values in this table correspond to the nominal creepage and clearance values. VDE certifies the clearance and
creepage limits as 4.7 mm minimum for the NB SOIC-16 and QSOP-16 packages and 8.5 mm minimum for the WB
SOIC-16 package. UL does not impose a clearance and creepage minimum for component-level certifications. CSA
certifies the clearance and creepage limits as 3.9 mm minimum for the NB SOIC-16, 3.6 mm minimum for the QSOP16 packages and 7.6 mm minimum for the WB SOIC-16 package.
2. To determine resistance and capacitance, the Si86xx is converted into a 2-terminal device. Pins 1–8 are shorted
together to form the first terminal and pins 9–16 are shorted together to form the second terminal. The parameters are
then measured between these two terminals.
3. Measured from input pin to ground.
14
Rev. 1.6
Si8650/51/52/55
Table 7. IEC 60664-1 (VDE 0844 Part 2) Ratings
Specification
Test Conditions
Parameter
Basic Isolation Group
NB SOIC-16
WB SOIC-16
I
I
Rated Mains Voltages < 150 VRMS
I-IV
I-IV
Rated Mains Voltages < 300 VRMS
I-III
I-IV
Rated Mains Voltages < 400 VRMS
I-II
I-III
Rated Mains Voltages < 600 VRMS
I-II
I-III
Material Group
Installation Classification
Table 8. IEC 60747-5-2 Insulation Characteristics for Si86xxxx*
Characteristic
Symbol
Parameter
Maximum Working Insulation
Voltage
Input to Output Test Voltage
Transient Overvoltage
Test Condition
WB
SOIC-16
NB
SOIC-16
Unit
1200
630
Vpeak
VPR
Method b1
(VIORM x 1.875 = VPR, 100%
Production Test, tm = 1 sec,
Partial Discharge < 5 pC)
2250
1182
VIOTM
t = 60 sec
6000
6000
2
2
>109
>109
VIORM
Pollution Degree
(DIN VDE 0110, Table 1)
Insulation Resistance at TS,
VIO = 500 V
RS
Vpeak
*Note: Maintenance of the safety data is ensured by protective circuits. The Si86xxxx provides a climate classification of
40/125/21.
Table 9. IEC Safety Limiting Values1
Max
Parameter
Symbol
Case Temperature
TS
Safety Input, Output, or
Supply Current
IS
Device Power
Dissipation2
PD
Test Condition
JA = 100 °C/W (WB SOIC-16),
105 °C/W
(NB SOIC-16, QSOP-16),
VI = 5.5 V, TJ = 150 °C, TA = 25 °C
Min Typ
WB
SOIC-16
NB
SOIC-16
Unit
—
—
150
150
°C
—
—
220
215
mA
—
—
415
415
mW
Notes:
1. Maximum value allowed in the event of a failure; also see the thermal derating curve in Figures 3 and 4.
2. The Si86xx is tested with VDD1 = VDD2 = 5.5 V, TJ = 150 ºC, CL = 15 pF, input a 150 Mbps 50% duty cycle square
wave.
Rev. 1.6
15
Si8650/51/52/55
Table 10. Thermal Characteristics
Parameter
Symbol
Test Condition
WB SOIC-16
NB SOIC-16
QSOP-16
Unit
100
105
ºC/W
JA
IC Junction-to-Air Thermal
Resistance
Safety-Limiting Current (mA)
500
450
VDD1, VDD2 = 2.70 V
400
370
VDD1, VDD2 = 3.6 V
300
220
200
VDD1, VDD2 = 5.5 V
100
0
0
50
100
Temperature (ºC)
150
200
Figure 3. (WB SOIC-16) Thermal Derating Curve, Dependence of Safety Limiting Values
with Case Temperature per DIN EN 60747-5-2
Safety-Limiting Current (mA)
500
430
VDD1, VDD2 = 2.70 V
400
360
VDD1, VDD2 = 3.6 V
300
215
200
VDD1, VDD2 = 5.5 V
100
0
0
50
100
Temperature (ºC)
150
200
Figure 4. (NB SOIC-16) Thermal Derating Curve, Dependence of Safety Limiting Values
with Case Temperature per DIN EN 60747-5-2
16
Rev. 1.6
Si8650/51/52/55
Table 11. Absolute Maximum Ratings1
Parameter
Symbol
Min
Typ
Max
Unit
TSTG
–65
—
150
ºC
Ambient Temperature Under Bias
TA
–40
—
125
ºC
Junction Temperature
TJ
—
—
150
°C
VDD1, VDD2
–0.5
—
7.0
V
Input Voltage
VI
–0.5
—
VDD + 0.5
V
Output Voltage
VO
–0.5
—
VDD + 0.5
V
Output Current Drive Channel
(All devices unless otherwise stated)
IO
—
—
10
mA
Output Current Drive Channel
(All Si865xxA-x-xx devices)
IO
—
—
22
mA
Latchup Immunity3
—
—
100
V/ns
Lead Solder Temperature (10 s)
—
—
260
ºC
Maximum Isolation (Input to Output) (1 sec)
NB SOIC-16, QSOP-16
—
—
4500
VRMS
Maximum Isolation (Input to Output) (1 sec)
WB SOIC-16
—
—
6500
VRMS
Storage Temperature2
Supply Voltage
Notes:
1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be
restricted to conditions as specified in the operational sections of this data sheet.
2. VDE certifies storage temperature from –40 to 150 °C.
3. Latchup immunity specification is for slew rate applied across GND1 and GND2.
Rev. 1.6
17
Si8650/51/52/55
2. Functional Description
2.1. Theory of Operation
The operation of an Si865x channel is analogous to that of an opto coupler, except an RF carrier is modulated
instead of light. This simple architecture provides a robust isolated data path and requires no special
considerations or initialization at start-up. A simplified block diagram for a single Si865x channel is shown in
Figure 5.
Transmitter
Receiver
RF
OSCILLATOR
A
MODULATOR
SemiconductorBased Isolation
Barrier
DEMODULATOR
B
Figure 5. Simplified Channel Diagram
A channel consists of an RF Transmitter and RF Receiver separated by a semiconductor-based isolation barrier.
Referring to the Transmitter, input A modulates the carrier provided by an RF oscillator using on/off keying. The
Receiver contains a demodulator that decodes the input state according to its RF energy content and applies the
result to output B via the output driver. This RF on/off keying scheme is superior to pulse code schemes as it
provides best-in-class noise immunity, low power consumption, and better immunity to magnetic fields. See
Figure 6 for more details.
Input Signal
Modulation Signal
Output Signal
Figure 6. Modulation Scheme
18
Rev. 1.6
Si8650/51/52/55
2.2. Eye Diagram
Figure 7 illustrates an eye-diagram taken on an Si8650. For the data source, the test used an Anritsu (MP1763C)
Pulse Pattern Generator set to 1000 ns/div. The output of the generator's clock and data from an Si8650 were
captured on an oscilloscope. The results illustrate that data integrity was maintained even at the high data rate of
150 Mbps. The results also show that 2 ns pulse width distortion and 350 ps peak jitter were exhibited.
Figure 7. Eye Diagram
Rev. 1.6
19
Si8650/51/52/55
3. Device Operation
Device behavior during start-up, normal operation, and shutdown is shown in Figure 8, where UVLO+ and UVLOare the positive-going and negative-going thresholds respectively. Refer to Table 12 to determine outputs when
power supply (VDD) is not present. Additionally, refer to Table 13 for logic conditions when enable pins are used.
Table 12. Si865x Logic Operation
VI
Input1,2
EN
Input1,2,3,4
VDDI
State1,5,6
VDDO
State1,5,6
VO Output1,2
H
H or NC
P
P
H
L
H or NC
P
P
L
X7
L
P
P
Hi-Z8
H or NC
UP
P
L9
H9
X7
L
UP
P
Hi-Z8
X7
X7
P
UP
X
7
Comments
Enabled, normal operation.
Disabled.
Upon transition of VDDI from unpowered to powered, VO returns to the same state as VI in less
than 1 µs.
Disabled.
Undetermined Upon transition of VDDO from unpowered to powered, VO returns to the same state as VI within
1 µs, if EN is in either the H or NC state. Upon transition of VDDO from unpowered to powered, VO
returns to Hi-Z within 1 µs if EN is L.
Notes:
1. VDDI and VDDO are the input and output power supplies. VI and VO are the respective input and output terminals. EN
is the enable control input located on the same output side.
2. X = not applicable; H = Logic High; L = Logic Low; Hi-Z = High Impedance.
3. It is recommended that the enable inputs be connected to an external logic high or low level when the Si865x is
operating in noisy environments.
4. No Connect (NC) replaces EN1 on Si8650. No Connects are not internally connected and can be left floating, tied to
VDD, or tied to GND.
5. “Powered” state (P) is defined as 2.5 V < VDD < 5.5 V.
6. “Unpowered” state (UP) is defined as VDD = 0 V.
7. Note that an I/O can power the die for a given side through an internal diode if its source has adequate current.
8. When using the enable pin (EN) function, the output pin state is driven into a high-impedance state when the EN pin is
disabled (EN = 0).
9. See "6. Ordering Guide" on page 28 for details. This is the selectable fail-safe operating mode (ordering option). Some
devices have default output state = H, and some have default output state = L, depending on the ordering part number
(OPN). For default high devices, the data channels have pull-ups on inputs/outputs. For default low devices, the data
channels have pull-downs on inputs/outputs.
20
Rev. 1.6
Si8650/51/52/55
Table 13. Enable Input Truth1
P/N
Si8650
Si8651
Si8652
Si8655
Operation
EN11,2 EN21,2
—
H
Outputs B1, B2, B3, B4, B5 are enabled and follow input state.
—
L
Outputs B1, B2, B3, B4, B5 are disabled and Logic Low or in high impedance
state.3
H
X
Output A5 enabled and follow input state.
L
X
Output A5 disabled and in high impedance state.3
X
H
Outputs B1, B2, B3, B4 are enabled and follow input state.
X
L
Outputs B1, B2, B3, B4 are disabled and in high impedance state.3
H
X
Outputs A4 and A5 are enabled and follow input state.
L
X
Outputs A4 and A5 are disabled and in high impedance state.3
X
H
Outputs B1, B2, B3 are enabled and follow input state.
X
L
Outputs B1, B2, B3 are disabled and in high impedance state.3
—
—
Outputs B1, B2, B3, B4, B5 are enabled and follow input state.
Notes:
1. Enable inputs EN1 and EN2 can be used for multiplexing, for clock sync, or other output control. These inputs are
internally pulled-up to local VDD by a 2 µA current source allowing them to be connected to an external logic level (high
or low) or left floating. To minimize noise coupling, do not connect circuit traces to EN1 or EN2 if they are left floating. If
EN1, EN2 are unused, it is recommended they be connected to an external logic level, especially if the Si865x is
operating in a noisy environment.
2. X = not applicable; H = Logic High; L = Logic Low.
3. When using the enable pin (EN) function, the output pin state is driven into a high-impedance state when the EN pin is
disabled (EN = 0).
Rev. 1.6
21
Si8650/51/52/55
3.1. Device Startup
Outputs are held low during powerup until VDD is above the UVLO threshold for time period tSTART. Following
this, the outputs follow the states of inputs.
3.2. Undervoltage Lockout
Undervoltage Lockout (UVLO) is provided to prevent erroneous operation during device startup and shutdown or
when VDD is below its specified operating circuits range. Both Side A and Side B each have their own
undervoltage lockout monitors. Each side can enter or exit UVLO independently. For example, Side A
unconditionally enters UVLO when VDD1 falls below VDD1(UVLO–) and exits UVLO when VDD1 rises above
VDD1(UVLO+). Side B operates the same as Side A with respect to its VDD2 supply.
UVLO+
UVLO-
VDD1
UVLO+
UVLO-
VDD2
INPUT
tSTART
tSD
tSTART
tSTART
tPHL
OUTPUT
Figure 8. Device Behavior during Normal Operation
22
Rev. 1.6
tPLH
Si8650/51/52/55
3.3. Layout Recommendations
To ensure safety in the end user application, high voltage circuits (i.e., circuits with >30 VAC) must be physically
separated from the safety extra-low voltage circuits (SELV is a circuit with 1 kVRMS are AEC-Q100 qualified.
28
Rev. 1.6
Si8650/51/52/55
7. Package Outline: 16-Pin Wide Body SOIC
Figure 16 illustrates the package details for the Si865x Digital Isolator. Table 15 lists the values for the dimensions
shown in the illustration.
Figure 16. 16-Pin Wide Body SOIC
Rev. 1.6
29
Si8650/51/52/55
Table 15. Package Diagram Dimensions
Dimension
Min
Max
A
—
2.65
A1
0.10
0.30
A2
2.05
—
b
0.31
0.51
c
0.20
0.33
D
10.30 BSC
E
10.30 BSC
E1
7.50 BSC
e
1.27 BSC
L
0.40
1.27
h
0.25
0.75
0°
8°
aaa
—
0.10
bbb
—
0.33
ccc
—
0.10
ddd
—
0.25
eee
—
0.10
fff
—
0.20
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC Outline MS-013, Variation AA.
4. Recommended reflow profile per JEDEC J-STD-020C specification for
small body, lead-free components.
30
Rev. 1.6
Si8650/51/52/55
8. Land Pattern: 16-Pin Wide-Body SOIC
Figure 17 illustrates the recommended land pattern details for the Si865x in a 16-pin wide-body SOIC. Table 16
lists the values for the dimensions shown in the illustration.
Figure 17. 16-Pin SOIC Land Pattern
Table 16. 16-Pin Wide Body SOIC Land Pattern Dimensions
Dimension
Feature
(mm)
C1
Pad Column Spacing
9.40
E
Pad Row Pitch
1.27
X1
Pad Width
0.60
Y1
Pad Length
1.90
Notes:
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P1032X265-16AN
for Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card
fabrication tolerance of 0.05 mm is assumed.
Rev. 1.6
31
Si8650/51/52/55
9. Package Outline: 16-Pin Narrow Body SOIC
Figure 18 illustrates the package details for the Si865x in a 16-pin narrow-body SOIC (SO-16). Table 17 lists the
values for the dimensions shown in the illustration.
Figure 18. 16-pin Small Outline Integrated Circuit (SOIC) Package
32
Rev. 1.6
Si8650/51/52/55
Table 17. Package Diagram Dimensions
Dimension
Min
Max
A
—
1.75
A1
0.10
0.25
A2
1.25
—
b
0.31
0.51
c
0.17
0.25
D
9.90 BSC
E
6.00 BSC
E1
3.90 BSC
e
1.27 BSC
L
0.40
L2
1.27
0.25 BSC
h
0.25
0.50
θ
0°
8°
aaa
0.10
bbb
0.20
ccc
0.10
ddd
0.25
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MS-012,
Variation AC.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020
specification for Small Body Components.
Rev. 1.6
33
Si8650/51/52/55
10. Land Pattern: 16-Pin Narrow Body SOIC
Figure 19 illustrates the recommended land pattern details for the Si865x in a 16-pin narrow-body SOIC. Table 18
lists the values for the dimensions shown in the illustration.
Figure 19. 16-Pin Narrow Body SOIC PCB Land Pattern
Table 18. 16-Pin Narrow Body SOIC Land Pattern Dimensions
Dimension
Feature
(mm)
C1
Pad Column Spacing
5.40
E
Pad Row Pitch
1.27
X1
Pad Width
0.60
Y1
Pad Length
1.55
Notes:
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P600X165-16N
for Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card
fabrication tolerance of 0.05 mm is assumed.
34
Rev. 1.6
Si8650/51/52/55
11. Package Outline: 16-Pin QSOP
Figure 20 illustrates the package details for the Si865x in a 16-pin QSOP package. Table 19 lists the values for the
dimensions shown in the illustration.
Figure 20. 16-pin QSOP Package
Rev. 1.6
35
Si8650/51/52/55
Table 19. Package Diagram Dimensions
Dimension
Min
Max
A
—
1.75
A1
0.10
0.25
A2
1.25
—
b
0.20
0.30
c
0.17
0.25
D
4.89 BSC
E
6.00 BSC
E1
3.90 BSC
e
0.635 BSC
L
0.40
L2
1.27
0.25 BSC
h
0.25
0.50
θ
0°
8°
aaa
0.10
bbb
0.20
ccc
0.10
ddd
0.25
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-137, Variation AB.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification
for Small Body Components.
36
Rev. 1.6
Si8650/51/52/55
12. Land Pattern: 16-Pin QSOP
Figure 21 illustrates the recommended land pattern details for the Si865x in a 16-pin narrow-body SOIC. Table 20
lists the values for the dimensions shown in the illustration.
Figure 21. 16-Pin QSOP PCB Land Pattern
Table 20. 16-Pin QSOP Land Pattern Dimensions
Dimension
Feature
(mm)
C1
Pad Column Spacing
5.40
E
Pad Row Pitch
0.635
X1
Pad Width
0.40
Y1
Pad Length
1.55
Notes:
1. This Land Pattern Design is based on IPC-7351 pattern SOP63P602X173-16N for
Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card
fabrication tolerance of 0.05 mm is assumed.
Rev. 1.6
37
Si8650/51/52/55
13. Top Markings
13.1. Top Marking (16-Pin Wide Body SOIC)
Si86XYSV
YYWWRTTTTT
e3
TW
13.2. Top Marking Explanation (16-Pin Wide Body SOIC)
Line 1 Marking:
Base Part Number
Ordering Options
Line 2 Marking:
YY = Year
WW = Workweek
Assigned by assembly subcontractor. Corresponds to the
year and work week of the mold date.
RTTTTT = Mfg Code
Manufacturing code from assembly house
“R” indicates revision
Circle = 1.5 mm Diameter
(Center-Justified)
“e3” Pb-free symbol
Country of Origin ISO Code
Abbreviation
TW = Taiwan
Line 3 Marking:
Si86 = Isolator product series
XY = Channel Configuration
X = # of data channels (5, 4, 3, 2, 1)
(See Ordering Guide for more
Y = # of reverse channels (2, 1, 0)*
information).
S = Speed Grade (max data rate) and operating mode:
A = 1 Mbps (default output = low)
B = 150 Mbps (default output = low)
D = 1 Mbps (default output = high)
E = 150 Mbps (default output = high)
V = Insulation rating
A = 1 kV; B = 2.5 kV; C = 3.75 kV; D = 5.0 kV
*Note: Si8655 has 0 reverse channels.
38
Rev. 1.6
Si8650/51/52/55
13.3. Top Marking (16-Pin Narrow Body SOIC)
e3
Si86XYSV
YYWWRTTTTT
13.4. Top Marking Explanation (16-Pin Narrow Body SOIC)
Base Part Number
Ordering Options
Line 1 Marking:
(See Ordering Guide for more
information).
Line 2 Marking:
Si86 = Isolator product series
XY = Channel Configuration
X = # of data channels (5, 4, 3, 2, 1)
Y = # of reverse channels (2, 1, 0)*
S = Speed Grade (max data rate) and operating mode:
A = 1 Mbps (default output = low)
B = 150 Mbps (default output = low)
D = 1 Mbps (default output = high)
E = 150 Mbps (default output = high)
V = Insulation rating
A = 1 kV; B = 2.5 kV; C = 3.75 kV
Circle = 1.2 mm Diameter
“e3” Pb-Free Symbol
YY = Year
WW = Work Week
Assigned by the assembly subcontractor. Corresponds
to the year and work week of the mold date.
RTTTTT = Mfg Code
Manufacturing code from assembly house
“R” indicates revision
Circle = 1.2 mm diameter
“e3” Pb-Free Symbol.
*Note: Si8655 has 0 reverse channels.
Rev. 1.6
39
Si8650/51/52/55
13.5. Top Marking (16-Pin QSOP)
e3
Si86XYSV
YYWWRTTTTT
13.6. Top Marking Explanation (16-Pin QSOP)
Line 1 Marking:
Base Part Number
Ordering Options
(See Ordering Guide for more
information).
Line 2 Marking:
Si86 = Isolator product series
XY = Channel Configuration
X = # of data channels (4, 3, 2, 1)
Y = # of reverse channels (2, 1, 0)*
S = Speed Grade (max data rate) and operating mode:
A = 1 Mbps (default output = low)
B = 150 Mbps (default output = low)
D = 1 Mbps (default output = high)
E = 150 Mbps (default output = high)
V = Insulation rating
A = 1 kV; B = 2.5 kV; C = 3.75 kV
Circle = 1.2 mm Diameter
“e3” Pb-Free Symbol
YY = Year
WW = Work Week
Assigned by the assembly house. Corresponds to the
year and work week of the mold date.
RTTTTT = Mfg Code
Manufacturing code from assembly house
“R” indicates revision
Circle = 1.2 mm diameter
“e3” Pb-free symbol.
*Note: Si8655 has 0 reverse channels.
40
Rev. 1.6
Si8650/51/52/55
DOCUMENT CHANGE LIST
Revision 1.4 to Revision 1.5
Updated "6. Ordering Guide" on page 28 to include
MSL2A.
Updated Table 14, “Ordering Guide for Valid
OPNs1,2,” on page 28.
Revision 0.1 to Revision 0.2
Deleted sections 4.3.4 and 4.3.5.
Updated "6. Ordering Guide" on page 28.
Table 14, “Ordering Guide for Valid OPNs1,2,”
on page 28.
Updated
Added "3.4. Fail-Safe Operating Mode" on page 23.
Updated Table 11 on page 17.
Added
Revision 0.2 to Revision 1.0
Revision 1.5 to Revision 1.6
junction temperature spec.
Added chip graphics on page 1.
Moved Tables 1 and 11 to page 17.
Updated Table 6, “Insulation and Safety-Related
Specifications,” on page 14.
Updated Table 8, “IEC 60747-5-2 Insulation
Characteristics for Si86xxxx*,” on page 15.
Moved Table 12 to page 20.
Moved Table 13 to page 21.
Moved “Typical Performance Characteristics” to
page 24.
Updated "4. Pin Descriptions (Si8650/51/52)" on
page 26.
Updated "5. Pin Descriptions (Si8655)" on page 27.
Updated "6. Ordering Guide" on page 28.
Updated "3.3.1. Supply Bypass" on page 23.
Removed “3.3.2. Pin Connections” on page 23.
Updated "4. Pin Descriptions (Si8650/51/52)" on
page 26.
Updated
table notes.
Updated "6. Ordering Guide" on page 28.
Removed
Rev A devices.
Updated "7. Package Outline: 16-Pin Wide Body
SOIC" on page 29.
Updated Top Marks.
Added
revision description.
Revision 1.0 to Revision 1.1
Reordered spec tables to conform to new
convention.
Removed “pending” throughout document.
Revision 1.1 to Revision 1.2
Updated High Level Output Voltage VOH to 3.1 V in
Table 3, “Electrical Characteristics,” on page 8.
Updated High Level Output Voltage VOH to 2.3 V in
Table 4, “Electrical Characteristics,” on page 11.
Revision 1.2 to Revision 1.3
Added Output Current Drive Channel specification
for Si865xxA-x-xx devices.
Added Latchup Immunity specification.
Revision 1.3 to Revision 1.4
Updated Table 14, “Ordering Guide for Valid
OPNs1,2,” on page 28.
Updated
Note 1 with MSL2A.
Rev. 1.6
41
Si8650/51/52/55
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