Si8751/52 Data Sheet
Isolated FET Driver with Pin Control or Diode Emulator Inputs
KEY FEATURES
The Si875x enables new pathways to the creation of custom Solid State Relay (SSR)
configurations. The Si875x integrates robust isolation technology with an SSR FET driver. A
floating secondary side dc power supply is unnecessary as the product generates its own
self-contained gate drive output voltage. When combined with a customer-selected external
FET, a complete Solid State Relay is formed, allowing customers to optimize their system
for cost, PCB area, power, On-Resistance, and thermal performance.
Customers have a choice of digital input control (Si8751) or diode emulation control
(Si8752) to best suit their application. The Si875x integrates versatile outputs that support
driving AC or DC load configurations.
The Si875x eliminates the need for bulky mechanical relays which can be difficult to assemble onto PCBs and add switching noise to the system.
Traditional SSRs integrate optocoupler-style LED inputs, which limit the operating temperature range of the solution. The Si875x experiences no such limitation and can support full
industrial and automotive temperature ranges with increased stability and longer life.
The Si875x drives FET gates with a nominal 10 V using as little as 1 mA input current.
Increasing the input current to 10 mA enables turn-on times as fast as 94 μs. Input side
voltages on the Si8751 are flexible from 2.25 V to 5.5 V supporting seamless connection
to low-power controllers. The Si875x devices provide an Active Miller Clamp to prevent the
unintended turn-on of the external FET when a high dV/dt is present on the FET’s drain.
The Si875x is qualified to the AEC-Q100 standard, making it suitable for automotive applications. Further, its 2.5 KVrms isolation rating forms the basis for full certification to UL, CSA,
VDE, and CQC.
Applications include mechanical relay, photo switch, or SSR replacement in motor control,
valve control, HVAC relay, automotive, charging, battery monitoring, ac mains line switching,
and more.
The Si8751 and Si8752 come in ROHS-compliant SOIC-8 packaging, providing a compact,
industry-standard footprint and generous margin to creepage and clearance requirements.
1
• Drives user-selected external FETs
• Choice of digital input control (Si8751)
or diode emulation control (Si8752)
• Internally generated secondary side
power supply
• 10 V output with 1 mA input current
• As fast as 82 μs turn-on time and 46
us turn-off time
• Active Miller Clamp to prevent
unintended turn-on and reduce
inductive chatter
• Supports AC or DC load switching
• 2.5 KVrms isolation rating
• UL, CSA, VDE, and CQC certifications
• AEC-Q100 qualified
• Industrial –40 to 105 °C or Automotive
–40 to 125 °C temperature ranges
• ROHS-compliant SOIC-8 Package
APPLICATIONS
• Motor Controls
• Valve Controls
• HVAC Relays
• HEV/EV Automotive Charging
• Battery Monitoring
• AC Mains Line Switching
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Si8751/52 Data Sheet • Ordering Guide
1. Ordering Guide
Table 1.1. Si8751/2 Ordering Guide
Input Support
Package
Temperature Range (Ambient)
Isolation Rating (kVrms)
Si8751AB-IS
Digital CMOS
SOIC-8
–40 to 105 °C Industrial
2.5 kV
Si8751AB-AS
Digital CMOS
SOIC-8
–40 to 125 °C Automotive
2.5 kV
Si8752AB-IS
Diode Emulation
SOIC-8
–40 to 105 °C Industrial
2.5 kV
Si8752AB-AS
Diode Emulation
SOIC-8
–40 to 125 °C Automotive
2.5 kV
Ordering Part Number1,
2
Note:
1. "Si" and "SI" are used interchangeably.
2. Add an “R” at the end of the device to denote tape and reel option
2
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Si8751/52 Data Sheet • System Overview
2. System Overview
IN
Receiver
TT
MCAP1
CMOS Isolation
Signal & Power Transmitter
VDD
GATE
SOURCE
GND
MCAP2
Figure 2.1. Si8751 Block Diagram
ANODE
CATHODE
Receiver
CMOS Isolation
e
Signal & Power Transmitter
MCAP1
GATE
SOURCE
MCAP2
Figure 2.2. Si8752 Block Diagram
3
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Si8751/52 Data Sheet • System Overview
The operation of an Si875x channel is analogous to that of an optocoupler and gate driver, except an RF carrier is modulated instead of
light. This simple architecture provides a robust isolated data path and requires no special considerations or initialization at start-up. A
simplified block diagram for a single Si875x channel is shown in the figure below.
Transmitter
A
Receiver
SemiconductorBased Isolation
Barrier
MODULATOR
B
DEMODULATOR
RF OSCILLATOR
Figure 2.3. Simplified Channel Diagram
A channel consists of an RF Transmitter and RF Receiver separated by a semiconductor-based isolation barrier. Referring to the
Transmitter, input A modulates the carrier provided by an RF oscillator using on/off keying. The Receiver contains a demodulator that
decodes the input state according to its RF energy content and applies the result to output B via the output driver. This RF on/off keying
scheme is superior to pulse code schemes as it provides best-in-class noise immunity, low power consumption, and better immunity to
magnetic fields. See figure below for more details.
Input Signal
Modulation Signal
Output Signal
Figure 2.4. Modulation Scheme
2.1 Device Behavior
The following are truth tables for the Si875x family.
Table 2.1. Si8751 Truth Table
VDD
IN
Gate
Powered
H
H
Powered
L
L
Unpowered
X
L
Table 2.2. Si8752 Truth Table
4
Input Current
Gate
> If(TH)
H
< If(TH)
L
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Si8751/52 Data Sheet • System Overview
2.2 Power Supply Connections (Si8751 Only)
The Si8751 requires a 0.1 µF bypass capacitor between VDD and GND. The capacitor should be placed as close as possible to the
package. To enhance the robustness of a design, the user may also include a 1 µf capacitor for bulk decoupling as well as a resistor
(50–300 Ω) in series with the input if the system is excessively noisy.
2.3 TT Pin Description (Si8751 Only)
The Si8751 provides a pin to control how much current is consumed by the supply when the input pin is logic high. The more current
consumed by the input supply, the faster the output can turn on the external FET. This allows the application designer to optimize the
tradeoff between power consumption and switching time.
Typically, this pin is connected to the supply ground through a resistor. The greater the value of the resistor, the less current is
consumed by the input supply. Values can range from 0 Ω (shorted to ground) to open (TT not connected).
IN
IN
MCAP1
Receiver
TT
CMOS Isolation
VDD
Signal & Power Transmitter
In addition to a resistor, a capacitor, typically 0.1 µf, can be placed in parallel to the resistor. This allows the device to draw more
current to switch the external FET on quickly yet draw less supply current in the steady state. Total power over time is reduced while
maintaining fast switching of the FET.
GATE
Max Drive
Current
Static Drive
Current
~1/C
SOURCE
GND
MCAP2
t
Figure 2.5. Si8751 TT Example
Figure 2.6. Drive Current vs. Time Using TT with Capacitor
2.4 LED Emulator Input (Si8752 Only)
Figure 2.8. Diode Emulator Model and I-V Curve
The Si8752 uses input current to achieve the development of power across the isolation barrier. Therefore, the more current provided to
the input, the more power is developed on the isolated side of the device. This translates into a faster turn on time of the external FET.
This benefit is limited to an input current of about 15 mA. Beyond that, increasing the input current has little effect on the switching time
of the external FET.
5
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Si8751/52 Data Sheet • System Overview
2.5 Output Description
The output of the Si875x device develops a positive voltage on the GATE pin with respect to the SOURCE pin. This voltage is used to
turn on a typical field effect transistor (FET). Because power is transmitted across the isolation barrier, no isolated supply is required.
This can be used to drive a FET configured as a switch for a dc load. It can also be used to drive a pair of FETs configured as a switch
for an ac load. See 3. Applications.
2.6 Miller Clamp
2.6.1 Miller Clamp Description
The Si875x devices provide a clamping device to prevent unintended turn on of the external FET when a high dV/dt is present on the
FET’s drain. To use this feature, a capacitor is connected between the drain(s) of the FET(s) and one of the MCAPx inputs. A sudden,
positive slope on this pin will cause the clamp device within the Si875x to activate and provide a low impedance path between the gate
and source pins. This will prevent the FET from being unintentionally turned on.
The Si875x device provides two miller clamp input pins. This allows for both FET’s to be protected from unintended turn on when the
device is used in an AC switch configuration. In this case each drain is connected to an MCAPx input through a capacitor.
Connection to a MCAPx pin, and use of the Miller Clamp feature, is optional. The device will function as expected if these pins are left
unconnected.
2.6.2 Sizing Miller Clamp Capacitors
The recommended value of the capacitor used to connect the drain of the external FET to the Si875x device is typically 10 pf. If the
application has a very large dV/dt and the clamp is not adequately keeping the external FET off, then this capacitor value can be
increased up to 100 pf. The voltage rating of the capacitor should be greater than or equal to the peak voltage expected at the drain
of the FET. The relationship of the capacitor and the dV/dt is governed by the equation: C = IMC/(dV/dt); where: IMC is the Miller Clamp
input current (6mA max, as specified in Electrical Tables), and dV/dt is the expected slew rate.
6
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Si8751/52 Data Sheet • Applications
3. Applications
The following examples illustrate typical circuit configurations using the Si8751/52.
3.1 DC SSR Example
The Si875x device can be used to control a dc load as shown in the following figure:
Receiver
IN
MCAP1
CMOS Isolation
TT
VDC
Signal & Power Transmitter
VDD
GATE
SOURCE
GND
MCAP2
DC Load
Figure 3.1. Driving an FET for DC Load Including Miller Clamp Capacitor
In this configuration, the Si8751 charges the gate of the external FET; turning it on. This switches on power, supplied by VDC, to the
load. The output side circuitry is identical if using the Si8752.
3.2 AC SSR Example
IN
MCAP1
Receiver
TT
AC Load
CMOS Isolation
VDD
Signal & Power Transmitter
The Si875x can be used to control power to an ac load using the following circuit:
AC
Supply
GATE
SOURCE
GND
MCAP2
Figure 3.2. Driving FETs for AC Load Switching
In this configuration, both FET’s are turned on by the charge delivered by the Si8751. This allows ac current to flow to the load. When
the Si875x is turned off, charge is drained form the gates of both FET’s and the ac current is turned off. The output side circuitry is
identical if using the Si8752.
7
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Si8751/52 Data Sheet • Electrical Specifications
4. Electrical Specifications
Table 4.1. Electrical Specifications
• Automotive: VDD=2.25 to 5.5V; GND=0V; TA=-40 to +125ºC; typical specs at 25ºC; TJ=-40 to +150ºC
• Industrial: VDD=2.25 to 5.5V; GND=0V; TA=-40 to +105ºC; typical specs at 25ºC; TJ=-40 to +150ºC
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
2.25
3.3
5.5
V
IN = 0V
—
140
—
nA
IN = VDD, TT = GND
—
13.8
17
mA
IN = VDD, TT = 10 kΩ
—
7.8
9.5
mA
IN = VDD, TT unconnected
—
1.5
1.8
mA
Si8751 Only
Input Side
Supply Voltage
VDD
Supply Current
IDD
High Level Input Voltage
VIH
50% of VDD
—
—
V
Low Level Input Voltage
VIL
—
—
25% of VDD
V
Input Hystersis
VHYS
—
180
—
mV
Driver Side
GATE Off Voltage
VG(OFF)
IN = 0 V
—
0
—
mV
GATE On Voltage
VG(ON)
IN = VDD, TT = GND
7.5
10
13
V
IN = VDD, TT = 10 kΩ
9
10.8
13
V
IN = VDD, TT unconnected
9
10.8
13
V
IN = VDD, TT = GND
—
162
330
kΩ
IN = VDD, TT = 10 kΩ
—
265
370
kΩ
IN = VDD, TT unconnected
—
1.5
1.85
MΩ
GATE On Impedance
RG
Turn-off Time
TG(OFF)
IN = 0 V
—
15
35
µs
Turn-on Time (50% of VG(ON))
TG(ON)
TT = GND
—
42
120
µs
TT = 10 kΩ
—
58
170
µs
TT unconnected
—
286
650
µs
TT = GND
—
85.3
190
µs
TT = 10 kΩ
—
130
260
µs
TT unconnected
—
0.7
1.2
ms
Turn-on Time (90% of VG(ON))
TG(ON)
Si8752 Only
Input Side
8
Input Current
IF(ON)
1.0
—
30.0
mA
Guaranteed Off Current
IF(OFF)
—
—
10
µA
Forward Voltage (OFF)
VF(OFF)
—
0
—
V
Measured ANODE with respect to Cathode
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Si8751/52 Data Sheet • Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Forward Voltage (ON)
VF(ON)
1 mA < IF < 10 mA, measured ANODE with
respect to cathode
1.8
—
2.35
V
10 mA < IF < 30 mA, measured ANODE with
respect to cathode
2.03
—
2.7
V
Driver Side
GATE Off Voltage
VG(OFF)
IF = 0 mA
—
0
—
mV
GATE On Voltage
VG(ON)
IF = 1 mA
8
10.3
13
V
IF = 10 mA
8
10.3
13
V
IF = 30 mA
8
10.9
13
V
IF = 1 mA
—
2.7
3.5
MΩ
IF = 10 mA
—
194
300
kΩ
IF = 30 mA
—
168
290
kΩ
GATE On Impedance
RG
Turn-off Time
TG(OFF)
IF = 0 mA
—
15
35
µs
Turn-on Time (50% of VG(ON))
TG(ON)
IF = 1 mA
—
463
720
µs
IF = 10 mA
—
41
125
µs
IF = 30 mA
—
36
90
µs
IF = 1 mA
—
1.1
1.49
ms
IF = 10 mA
—
94
190
µs
IF = 30 mA
—
82
180
µs
Turn-on Time (90% of VG(ON))
TG(ON)
Si8751 and Si8752
Miller Clamp Current
IMC
Max input current
—
—
6
mA
Miller Clamp Pull-Down Current
IG
IMC = 50 µA; VGate = 1 V
5
12.8
—
mA
IF = 0 mA (Si8752)
—
21.5
—
MΩ
20
—
—
kV/µs
Gate OFF Impedance
IN = 0 V (Si8751)
Common Mode Transient Immunity
VCM = 1500 V
Note:
1. All measurements use 100 pF gate capacitance load unless specified.
9
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Si8751/52 Data Sheet • Electrical Specifications
4.1 Test Circuits
The following figure depicts a common-mode transient immunity test circuit:
Si8751
VDD
IN
TT
GND
Isolated +
Supply -
GATE
MCAP1
MCAP2
SOURCE
Isolated
Ground
High-Voltage Surge
Generator
Oscilloscope
High-Voltage
Differential
Probe
Figure 4.1. Common-Mode Transient Immunity Test Circuit
4.2 Regulatory Information
Table 4.2. Regulatory Information1,2
CSA
The Si875x is certified under CSA Component Acceptance Notice 5A. For more details, see Master Contract Number 232873.
60950-1: Up to 125 VRMS reinforced insulation working voltage; up to 600 VRMS basic insulation working voltage.
VDE
The Si875x is certified according to VDE 0884-10. For more details, see Certificate 40018443.
VDE 0884-10: Up to 630 Vpeak for basic insulation working voltage.
UL
The Si875x is certified under UL1577 component recognition program. For more details, see File E257455.
Rated up to 2500 VRMS isolation voltage for basic protection.
CQC
The Si875x is certified under GB4943.1-2011. For more details, see Certificate CQC17001177960.
Rated up to 125 VRMS reinforced insulation working voltage; up to 600 VRMS basic insulation working voltage.
1. Regulatory Certifications apply to 2.5 kVRMS rated devices which are production tested to 3.0 kVRMS for 1 sec.
2. For more information, see 1. Ordering Guide.
10
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Si8751/52 Data Sheet • Electrical Specifications
Table 4.3. Insulation and Safety-Related Specifications
Parameter
Nominal External Air Gap
Symbol
Test Condition
SOIC-8 Value
Unit
CLR
4.7
mm
CPG
3.9
mm
DTI
0.008
mm
600
V
(Clearance)
Nominal External Tracking
(Creepage)
Minimum Internal Gap
(Internal Clearance)
Tracking Resistance
PTI
IEC60112
Erosion Depth
ED
0.04
mm
Resistance
RIO
1012
Ω
0.5
pF
3.0
pF
(Input-Output)1
Capacitance
CIO
f = 1 MHz
(Input-Output)1
Input Capacitance2
CI
Notes:
1. To determine resistance and capacitance, the Si875x is converted into a 2-terminal device. All pins on side 1 are shorted to
create terminal 1, and all pins on side 2 are shorted to create terminal 2. The parameters are then measured between these two
terminals.
2. Measured from input pin to ground.
Table 4.4. IEC 60664-1 Ratings
11
Parameter
Test Condition
SOIC-8 Specification
Basic Isolation Group
Material Group
I
Installation Classification
Rated Mains Voltages < 150 VRMS
I-IV
Rated Mains Voltages < 300 VRMS
I-III
Rated Mains Voltages < 400 VRMS
I-II
Rated Mains Voltages < 600 VRMS
I-II
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Si8751/52 Data Sheet • Electrical Specifications
Table 4.5. VDE 0884 Insulation Characteristics1
Parameter
Symbol
Maximum Working Insulation Voltage
Test Condition
Characteristic
Unit
630
V peak
VIORM
Input to Output Test Voltage
VPR
Method b1
(VIORM x 1.875 = VPR, 100%
Production Test, tm = 1 sec,
Partial Discharge < 5 pC)
1181
V peak
Transient Overvoltage
VIOTM
t = 60 sec
4000
V peak
Surge Voltage
VIOSM
Tested per IEC 60065 with surge
voltage of 1.2 µs/50 µs
3077
Vpeak
Si875x tested with 4000 V
Pollution Degree
2
(DIN VDE 0110, Table 1)
Insulation Resistance at
RS
Ω
>109
TS, VIO = 500 V
Note:
1. Maintenance of the safety data is ensured by protective circuits. The Si875x provides a climate classification of 40/125/21.
Table 4.6. IEC Safety Limiting Values1
Parameter
Symbol
Safety Temperature
TS
Safety Input Current
(Si8751)
ΙS
Test Condition
θJA = 110 °C/W
SOIC-8
Unit
150
°C
206
mA
313
mA
413
mA
454
mA
VDD = 5.5 V,
TJ = 150 °C,
TA = 25 °C
θJA = 110 °C/W
VDD = 3.63 V,
TJ = 150 °C,
TA = 25 °C
θJA = 110 °C/W
VDD = 2.75 V,
TJ = 150 °C,
TA = 25 °C
Safety Input Current
(Si8752)
ΙS
θJA = 110 °C/W
VF = 2.5 V,
TJ = 150 °C,
TA = 25 °C
12
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Si8751/52 Data Sheet • Electrical Specifications
Parameter
Safety Input Power
(Si8752)
Symbol
Test Condition
SOIC-8
Unit
PS
θJA = 110 °C/W
1136
mW
1
W
VF = 2.5 V,
TJ = 150 °C,
TA = 25 °C
Device Power Dissipation
PD
Note:
1. Maximum value allowed in the event of a failure. Refer to the thermal derating curves below.
13
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Si8751/52 Data Sheet • Electrical Specifications
Table 4.7. Thermal Characteristics
Parameter
Symbol
SOIC-8
Unit
IC Junction-to-Air
Thermal Resistance
θJA
110
°C/W
Figure 4.2. Thermal Derating Curve for Safety Limiting Current (Si8751)
Figure 4.3. Thermal Derating Curve for Safety Limiting Current (Si8752)
14
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Si8751/52 Data Sheet • Electrical Specifications
Table 4.8. Absolute Maximum Ratings1
Parameter
Symbol
Min
Max
Units
TSTG
–65
+150
°C
Operating Temperature
TA
–40
+125
°C
Junction Temperature
TJ
—
+150
°C
Input-side supply voltage (Si8751)
VDD
–0.6
6.0
V
Voltage on any input side pin with respect to ground (pin
4, Si8751 only)
VIO
–0.5
VDD + 0.5
V
IF(AVG)
—
30
mA
VR
—
0.3
V
Lead Solder Temperature (10 s)
—
260
°C
ESD Rating, HBM
—
3500
V
ESD Rating, CDM
—
2000
V
Maximum Isolation Voltage (Input to Output) (1 sec)
—
3000
VRMS
—
400
kV/μs
Storage Temperature
Average Forward Anode Current (Si8752)
Reverse Anode Voltage (Si8752)
SOIC-8
Latch-up Immunity
Note:
1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be restricted to
the conditions specified in the operational sections of this data sheet.
15
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Si8751/52 Data Sheet • Electrical Specifications
4.3 Typical Operating Characteristics
16
Figure 4.4. Si8751 Typical Gate Voltage vs. Temperature
and TT
Figure 4.5. Si8752 Typical Gate Voltage vs. Temperature
and Anode Current
Figure 4.6. Si8751 Typical Turn-On Time vs. Temperature
and TT with 100 pF Load (50% of Output)
Figure 4.7. Si8752 Typical Turn-On Time vs. Temperature
and Anode Current with 100 pF Load (50% of Output)
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Si8751/52 Data Sheet • Electrical Specifications
Figure 4.8. Si8751 Typical Turn-On Time vs. Temperature
and TT with 100 pF Load (90% of Output)
Figure 4.9. Si8752 Typical Turn-On Time vs. Temperature
and Anode Current with 100 pF Load (90% of Output)
Figure 4.10. Si8751 Typical Turn-On Time vs. Capacitance
and TT (50% of Output)
Figure 4.11. Si8752 Typical Turn-On Time vs. Capacitance
and Anode Current (50% of Output)
17
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Si8751/52 Data Sheet • Electrical Specifications
Figure 4.12. Si8751 Typical Turn-On Time vs. Capacitance
and TT (90% of Output)
18
Figure 4.13. Si8752 Typical Turn-On Time vs. Capacitance
and Anode Current (90% of Output)
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Si8751/52 Data Sheet • Pin Descriptions
5. Pin Descriptions
5.1 Si8751 Pin Descriptions
8 GATE
VDD 1
TT 2
IN 3
Si8751
7 MCAP1
6 MCAP2
5 SOURCE
GND 4
Figure 5.1. Pin Assignments Si8751
Table 5.1. Si8751 Pin Descriptions
19
Pin
Name
Description
1
VDD
2
TT
Turn-on time control (optional)
3
IN
Digital control input
4
GND
5
SOURCE
6
MCAP2
Miller capacitance control 2 (optional)
7
MCAP1
Miller capacitance control 1 (optional)
8
GATE
Input side power supply
Input side ground
Connection to switch FET Source
Connection to switch FET Gate
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Si8751/52 Data Sheet • Pin Descriptions
5.2 Si8752 Pin Descriptions
8 GATE
NC 1
ANODE 2
NC 3
7 MCAP1
Si8752
CATHODE 4
6 MCAP2
5 SOURCE
Figure 5.2. Pin Assignments Si8752
Table 5.2. Si8752 Pin Descriptions
20
Pin
Name
Description
1
NC
2
ANODE
3
NC
4
CATHODE
Cathode of LED emulator
5
SOURCE
Connection to switch FET Source
6
MCAP2
Miller capacitance control 2 (optional)
7
MCAP1
Miller capacitance control 1 (optional)
8
GATE
No Connect
Anode of LED emulator
No Connect
Connection to switch FET Gate
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Si8751/52 Data Sheet • Package Outlines
6. Package Outlines
6.1 Package Outline: 8-Pin Narrow Body SOIC
The figure below illustrates the package details for the Si875x in an 8-pin narrow-body SOIC package. The table below lists the values
for the dimensions shown in the illustration.
Figure 6.1. 8-Pin Narrow Body SOIC Package
21
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Si8751/52 Data Sheet • Package Outlines
Table 6.1. 8-Pin Narrow Body SOIC Package Diagram Dimensions
Symbol
Millimeters
Min
Max
A
1.35
1.75
A1
0.10
0.25
A2
1.40 REF
1.55 REF
B
0.33
0.51
C
0.19
0.25
D
4.80
5.00
E
3.80
4.00
e
22
1.27 BSC
H
5.80
6.20
h
0.25
0.50
L
0.40
1.27
α
0°
8°
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Si8751/52 Data Sheet • Land Patterns
7. Land Patterns
7.1 Land Pattern: 8-Pin Narrow Body SOIC
The figure below illustrates the recommended land pattern details for the Si875x in an 8-pin narrow-body SOIC. The table below lists
the values for the dimensions shown in the illustration.
Figure 7.1. 8-Pin Narrow Body SOIC Land Pattern
Table 7.1. 8-Pin Narrow Body SOIC Land Pattern Dimensions
Dimension
Feature
(mm)
C1
Pad Column Spacing
5.40
E
Pad Row Pitch
1.27
X1
Pad Width
0.60
Y1
Pad Length
1.55
Notes:
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P600X173-8N for Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0.05 mm is assumed.
23
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Si8751/52 Data Sheet • Top Markings
8. Top Markings
8.1 8-Pin Narrow Body SOIC
Table 8.1. Top Marking Explanation
Line 1 Marking:
Customer Part Number
Si875 = ISOdriver product series
X: 1 = Digital input, 2 = LED emulator input
A: Reserved
V: B = 2.5 kV isolation rating
Line 2 Marking:
TTTTTT = Mfg code
Manufacturing Code from Assembly Purchase Order form.
Line 3 Marking:
YY = Year
Assigned by the Assembly House. Corresponds to the year and
workweek of the mold date.
WW = Work week
24
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Si8751/52 Data Sheet • Revision History
9. Revision History
Revision A, July 2022
• Added Agile data sheet revision in footer
Revision 1.0, December 2017
• Significant edits with production electrical specifications and load switching diagram.
Revision 0.5, September 2016
• Significant edits with production electrical specifications.
Revision 0.1, May 2016
• Initial revision.
25
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Table of Contents
1. Ordering Guide
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2. System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1 Device Behavior
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2.2 Power Supply Connections (Si8751 Only) .
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2.6 Miller Clamp . . . . . . . . .
2.6.1 Miller Clamp Description . . .
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3. Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1 DC SSR Example .
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3.2 AC SSR Example .
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4. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
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5. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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5.1 Si8751 Pin Descriptions .
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5.2 Si8752 Pin Descriptions .
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6. Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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6.1 Package Outline: 8-Pin Narrow Body SOIC .
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7. Land Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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7.1 Land Pattern: 8-Pin Narrow Body SOIC
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8. Top Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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8.1 8-Pin Narrow Body SOIC
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9. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25
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