SPL505YC256BTT

SPL505YC256BT/ SPL505YC256BS Clock Generator for Intel Bearlake Chipset Features • Compliant to Intel® CK505 • Selectable CPU frequencies • Buffered Reference Clock 14.318 MHz • Low-voltage frequency select input • I2C support with readback capabilities • Differential CPU clock pairs • Triangular Spread Spectrum profile for maximum electromagnetic interference (EMI) reduction • 100 MHz Differential SRC clocks • 3.3V Power supply/0.7V for Diff IOs • 100 MHz Differential LCD clock • 56-pin TSSOP and SSOP package • 96 MHz Differential Dot clock • 48 MHz USB clocks Table 1. Output Configuration Table • 33 MHz PCI clock CPU SRC • 25 MHz WOL or PATA clock x2/x3 x8/12 PCI REF DOT96 USB_48M x6 x1 x1 x1 LCD x1 • 27 MHz non-spread Video Clock Block Diagram Pin Configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 SPL505YC256BT/S PCI_0 / OE#_0/2_A VDD_PCI PCI_1 / OE#_1/4_A PCI_2 / TME PCI_3 / CFG0* PCI_4 / SRC5_EN PCIF_0 / ITP_EN VSS_PCI VDD_48 USB_48 / FSA VSS_48 VDD_IO SRC0 / DOT96 SRC0# / DOT96# VSS_IO VDD_PLL3 SRC1 / LCD_100/SE1 SRC1# / LCD_100#/SE2 VSS_PLL3 VDD_PLL3_IO SRC2 / SATA SRC2# / SATA# VSS_SRC SRC3/OE#_0/2_B SRC3# / OE#_1/4_B VDD_SRC_IO SRC4 SRC4# SCLK SDATA REF0 / FSC / TEST_SEL VDD_REF XTAL_IN XTAL_OUT VSS_REF FSB / TEST_MODE CK_PW RGD / PW RDW N# VDD_CPU CPU0 CPU0# VSS_CPU CPU1 CPU1# VDD_CPU_IO IO_VOUT SRC8 / CPU2_ITPT SRC8# / CPU2_ITPC VDD_SRC_IO SRC7 / OE#_8 SRC7# / OE#_6 VSS_SRC SRC6 SRC6# VDD_SRC SRC5 / PCI_STOP# SRC5# / CPU_STOP# * Internal Pull-Down ...................... Document #: 001-03543 Rev *E Page 1 of 27 400 West Cesar Chavez, Austin, TX 78701 1+(512) 416-8500 1+(512) 416-9669 www.silabs.com SPL505YC25 Pin Definitions Pin No. Name 1 PCI_0/OE#_0/2_A Type Description I/O, SE 33 MHz clock/3.3V OE# Input mappable via I2C to control either SRC 0 or SRC 2. Default PCI0 2 VDD_PCI 3 PCI_1/OE#_1/4_A I/O, SE 33 MHz clock/3.3V OE# Input mappable via I2C to control either SRC 1 or SRC 4. Default PCI1. PWR 4 PCI_2/TME I/O, SE 3.3V tolerance input for overclocking enable pin 33 MHz clock. Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications. 5 PCI_3/CFG0 I/O, SE, 3.3V tolerant input for CPU frequency selection/33 MHz clock. PD Refer to DC Electrical Specifications table for Vil_PCI3/CFG0 and Vih_PCI3/CFG0 specifications. 6 PCI_4/SRC5_SEL I/O, SE 3.3V tolerant input to enable SRC5/33 MHz clock output. (sampled on the CK_PWRGD assertion) 1 = SRC5, 0 = CPU_STOP# 7 PCIF_0/ITP_EN I/O, SE 3.3V LVTTL input to enable SRC8 or CPU2_ITP/33 MHz clock output. (sampled on the CK_PWRGD assertion) 1 = CPU2_ITP, 0 = SRC8 8 VSS_PCI GND 9 VDD_48 PWR 10 USB_48/FSA 11 VSS_48 GND Ground for outputs. 12 VDD_IO PWR 0.7V Power supply for outputs. 13 SRC0/DOT96 O, DIF 100 MHz Differential serial reference clocks/Fixed 96 MHz clock output. Selected via I2C default is SRC0. 14 SRC0#/DOT96# O, DIF 100 MHz Differential serial reference clocks/Fixed 96 MHz clock output. Selected via I2C default is SRC0. 15 VSS_IO GND Ground for PLL2. 16 VDD_PLL3 PWR 3.3V Power supply for PLL3 17 SRC1/LCD_100/SE1 O, DIF, 100 MHz Differential serial reference clocks/100 MHz LCD video clock/SE1 SE and SE2 clocks. Default SRC1 18 SRC1#/LCD_100#/SE2 O, DIF, 100 MHz Differential serial reference clocks/100 MHz LCD video clock/SE1 SE and SE2 clocks. Default SRC1 I/O 3.3V Power supply for PCI PLL. Ground for outputs. 3.3V Power supply for outputs and PLL. 3.3V tolerant input for CPU frequency selection/fixed 48 MHz clock output. Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications. 19 VSS_PLL3 GND Ground for PLL3. 20 VDD_PLL3_IO PWR 0.7V Power supply for PLL3 outputs. 21 SRC2/SATA O, DIF 100 MHz Differential serial reference clocks / 100MHz SATA clock 22 SRC2#/SATA# O, DIF 100 MHz Differential serial reference clocks / 100MHz SATA clock 23 VSS_SRC 24 SRC3/OE#_0/2_B I/O, Dif 100-MHz Differential serial reference clocks / 3.3V OE#_0/2_B, input, mappable via I2C to control either SRC 0 or SRC 2 25 SRC3#/OE#_1/4_B I/O, Dif 100-MHz Differential serial reference clocks / 3.3V OE#_1/4_B input, mappable via I2C to control either SRC 1 or SRC 4. Default SRC3 26 VDD_SRC_IO GND PWR Ground for outputs. 0.7V power supply for SRC outputs. 27 SRC4 O, DIF 100 MHz Differential serial reference clocks. 28 SRC4# O, DIF 100 MHz Differential serial reference clocks. 29 SRC5#/PCI_STOP# I/O, Dif 3.3V tolerant input for stopping PCI and SRC outputs /100 MHz Differential serial reference clocks. ......................Document #: 001-03543 Rev *E Page 2 of 27 SPL505YC25 Pin Definitions (continued) Pin No. Name 30 SRC5/CPU_STOP# Type I/O, Dif Description 3.3V tolerant input for stopping CPU outputs/100 MHz Differential serial reference clocks. 31 VDD_SRC PWR 3.3V Power supply for SRC PLL. 32 SRC6# O, DIF 100 MHz Differential serial reference clocks. 33 SRC6 O, DIF 100 MHz Differential serial reference clocks. 34 VSS_SRC 35 SRC7#/OE#_6 GND Ground for outputs. I/O, Dif 100 MHz Differential serial reference clocks/3.3V OE#6 Input controlling SRC6. Default SRC7. 100 MHz Differential serial reference clocks/3.3V OE#8 Input controlling SRC8. Default SRC7. 36 SRC7/OE#_8 I/O, Dif 37 VDD_SRC_IO PWR 38 SRC8#/CPUT2_ITP# 0.7V power supply for SRC outputs. O, DIF Selectable differential CPU or SRC clock output. ITP_EN = 0 @ CK_PWRGD assertion = SRC8 ITP_EN = 1 @ CK_PWRGD assertion = CPU2 Note: CPU2 is an iAMT clock in iAMT mode depending on the configuration set in Byte 11 Bit3:2. 39 SRC8/CPUC2_ITP O, DIF Selectable differential CPU or SRC clock output. ITP_EN = 0 @ CK_PWRGD assertion = SRC8 ITP_EN = 1 @ CK_PWRGD assertion = CPU2 Note: CPU2 is an iAMT clock in iAMT mode depending on the configuration set in Byte 11 Bit3:2. 40 IO_VOUT O Integrated Linear Regulator Control. 41 VDD_CPU_IO 42 CPU1# O, DIF Differential CPU clock outputs. Note: CPU1 is an iAMT clock in iAMT mode PWR 0.7V Power supply for CPU outputs. 43 CPU1 O, DIF Differential CPU clock outputs. Note: CPU1 is an iAMT clock in iAMT mode 44 VSS_CPU 45 CPU0# O, DIF Differential CPU clock outputs. 46 CPU0 O, DIF Differential CPU clock outputs. depending on the configuration set in Byte 11 Bit3:2. depending on the configuration set in Byte 11 Bit3:2. GND PWR Ground for outputs. 47 VDD_CPU 48 CK_PWRGD/PWRDWN# I 3.3V Power supply for CPU PLL. 3.3V LVTTL input. This pin is a level sensitive strobe used to latch the FS_A, FS_B, FS_C, FS_D, SRC5_SEL, and ITP_EN. After CK_PWRGD (active HIGH) assertion, this pin becomes a real-time input for asserting power down (active LOW). 49 FSB/TEST_MODE I 3.3V tolerant input for CPU frequency selection. Selects Ref/N or Tri-state when in test mode 0 = Tri-state, 1 = Ref/N. Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications. 50 VSS_REF GND 51 XOUT O, SE 14.318 MHz Crystal output. I Ground for outputs. 52 XIN 53 VDD_REF 54 REF0/FSC/TEST_SEL I/O 3.3V tolerant input for CPU frequency selection/fixed 14.318 clock output. Selects test mode if pulled to VIHFS_C when CK_PWRGD is asserted HIGH. Refer to DC Electrical Specifications table for VILFS_C, VIMFS_C, VIHFS_C specifications. 55 SMB_DATA I/O SMBus compatible SDATA. 56 SMB_CLK I PWR 14.318 MHz Crystal input. 3.3V Power supply for outputs and also maintains SMBUS registers during power-down. SMBus compatible SCLOCK. ......................Document #: 001-03543 Rev *E Page 3 of 27 SPL505YC25 Frequency Select Pin (FSA, FSB, and FSC) To achieve host clock frequency selection, apply the appropriate logic levels to FS_A, FS_B, and FS_C, inputs before CK_PWRGD assertion (as seen by the clock synthesizer). When CK_PWRGD is sampled HIGH by the clock chip (indicating processor CK_PWRGD voltage is stable), the clock chip samples the FS_A, FS_B, and FS_C, input values. For all logic levels of FS_A, FS_B, and FS_C CK_PWRGDemploys a one-shot functionality, in that once a valid HIGH on CK_PWRGD has been sampled, all further CK_PWRGD FS_A, FS_B, and FS_C, transitions will be ignored, except in test mode. Frequency Select Pin (FSA, FSB, and FSC) Input Conditions Output Frequency FSC FSB FSA FSEL_2 FSEL_1 FSEL_0 CPU (MHz) 1 0 1 100 0 0 1 133 0 1 1 166 0 1 0 200 0 0 0 266 1 0 0 333 1 1 0 400 1 1 1 200 SRC (MHz) SATA (MHz) DOT96 (MHz) USB (MHz) PCI (MHz) REF (MHz) 100 100 96 48 33.3 14.318 Serial Data Interface Data Protocol To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions, such as individual clock output buffers, can be individually enabled or disabled. The registers associated with the Serial Data Interface initialize to their default setting upon power-up, and therefore use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. The interface cannot be used during system operation for power management functions. The clock driver serial protocol accepts byte write, byte read, block write, and block read operations from the controller. For block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For byte write and byte read operations, the system controller can access individually indexed bytes. The offset of the indexed byte is encoded in the command code, as described in Table 2. The block write and block read protocol is outlined in Table 3 while Table 4 outlines the corresponding byte write and byte read protocol. The slave receiver address is 11010010 (D2h) . Table 2. Command Code Definition Bit 7 (6:0) Description 0 = Block read or block write operation, 1 = Byte read or byte write operation Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000' ......................Document #: 001-03543 Rev *E Page 4 of 27 SPL505YC25 Table 3. Block Read and Block Write Protocol Block Write Protocol Bit 1 8:2 Description Start Block Read Protocol Bit 1 Slave address–7 bits 8:2 Description Start Slave address–7 bits 9 Write 9 Write 10 Acknowledge from slave 10 Acknowledge from slave 18:11 19 27:20 28 36:29 37 45:38 Command Code–8 bits 18:11 Command Code–8 bits Acknowledge from slave 19 Acknowledge from slave Byte Count–8 bits (Skip this step if I2C_EN bit set) 20 Repeat start Acknowledge from slave Data byte 1–8 bits Acknowledge from slave Data byte 2–8 bits 27:21 Read = 1 29 Acknowledge from slave 37:30 46 Acknowledge from slave .... Data Byte/Slave Acknowledges .... Data Byte N–8 bits .... Acknowledge from slave .... Stop Slave address–7 bits 28 38 46:39 47 55:48 Byte Count from slave–8 bits Acknowledge Data byte 1 from slave–8 bits Acknowledge Data byte 2 from slave–8 bits 56 Acknowledge .... Data bytes from slave/Acknowledge .... Data Byte N from slave–8 bits .... NOT Acknowledge .... Stop Table 4. Byte Read and Byte Write Protocol Byte Write Protocol Bit 1 8:2 Description Start Byte Read Protocol Bit 1 Slave address–7 bits 8:2 Description Start Slave address–7 bits 9 Write 9 Write 10 Acknowledge from slave 10 Acknowledge from slave 18:11 19 27:20 Command Code–8 bits Acknowledge from slave Data byte–8 bits 18:11 19 20 28 Acknowledge from slave 29 Stop 27:21 Command Code–8 bits Acknowledge from slave Repeated start Slave address–7 bits 28 Read 29 Acknowledge from slave 37:30 Data from slave–8 bits 38 NOT Acknowledge 39 Stop Control Registers Byte 0: Control Register 0 Bit @Pup Name ......................Document #: 001-03543 Rev *E Page 5 of 27 Description SPL505YC25 Byte 0: Control Register 0 7 HW FS_C CPU Frequency Select Bit, set by HW 6 HW FS_B CPU Frequency Select Bit, set by HW 5 HW FS_A CPU Frequency Select Bit, set by HW 4 0 iAMT_EN 3 0 RESERVED 2 0 SRC_MAIN_SEL 1 0 SATA_SEL Select source of SATA clock 0 = SATA SRC_MAIN, 1= SATA PLL2 0 1 PD_Restore Save Config. In powerdown 0 = Config. Cleared, 1 = Config. Saved Set via SMBus or by combination of PWRDWN, CPU_STP, and PCI_STP 0 = Legacy Mode, 1 = iAMT Enabled, Sticky 1 RESERVED Select source for SRC clock, 0 = SRC_MAIN = PLL1, PLL3_CFB Table applies 1 = SRC_MAIN = PLL3, PLL3_CFB Table does not apply Byte 1: Control Register 1 Bit @Pup Name Description 7 0 SRC0_SEL 6 0 PLL1_SS_DC Select for down or center SS, 0 = Down spread, 1 = Center spread 5 0 PLL3_SS_DC Select for down or center SS, 0 = Down spread, 1 = Center spread 4 0 PLL3_CFB3 Bit 4:1 only apply when SRC_SEL=0 3 0 PLL3_CFB2 2 0 PLL3_CFB1 1 1 PLL3_CFB0 Select for SRC0 or DOT96, 0 = SRC0, 1 = DOT96 0000 = PLL3 Disable Default PLL3 OFF, SRC1 = SRC_MAIN 0001 = 100 MHz 0.5% SSC Stby PLL3 ON, SRC1 = SRC_MAIN 0010 = 100 MHz 0.5% SSC Only SRC1 sourced from PLL3 0011 = 100 MHz 1.0% SSC Only SRC1 sourced from PLL3 0100 = 100 MHz 1.5% SSC Only SRC1 sourced from PLL3 0101 = 100 MHz 2.0% SSC Only SRC1 sourced from PLL3 0110 = RESERVED 0111 = RESERVED 1000 = RESERVED Note: SE clocks required to be 1001 = RESERVED enabled through Byte 8 Bit1:0 1010 = RESERVED 1011 = 27MHz_NSS on SE1 and SE2 1100 = 25MHz on SE1 and SE2 1101 = 25MHz on SE1 and SE2 Disabled (set whenPCI3/CFB0 is set high to config to HW mode 3) 1110 = RESERVED 1111 = RESERVED 0 1 PCI_SEL Select PCI Clock source from PLL1 or SRC_MAIN 0 = PLL1, 1 = SRC_MAIN Byte 2: Control Register 2 Bit @Pup Name 7 1 REF_OE Output enable for REF 0 = Output Disabled, 1 = Output Enabled Description 6 1 USB_OE Output enable for USB 0 = Output Disabled, 1 = Output Enabled 5 1 PCIF0_OE Output enable for PCIF0 0 = Output Disabled, 1 = Output Enabled 4 1 PCI4_OE Output enable for PCI4, 0 = Output Disabled, 1 = Output Enabled 3 1 PCI3_OE Output enable for PCI3, 0 = Output Disabled, 1 = Output Enabled ......................Document #: 001-03543 Rev *E Page 6 of 27 SPL505YC25 Byte 2: Control Register 2 (continued) Bit @Pup Name Description 2 1 PCI2_OE Output enable for PCI2, 0 = Output Disabled, 1 = Output Enabled 1 1 PCI1_OE Output enable for PCI1, 0 = Output Disabled, 1 = Output Enabled 0 1 PCI0_OE Output enable for PCI0, 0 = Output Disabled, 1 = Output Enabled Byte 3: Control Register 3 Bit @Pup Name 7 1 SRC11_OE Description 6 1 SRC10_OE Output enable for SRC10, 0 = Output Disabled, 1 = Output Enabled 5 1 SRC9_OE Output enable for SRC9, 0 = Output Disabled, 1 = Output Enabled 4 1 SRC8/ITP_OE 3 1 SRC7_OE Output enable for SRC7, 0 = Output Disabled, 1 = Output Enabled 2 1 SRC6_OE Output enable for SRC6, 0 = Output Disabled, 1 = Output Enabled 1 1 SRC5_OE Output enable for SRC5, 0 = Output Disabled, 1 = Output Enabled 0 1 SRC4_OE Output enable for SRC4, 0 = Output Disabled, 1 = Output Enabled Output enable for SRC11, 0 = Output Disabled, 1 = Output Enabled Output enable for SRC8 or ITP, 0 = Output Disabled, 1 = Output Enabled Byte 4: Control Register 4 Bit @Pup Name 7 1 SRC3_OE 6 1 SRC2/SATA_OE Description Output enable for SRC3, 0 = Output Disabled, 1 = Output Enabled Output enable for SATA/SRC2, 0 = Output Disabled, 1 = Output Enabled 5 1 SRC1_OE 4 1 SRC0/DOT96_OE Output enable for SRC, 0 = Output Disabled, 1 = Output Enabled 3 1 CPU1_OE Output enable for CPU1, 0 = Output Disabled, 1 = Output Enabled Output enable for CPU0, 0 = Output Disabled, 1 = Output Enabled Output enable for SRC0/DOT96 0 = Output Disabled, 1 = Output Enabled 2 1 CPU0_OE 1 1 PLL1_SS_EN Enable PLL1’s spread modulation, 0 = Spread Disabled 1 = Spread Enabled 0 1 PLL3_SS_EN Enable PLL3’s spread modulation 0 = Spread Disabled, 1 = Spread Enabled Byte 5: Control Register 5 Bit @Pup Name 7 0 OE#_0/2_EN_A Enable OE#_0/2 (clk req) 0 = Disabled OE#_0/2, 1 = Enabled OE#_0/2, Description 6 0 OE#_0/2_SEL_A Set OE#_0/2  SRC0 or SRC2 0 = OE#_0/2SRC0, 1 = OE#_0/2SRC2 5 0 OE#_1/4_EN_A Enable OE#_1/4 (clk req) 0 = Disabled OE#_1/4, 1 = Enabled OE#_1/4, 4 0 OE#_1/4_SEL_A Set OE#_1/4  SRC1 or SRC4 0 = OE#_1/4SRC1, 1 = OE#_1/4SRC4 3 0 OE#_0/2_EN_B Enable OE#_0/2 (clk req) 0 = Disabled OE#_0/2 1 = Enabled OE#_0/2 2 0 OE#_0/2_SEL_B Set OE#_0/2  SRC0 or SRC2 0 = OE#_0/2SRC0, 1 = OE#_0/2SRC2 1 0 OE#_1/4_EN_B Enable OE#_1/4 (clk req) 0 = Disabled OE#_1/4, 1 = Enabled OE#_1/4, 0 0 OE#_1/4_SEL_B Set OE#_1/4 SRC1 or SRC4 0 = OE#_1/4SRC1, 1 = OE#_1/4SRC4 ......................Document #: 001-03543 Rev *E Page 7 of 27 SPL505YC25 Byte 6: Control Register 6 Bit @Pup Name 7 0 OE#_6_EN Enable OE#_6 (clk req)  SRC6 Description 6 0 OE#_8_EN Enable OE#_8 (clk req)  SRC8 5 0 OE#_9_EN Enable OE#_9 (clk req) SRC9 4 0 OE#_10_EN Enable OE#_10 (clk req)  SRC10 3 0 RESERVED RESERVED 2 0 RESERVED RESERVED 1 0 LCD_100_STP_CTRL 0 0 SRC_STP_CTRL Allows control of LCD_100 with assertion of PCI_STOP# 0 = Free runningLCD_100, 1 = Stopped with PCI_STOP# Allows control of SRC with assertion of PCI_STOP# 0 = Free running SRC 1 = Stopped with PCI_STOP# Byte 7: Vendor ID Bit @Pup Name 7 0 Rev Code Bit 3 Revision Code Bit 3 Description 6 0 Rev Code Bit 2 Revision Code Bit 2 5 0 Rev Code Bit 1 Revision Code Bit 1 4 1 Rev Code Bit 0 Revision Code Bit 0 3 1 Vendor ID bit 3 Vendor ID Bit 3 2 0 Vendor ID bit 2 Vendor ID Bit 2 1 0 Vendor ID bit 1 Vendor ID Bit 1 0 0 Vendor ID bit 0 Vendor ID Bit 0 Byte 8: Control Register 8 Bit @Pup Name Description 7 0 Device_ID3 7 0 Device_ID2 5 0 Device_ID1 4 0 Device_ID0 3 0 RESERVED RESERVED 2 0 RESERVED RESERVED 1 0 SE1_OE SE1 Output enable 0 = Output Disabled, 1 = Output Enabled 0 0 SE2_OE SE2 Output enable 0 = Output Disabled, 1 = Output Enabled 0000 = CK505 Yellow Cover Device, 56-pin TSSOP 0001 = CK505 Yellow Cover Device, 64-pin TSSOP 0010 = CK505 Yellow Cover Device, 48-pin QFN (reserved) 0011 = CK505 Yellow Cover Device, 56-pin QFN (reserved) 0100 = CK505 Yellow Cover Device, 64-pin QFN (reserved) 0101 = CK505 Yellow Cover Device, 72-pin QFN (reserved) 0110 = CK505 Yellow Cover Device, 48-pin SSOP (reserved) 0111 = CK505 Yellow Cover Device, 56-pin SSOP (reserved) 1000 = Reserved 1001 = Reserved 1010 = Reserved 1011 = Reserved 1100 = Reserved 1101 = Reserved 1110 = Reserved 1111 = Reserved Byte 9 Control Register 9 Bit @Pup Name ......................Document #: 001-03543 Rev *E Page 8 of 27 Description SPL505YC25 Byte 9 Control Register 9 7 0 PCIF0_STP_CTRL 6 HW_Pin TME_STRAP 5 1 REF_DSC1 4 0 TEST_MODE_SEL 3 0 TEST_MODE_ENTRY 2 1 IO_VOUT2 1 0 IO_VOUT1 0 1 IO_VOUT0 Allows control of PCIF0 with assertion of PCI_STOP# 0 = Free running PCIF, 1 = Stopped with PCI_STOP# Trusted mode enable strap status, 0 = normal, 1 = no overclocking REF drive strength control, See Byte 18 for more setting 0 = Low, 1 = High Mode select either REF/N or tri-state 0 = All output tri-state, 1 = All output REF/N Allow entry into test mode 0=Normal operation, 1=Enter test mode IO_VOUT[2,1,0] 000 = 0.3V 001 = 0.4V 010 = 0.5V 011 = 0.6V 100 = 0.7V 101 = 0.8V, Default 110 = 0.9V 111 = 1.0V Byte 10 Control Register 10 Bit @Pup Name 7 HW SRC5_EN_STRAP Description 6 1 PLL3_EN PLL3 Enabled 0 = PLL3 disabled, 1 = PLL3 enabled 5 1 PLL2_EN PLL2 Enabled 0 = PLL2 disabled, 1 = PLL2 enabled 4 1 SRC_DIV_EN SRC Divider Enabled 0 = SRC Divider disabled, 1 = SRC Divider enabled 3 1 PCI_DIV_EN PCI Divider Enabled 0 = PCI Divider disabled, 1 = PCI Divider enabled 2 1 CPU_DIV_EN CPU Divider Enabled 0 = CPU Divider disabled, 1 = CPU Divider enabled 1 1 CPU1_STP_CRTL Allow control of CPU1 with assertion of CPU_STOP# 0 = Free running, 1 = Stopped with CPU_STOP# 0 1 CPU0_STP_CRTL Allow control of CPU0 with assertion of CPU_STOP# 0 = Free running, 1 = Stopped with CPU_STOP# Read only bit for SRC5_EN_STRAP 0 = CPU/PCI_STOP enabled, 1 = SRC5 pair enabled Byte 11 Control Register 11 Bit @Pup Name 7 HW PCI3_CFG1 6 HW PCI3_CFG0 5 0 25MHz_EN_SE1 Description PCI3/ PCI3/ CGF1 CGF0 PLL1 PLL2 PLL3 Mode Output SSC Output SSC Output 0 0 -Def CPU / SRC / PCI33 Down USB NA -- -- 0 1 1 CPU Down USB NA SRC/PCI33 Down 1 0 2 CPU Center USB NA SRC/PCI33 Down 1 1 3 CPU Center USB/25M NA SRC/PCI33 Down 25MHz Output Enabled applies to Powerdown / M1 (Only applies when PCI3/CGFG0 strap is set high to enter HW mode 3) 0 = 25MHz disabled in Powerdown / M1 1 = 25MHz enabled in Powerdown / M1; Sticky 1 4 1 RESERVED SSC 0 RESERVED ......................Document #: 001-03543 Rev *E Page 9 of 27 SPL505YC25 Byte 11 Control Register 11 3 0 CPU2_AMT_EN 2 1 CPU1_AMT_EN 1 HW PCI-E_GEN2 0 1 CPU2_STP_CRTL PCIF0/ITP_EN AMT_EN CPU2_AMT_EN CPU1_AMT_EN x 1 0 0 Description Reserved x 1 0 1 CPU1 = M1 Clock 1 1 1 0 CPU2 - M1 Clock 1 1 1 1 CPU1 and CPU2 = M1 Clock PCI-E_Gen2 Compliant 0 = non Gen2, 1= Gen2 Compliant Allow control of CPU2 with assertion of CPU_STOP# 0 = Free running, 1 = Stopped with CPU_STOP# Byte 12 Byte Count Bit @Pup Name 7 0 RESERVED Description 6 0 RESERVED 5 0 BC5 Byte count 4 0 BC4 Byte count 3 1 BC3 Byte count 2 1 BC2 Byte count 1 0 BC1 Byte count 0 1 BC0 Byte count RESERVED RESERVED Byte 13 Control Register 13 Bit @Pup Name Description 7 1 USB_DSC1 USB drive strength control, See Byte 18 for more setting 0 = Low, 1= High 6 1 PCI/PCIF_DSC1 PCI drive strength control, See Byte 18 for more setting 0 = Low, 1 = High 5 0 RESERVED 4 0 SATA_SS_EN 3 1 EN_CFG0_SET By defalult CFG0 pin strap sets the SMBus initial values to select the HW mode. When this bit is written0, subsequent SMBus accesses is the Lathes Open state, can overwrite the CFG0 pin setting into the SMBus bits and set the mode before the M0 state: specifically B0b2, B1b[6,4,3], B9b1, B11b5 2 1 SE1/SE2_DSC1 SE1 and SE2 drive strength control, See Byte 18 for more setting 0 = Low, 1 = High 1 1 RESERVED 0 1 SW_PCI SW PCI_STP# Function 0 = SW PCI_STP assert, 1 = SW PCI_STP deassert When this bit is set to 0, all STOPPABLE PCI, PCIF and SRC outputs will be stopped in a synchronous manner with no short pulses. When this bit is set to 1, all STOPPED PCI, PCIF and SRC outputs will resume in a synchronous manner with no short pulses. Name Description RESERVED Enable SATA spread modulation, 0 = Spread Disabled 1 = Spread Enabled RESERVED Byte 14 Control Register 14 Bit @Pup ....................Document #: 001-03543 Rev *E Page 10 of 27 SPL505YC25 Byte 14 Control Register 14 7 0 CPU_DAF_N7 6 0 CPU_DAF_N6 5 0 CPU_DAF_N5 4 0 CPU_DAF_N4 3 0 CPU_DAF_N3 2 0 CPU_DAF_N2 1 0 CPU_DAF_N1 0 0 CPU_DAF_N0 If Prog_CPU_EN is set, the values programmed in CPU_DAF_N[8:0] and CPU_DAF_M[6:0] will be used to determine the CPU output frequency. The setting of the FS_Override bit determines the frequency ratio for CPU and other output clocks. When it is cleared, the same frequency ratio stated in the Latched FS[C:A] register will be used. When it is set, the frequency ratio stated in the FSEL[2:0] register will be used Byte 15 Control Register 15 Bit @Pup Name 7 0 CPU_DAF_N8 See Byte 14 for description Description 6 0 CPU_DAF_M6 5 0 CPU_DAF_M5 4 0 CPU_DAF_M4 3 0 CPU_DAF_M3 2 0 CPU_DAF_M2 If Prog_CPU_EN is set, the values programmed are in CPU_FSEL_N[8:0] and CPU_FSEL_M[6:0] will be used to determine the CPU output frequency. The setting of the FS_Override bit determines the frequency ratio for CPU and other output clocks. When it is cleared, the same frequency ratio stated in the Latched FS[C:A] register will be used. When it is set, the frequency ratio stated in the FSEL[2:0] register will be used 1 0 CPU_DAF_M1 0 0 CPU_DAF_M0 Byte 16 Control Register 16 Bit @Pup Name Description 7 0 PCI-E_N7 6 0 PCI-E_N6 If Prog_SRC_EN is set, the values programmed in SRC_DAF_N[7:0] will be used to determine the SRC output frequency. 5 0 PCI-E_N5 4 0 PCI-E_N4 3 0 PCI-E_N3 2 0 PCI-E_N2 1 0 PCI-E_N1 0 0 PCI-E_N0 Byte 17 Control Register 17 Bit @Pup Name Description 7 0 SMSW_EN Enable Smooth Switching, 0 = Disabled, 1= Enabled 6 0 SMSW_SEL Smooth switch select, 0 = CPU_PLL, 1 = SRC_PLL 5 0 RESERVED 4 0 Prog_PCI-E_EN Programmable PCI-E frequency enable 0 = Disabled, 1= Enabled 3 0 Prog_CPU_EN Programmable CPU frequency enable 0 = Disabled, 1= Enabled 2 0 RESERVED RESERVED 1 0 RESERVED RESERVED 0 0 RESERVED RESERVED RESERVED ....................Document #: 001-03543 Rev *E Page 11 of 27 SPL505YC25 Byte 18 Control Register 18 Bit @Pup Name Description 7 0 PCI_DSC2 6 1 PCI_DSC0 5 0 USB_DSC2 4 0 USB_DSC0 3 0 SE1/SE2_DSC2 2 0 SE1/SE2_DSC0 1 0 REF_DSC2 0 0 REF_DSC0 Drive Strength Control - DSC[2:0] DSC_2 (Byte18) 1 (Vario us B ytes) 1 DSC_0 (Byte 18) 1 1 1 0 1 0 1 1 0 0 Def ault PCI 0 1 1 Def ault REF/Usb 0 1 0 0 0 1 0 0 0 DSC_1 Buf f er Strength Strongest Weakest Table 5. Crystal Recommendations Frequency (Fund) Cut Loading Load Cap Drive (max.) Shunt Cap (max.) Motional (max.) Tolerance (max.) Stability (max.) Aging (max.) 14.31818 MHz AT Parallel 0.1 mW 5 pF 0.016 pF 35 ppm 30 ppm 5 ppm 20 pF The SPL505YC256BT/ SPL505YC256BS requires a parallel resonance crystal. Substituting a series resonance crystal causes the SPL505YC256BT/ SPL505YC256BS to operate at the wrong frequency and violate the ppm specification. For most applications there is a 300-ppm frequency shift between series and parallel crystals due to incorrect loading. Crystal Loading Crystal loading plays a critical role in achieving low ppm performance. To realize low ppm performance, the total capacitance the crystal sees must be considered to calculate the appropriate capacitive loading (CL). Calculating Load Capacitors In addition to the standard external trim capacitors, trace capacitance and pin capacitance must also be considered to correctly calculate crystal loading. As mentioned previously, the capacitance on each side of the crystal is in series with the crystal. This means the total capacitance on each side of the crystal must be twice the specified crystal load capacitance (CL). While the capacitance on each side of the crystal is in series with the crystal, trim capacitors (Ce1,Ce2) should be calculated to provide equal capacitive loading on both sides. Clock Chip Figure 1 shows a typical crystal configuration using the two trim capacitors. An important clarification for the following discussion is that the trim capacitors are in series with the crystal not parallel. The common misconception that load capacitors are in parallel with the crystal and should be approximately equal to the load capacitance of the crystal is not true. Ci2 Ci1 Pin 3 to 6p Cs1 X2 X1 Cs2 Trace 2.8 pF XTAL Ce1 Ce2 Trim 33 pF Figure 2. Crystal Loading Example Figure 1. Crystal Capacitive Clarification ....................Document #: 001-03543 Rev *E Page 12 of 27 SPL505YC25 Use the following formulas to calculate the trim capacitor values for Ce1 and Ce2. 0, the allowable values for M are detailed in the Frequency Select Table. Load Capacitance (each side) SRC_DAF Enable – This bit enables SRC DAF mode. By default, it is not set. When set, the operating frequency is determined by the values entered into the SRC_DAF_N register. Note that the SRC_DAF_N register must contain valid values before SRC_DAF is set. Default = 0, (No DAF). Ce = 2 * CL – (Cs + Ci) Total Capacitance (as seen by the crystal) CLe = 1 1 ( Ce1 + Cs1 + Ci1 + 1 Ce2 + Cs2 + Ci2 ) CL ................................................... Crystal load capacitance CLe .........................................Actual loading seen by crystal using standard value trim capacitors Ce .....................................................External trim capacitors Cs ............................................. Stray capacitance (terraced) Ci .......................................................... Internal capacitance (lead frame, bond wires etc.) Dial-A-Frequency (CPU & PCIEX) This feature allows users to over-clock their systems by slowly stepping up the CPU or SRC frequency. When the programmable output frequency feature is enabled, the CPU and SRC frequencies are determined by the following equation: Fcpu = G * N/M or Fcpu=G2 * N, where G2 = G/M. ‘N’ and ‘M’ are the values programmed in Programmable Frequency Select N-Value Register and M-Value Register, respectively. ‘G’ stands for the PLL Gear Constant, which is determined by the programmed value of FS[E:A]. See Frequency Table for the Gear Constant for each Frequency selection. The PCI Express only allows user control of the N register, the M value is fixed and documented in the Frequency Select Table. In this mode, the user writes the desired N and M value into the DAF I2C registers. The user cannot change only the M value and must change both the M and the N values at the same time, if they require a change to the M value. The user may change only the required N value. Associated Register Bits CPU_DAF Enable – This bit enables CPU DAF mode. By default, it is not set. When set, the operating frequency is determined by the values entered into the CPU_DAF_N register. Note that the CPU_DAF_N and M register must contain valid values before CPU_DAF is set. Default = 0, (No DAF). CPU_DAF_N – There are nine bits (for 512 values) to linearly change the CPU frequency (limited by VCO range). Default = 0, (0000). The allowable values for N are detailed in the Frequency Select Table. CPU DAF M – There are 7 bits (for 128 values) to linearly change the CPU frequency (limited by VCO range). Default = ....................Document #: 001-03543 Rev *E Page 13 of 27 SRC_DAF_N – There are nine bits (for 512 values) to linearly change the CPU frequency (limited by VCO range). Default = 0, (0000). The allowable values for N are detailed in the Frequency Select Table. Smooth Switching The device contains 1 smooth switch circuit that is shared by the CPU PLL and SRC PLL. The smooth switch circuit ensures that when the output frequency changes by overclocking, the transition from the old frequency to the new frequency is a slow, smooth transition containing no glitches. The rate of change of output frequency when using the smooth switch circuit is less than 1 MHz/0.667 s. The frequency overshoot and undershoot is less than 2%. The Smooth Switch circuit can be assigned as auto or manual. In Auto mode, clock generator will assign smooth switch automatically when the PLL does overclocking. For manual mode, the smooth switch circuit can be assigned to either PLL via SMBus. By default the smooth switch circuit is set to auto mode. Either PLL can still be over-clocked when it does not have control of the smooth switch circuit but it is not guaranteed to transition to the new frequency without large frequency glitches. It is not recommended to enable over-clocking and change the N values of both PLLs in the same SMBUS block write and use smooth switch mechanism on spread spectrum on/off. PD# Clarification The CK_PWRGD/PD# pin is a dual-function pin. During initial power-up, the pin functions as CK_PWRGD. Once CK_PWRGD has been sampled HIGH by the clock chip, the pin assumes PD# functionality. The PD# pin is an asynchronous active LOW input used to shut off all clocks cleanly prior to shutting off power to the device. This signal is synchronized internal to the device prior to powering down the clock synthesizer. PD# is also an asynchronous input for powering up the system. When PD# is asserted LOW, all clocks need to be driven to a LOW value and held prior to turning off the VCOs and the crystal oscillator. PD Assertion When PS is sampled HIGH by two consecutive rising edges of CPUC, all single-ended outputs will be held LOW on their next HIGH-to-LOW transition and differential clocks must held LOW. In the event that PD mode is desired as the initial power-on state, PD must be asserted HIGH in less than 10 s after asserting CK_PWRGD. SPL505YC25 PD# CPUT, 133MHz CPUC, 133MHz SRCT 100MHz SRCC 100MHz USB, 48MHz DOT96T DOT96C PCI, 33 MHz REF Figure 3. PD Assertion Timing Waveform PD# Deassertion The power-up latency is less than 1.8 ms. This is the time from the deassertion of the PD# pin or the ramping of the power supply until the time that stable clocks are output from the clock chip. All differential outputs stopped in a three-state condition resulting from power down will be driven high in less than 300 s of PD# deassertion to a voltage greater than 200 mV. After the clock chip’s internal PLL is powered up and locked, all outputs will be enabled within a few clock cycles of each other. Below is an example showing the relationship of clocks coming up. Tstable 200 mV CPU_STP# Deassertion Waveform 1.8mS CPU_STOP# PD# CPUT(Free Running CPUC(Free Running CPUT(Stoppable) CPUC(Stoppable) DOT96T DOT96C CPU_STP# = Driven, CPU_PD = Driven, DOT_PD = Driven ....................Document #: 001-03543 Rev *E Page 15 of 27 SPL505YC25 1.8mS CPU_STOP# PD# CPUT(Free Running) CPUC(Free Running) CPUT(Stoppable) CPUC(Stoppable) DOT96T DOT96C CPU_STP# = Tri-state, CPU_PD = Tri-state, DOT_PD = Tri-state PCI_STP# Assertion The PCI_STP# signal is an active LOW input used to synchronously stop and start the PCI outputs while the rest of the clock generator continues to function. The set-up time for capturing PCI_STP# going LOW is 10 ns (tSU). (See Figure 5.) The PCIF clocks will not be affected by this pin if their corresponding control bit in the SMBus register is set to allow them to be free running. T su P C I_S T P # P C I_F PCI S R C 100M H z Figure 5. PCI_STP# Assertion Waveform PCI_STP# Deassertion The deassertion of the PCI_STP# signal causes all PCI and stoppable PCIF clocks to resume running in a synchronous manner within two PCI clock periods after PCI_STP# transitions to a HIGH level. Tsu Tdrive_SRC PCI_STP# PCI_F PCI SRC 100MHz Figure 6. PCI_STP# Deassertion Waveform ....................Document #: 001-03543 Rev *E Page 16 of 27 SPL505YC25 Figure 7. CK_PWRGD Timing Diagram . Table 6. Output Driver Status during PCI-STOP# and CPU-STOP# PCI_STOP# Asserted Single-ended Clocks Stoppable Differential Clocks CPU_STOP# Asserted Driven Low Running SMBus OE Disabled Driven Low Non Stoppable Running Running Stoppable Clock Drive High Clock# Driven Low Clock Drive High Clock# Driven Low Non Stoppable Running Running Driven Low or 20K pulldown Table 7. Output Driver Status All Single-ended Clocks All Differential Clocks except CPU1 w/o Strap w/Strap Clock Latches Open State Low Hi-Z Low or 20K pulldown Low Low or 20K pulldown Low Powerdown Low Hi-Z Low or 20K pulldown Low Low or 20K pulldown Low M1 Low Hi-Z Low or 20K pulldown Low Running PD_RESTORE If a ‘0’ is set for Byte 0 bit 0 then, upon assertion of PWRDWN# LOW, the CY505 will initiate a full reset. The results of this will be that the clock chip will emulate a cold power on start and go to the ‘Latches Open’ state. If the PD_RESTORE bit is set to a ‘1’ then the configuration is stored upon PWRDWN# asserted LOW. Note that if the iAMT bit, Byte 0 bit 3, is set to a ‘1’ then the PD_RESTORE bit must be ignored. In other words, in Intel iAMT mode, PWRDWN# reset is not allowed. ....................Document #: 001-03543 Rev *E Page 17 of 27 Clock# CPU1 Clock Clock# Running SPL505YC25 Figure 8. Clock Generator Power-up/Run State Diagram ....................Document #: 001-03543 Rev *E Page 18 of 27 SPL505YC25 Absolute Maximum Conditions Parameter Description Condition Min. Max. Unit VDD Core Supply Voltage –0.5 4.6 V VDD_A Analog Supply Voltage –0.5 4.6 V VDD_IO IO Supply Voltage 1.5 V VIN Input Voltage Relative to VSS –0.5 4.6 VDC TS Temperature, Storage Non-functional –65 150 °C TA Temperature, Operating Ambient Functional 0 85 °C TJ Temperature, Junction Functional – 150 °C ØJC Dissipation, Junction to Case Mil-STD-883E Method 1012.1 – 20 °C/W ØJA Dissipation, Junction to Ambient JEDEC (JESD 51) – 60 °C/W ESDHBM ESD Protection (Human Body Model) MIL-STD-883, Method 3015 2000 – V UL-94 Flammability Rating MSL Moisture Sensitivity Level At 1/8 in. V–0 1 Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. DC Electrical Specifications Parameter Description VDD core 3.3V Operating Voltage Condition 3.3 ± 5% Min. Max. Unit 3.135 3.465 V VIH 3.3V Input High Voltage (SE) 2.0 VDD + 0.3 V VIL 3.3V Input Low Voltage (SE) VSS–0.3 0.8 V VIHI2C Input High Voltage SDATA, SCLK 2.2 – V VILI2C Input Low Voltage SDATA, SCLK – 1.0 V VIH_FS FS_[A,B] Input High Voltage 0.7 1.5 V VIL_FS FS_[A,B] Input Low Voltage VSS–0.3 0.35 V VIHFS_C_TEST FS_C Input High Voltage 2 VDD + 0.3 V 0.7 1.5 V VIMFS_C_NORMAL FS_C Input Middle Voltage VILFS_C_NORMAL FS_C Input Low Voltage PCI3/CFG0_HIGH PCI3/CFG0 Input High Voltage PCI3/CFG0_MID PCI3/CFG0 Input Mid Voltage VSS–0.3 0.35 V Typ. 2.75V 2.40 VDD V Typ. 1.65V 1.30 2.00 V PCI3/CFG0_LOW PCI3/CFG0 Input Low Voltage Typ. 0.550V 0 0.900 V IIH Input High Leakage Current except internal pull-down resistors, 0< VIN