Si823Hx Data Sheet
4.0 A Symmetric Drive ISODrivers with Low Propagation Delay
and High Transient Immunity
The Si823Hx combines two isolated gate drivers into a single package for high power
applications. The Si823Hx includes devices with single or dual control inputs with
independent or high-side/low-side outputs. These drivers can operate with a 3.0 – 5.5
V input VDD and a maximum drive supply voltage of 30 V.
The Si823Hx is ideal for driving power MOSFETs and IGBTs used in a wide variety
of switched power and motor control applications. These drivers utilize Skyworks'
proprietary silicon isolation technology, supporting up to 5 kVRMS for 1 minute isolation
voltage. This technology enables high CMTI (125 kV/µs), lower propagation delays
and skew, little variation with temperature and age, and low part-to-part matching.
The unique architecture of the output stage features a booster device that provides
a higher pull up capability at the Miller plateau region of the load power switch to
support faster turn-on times. This driver family also offers some unique features such
as over-temperature protection, output Undervoltage Lockout (UVLO) fault detection,
dead time programmability and fail-safe drivers with default low in case of loss of
input side power. The Si823Hx family offers longer service life and dramatically higher
reliability compared to opto-coupled gate drivers.
Automotive Grade is available. These products are built using automotive specific
flows at all steps in the manufacturing process to ensure the robustness and low
defectivity required for automotive applications.
Industrial Applications
• Power delivery systems
• Motor control systems
• Isolated dc-dc power supplies
Automotive Applications
• On-board chargers
• Battery management systems
• Charging stations
KEY FEATURES
• Single or two isolated drivers in one package
• Up to 5 kVRMS isolation
• Up to 1500 VDC peak driver-to-driver
differential voltage
• EN pin for enhanced safety or DIS pin option
• PWM and dual driver versions
• 4.0 A sink/source peak output
• High electromagnetic immunity
• 30 ns max propagation delay
• Transient immunity: >125 kV/µs
• Programmable dead time: 20 – 200 ns
• Deglitch option for filtering noise
• Wide temperature range: –40 to +125 °C
• RoHS-compliant packages
• WB SOIC-14
• DFN-14
• NB SOIC-8
• SSO-8
• NB SOIC-16
• AEC-Q100 qualification
• Lighting control systems
• Solar and industrial inverters
• Automotive-grade OPNs available
• AIAG-compliant PPAP documentation
support
• IMDS and CAMDS listing support
• Traction inverters
• Hybrid Electric Vehicles
• Battery Electric Vehicles
Safety Approval
• UL 1577 recognized
• Up to 5000 VRMS for 1 minute
• CSA certification conformity
• IEC 62368-1 (reinforced insulation)
• VDE certification conformity
• EN 62368-1 (reinforced insulation)
• CQC certification approval
• GB4943.1
1
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • December 3, 2021
1
Si823Hx Data Sheet • Ordering Guide
1. Ordering Guide
Industrial and Automotive Grade OPNs
Industrial-grade devices (part numbers having an “-I” in their suffix) are built using well-controlled, high-quality manufacturing flows to
ensure robustness and reliability. Qualifications are compliant with JEDEC, and defect reduction methodologies are used throughout
definition, design, evaluation, qualification, and mass production steps.
Automotive-grade devices (part numbers having an “-A” in their suffix) are built using automotive-specific flows at all steps in the
manufacturing process to ensure robustness and low defectivity. These devices are supported with AIAG-compliant Production Part
Approval Process (PPAP) documentation, and feature International Material Data System (IMDS) and China Automotive Material
Data System (CAMDS) listing. Qualifications are compliant with AEC-Q100, and a zero-defect methodology is employed throughout
definition, design, evaluation, qualification, and mass production steps.
Table 1.1. Si823Hx Ordering Guide
Ordering Part
Number (OPN)
Automotive
OPN
Configuration
Output Enable /
UVLO Disable
(V)
Dead
Time
Setting
(ns)
Deglitch
Delayed
Startup
Time
Package
Type
Isolation
Rating
(kVRMS)
Products Available Now
Si823H9AC-IS
Si823H9AC-AS
Single
6
EN
N/A
No
No
NB SOIC-8
3.75
Si823H9BC-IS
Si823H9BC-AS
Single
8
EN
N/A
No
No
NB SOIC-8
3.75
Si823H9CC-IS
Si823H9CC-AS
Single
12
EN
N/A
No
No
NB SOIC-8
3.75
Si823H9TC-IS
Si823H9TC-AS
Single
12
DIS
N/A
No
No
NB SOIC-8
3.75
Si823H1AB-IS1 Si823H1AB-AS1
HS/LS, VIA/VIB
6
DIS
20–200
No
No
NB SOIC-16
2.5
Si823H1BB-IS1 Si823H1BB-AS1
HS/LS, VIA/VIB
8
DIS
20–200
No
No
NB SOIC-16
2.5
Si823H1CB-IS1 Si823H1CB-AS1 HS/LS, VIA/VIB
12
DIS
20–200
No
No
NB SOIC-16
2.5
Si823H2AB-IS1 Si823H2AB-AS1
HS/LS, VIA/VIB
6
EN
20–200
No
No
NB SOIC-16
2.5
Si823H2BB-IS1 Si823H2BB-AS1
HS/LS, VIA/VIB
8
EN
20–200
No
No
NB SOIC-16
2.5
Si823H2CB-IS1 Si823H2CB-AS1 HS/LS, VIA/VIB
12
EN
20–200
No
No
NB SOIC-16
2.5
Si823H3AB-IS1 Si823H3AB-AS1
HS/LS, VIA/VIB
6
DIS
20–200
Yes
No
NB SOIC-16
2.5
Si823H3BB-IS1 Si823H3BB-AS1
HS/LS, VIA/VIB
8
DIS
20–200
Yes
No
NB SOIC-16
2.5
Si823H3CB-IS1 Si823H3CB-AS1 HS/LS, VIA/VIB
12
DIS
20–200
Yes
No
NB SOIC-16
2.5
Si823H4AB-IS1 Si823H4AB-AS1
HS/LS, PWM
6
EN
20–200
No
No
NB SOIC-16
2.5
Si823H4BB-IS1 Si823H4BB-AS1
HS/LS, PWM
8
EN
20–200
No
No
NB SOIC-16
2.5
Si823H4CB-IS1 Si823H4CB-AS1
HS/LS, PWM
12
EN
20–200
No
No
NB SOIC-16
2.5
Si823H5AB-IS1 Si823H5AB-AS1
Dual, VIA, VIB
6
EN
N/A
No
No
NB SOIC-16
2.5
Si823H5BB-IS1 Si823H5BB-AS1
Dual, VIA, VIB
8
EN
N/A
No
No
NB SOIC-16
2.5
Si823H5CB-IS1 Si823H5CB-AS1
Dual, VIA, VIB
12
EN
N/A
No
No
NB SOIC-16
2.5
Si823H6AB-IS1 Si823H6AB-AS1
Dual, VIA, VIB
6
DIS
N/A
No
No
NB SOIC-16
2.5
Si823H6BB-IS1 Si823H6BB-AS1
Dual, VIA, VIB
8
DIS
N/A
No
No
NB SOIC-16
2.5
Si823H6CB-IS1 Si823H6CB-AS1
Dual, VIA, VIB
12
DIS
N/A
No
No
NB SOIC-16
2.5
Si823H7AB-IS1 Si823H7AB-AS1
Dual, VIA, VIB
6
EN
N/A
No
Yes
NB SOIC-16
2.5
Si823H7BB-IS1 Si823H7BB-AS1
Dual, VIA, VIB
8
EN
N/A
No
Yes
NB SOIC-16
2.5
Si823H7CB-IS1 Si823H7CB-AS1
Dual, VIA, VIB
12
EN
N/A
No
Yes
NB SOIC-16
2.5
2
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • December 3, 2021
2
Si823Hx Data Sheet • Ordering Guide
Ordering Part
Number (OPN)
Automotive
OPN
Configuration
Output Enable /
UVLO Disable
(V)
Dead
Time
Setting
(ns)
Deglitch
Delayed
Startup
Time
Package
Type
Isolation
Rating
(kVRMS)
Si823H8AB-IS1 Si823H8AB-AS1
HS/LS, PWM
6
DIS
20–200
No
No
NB SOIC-16
2.5
Si823H8BB-IS1 Si823H8BB-AS1
HS/LS, PWM
8
DIS
20–200
No
No
NB SOIC-16
2.5
Si823H8CB-IS1 Si823H8CB-AS1
HS/LS, PWM
12
DIS
20–200
No
No
NB SOIC-16
2.5
Si823H1AB-IM1 Si823H1AB-AM1 HS/LS, VIA/VIB
6
DIS
20–200
No
No
DFN-14
2.5
Si823H1BB-IM1 Si823H1BB-AM1 HS/LS, VIA/VIB
8
DIS
20–200
No
No
DFN-14
2.5
Si823H1CB-IM1 Si823H1CB-AM1 HS/LS, VIA/VIB
12
DIS
20–200
No
No
DFN-14
2.5
Si823H3AB-IM1 Si823H3AB-AM1 HS/LS, VIA/VIB
6
DIS
20–200
Yes
No
DFN-14
2.5
Si823H3BB-IM1 Si823H3BB-AM1 HS/LS, VIA/VIB
8
DIS
20–200
Yes
No
DFN-14
2.5
Si823H3CB-IM1 Si823H3CB-AM1 HS/LS, VIA/VIB
12
DIS
20–200
Yes
No
DFN-14
2.5
Si823H5AB-IM1 Si823H5AB-AM1
Dual, VIA, VIB
6
EN
N/A
No
No
DFN-14
2.5
Si823H5BB-IM1 Si823H5BB-AM1
Dual, VIA, VIB
8
EN
N/A
No
No
DFN-14
2.5
Si823H5CB-IM1 Si823H5CB-AM1
Dual, VIA, VIB
12
EN
N/A
No
No
DFN-14
2.5
Si823H6AB-IM1 Si823H6AB-AM1
Dual, VIA, VIB
6
DIS
N/A
No
No
DFN-14
2.5
Si823H6BB-IM1 Si823H6BB-AM1
Dual, VIA, VIB
8
DIS
N/A
No
No
DFN-14
2.5
Si823H6CB-IM1 Si823H6CB-AM1
Dual, VIA, VIB
12
DIS
N/A
No
No
DFN-14
2.5
Si823H8AB-IM1 Si823H8AB-AM1
HS/LS, PWM
6
DIS
20–200
No
No
DFN-14
2.5
Si823H8BB-IM1 Si823H8BB-AM1
HS/LS, PWM
8
DIS
20–200
No
No
DFN-14
2.5
Si823H8CB-IM1 Si823H8CB-AM1
HS/LS, PWM
12
DIS
20–200
No
No
DFN-14
2.5
Si823H9AD-IS4 Si823H9AD-AS4
Single
6
EN
N/A
No
No
SSO-8
5
Si823H9BD-IS4 Si823H9BD-AS4
Single
8
EN
N/A
No
No
SSO-8
5
Si823H9CD-IS4 Si823H9CD-AS4
Single
12
EN
N/A
No
No
SSO-8
5
Si823H9TD-IS4 Si823H9TD-AS4
Single
12
DIS
N/A
No
No
SSO-8
5
Si823H1AD-IS3 Si823H1AD-AS3 HS/LS, VIA/VIB
6
DIS
20–200
No
No
WB SOIC-14
5
Si823H1BD-IS3 Si823H1BD-AS3 HS/LS, VIA/VIB
8
DIS
20–200
No
No
WB SOIC-14
5
Si823H1CD-IS3 Si823H1CD-AS3 HS/LS, VIA/VIB
12
DIS
20–200
No
No
WB SOIC-14
5
Si823H2AD-IS3 Si823H2AD-AS3 HS/LS, VIA/VIB
6
EN
20–200
No
No
WB SOIC-14
5
Si823H2BD-IS3 Si823H2BD-AS3 HS/LS, VIA/VIB
8
EN
20–200
No
No
WB SOIC-14
5
Si823H2CD-IS3 Si823H2CD-AS3 HS/LS, VIA/VIB
12
EN
20–200
No
No
WB SOIC-14
5
Si823H3AD-IS3 Si823H3AD-AS3 HS/LS, VIA/VIB
6
DIS
20–200
Yes
No
WB SOIC-14
5
Si823H3BD-IS3 Si823H3BD-AS3 HS/LS, VIA/VIB
8
DIS
20–200
Yes
No
WB SOIC-14
5
Si823H3CD-IS3 Si823H3CD-AS3 HS/LS, VIA/VIB
12
DIS
20–200
Yes
No
WB SOIC-14
5
Si823H4AD-IS3 Si823H4AD-AS3
HS/LS, PWM
6
EN
20–200
No
No
WB SOIC-14
5
Si823H4BD-IS3 Si823H4BD-AS3
HS/LS, PWM
8
EN
20–200
No
No
WB SOIC-14
5
Si823H4CD-IS3 Si823H4CD-AS3
HS/LS, PWM
12
EN
20–200
No
No
WB SOIC-14
5
Si823H5AD-IS3 Si823H5AD-AS3
Dual, VIA, VIB
6
EN
N/A
No
No
WB SOIC-14
5
3
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • December 3, 2021
3
Si823Hx Data Sheet • Ordering Guide
Ordering Part
Number (OPN)
Automotive
OPN
Configuration
Output Enable /
UVLO Disable
(V)
Dead
Time
Setting
(ns)
Deglitch
Delayed
Startup
Time
Package
Type
Isolation
Rating
(kVRMS)
Si823H5BD-IS3 Si823H5BD-AS3
Dual, VIA, VIB
8
EN
N/A
No
No
WB SOIC-14
5
Si823H5CD-IS3 Si823H5CD-AS3
Dual, VIA, VIB
12
EN
N/A
No
No
WB SOIC-14
5
Si823H6AD-IS3 Si823H6AD-AS3
Dual, VIA, VIB
6
DIS
N/A
No
No
WB SOIC-14
5
Si823H6BD-IS3 Si823H6BD-AS3
Dual, VIA, VIB
8
DIS
N/A
No
No
WB SOIC-14
5
Si823H6CD-IS3 Si823H6CD-AS3
Dual, VIA, VIB
12
DIS
N/A
No
No
WB SOIC-14
5
Si823H7AD-IS3 Si823H7AD-AS3
Dual, VIA, VIB
6
EN
N/A
No
Yes
WB SOIC-14
5
Si823H7BD-IS3 Si823H7BD-AS3
Dual, VIA, VIB
8
EN
N/A
No
Yes
WB SOIC-14
5
Si823H7CD-IS3 Si823H7CD-AS3
Dual, VIA, VIB
12
EN
N/A
No
Yes
WB SOIC-14
5
Si823H8AD-IS3 Si823H8AD-AS3
HS/LS, PWM
6
DIS
20–200
No
No
WB SOIC-14
5
Si823H8BD-IS3 Si823H8BD-AS3
HS/LS, PWM
8
DIS
20–200
No
No
WB SOIC-14
5
Si823H8CD-IS3 Si823H8CD-AS3
HS/LS, PWM
12
DIS
20–200
No
No
WB SOIC-14
5
• All products are rated at 4 A sink and source output drive current max.
• All packages are RoHS-compliant with peak reflow temperatures of 260 °C according to the JEDEC industry standard classifications and peak solder temperatures.
• “Si” and “SI” are used interchangeably.
• All HS/LS drivers have built-in overlap protection while the single and dual drivers do not.
• All options are rated for ambient temperatures from -40 °C to +125 °C, and are recommended for industrial or automotive grade
operation.
• An “R” at the end of the part number denotes tape and the reel packaging option.
• Automotive-Grade devices (with an “-A” suffix) are identical in construction materials and electrical parameters to their IndustrialGrade (with an “-I” suffix) version counterpart. Automotive-Grade products are produced utilizing full automotive process flows
and additional statistical process controls throughout the manufacturing flow. The Automotive-Grade part number is included on
shipping labels.
• In Top Markings, the Manufacturing Code represented by either “RTTTTT” or “TTTTTT” contains as its first character a letter in the
range N through Z to indicate Automotive-Grade.
4
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Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • December 3, 2021
4
Table of Contents
1. Ordering Guide
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 Functional Description
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. 7
2.2 Family Overview and Logic Operation During Startup .
2.2.1 Device Behavior . . . . . . . . . . . .
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2.3 Layout Considerations .
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.10
2.4 Undervoltage Lockout Operation .
2.4.1 Device Startup . . . . .
2.4.2 Undervoltage Lockout . . .
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2.5 Control Inputs .
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2.6 Enable Input .
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2.7 Disable Input
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.12
2.8 Delayed Startup Time.
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2.9 Programmable Dead Time and Overlap Protection .
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2.10 De-glitch Feature .
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.14
2.11 Thermal Protection .
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.14
2.12 Driver Output Booster Function .
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.14
3. Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15
3.1 Si823H9 Single Driver
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.15
3.2 Si823H9T Single Driver .
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.15
3.3 PWM Input Driver .
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.16
3.4 Dual Driver or HS/LS Driver
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.17
4. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .
18
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4.1 Typical Operating Characteristics .
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.24
5. Top-Level Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . .
26
6. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
30
7. Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32
7.1 8-Pin Narrow Body SOIC (NB SOIC-8) .
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.32
7.2 8-Pin Wide Body Stretched SOIC (SSO-8)
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.33
7.3 16-Pin Narrow Body SOIC (NB SOIC-16) .
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.34
7.4 14-Pin Wide Body SOIC (WB SOIC-14)
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7.5 14 LD DFN (DFN-14) .
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8. Land Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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8.1 8-Pin Narrow Body SOIC (NB SOIC-8) .
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8.2 8-Pin Wide Body Stretched SOIC (SSO-8)
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8.3 16-Pin Narrow Body SOIC (NB SOIC-16) .
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8.4 14-Pin Wide Body SOIC (WB SOIC-14)
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9. Top Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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9.1 8-Pin Narrow Body SOIC (NB SOIC-8) .
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9.2 8-Pin Wide Body Stretched SOIC (SSO-8)
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9.3 16-Pin Narrow Body SOIC (NB SOIC-16) .
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9.4 14-Pin Wide Body SOIC (WB SOIC-14)
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9.5 14 LD DFN .
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10. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Si823Hx Data Sheet • System Overview
2. System Overview
2.1 Functional Description
The operation of an Si823Hx channel is analogous to that of an optocoupler and gate driver, except an RF carrier is modulated instead
of light. This simple architecture provides a robust isolated data path and requires no special considerations or initialization at start-up.
A simplified block diagram for a single Si823Hx channel is shown in the figure below.
Transmitter
Receiver
Driver
RF OSCILLATOR
VDD
A
DEAD TIME
CONTROL
MODULATOR
SemiconductorBased Isolation
Barrier
DEMODULATOR
4 A peak
B
Gnd
Figure 2.1. Simplified Channel Diagram
A channel consists of an RF Transmitter and RF Receiver separated by a semiconductor based isolation barrier. Referring to the
Transmitter, input A modulates the carrier provided by an RF oscillator using on/off keying. The Receiver contains a demodulator that
decodes the input state according to its RF energy content and applies the result to output B via the output driver. This RF on/off keying
scheme is superior to pulse code schemes as it provides best-in-class noise immunity, low power consumption, and better immunity to
magnetic fields. See the figure below for more details.
Input Signal
Modulation Signal
Output Signal
Figure 2.2. Modulation Scheme
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Si823Hx Data Sheet • System Overview
2.2 Family Overview and Logic Operation During Startup
The Si823Hx family of isolated drivers consists of single, high-side/low-side, and dual driver configurations.
2.2.1 Device Behavior
The following are truth tables for the Si823Hx families.
Table 2.1. Si823H9 Single Channel Driver
VI
EN1
VDDI
VDD
VO+
VO-
Notes
H
H
P
P
H
Hi-Z
L
H
P
P
Hi-Z
L
X
L or NC
P
P
Hi-Z
L
Device disabled
X
X
UP1
P
Hi-Z
L
Fail-safe output when VDDI is unpowered.
X
X
X
UP
UD2
UD2
Output undetermined if VDD is unpowered.
P = Powered, UP = Unpowered
Notes:
1. The chip can be powered through the VI input ESD diodes even if VDDI is unpowered. It is recommended that inputs be left
unpowered when VDDI is unpowered.
2. UD = undetermined if same side power is UP.
Table 2.2. Si823H9T Single Channel Driver
VI
DIS
VDDI1
VDD1
VO
H
L or NC
P
P
H
L
L or NC
P
P
L
X
H
P
P
L
Device disabled.
X
X
UP2
P
L
Fail-safe output when VDDI is unpowered.
X
X
X
UP
UD3
Output undetermined if VDD is unpowered.
Notes
Note:
1. P = Powered; UP = Unpowered.
2. The chip can be powered through the VI input ESD diodes even if VDDI is unpowered. It is recommended that inputs be left
unpowered when VDDI is unpowered.
3. UD = undetermined if same side power is UP.
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Si823Hx Data Sheet • System Overview
Table 2.3. Si823H1/2/3/5/6/7 HS/LS and Dual (VIA/VIB) Drivers
VIA
VIB
DIS / EN1
VDDI
VDDA
VDDB
VOA
VOB
Notes
H
L
L/H
P
P
P
H
L
L
H
L/H
P
P
P
L
H
H
H
L/H
P
P
P
H / L4
H / L4
L
L
L/H
P
P
P
L
L
X
X
H / L or NC
P
P
P
L
L
Device disabled
X
X
X
UP2
P
P
L
L
Fail-safe output when VDDI unpowered
H
X
L/H
P
P
UP
H
UD3
L
X
L/H
P
P
UP
L
UD3
X
H
L/H
P
UP
P
UD3
H
X
L
L/H
P
UP
P
UD3
L
VOB depends on VDDB state
VOA depends on VDDA state
P = Powered, UP = Unpowered
Notes:
1. There are different product options available. For any one product, either EN or DIS is present.
2. The chip can be powered through the VIA,VIB input ESD diodes even if VDDI is unpowered. It is recommended that inputs be left
unpowered when VDDI is unpowered.
3. UD = undetermined if same side power is UP.
4. On the HS/LS driver (Si823H1/2/3) options, VOA and VOB = L when VIA and VIB =H; for dual driver options (Si823H5/6), VOA
and VOB = H when VIA and VIB = H.
Table 2.4. Si823H4/8 PWM Input HS/LS Drivers
PWM
DIS / EN1
VDDI
VDDA
VDDB
VOA
VOB
Notes
H
L/H
P
P
P
H
L
L
L/H
P
P
P
L
H
X
H / L or NC
P
P
P
L
L
Device disabled
X
X
UP2
P
P
L
L
Fail-safe output when VDDI unpowered
H
L/H
P
P
UP
H
UD3
L
L/H
P
P
UP
L
UD3
H
L/H
P
UP
P
UD3
L
L
L/H
P
UP
P
UD3
H
See Figure 2.7 Dead Time note and Dead
Time Waveforms for High-Side/Low-Side
Drivers on page 13 for timing
VOB depends on VDDB state
VOA depends on VDDA state
P = Powered, UP = Unpowered
Note:
1. There are different product options available. For any one product, either EN or DIS is present.
2. The chip can be powered through the VIA,VIB input ESD diodes even if VDDI is unpowered. It is recommended that inputs be left
unpowered when VDDI is unpowered. The EN pin has a special ESD circuit that prevents the IC from powering up through the
EN pin.
3. UD = undetermined if same side power is UP.
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Si823Hx Data Sheet • System Overview
2.3 Layout Considerations
It is most important to minimize ringing in the drive path and noise on the Si823Hx VDD lines. Care must be taken to minimize parasitic
inductance in these paths by locating the Si823Hx as close to the device it is driving as possible. In addition, the VDD supply and
ground trace paths must be kept short. For this reason, the use of power and ground planes is highly recommended. A split ground
plane system having separate ground and VDD planes for power devices and small signal components provides the best overall noise
performance. For placement of the decoupling capacitors, it is recommended that the 0.1 μf capacitor should be placed as close as
possible to the VDDA/B supply pins. The 10 μf capacitor can be a little farther away.
2.4 Undervoltage Lockout Operation
Device behavior during start-up, normal operation and shutdown is shown in 2.4.2 Undervoltage Lockout, where UVLO+ and UVLOare the positive-going and negative-going thresholds respectively. Note that outputs VOA and VOB default low when input side power
supply (VDDI) is not present.
2.4.1 Device Startup
Outputs VOA and VOB are held low during power-up until VDD is above the UVLO threshold for time period tSTART. Following this, the
outputs follow the states of inputs VIA and VIB.
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Si823Hx Data Sheet • System Overview
2.4.2 Undervoltage Lockout
Undervoltage Lockout (UVLO) is provided to prevent erroneous operation during device startup and shutdown or when VDD is below its
specified operating circuits range. The input (control) side, Driver A, and Driver B each have their own undervoltage lockout monitors.
The Si823Hx input side enters UVLO when VDDI ≤VDDIUV–, and exits UVLO when VDDI > VDDIUV+. The driver outputs, VOA and
VOB, remain low when the input side of the Si823Hx is in UVLO and their respective VDD supply (VDDA, VDDB) is within tolerance.
Each driver output can enter or exit UVLO independently. For example, VOA unconditionally enters UVLO when VDDA falls below
VDDAUV– and exits UVLO when VDDA rises above VDDAUV+.
UVLO+
UVLO-
VDDHYS
VDDI
UVLO+
UVLO-
VDDHYS
VDDA
VIA/PWM
EN
tSTART_OUT
tSTART
tSTART
tSD
tRESTART
tPHL
tPLH
VOA
Figure 2.3. Si823H2/4/5/7/9 Device Behavior During Normal Operation and Shutdown
UVLO+
UVLO-
VDDHYS
VDDI
UVLO+
UVLO-
VDDHYS
VDDA
VIA/PWM
DIS
tSTART_OUT
tSTART
tSTART
tSD
tRESTART
tPHL
tPLH
VOA
Figure 2.4. Si823H1/3/6/8 Device Behavior During Normal Operation and Shutdown
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Si823Hx Data Sheet • System Overview
Figure 2.5. Si823H7 (Delayed Startup Time of tSTART_SAFE) Device Behavior During Normal Operation and Shutdown
2.5 Control Inputs
VIA, VIB, and PWM inputs are high-true, TTL level-compatible logic inputs. A logic high signal on VIA or VIB causes the corresponding
output to go high. For PWM input versions (Si823H4/8), VOA is high and VOB is low when the PWM input is high, and VOA is low and
VOB is high when the PWM input is low.
2.6 Enable Input
When brought low, the EN input unconditionally drives VOA and VOB low regardless of the states of VIA and VIB. Device operation
terminates within tSD after EN = VIL and resumes within tRESTART after EN = VIH. The EN input has no effect if VDDI is below its
UVLO level (i.e., VOA, VOB remain low). There is an internal pull-down resistor of 100 kOhm on the EN pin.
2.7 Disable Input
When brought high, the DISABLE input unconditionally drives VOA and VOB low regardless of the states of VIA and VIB. (For the
Si823H9Tx, when brought high, the DISABLE input unconditionally drives VO low regardless of the state of VI.) Device operation
terminates within tSD after DISABLE =VIH and resumes within tRESTART after DISABLE = VIL or open. The DISABLE input has no
effect if VDDI is below its UVLO level (i.e., VOA, VOB remain low). There is an internal pull-down resistor of 100 kΩ on the DIS pin.
2.8 Delayed Startup Time
Product options Si823H7 have a safe startup time (tSTARTUP_SAFE) of 1 ms typical from input power valid to output showing valid
data. This feature allows users to proceed through a safe initialization sequence with a monotonic output behavior.
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Si823Hx Data Sheet • System Overview
2.9 Programmable Dead Time and Overlap Protection
All high-side/low-side drivers and PWM drivers (single input) include programmable dead time, which adds a user-programmable delay
between transitions of VOA and VOB. When asserted, dead time is present only on output rising edges, when the other input is
also high. If only one input is high, there is no dead time added to the output transition. Please see figure below for a graphical
representation of dead time implementation. The amount of dead time delay (DT) is programmed by a single resistor (RDT) connected
from the DT input to ground per the equation below. The DT is measured as the time elapsed between VOA low to VOB high and vice
versa.
For products with Dead Time setting of 20-200ns:
DT ~ 1.8 x (RDT) + 12, where DT = Typical Dead Time in ns, RDT = Dead Time Resistor in kΩ
Pulse 1
Pulse 2
Pulse 3
VIA
VIB
DT present to
ensure VOB = low
Pulse 2 is before VOA = high
missing
(VIB = high)
Pulse 1 edges
have no DT
(VIB = low)
VOA
DT present to
ensure VOA = low
before VOB = high
No DT
(VIA = low)
DT present to
ensure VOA = low
before VOB = high
VOB
No DT since immediate
turn-off is required
(VIA = VIB = high)
Figure 2.6. Dead Time Implementation & Behavior
VIA/
PWM
VIB
DT
90%
VOA
10%
90%
VOB
DT
10%
Figure 2.7. Dead Time Waveforms for High-Side/Low-Side Drivers
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Si823Hx Data Sheet • System Overview
2.10 De-glitch Feature
A de-glitch feature is provided on some devices, as defined in the 1. Ordering Guide. The de-glitch basically provides an internal time
delay during which any noise is ignored and will not pass through the IC. There are two distinct de-glitch circuits, one each on the input
and output (after the signal has been coupled across the isolation barrier) side. Please see Table 4.1 Electrical Characteristics on page
18 for the delays associated with these circuits.
2.11 Thermal Protection
Si823Hx has built-in temperature sensors for protection against high temperature resulting from overloading the driver, too high of an
ambient temperature, or external component failures. If high internal temperature (>150 °C) is detected, the output is forced to low
state.
2.12 Driver Output Booster Function
The output driver pull-up capability is enabled by two parallel drivers: a standard PMOS device and an NMOS helper transistor. The
PMOS device provides a standard 1 A pull-up and the DC pull-up when VO is close to VDD. The NMOS helper provides higher pull-up
currents around the miller plateau of the driven power transistor, supporting fast turn-on times. See Figure 2.8 on page 14 for the
internal architecture scheme and Figure 2.9 on page 14 for the pull-up current characteristics.
VDD
1A
3A i1
i2
+3A peak
Pullup booster
VO
FET load
4A
GND
Figure 2.8. Pull-Up Booster Simplified Architecture
Figure 2.9. Pull-Up Current Characteristics, VDD = 12 V
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Si823Hx Data Sheet • Applications
3. Applications
The following examples illustrate typical circuit configurations using the Si823Hx.
3.1 Si823H9 Single Driver
The following figure shows the Si823H9 single driver controlled by a single digital signal. Note that the input side of the Si823H9
requires VDDI in the range of 3.0 to 5.5 V, while the VDD output side supply must be between 5.5 and 30 V referred to GND. The VO+
(pull-up) and VO- (pull-down) outputs are shown connected to the gate of Q1. The gate resistors Rg1 and Rg2 shown could be different
values to allow full utilization of the separate pull-up and pull-down outputs provided to control turn-on and turn-off times respectively.
Also note that the bypass capacitors on the Si823H9 should be located as close to the chip as possible.
VDD
VDDI
C1
1 µF
CONTROLLER
C2
0.1 µF
VDDI
VDD
GNDI
GND
C4
10 µF
C3
0.1 µF
1500 V max
Rg1
Si823H9
VO+
Q1
VI
OUT
Rg2
VO-
I/O
EN
Figure 3.1. Si823H9 Single Driver
3.2 Si823H9T Single Driver
The following figure shows the Si823H9T single driver controlled by a single digital signal. Note that the input side of the Si823H9
requires VDDI in the range of 3.0 to 5.5 V, while the VDD output side supply must be between 5.5 and 30 V referred to GND. The VO
output is shown connected to the gate of Q1. The gate resistor shown, Rg, can have different values to control turn-on and turn-off
times. Also note that the bypass capacitors on the Si823H9T should be located as close to the chip as possible.
VDD
VDDI
C1
1 µF
CONTROLLER
C2
0.1 µF
VDDI
VDD
GNDI
GNDB
Si823H9T
OUT
I/O
VI
C4
10 µF
C3
0.1 µF
Rg
VO
1500 V max
Q1
DIS
Figure 3.2. Si823H9T Single Driver
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Si823Hx Data Sheet • Applications
3.3 PWM Input Driver
The following figure shows the Si823Hx controlled by a single PWM signal.
Power Supply
for VDDB
C3
1 µF
VDDI
C1
1 µF
D1
VDDI
C2
0.1 µF
1500 V max
GNDI
VDDA
CB
PWMOUT
CDT
100 pF
CONTROLLER
Q1
PWM
VOA
GNDA
DT
RDT
Si823Hx
Power Supply
for VDDB
VDDB
C4
0.1 µF
I/O
C5
10 µF
EN / DIS
GNDB
Q2
VOB
Figure 3.3. Si823H4/8 PWM input with EN/DIS Pin Application Diagram
In the above figure, D1 and CB form a conventional bootstrap circuit that allows VOA to operate as a high-side driver for Q1, which
has a maximum drain voltage of 1500 V. VOB is connected as a conventional low-side driver. Note that the input side of the Si823Hx
requires VDDI in the range of 3.0 to 5.5 V, while the VDDA and VDDB output side supplies must be between 5.5 and 30 V referred to
their respective grounds. The boot-strap start up time will depend on the CB cap chosen. Also note that the bypass capacitors on the
Si823Hx should be located as close to the chip as possible.
16
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Si823Hx Data Sheet • Applications
3.4 Dual Driver or HS/LS Driver
The following figure shows the device configured as a dual driver or HS/LS driver. Note that the drain voltages of Q1 and Q2 can be
referenced to a common ground or to different grounds with as much as 1500 Vdc between them.
Power Supply
for VDDB
C3
1 µF
VDDI
C1
1 µF
D1
VDDI
C2
0.1 µF
1500 V max
GNDI
VDDA
CB
OUT 1
VIA
OUT 2
VIB
Q1
VOA
GNDA
Si823Hx
CONTROLLER
Power Supply
for VDDB
VDDB
C4
0.1 µF
I/O
C5
10 µF
EN / DIS
GNDB
Q2
VOB
Figure 3.4. Si823H1/2/3/5/6/7 with EN/DIS Pin Application Diagram
Because each output driver resides on its own die, the relative voltage polarities of VOA and VOB can reverse without damaging the
driver. A dual driver can operate as a dual low-side or dual high-side driver and is unaffected by static or dynamic voltage polarity
changes.
17
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Si823Hx Data Sheet • Electrical Characteristics
4. Electrical Characteristics
Table 4.1. Electrical Characteristics1, 2
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
5.5
V
DC Specifications
Input-side Power Supply Voltage
Driver Supply Voltage
Input Supply Quiescent Current EN = 0
VDDI
VDDA, VDDB, VDD
3.0
Voltage between VDDA and
GNDA, and VDDB and GNDB,
or VDD and GND
IDDI(Q)
5.5
—
30
V
—
1.3
2.0
mA
Input Supply Active Current
(with one channel active)
IDDI
Input freq = 1 MHz
—
2.2
3.3
mA
Input Supply Active Current
(with both channels active)
IDDI
Input freq = 1 MHz
—
3.6
4.75
mA
—
2.3
2.8
mA
—
5.6
9.0
mA
Output Supply Quiescent Current,
per channel EN = 0
Output Supply Active Current, per channel
IDDA(Q), IDDB(Q),
IDD (Q)
IDDA/B, IDD
Input freq = 1 MHz,
no load
Input Pin Leakage Current, VIA, VIB, VI,
PWM
IVIA, IVIB, IPWM, IVI
–10
—
+10
µA
Input Pin Leakage Current, EN, DIS
IENABLE, IDISABLE
–40
—
+40
µA
Logic High Input Threshold
VIH
TTL Levels
1.6
1.8
2.0
V
Logic Low Input Threshold
VIL
TTL Levels
0.8
1
1.2
V
800
—
mV
—
—
V
Input Hysteresis
VIHYST
Logic High Output Voltage
VOAH, VOBH, VOH+,
VOH
IO = –1 mA
VDDA–
0.064,
VDDB–
0.064,
VDD–
0.064
Logic Low Output Voltage
VOAL, VOBL, VOL–,
VOL
IO = 1 mA
—
—
0.04
V
Output Short-Circuit Pulsed Sink Current
IOA(SCL), IOB(SCL),
IO-(SCL), IO(SCL)
CL = 220 nF
—
4.0
—
A
Output Short-Circuit Pulsed Source Current
IOA(SCH), IOB(SCH),
IO+(SCH), IO(SCH)
CL = 220 nF
—
4.0
—
A
RON(SINK)
—
1.0
—
Ω
RON(SOURCE)
—
4.2
—
Ω
Output Sink Resistance
Output Source Resistance
VDDI Undervoltage Threshold
VDDI Lockout Hysteresis
18
VDDIUV+
VDDI rising
1.9
2.1
2.4
V
VDDIUV-
VDDI falling
1.85
2.0
2.3
V
30
60
—
mV
VDDIHYS
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Si823Hx Data Sheet • Electrical Characteristics
Parameter
Symbol
Test Condition
Min
Typ
Max
VDDAUV+,VDDBUV+,
VDDUV+
VDDA, VDDB, VDD rising
Unit
5.6
6.1
6.6
7.5
8.1
8.8
11.3
12.2
13.4
5.4
5.8
6.3
7.0
7.6
8.2
10.3
11.1
12.0
UVLO = 6 V
250
320
—
UVLO = 8 V
450
550
—
UVLO = 12 V
950
1200
—
Si823H1/2/5/6/7/9x
(with no deglitch)
—
30
—
ns
Si823H3x
(with deglitch)
—
96
—
ns
tpHL, tpLH
Si823H1/2/5/6/7/9x
(with no deglitch)
10
19
30
ns
tpHL, tpLH
Si823H3x
(with deglitch)
56
89
116
ns
10
19
30
ns
14
39
58
ns
3
5
ns
—
—
10
ns
—
2.7
5
ns
RDT = 6 kΩ
10
20
28
RDT = 15 kΩ
29
38
47
RDT = 100 kΩ
145
180
210
CL = 200 pF
—
—
12
All options with
no deglitch
—
—
35
All options with
deglitch
—
—
65
All options with
no deglitch
—
—
35
All options with
deglitch
—
VDDA, VDDB Undervoltage Threshold
6 V Threshold
8 V Threshold
12 V Threshold
V
VDDA, VDDB Undervoltage Threshold
6 V Threshold
8 V Threshold
VDDAUV–,VDDBUV–,
VDDUV–
VDDA, VDDB,
VDD falling
12 V Threshold
VDDA, VDDB Lockout Hysteresis
VDDAHYS,VDDBHYS,
VDDHYS
V
mV
AC Specifications
Minimum Pulse Width (No Load)
PWmin
Propagation Delay
VDDA/B = 12 V
CL = 0 pF
tpHL
tpLH
Output Channel to Channel Skew
Propagation Delay Skew3
Pulse Width Distortion |tPLH – tPHL|
Programmed Dead Time when available
Output Rise and Fall Time
Shutdown Time from Enable False
(or Disable True)
Restart Time from Enable True
(or Disable False)
19
Si823H4/8
(with no deglitch; measured
with 6 kΩ RDT resistor; includes minimum dead time)
tPSK
tPSK(P-P)
PWD
DT
tR,tF
tSD
tRESTART
VDDA/B = 12 V
CL = 0 pF
ns
ns
ns
ns
—
65
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Si823Hx Data Sheet • Electrical Characteristics
Parameter
Device Start-up Time Input
Time from VDDI_ = VDDI_UV+ to
VOA,VOB = VIA, VIB
Symbol
Test Condition
Min
Typ
Max
Unit
tSTART_SAFE
Si823H7
—
1
—
ms
tSTART
Si823H1/2/3/4/5/6/8/9
—
40
—
μs
tSTART_OUT
Si823H1/2/3/4/5/6/7/8/9
—
60
—
μs
CMTI
VIA, VIB, VI, PWM = VDDI
or 0 V, VCM = 1500 V
125
—
—
kV/μs
Device Start-up Time Output
Time from VDDA/B/VDD = VDDA/VDDB/
VDD_UV+ to VOA, VOB, VO = VIA, VIB,
VI
Common Mode Transient Immunity
Note:
1. 3.0 V < VDDI < 5.5 V; 6.5 V < VDDA, VDDB < 30 V; TA = –40 to +125 °C.
2. Typical specs at 25 °C, VDDA = VDDB = 12 V for 5 V and 8 V UVLO devices, otherwise 15 V.
3. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same
supply voltages, load, and ambient temperature.
Test Circuits
12 V
Supply
Input Signal
Switch
5V
Isolated
Supply
VDDI
VDDA
INPUT
VOA
DIS
GNDA
DT
VDDB
Oscilloscope
VOB
100k
GNDI
GNDB
Isolated
Ground
Input
High Voltage
Differential
Probe
Output
Vcm Surge
Output
High Voltage
Surge Generator
Figure 4.1. Common Mode Transient Immunity (CMTI) Test Circuit
20
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Si823Hx Data Sheet • Electrical Characteristics
Table 4.2. Regulatory Information1, 3, 4
CSA
The Si823Hx is certified under CSA, see Master Contract Number 232873.
62368-1: Up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage.
VDE
The Si823Hx is certified under VDE. For more details, see File 5006301.
62368-1: Up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage.
UL
The Si823Hx is certified under UL1577 component recognition program. For more details, see File E257455.
Rated up to 5000 VRMS isolation voltage VISO for basic protection.
CQC
The Si823Hx is certified under GB4943.1-2011.
Rated up to 250 VRMS reinforced insulation working voltage at 5000 meters.
Note:
1. Regulatory Certifications apply to 2.5 kVRMS rated devices which are production tested to 3.0 kVRMS for 1sec.
2. Regulatory Certifications apply to 3.75 kVRMS rated devices which are production tested to 4.5 kVRMS for 1sec.
3. Regulatory Certifications apply to 5.0 kVRMS rated devices which are production tested to 6.0 kVRMS for 1sec.
4. For more information, see Chapter 1. Ordering Guide.
21
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Si823Hx Data Sheet • Electrical Characteristics
Table 4.3. Insulation and Safety-Related Specifications
Parameter
Symbol
Test
Condition
Value
NB SOIC-16
2.5 kVRMS
NB SOIC-8
3.75 kVRMS
SSO-8
5 kVRMS
WB SOIC-14
5 kVRMS
DFN-14
2.5 kVRMS
Unit
Nominal External Air Gap
(Clearance)1
CLR
4.7
4.7
9.0
8.0
3.5
mm
Nominal External Tracking
(Creepage)1
CRP
3.9
3.9
8.0
8.0
3.5
mm
Minimum Internal Gap
(Internal Clearance)
DTI
0.016
0.016
0.016
0.016
0.016
mm
600
600
600
600
600
V
Tracking Resistance
CTI or PTI
IEC60112
Top: 0.051
Erosion Depth
ED
0.019
0.031
0.040
0.019
Resistance
(Input-Output)2
RIO
1012
1012
1012
1012
1012
Ω
Capacitance
(Input-Output)2
CIO
2.0
1.3
1.0
1.7
1.7
pF
3.0
2.8
2.8
3.0
2.9
pF
Input Capacitance3
f = 1 MHz
CI
mm
Bottom: 0.087
Notes:
1. The values in this table correspond to the nominal creepage and clearance values.
2. To determine resistance and capacitance, the device is converted into a 2-terminal device. All pins on side 1 and all pins on side
2 are shorted.
3. Measured from input pin to ground.
Table 4.4. IEC 60664-1 Ratings
Specification
Parameter
Test Condition
SSO-8,
WB SOIC-14
NB SOIC-8/16,
DFN-14
Material Group
I
I
Rated Mains Voltages < 150 VRMS
I-IV
I-IV
Rated Mains Voltages < 300 VRMS
I-IV
I-IV
Rated Mains Voltages < 400 VRMS
I-IV
I-III
Rated Mains Voltages < 600 VRMS
I-IV
I-III
Basic Isolation Group
Installation Classification
Table 4.5. Thermal Characteristics
22
Parameter
Symbol
NB SOIC-16
NB SOIC-8
SSO-8
WB SOIC-14
DFN-14
Unit
IC Junction-to-Air
Thermal Resistance
θJA
63
110
90
59
105
°C/W
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Si823Hx Data Sheet • Electrical Characteristics
Table 4.6. Absolute Maximum Ratings1
Parameter
Symbol
Min
Max
Unit
Ambient Temperature under Bias
TA
–40
+125
°C
Storage Temperature
TSTG
–65
+150
°C
Junction Temperature
TJ
—
+150
°C
Input-side Supply Voltage
VDDI
–0.6
6.0
V
Driver-side Supply Voltage
VDDA, VDDB, VDD
–0.6
36
V
–5.0
VDD + 0.5
VIA, VIB, VI, EN, DIS,DT
-0.6
VDD + 0.5
IOPK
—
6.0
A
—
260
°C
HBM
—
4
kV
CDM
(EN/DIS pin only)
—
0.25
kV
CDM
(all other pins)
—
0.5
kV
VIA, VIB, VI
Voltage on any Pin with respect
to Ground
Peak Output Current (tPW = 10
µs, duty cycle = 0.2%)
Transient for 50 ns
Lead Solder Temperature (10 s)
ESD per AEC-Q100
V
Note:
1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be restricted to
the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
23
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Si823Hx Data Sheet • Electrical Characteristics
4.1 Typical Operating Characteristics
The typical performance characteristics depicted in this subsection are for information purposes only. Refer to Chapter 4. Electrical
Characteristics for actual specification limits.
30
Tr
4
Tf
3
2
TA = 25 °C
CL = 100 pF
1
Propagation Delay (ns)
Rise/Fall Time (ns)
5
0
25
TPHL
20
TPLH
15
TA = 25 °C
CL = 100 pF
10
10
15
20
VDDA/B (V)
25
30
Figure 4.2. Rise/Fall Time vs. Supply Voltage
10
15
20
VDDA/B (V)
25
30
Figure 4.3. Propagation Delay vs. Supply Voltage
(No de-glitch product options)
Rise/Fall Time
25
Tr
20
15
Tf
10
TA = 25 °C
VDDA/B = 12 V
5
Propagation Delay (ns)
30
TPHL
25
20
TPLH
15
10
TA = 25 °C
VDDA/B = 12 V
5
0
0
2
4
Load (nF)
Figure 4.4. Rise/Fall Time vs. Load
24
6
0
2
4
Load (nF)
6
Figure 4.5. Propagation Delay vs. Load
(No de-glitch product options)
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Si823Hx Data Sheet • Electrical Characteristics
4
TPHL
25
20
TPLH
15
10
CL = 100 pF
VDDA/B = 12 V
5
Supply Current (mA)
Propagation Delay (ns)
30
0
IDD
2
Duty Cycle = 50%
f = 100 kHz
1 Channel Switching
CL = 0 pF
VDDA/B = 12 V
1
0
0
50
Temperature (°C)
100
0
Figure 4.6. Propagation Delay vs. Temperature
50
Temperature (°C)
100
Figure 4.7. Supply Current vs. Temperature
12
6
1000kHz
500kHz
4
100kHz
50 kHz
2
Duty Cycle = 50%
f = 100 kHz
1 Channel Switching
Supply Current (mA)
8
Supply Current (mA)
3
10
0
Duty Cycle = 50%
f = 100 kHz
1 Channel Switching
8
1000kHz
6
500kHz
4
100kHz
50 kHz
2
0
10
15
20
25
Supply Voltage (V)
30
Figure 4.8. Supply Current vs. Supply Voltage (CL = 0 pF)
10
15
20
25
Supply Voltage (V)
30
Figure 4.9. Supply Current vs. Supply Voltage (CL = 100 pF)
9
7
Output Current (A)
Output Current (A)
8
7
Sink
6
5
Source
6
Sink
5
Source
4
4
VDDA/B = 15 V
3
3
5
10
15
20
Supply Voltage (V)
25
30
Figure 4.10. Peak Output Current vs. Supply Voltage
25
0
50
Temperature (°C)
100
Figure 4.11. Peak Output Current vs. Temperature
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Si823Hx Data Sheet • Top-Level Block Diagrams
5. Top-Level Block Diagrams
VDD
VDDI
UVLO
I S O L A TI O N
VI
UVLO
OVER-TEMPERATURE
PROTECTION
VO+
VO-
EN
GND
GNDI
Figure 5.1. Si823H9 Single Isolated Drivers
VDD
VDDI
UVLO
I S O L A TI O N
VI
UVLO
VO
OVER-TEMPERATURE
PROTECTION
DIS
GNDB
GNDI
Figure 5.2. Si823H9T Single Isolated Drivers
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Si823Hx Data Sheet • Top-Level Block Diagrams
VDDA
I S O L A TI O N
VIA
UVLO
VOA
OVER-TEMPERATURE
PROTECTION
DT CONTROL
&
OVERLAP
PROTECTION
DT
GNDA
VDDB
I S O L A TI O N
VDDI
UVLO
UVLO
VOB
OVER-TEMPERATURE
PROTECTION
EN
GNDB
VIB
GNDI
Figure 5.3. Si823H2 HS/LS Isolated Drivers with EN
VDDA
I S O L A TI O N
VIA
UVLO
VOA
OVER-TEMPERATURE
PROTECTION
DT CONTROL
&
OVERLAP
PROTECTION
DT
GNDA
VDDB
UVLO
DIS
I S O L A TI O N
VDDI
UVLO
VOB
OVER-TEMPERATURE
PROTECTION
GNDB
VIB
GNDI
Figure 5.4. Si823H1/3 HS/LS Isolated Drivers with DIS
27
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Si823Hx Data Sheet • Top-Level Block Diagrams
VDDA
I S O L A TI O N
PWM
LPWM
UVLO
VOA
OVER-TEMPERATURE
PROTECTION
DT CONTROL
&
OVERLAP
PROTECTION
DT
GNDA
VDDB
I S O L A TI O N
VDDI
UVLO
UVLO
VOB
OVER-TEMPERATURE
PROTECTION
EN
GNDB
LPWM
GNDI
Figure 5.5. Si823H4 Single-Input Isolated Drivers with EN
VDDA
I S O L A TI O N
PWM
LPWM
UVLO
VOA
OVER-TEMPERATURE
PROTECTION
DT CONTROL
&
OVERLAP
PROTECTION
DT
GNDA
VDDB
UVLO
I S O L A TI O N
VDDI
UVLO
VOB
OVER-TEMPERATURE
PROTECTION
DIS
GNDB
LPWM
GNDI
Figure 5.6. Si823H8 Single-Input Isolated Drivers with DIS
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Si823Hx Data Sheet • Top-Level Block Diagrams
VDDA
I S O L A TI O N
VIA
UVLO
VOA
OVER-TEMPERATURE
PROTECTION
GNDA
VDDB
UVLO
I S O L A TI O N
VDDI
UVLO
VOB
OVER-TEMPERATURE
PROTECTION
DIS
GNDB
VIB
GNDI
Figure 5.7. Si823H6 Dual Isolated Drivers with DIS
VDDA
I S O L A TI O N
VIA
UVLO
VOA
OVER-TEMPERATURE
PROTECTION
GNDA
VDDB
UVLO
EN
I S O L A TI O N
VDDI
UVLO
VOB
OVER-TEMPERATURE
PROTECTION
GNDB
VIB
GNDI
Figure 5.8. Si823H5/7 Dual Isolated Drivers with EN
29
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Si823Hx Data Sheet • Pin Descriptions
6. Pin Descriptions
VI
1
VDDI
2
GNDI
3
EN
4
Si823H9
8
VDD
VDDI
1
7
VO+
VI
2
6
VO-
DIS
3
5
GND
GNDI
4
Si823H9T
8
GND
7
NC
6
VO
5
VDD
Figure 6.1. Si823H9 NB and Si823H9T NB SOIC-8 and SSO-8
PWM
1
16
VDDA
NC
2
15
VOA
GNDA
VDDI
3
14
GNDA
13
NC
GNDI
4
13
NC
12
NC
EN/DIS
5
12
NC
6
11
VDDB
DT
6
11
VDDB
NC
7
10
VOB
NC
7
10
VOB
VDDI
8
9
VDDI
8
9
GNDB
VIA
1
16
VDDA
VIB
2
15
VOA
VDDI
3
14
GNDI
4
EN/DIS
5
DT/NC
Si823H1/2/3/5/6/7
GNDB
Si823H4/8
Figure 6.2. Si823Hx NB SOIC-16
PWM
1
14
VDDA
NC
2
13
VOA
VDDI
3
12
GNDA
GNDI
4
EN/DIS
5
VDDB
DT
6
11
VDDB
VOB
NC
7
10
VOB
VDDI
8
9
VIA
1
14
VDDA
VIB
2
13
VOA
VDDI
3
12
GNDA
GNDI
4
EN/DIS
5
DT/NC
6
11
NC
7
10
VDDI
8
9
Si823H1/2/3/5/6/7
GNDB
Si823H4/8
GNDB
Figure 6.3. Si823Hx WB SOIC-14
30
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Si823Hx Data Sheet • Pin Descriptions
GNDI
1
14
VDDA
VIA/PWM
2
13
VOA
VIB
3
12
GNDA
VDDI
4
11
NC
EN/DIS
5
10
VDDB
DT/NC
6
9
VOB
VDDI
7
8
GNDB
Si823H1/3/5/6/8
Figure 6.4. Si823Hx DFN-14
Table 6.1. Pin Descriptions
Pin Name
PWM
VI
PWM input
Non-inverting logic input terminal for single driver.
VIA
Non-inverting logic input terminal for Driver A.
VIB
Non-inverting logic input terminal for Driver B.
VDDI
Input-side power supply terminal; connect to a source of 3.0 to 5.5 V.
GNDI
Input-side ground terminal.
EN
Device ENABLE. When asserted, this input enables normal operation of the device. When low
or NC, this input unconditionally drives outputs VOA, VOB LOW. When high, device is enabled
to perform in normal operating mode. It is strongly recommended that this input be connected to
external logic level to avoid erroneous operation due to capacitive noise coupling.
DIS
Device DISABLE. When asserted, this input unconditionally drives outputs VOA, VOB LOW. (For
Si823H9Tx, when asserted, this input unconditionally drives output VO LOW.) When low or NC,
device is enabled to perform in normal operating mode. It is strongly recommended that this input
be connected to external logic level to avoid erroneous operation due to capacitive noise coupling.
DT
Dead time programming input. The value of the resistor connected from DT to ground sets the dead
time between output transitions of VOA and VOB.
NC
No connection.
GNDB
Ground terminal for Driver B.
GND
Ground terminal for single driver.
VOB
Driver B output (low-side driver).
VDDB
Driver B power supply voltage terminal; connect to a source of 5.5 to 30 V.
GNDA
Ground terminal for Driver A.
VOA
Driver A output (high-side driver).
VO+
Pull-up output for single driver.
VO–
Pull-down output for single driver.
VO
Driver output for single driver.
VDD
Driver supply for single driver.
VDDA
31
Description
Driver A power supply voltage terminal; connect to a source of 5.5 to 30 V.
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Si823Hx Data Sheet • Package Outlines
7. Package Outlines
7.1 8-Pin Narrow Body SOIC (NB SOIC-8)
The figure below illustrates the package details for the Si823Hx in an 8-pin narrow-body SOIC package. The table below lists the values
for the dimensions shown in the illustration.
α
Figure 7.1. 8-Pin Narrow Body SOIC Package
Table 7.1. 8-Pin Narrow Body SOIC Package Diagram Dimensions
Symbol
Millimeters
Min
Max
A
1.35
1.75
A1
0.10
0.25
A2
1.40 REF
1.55 REF
B
0.33
0.51
C
0.19
0.25
D
4.80
5.00
E
3.80
4.00
e
32
1.27 BSC
H
5.80
6.20
h
0.25
0.50
L
0.40
1.27
∝
0°
8°
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Si823Hx Data Sheet • Package Outlines
7.2 8-Pin Wide Body Stretched SOIC (SSO-8)
The figure below illustrates the package details for the Si823Hx in a 8-Pin Wide Body Stretched SOIC package. The table below lists
the values for the dimensions shown in the illustration.
Figure 7.2. 8-Pin Wide Body Stretched SOIC Package
Table 7.2. 8-Pin Wide Body Stretched SOIC Package Diagram Dimensions
Dimension
MIN
MAX
A
2.49
2.79
A1
0.36
0.46
b
0.30
0.51
c
0.20
0.33
D
5.74
5.94
E
11.25
11.76
E1
7.39
7.59
e
33
1.27 BSC
L
0.51
1.02
h
0.25
0.76
θ
0°
8°
aaa
--
0.25
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Si823Hx Data Sheet • Package Outlines
Dimension
MIN
MAX
bbb
--
0.25
ccc
--
0.10
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. Recommended reflow profile per JEDEC J-STD-020C specification for small body, lead-free components.
7.3 16-Pin Narrow Body SOIC (NB SOIC-16)
The figure below illustrates the package details for the Si823Hx in a 16-pin narrow-body SOIC. The table below lists the values for the
dimensions shown in the illustration.
Figure 7.3. 16-Pin Narrow Body SOIC
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Si823Hx Data Sheet • Package Outlines
Table 7.3. 16-Pin Narrow Body SOIC Package Diagram Dimensions
Dimension
Min
Max
A
—
1.75
A1
0.10
0.25
A2
1.25
—
b
0.31
0.51
c
0.17
0.25
D
9.90 BSC
E
6.00 BSC
E1
3.90 BSC
e
1.27 BSC
L
0.40
L2
1.27
0.25 BSC
h
0.25
0.50
θ
0°
8°
aaa
0.10
bbb
0.20
ccc
0.10
ddd
0.25
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MS-012, Variation AC.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
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Si823Hx Data Sheet • Package Outlines
7.4 14-Pin Wide Body SOIC (WB SOIC-14)
The figure below illustrates the package details for the Si823Hx in a 14-pin wide-body SOIC. The table below lists the values for the
dimensions shown in the illustration.
Figure 7.4. 14-pin Small Outline Integrated Circuit (SOIC) Package
Table 7.4. Package Diagram Dimensions
Dimension
MIN
MAX
A
—
2.65
A1
0.10
0.30
A2
2.05
—
b
0.35
0.49
c
0.23
0.32
D
10.15
10.45
E
10.05
10.55
E1
7.40
7.60
e
1.27 BSC
e1
3.81 BSC
L
0.40
1.27
h
0.25
0.75
Θ
0ͦ
8ͦ
aaa
—
0.25
bbb
—
0.25
ccc
—
0.10
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. Recommended reflow profile per JEDEC J-STD-020C specification for small body, lead-free components.
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Si823Hx Data Sheet • Package Outlines
7.5 14 LD DFN (DFN-14)
The figure below illustrates the package details for the Si823Hx in an DFN outline. The table below lists the values for the dimensions
shown in the illustration.
Figure 7.5. Si823Hx 14-pin LD DFN Outline
Table 7.5. Package Diagram Dimensions
Dimension
MIN
NOM
MAX
A
0.74
0.85
0.90
A1
0
--
0.05
b
0.25
0.30
0.35
D
4.90
5.00
5.10
e
E
0.65 BSC
4.90
E1
5.00
5.10
3.60 REF
L
0.50
0.60
0.70
L1
0.05
0.10
0.15
ccc
--
--
0.08
ddd
--
--
0.10
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
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Si823Hx Data Sheet • Land Patterns
8. Land Patterns
8.1 8-Pin Narrow Body SOIC (NB SOIC-8)
The figure below illustrates the recommended land pattern details for the Si823Hx in an 8-pin narrow-body SOIC. The table below lists
the values for the dimensions shown in the illustration.
Figure 8.1. 8-Pin Narrow Body SOIC Land Pattern
Table 8.1. 8-Pin Narrow Body SOIC Land Pattern Dimensions
Dimension
Feature
(mm)
C1
Pad Column Spacing
5.40
E
Pad Row Pitch
1.27
X1
Pad Width
0.60
Y1
Pad Length
1.55
Notes:
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P600X173-8N for Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0.05 mm is assumed.
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Si823Hx Data Sheet • Land Patterns
8.2 8-Pin Wide Body Stretched SOIC (SSO-8)
The figure below illustrates the recommended land pattern details for the Si823Hx in a 8-Pin Wide Body Stretched SOIC package. The
table lists the values for the dimensions shown in the illustration.
Figure 8.2. 8-Pin Wide Body Stretched SOIC Land Pattern
Table 8.2. 8-Pin Wide Body Stretched SOIC Land Pattern Dimensions
Symbol
mm
C1
10.60
E
1.27
X1
0.60
Y1
1.85
Note:
General
1. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a
Fabrication Allowance of 0.05 mm.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
Solder Mask Design
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60mm
minimum, all the way around the pad.
Stencil Design
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pins.
Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
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Si823Hx Data Sheet • Land Patterns
8.3 16-Pin Narrow Body SOIC (NB SOIC-16)
The figure below illustrates the recommended land pattern details for the Si823Hx in a 16-pin Narrow Body SOIC. The table lists the
values for the dimensions shown in the illustration.
Figure 8.3. 16-Pin Narrow Body SOIC PCB Land Pattern
Table 8.3. 16-Pin Narrow Body SOIC Land Pattern Dimensions
Dimension
Feature
(mm)
C1
Pad Column Spacing
5.40
E
Pad Row Pitch
1.27
X1
Pad Width
0.60
Y1
Pad Length
1.55
Note:
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P600X165-16N for Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0.05 mm is assumed.
40
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Si823Hx Data Sheet • Land Patterns
8.4 14-Pin Wide Body SOIC (WB SOIC-14)
The figure below illustrates the recommended land pattern details for the Si823Hx in a 14-pin Wide Body SOIC. The table lists the
values for the dimensions shown in the illustration.
Figure 8.4. 14-Pin WB SOIC Land Pattern
Table 8.4. 14-Pin WB SOIC Land Pattern Dimensions
Dimension
Feature
(mm)
C1
Pad Column Spacing
9.70
E
Pad Row Pitch
1.27
X1
Pad Width
0.60
Y1
Pad Length
1.60
Notes:
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P1032X265-16AN for Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0.05 mm is assumed.
41
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Si823Hx Data Sheet • Land Patterns
8.5 14 LD DFN
The figure below illustrates the recommended land pattern details for the Si823Hx in a 14-pin LD DFN. The table below lists the values
for the dimensions shown in the illustration.
Figure 8.5. 14-Pin LGA/DFN Land Pattern
Table 8.5. 14-Pin LD DFN Land Pattern Dimensions
Dimension
(mm)
C1
4.20
E
0.65
X1
0.80
Y1
0.40
Notes:
General
1. All dimensions shown are in millimeters (mm).
2. This Land Pattern Design is based on the IPC-7351 guidelines.
3. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a
Fabrication Allowance of 0.05 mm.
Solder Mask Design
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm
minimum, all the way around the pad.
Stencil Design
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1.
Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
42
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Si823Hx Data Sheet • Top Markings
9. Top Markings
9.1 8-Pin Narrow Body SOIC (NB SOIC-8)
S
i
8
2
V
T
T
3
H
Y
U
Y
Y
W W
T
T
T
T
Table 9.1. Top Marking Explanation (8-Pin Narrow Body SOIC)
Line 1 Marking:
Base Part Number Ordering Options
Si823H = ISOdriver product series
See Chapter 1. Ordering Guide for
more information.
Y = Output configuration:
• 9 = Single driver
U = UVLO level: A, B, C, T
• A=6V
• B=8V
• C = 12 V
• T = 12 V1
Line 2 Marking:
V = Base Part Ordering Option.
See Chapter 1. Ordering Guide for
more information.
YY = Year
WW = Workweek
Line 3 Marking:
TTTTTT = Mfg Code
V = Isolation rating
• C = 3.75 kV
Assigned by Assembly House. Corresponds to the
year and workweek of the mold date.
Manufacturing Code from Assembly Purchase Order
form.
Note:
1. See Figure 6.1 Si823H9 NB and Si823H9T NB SOIC-8 and SSO-8 on page 30 for Si823H9TC pinout.
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Si823Hx Data Sheet • Top Markings
9.2 8-Pin Wide Body Stretched SOIC (SSO-8)
S
i
8
2
V
T
T
3
H
Y
U
Y
Y
W W
T
T
T
T
Table 9.2. Top Marking Explanation (8-Pin Wide Body Stretched SOIC)
Line 1 Marking:
Base Part Number Ordering Options
Si823H = ISOdriver product series
See Chapter 1. Ordering Guide for
more information.
Y = Output configuration:
• 9 = Single driver
U = UVLO level: A, B, C, T
• A=6V
• B=8V
• C = 12 V
• T = 12 V1
Line 2 Marking:
V = Base Part Ordering Option.
See Chapter 1. Ordering Guide
YY = Year
WW = Workweek
Line 3 Marking:
TTTTTT = Mfg Code
V = Isolation rating
• D = 5.0 kV
Assigned by Assembly House. Corresponds to the
year and workweek of the mold date.
Manufacturing Code from Assembly Purchase Order
form.
Note:
1. See Figure 6.1 Si823H9 NB and Si823H9T NB SOIC-8 and SSO-8 on page 30 for Si823H9TC pinout.
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Si823Hx Data Sheet • Top Markings
9.3 16-Pin Narrow Body SOIC (NB SOIC-16)
S
e4
i
8
2
3
H
Y
U
V
Y Y W W T T T T T T
Table 9.3. Top Marking Explanation (16-Pin Narrow Body SOIC)
Line 1 Marking:
Base Part Number Ordering Si823H = ISOdriver product series
Options
Y = Output configuration: 1, 2,3, 4, 5, 6, 7, 8
See 1. Ordering Guide for
• 1 = HS LS, VIA/VIB with a DIS pin
more information.
• 2 = HS LS, VIA/VIB with an EN pin
• 3 = HS LS, VIA/VIB with a DIS pin & de-glitch
• 4 = PWM, HS/LS, EN pin
• 5 = Dual driver, EN pin
• 6 = Dual driver, DIS pin
• 7 = Dual driver, delayed startup time, EN pin
• 8 = PWM, HS/LS, DIS pin
U = UVLO level: A, B, C
• A=6V
• B=8V
• C = 12 V
V = Isolation rating:
• B = 2.5 kV
Line 2 Marking:
YY = Year
WW = Workweek
TTTTTT = Mfg Code
Assigned by the Assembly House. Corresponds to the
year and workweek of the mold date.
Manufacturing Code from Assembly Purchase Order form.
e4 circle is 1.3 mm diameter e4 is Pb-Free Symbol
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Si823Hx Data Sheet • Top Markings
9.4 14-Pin Wide Body SOIC (WB SOIC-14)
S
i
8
2
3
H
Y
U
V
Y Y W W T T T T T T
e4
C C
Table 9.4. Top Marking Explanation (14-Pin Wide Body SOIC)
Line 1 Marking:
Base Part Number Ordering Si823H = ISOdriver product series
Options
Y = Output configuration: 1, 2,3, 4, 5, 6, 7, 8
See 1. Ordering Guide for
• 1 = HS LS, VIA/VIB with a DIS pin
more information.
• 2 = HS LS, VIA/VIB with an EN pin
• 3 = HS LS, VIA/VIB with a DIS pin & de-glitch
• 4 = PWM, HS/LS, EN pin
• 5 = Dual driver, EN pin
• 6 = Dual driver, DIS pin
• 7 = Dual driver, delayed startup time, EN pin
• 8 = PWM, HS/LS, DIS pin
U = UVLO level: A, B, C (applies to both product series)
• A=6V
• B=8V
• C = 12 V
V = Isolation rating:
• D = 5.0 kV
Line 2 Marking:
YY = Year
WW = Workweek
Line 3 Marking:
Assigned by the Assembly House. Corresponds to the
year and workweek of the mold date.
TTTTTT = Mfg Code
Manufacturing Code from Assembly Purchase Order form.
Circle = 1.5 mm Diameter
“e4” Pb-Free Symbol
(Center Justified)
Country of Origin
TW = Taiwan
ISO Code Abbreviation
e4 circle is 1.7 mm diameter e4 is Pb-Free Symbol
46
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Si823Hx Data Sheet • Top Markings
9.5 14 LD DFN
S
i
T
8
T
2
3
H
Y
U
V
T
T
T
T
Y
Y
W
W
Table 9.5. Top Marking Explanation (14-Pin DFN)
Line 1 Marking:
Base Part Number Ordering Si823H = ISOdriver product series
Options
Y = Output configuration: 0, 1, 2,3, 4, 5, 6, 7, 8
See 1. Ordering Guide for
• 1 = HS LS, VIA/VIB with a DIS pin
more information.
• 2 = HS LS, VIA/VIB with an EN pin
• 3 = HS LS, VIA/VIB with a DIS pin & de-glitch
• 4 = PWM, HS/LS, EN pin
• 5 = Dual driver, EN pin
• 6 = Dual driver, DIS pin
• 7 = Dual driver, delayed startup time, EN pin
• 8 = PWM, HS/LS, DIS pin
Line 2 Marking:
Ordering Options
U = UVLO level: A, B, C
• A=6V
• B=8V
• C = 12 V
V = Isolation rating
• B = 2.5 kV
Line 3 Marking:
TTTTTT = Mfg Code
Manufacturing Code from Assembly Purchase Order form.
Line 4 Marking:
YY = Year
Assigned by the Assembly House. Corresponds to the
year and workweek of the mold date.
WW = Workweek
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Si823Hx Data Sheet • Revision History
10. Revision History
Revision 1.1
November, 2021
• Added Electrical Characteristics for Si823H9x products to Table 4.1 Electrical Characteristics1, 2 on page 18.
• Added OPNs for new Si823H9Tx to Table 1.1 Si823Hx Ordering Guide on page 2.
• To address new Si823H9Tx products: added Table 2.2, modified Section 2.7, added Section 3.2 and Figure 3.2, modified Table 4.6,
added Figure 5.2, modified Figure 6.1, modified Table 6.1, updated Tables 9.1 and 9.2.
• Updated Table 4.2 Regulatory Information1, 3, 4 on page 21, Table 4.3 Insulation and Safety-Related Specifications on page 22, and
Table 4.4 IEC 60664-1 Ratings on page 22 with latest regulatory information.
• Deleted irrelevant curve figures from 4.1 Typical Operating Characteristics.
Revision 1.0
February, 2021
• Updated Ordering Guide.
• Formatting, typo, and uniformity edits.
• Changed DT waveform for accuracy.
• Modified EN pin CDM spec.
Revision 0.62
September, 2020
• Updated Electrical Specifications Table.
• Updated Top Marking for NB SOIC-8, SSO-8.
• Updated Insulation and Safety Related Specifications.
• Updated Theta_ja for WB SOIC-14 package.
• Changed nomenclature for DFN-14 package (updated from QFN-14).
• Added Truth Table for Si823H9 single driver.
Revision 0.61
January, 2020
• Updated Ordering Guide.
Revision 0.6
December, 2019
• Updated Ordering Guide.
• Updated 7.4 14-Pin Wide Body SOIC (WB SOIC-14).
Revision 0.5
June, 2019
• Updated Application Diagrams and Top-Level Block Diagrams.
• Added Ordering Guide for Automotive Grade OPNs.
Revision 0.34
January, 2019
• Added OPN Si823H8BB-IM1.
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Si823Hx Data Sheet • Revision History
Revision 0.33
December, 2018
• Separated Si825xx OPNs from this datasheet.
• Labeled 2.5 kVRMS and 3.75 kVRMS products as "Available Now" and 5 kVRMS as "Sampling Now".
• Added Section 2.13 Driver Output Booster Function Description.
• Added NB SOIC-16 package.
Revision 0.1
July, 2017
• Initial release.
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