SL74HC04
Hex Inverter
High-Performance Silicon-Gate CMOS
The SL74HC04 is identical in pinout to the LS/ALS04. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range: 2.0 to 6.0 V • Low Input Current: 1.0 µA • High Noise Immunity Characteristic of CMOS Devices
ORDERING INFORMATION SL74HC04N Plastic SL74HC04D SOIC TA = -55° to 125° C for all packages
LOGIC DIAGRAM PIN ASSIGNMENT
FUNCTION TABLE
Inputs A L H Output Y H L
PIN 14 =VCC PIN 7 = GND
SLS
System Logic Semiconductor
SL74HC04
MAXIMUM RATINGS *
Symbol VCC VIN VOUT IIN IOUT ICC PD T stg TL
*
Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package)
Value -0.5 to +7.0 -1.5 to VCC +1.5 -0.5 to VCC +0.5 ±20 ±25 ±50 750 500 -65 to +150 260
Unit V V V mA mA mA mW °C °C
Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VIN, VOUT TA tr, t f Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1) VCC =2.0 V VCC =4.5 V VCC =6.0 V Min 2.0 0 -55 0 0 0 Max 6.0 VCC +125 1000 500 400 Unit V V °C ns
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN a nd VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V ). CC Unused outputs must be left open.
SLS
System Logic Semiconductor
SL74HC04
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
VCC Symbol VIH Parameter Minimum HighLevel Input Voltage Maximum Low Level Input Voltage Minimum HighLevel Output Voltage Test Conditions VOUT=0.1 V IOUT≤ 20 µA VOUT= VCC-0.1 V IOUT ≤ 20 µA VIN=VIL IOUT ≤ 20 µA VIN=VIL IOUT ≤ 4.0 mA IOUT ≤ 5.2 mA VOL Maximum LowLevel Output Voltage VIN=VIH IOUT ≤ 20 µA VIN=VIH IOUT ≤ 4.0 mA IOUT ≤ 5.2 mA IIN ICC Maximum Input Leakage Current Maximum Quiescent Supply Current (per Package) VIN=VCC or GND VIN=VCC or GND IOUT=0µA V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 6.0 6.0 Guaranteed Limit 25 °C to -55°C 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.98 5.48 0.1 0.1 0.1 0.26 0.26 ±0.1 1.0 ≤85 °C 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.84 5.34 0.1 0.1 0.1 0.33 0.33 ±1.0 10 ≤125 °C 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.7 5.2 0.1 0.1 0.1 0.4 0.4 ±1.0 40 µA µA V Unit V
VIL
V
VOH
V
SLS
System Logic Semiconductor
SL74HC04
AC ELECTRICAL CHARACTERISTICS (CL=50pF,Input t r=t f=6.0 ns)
VCC Symbol tPLH, t PHL Parameter Maximum Propagation Delay, Input A to Output Y (Figures 1 and 2) Maximum Output Transition Time, Any Output (Figures 1 and 2) Maximum Input Capacitance V 2.0 4.5 6.0 2.0 4.5 6.0 Guaranteed Limit 25 °C to -55°C 75 15 13 75 15 13 10 ≤85°C 95 19 16 95 19 16 10 ≤125°C 110 22 19 110 22 19 10 Unit ns
tTLH, t THL
ns
CIN
pF
Power Dissipation Capacitance (Per Inverter) CPD Used to determine the no-load dynamic power consumption: PD=CPDVCC2f+ICCVCC
Typical @25°C,VCC=5.0 V 20 pF
Figure 1 Switching Waveforms.
Figure 2. Test Circuit
EXPANDED LOGIC DIAGRAM (1/6 of the Device)
SLS
System Logic Semiconductor
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