SL74HC161N

SL74HC161 Presettable Counters High-Performance Silicon-Gate CMOS The SL74HC161 is identical in pinout to the LS/ALS161. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. The SL74HC161 is programmable 4-bit synchronous counter that feature parallel Load, asynchronous Reset, a Carry Output for cascading and count-enable controls. The SL74HC161 is binary counter with asynchronous Reset. • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range: 2.0 to 6.0 V • Low Input Current: 1.0 µA • High Noise Immunity Characteristic of CMOS Devices LOGIC DIAGRAM ORDERING INFORMATION SL74HC161N Plastic SL74HC161D SOIC TA = -55° to 125° C for all packages PIN ASSIGNMENT PIN 16 =VCC PIN 8 = GND FUNCTION TABLE Inputs Reset L H H H H H Load X L H H H X Enable P X X X L H X Enable T X X L X H X Clock X Q0 L P0 Outputs Q1 L P1 Q2 L P2 Q3 L P3 Function Reset to “0” Preset Data No count No count Count No count No change No change Count up No change X=don’t care P0,P1,P2,P3 = logic level of Data inputs Ripple Carry Out = Enable T • Q0 • Q1 • Q2 • Q3 SLS System Logic Semiconductor SL74HC161 MAXIMUM RATINGS * Symbol VCC VIN VOUT IIN IOUT ICC PD T stg TL * Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) Value -0.5 to +7.0 -1.5 to VCC +1.5 -0.5 to VCC +0.5 ±20 ±25 ±50 750 500 -65 to +150 260 Unit V V V mA mA mA mW °C °C Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C SOIC Package: : - 7 mW/°C from 65° t o 125°C RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT TA tr, tf Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1) VCC =2.0 V VCC =4.5 V VCC =6.0 V Min 2.0 0 -55 0 0 0 Max 6.0 VCC +125 1000 500 400 Unit V V °C ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN a nd VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V ). CC Unused outputs must be left open. SLS System Logic Semiconductor SL74HC161 DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) VCC Symbol Parameter Test Conditions V Guaranteed Limit 25 °C to -55°C 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.98 5.48 0.1 0.1 0.1 0.26 0.26 ±0.1 4.0 ≤85 °C 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.84 5.34 0.1 0.1 0.1 0.33 0.33 ±1.0 40 ≤125 °C 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.7 5.2 0.1 0.1 0.1 0.4 0.4 ±1.0 160 µA µA V Unit VIH Minimum High-Level Input Vo ltage Maximum Low -Level Input Voltage Minimum High-Level Output Voltage VOUT=0.1 V or VCC-0.1 V IOUT≤ 20 µA VOUT=0.1 V or VCC-0.1 V IOUT ≤ 20 µA VIN=VIH or VIL IOUT ≤ 20 µA VIN=VIH or VIL IOUT ≤ 6.0 mA IOUT ≤ 7.8 mA 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 6.0 6.0 V VIL V VOH V VOL Maximum Low-Level Output Voltage VIN=VIH or VIL IOUT ≤ 20 µA VIN=VIH or VIL IOUT ≤ 6.0 mA IOUT ≤ 7.8 mA IIN ICC Maximum Input Leakage Current Maximum Quiescent Supply Current (per Package) VIN=VCC or GND VIN=VCC or GND IOUT=0µA SLS System Logic Semiconductor SL74HC161 AC ELECTRICAL CHARACTERISTICS (CL=50pF,Input t r=t f=6.0 ns) VCC Symbol fmax Parameter Maximum Clock Frequency (Figures 1,6) V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Guaranteed Limit 25 °C to -55°C 6 30 35 120 20 16 145 22 18 145 20 17 110 16 14 135 18 15 120 22 18 145 22 20 155 22 18 75 15 13 10 ≤85°C 5 24 28 160 23 20 185 25 20 185 22 19 150 18 15 175 20 16 160 27 22 185 28 24 190 26 22 95 19 16 10 ≤125°C 4 20 24 200 28 22 320 30 23 220 25 21 190 20 17 210 22 20 200 30 25 220 35 28 230 30 25 110 22 19 10 Unit MHz tPLH Maximum Propagation Delay Clock to Q tPHL (Figures 1,6) ns ns tPHL Maximum Propagation Delay Reset to Q (Figures 2 and 6) ns tPLH Maximum Propagation Delay Enable T to Ripple Carry Out tPHL (Figures 3,6) ns ns tPLH Maximum Propagation Delay Clock to Ripple tPHL Carry Out (Figures 1,6) ns ns tPHL Maximum Propagation Delay Reset to Ripple Carry Out (Figures 2,6) Maximum Output Transition Time, Any Output (Figures 1 and 6) Maximum Input Capacitance Power Dissipation Capacitance (Per Gate) ns tTLH, t THL ns CIN pF Typical @25°C,VCC=5.0 V 30 pF CPD Used to determine the no-load dynamic power consumption: PD=CPDVCC2f+ICCVCC SLS System Logic Semiconductor SL74HC161 TIMING REQUIREMENTS (CL=50pF,Input t r=t f=6.0 ns) VCC Symbol tSU Parameter Minimum Setup Time, Preset Data Inputs to Clock (Figure 4) Minimum Setup Time, Load to Clock (Figure 4) Minimum Setup Time, Enable T or Enable P to Clock (Figure 5) Minimum Hold Time, Clock to Load or Preset Data Inputs (Figure 4) Minimum Hold Time, Clock to Enable T or Enable P (Figure 5) Minimum Recovery Time, Reset Inactive to Clock (Figure 2) Minimum Recovery Time, Load Inactive to Clock (Figure 4) Minimum Pulse Width, Clock (Figure 1) V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Guaranteed Limit 25 °C to -55°C 40 15 12 60 15 12 80 20 17 3 3 3 3 3 3 80 15 12 80 15 12 60 12 10 60 12 10 1000 500 400 ≤85°C 60 20 18 75 20 18 95 25 23 3 3 3 3 3 3 95 20 17 95 20 17 75 15 13 75 15 13 1000 500 400 ≤125°C 80 30 20 90 30 20 110 35 25 3 3 3 3 3 3 110 26 23 110 26 23 90 18 15 90 18 15 1000 500 400 Unit ns tSU ns tSU ns th ns th ns trec ns trec ns tw ns tw Minimum Pulse Width, Reset (Figure 2) ns tr, tf Maximum Input Rise and Fall Times (Figure 1) ns SLS System Logic Semiconductor SL74HC161 Figure 1. Switching Waveforms Figure 2. Switching Waveforms Figure 3. Switching Waveforms Figure 4. Switching Waveforms Figure 5. Switching Waveforms Figure 6. Test Circuit SLS System Logic Semiconductor SL74HC161 VCC=Pin 16 GND=Pin 8 The flip-flops shown in the circuit diagrams are Toggle-Enable flip-flops. A Toggle-Enable flip-flop is a combination of a D flip-flop and a T flip-flop. When loading data from Preset inputs P0, P1, P2, and P3, the Load signal is used to disable the Toggle input (Tn) of the flip-flop. The logic level at the Pn input is then clocked to the Q output of the flip-flop on the next rising edge of the clock. A logic zero on the Reset device input forces the internal clock (C) high and resets the Q output of the flipflop low. Figure 7.Expanded logic diagram SLS System Logic Semiconductor SL74HC161 Sequence illustrated in waveforms: 1. Reset outputs to zero. 2. Preset to binary twelve. 3. Count to thirteen, fourteen, fifteen, zero, one, and two. 4. Inhibit. Figure 8. Timing Diagram SLS System Logic Semiconductor SL74HC161 TYPICAL APPLICATIONS CASCADING Note:When used in these cascaded configurations the clock fmax guaranteed limits may not apply. Actual performance will depend on number of stages. This limitation is due to set up times between Enable (Port) and clock. Figure 9. N-Bit Synchronous Counters Figure 10. Nibble Ripple Counter SLS System Logic Semiconductor