SL74HC258

SL74HC258 Quad 2-Input Data Selectors/Multiplexer with 3-State Outputs High-Performance Silicon-Gate CMOS The SL74HC258 is identical in pinout to the LS/ALS258. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. This device selects a (4-bit) nibble from either the A or B inputs as determined by the Select input. The nibble is presented at the outputs in inverted form when the Output Enable pin is at a low level. A high level on the Output Enable pin switches the outputs into the highimpedance state. • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range: 2.0 to 6.0 V • Low Input Current: 1.0 µA • High Noise Immunity Characteristic of CMOS Devices ORDERING INFORMATION SL74HC258N Plastic SL74HC258D SOIC TA = -55° to 125° C for all packages PIN ASSIGNMENT LOGIC DIAGRAM FUNCTION TABLE Inputs Output Enable H PIN 16 =VCC PIN 8 = GND L L Select X L H Outputs Y0-Y3 Z A 0-A3 B0-B3 X=don’t care Z = high-impedance state A0-A3,B0-B3=the levels of the respective Nibble Inputs SLS System Logic Semiconductor SL74HC258 MAXIMUM RATINGS * Symbol VCC VIN VOUT IIN IOUT ICC PD T stg TL * Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) Value -0.5 to +7.0 -1.5 to VCC +1.5 -0.5 to VCC +0.5 ±20 ±35 ±75 750 500 -65 to +150 260 Unit V V V mA mA mA mW °C °C Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C SOIC Package: : - 7 mW/°C from 65° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT TA tr, t f Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1) VCC =2.0 V VCC =4.5 V VCC =6.0 V Min 2.0 0 -55 0 0 0 Max 6.0 VCC +125 1000 500 400 Unit V V °C ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN a nd VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V ). CC Unused outputs must be left open. SLS System Logic Semiconductor SL74HC258 DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) VCC Symbol Parameter Test Conditions V Guaranteed Limit 25 °C to -55°C 1.5 3.15 4.2 0.3 0.9 1.2 1.9 4.4 5.9 3.98 5.48 0.1 0.1 0.1 0.26 0.26 ±0.1 ±0.5 ≤85 °C 1.5 3.15 4.2 0.3 0.9 1.2 1.9 4.4 5.9 3.84 5.34 0.1 0.1 0.1 0.33 0.33 ±1.0 ±5.0 ≤125 °C 1.5 3.15 4.2 0.3 0.9 1.2 1.9 4.4 5.9 3.7 5.2 0.1 0.1 0.1 0.4 0.4 ±1.0 ±10 µA µA V Unit VIH Minimum High-Level Input Voltage Maximum Low -Level Input Voltage Minimum High-Level Output Voltage VOUT=0.1 V or VCC-0.1 V IOUT≤ 20 µA VOUT=0.1 V or VCC-0.1 V IOUT ≤ 20 µA VIN=VIH or VIL IOUT ≤ 20 µA VIN=VIH or VIL IOUT ≤ 6.0 mA IOUT ≤ 7.8 mA 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 6.0 6.0 V VIL V VOH V VOL Maximum Low-Level Output Voltage VIN=VIH or VIL IOUT ≤ 20 µA VIN=VIH or VIL IOUT ≤ 6.0 mA IOUT ≤.7.8 mA IIN IOZ Maximum Input Leakage Current Maximum Three-State Leakage Current VIN=VCC or GND Output in High-Impedance State VIN= VIL or VIH VOUT= VCC or GND VIN=VCC or GND IOUT=0µA ICC Maximum Quiescent Supply Current (per Package) 6.0 8.0 80 160 µA SLS System Logic Semiconductor SL74HC258 AC ELECTRICAL CHARACTERISTICS (CL=50pF,Input t r=t f=6.0 ns) VCC Symbol tPLH, t PHL Parameter Maximum Propagation Delay, Nibble A or B to Output Y (Figures 1and 4) Maximum Propagation Delay , Select to Output Y (Figures 2 and 4) Maximum Propagation Delay , Output Enable to Output Y (Figures 3 and 5) Maximum Propagation Delay , Output Enable to Output Y (Figures 3 and 5) Maximum Output Transition Time, Any Output (Figures 1 and 4) Maximum Input Capacitance Maximum Three-State Output Capacitance (Output in High-Impedance State) Power Dissipation Capacitance (Per Package) CPD Used to determine the no-load dynamic power consumption: PD=CPDVCC2f+ICCVCC V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Guaranteed Limit 25 °C to -55°C 100 20 17 160 32 18 150 30 26 110 22 20 60 12 10 10 15 ≤85°C 125 25 21 200 40 35 190 38 33 140 28 25 75 15 13 10 15 ≤125°C 150 30 26 240 48 42 225 45 38 165 34 30 90 18 15 10 15 Unit ns tPLH, t PHL ns tPLZ, t PHZ ns tPZL, t PZH ns tTLH, t THL ns CIN COUT pF pF Typical @25°C,VCC=5.0 V 59 pF Figure 1. Switching Waveforms Figure 2. Switching Waveforms SLS System Logic Semiconductor SL74HC258 Figure 3. Switching Waveforms Figure 4. Test Circuit Figure 5. Test Circuit EXPANDED LOGIC DIAGRAM SLS System Logic Semiconductor SL74HC258 SLS System Logic Semiconductor