SL74HC367N

SL74HC367 Hex 3-State Noninverting Buffer with Separate 2-Bit and 4-Bit Sections High-Performance Silicon-Gate CMOS The SL74HC367 is identical in pinout to the LS/ALS367. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. This device is arranged into 2-Bit and 4-Bit sections, each having its own active-low Output Enable. When either of the enables is high, the affected buffer outputs are placed into high-impedance states. The SL74HC367 has noninverting outputs. • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range: 2.0 to 6.0 V • Low Input Current: 1.0 µA • High Noise Immunity Characteristic of CMOS Devices ORDERING INFORMATION SL74HC367N Plastic SL74HC367D SOIC TA = -55° to 125° C for all packages PIN ASSIGNMENT LOGIC DIAGRAM FUNCTION TABLE Inputs Enable 1,Enable 2 L L H PIN 16 =VCC PIN 8 = GND Z = high impedance X = don’t care A L H X Output Y L H Z SLS System Logic Semiconductor SL74HC367 MAXIMUM RATINGS * Symbol VCC VIN VOUT IIN IOUT ICC PD T stg TL * Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) Value -0.5 to +7.0 -1.5 to VCC +1.5 -0.5 to VCC +0.5 ±20 ±35 ±75 750 500 -65 to +150 260 Unit V V V mA mA mA mW °C °C Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C SOIC Package: : - 7 mW/°C from 65° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT TA tr, t f Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1) VCC =2.0 V VCC =4.5 V VCC =6.0 V Min 2.0 0 -55 0 0 0 Max 6.0 VCC +125 1000 500 400 Unit V V °C ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN a nd VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V ). CC Unused outputs must be left open. SLS System Logic Semiconductor SL74HC367 DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) VCC Symbol Parameter Test Conditions V Guaranteed Limit 25 °C to -55°C 1.5 3.15 4.2 0.3 0.9 1.2 1.9 4.4 5.9 3.98 5.48 0.1 0.1 0.1 0.26 0.26 ±0.1 ±0.5 ≤85 °C 1.5 3.15 4.2 0.3 0.9 1.2 1.9 4.4 5.9 3.84 5.34 0.1 0.1 0.1 0.33 0.33 ±1.0 ±5.0 ≤125 °C 1.5 3.15 4.2 0.3 0.9 1.2 1.9 4.4 5.9 3.7 5.2 0.1 0.1 0.1 0.4 0.4 ±1.0 ±10 µA µA V Unit VIH Minimum High-Level Input Voltage Maximum Low -Level Input Voltage Minimum High-Level Output Voltage VOUT= VCC-0.1 V IOUT≤ 20 µA VOUT=0.1 V IOUT ≤ 20 µA VIN=VIH IOUT ≤ 20 µA VIN=VIH IOUT ≤ 6.0 mA IOUT ≤ 7.8 mA 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 6.0 6.0 V VIL V VOH V VOL Maximum Low-Level Output Voltage VIN= VIL IOUT ≤ 20 µA VIN= VIL IOUT ≤ 6.0 mA IOUT ≤ 7.8 mA IIN IOZ Maximum Input Leakage Current Maximum Three-State Leakage Current VIN=VCC or GND Output in High-Impedance State VIN= VIL or VIH VOUT=VCC or GND VIN=VCC or GND IOUT=0µA ICC Maximum Quiescent Supply Current (per Package) 6.0 8.0 80 160 µA SLS System Logic Semiconductor SL74HC367 AC ELECTRICAL CHARACTERISTICS (CL=50pF,Input t r=t f=6.0 ns) VCC Symbol TPLH, t PHL Parameter Maximum Propagation Delay, Input A to Output Y (Figures 1 and 3) Maximum Propagation Delay ,Output Enable to Output Y (Figures 2 and 4) Maximum Propagation Delay ,Output Enable to Output Y (Figures 2 and 4) Maximum Output Transition Time, Any Output (Figures 1 and 3) Maximum Input Capacitance Maximum Three-State Output Capacitance (Output in High-Impedance State) Power Dissipation Capacitance (Per Buffer) CPD Used to determine the no-load dynamic power consumption: PD=CPDVCC2f+ICCVCC V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Guaranteed Limit 25 °C to -55°C 120 24 20 175 35 30 190 38 32 60 12 10 10 15 ≤85°C 150 30 26 220 44 37 240 48 41 75 15 13 10 15 ≤125°C 180 36 31 265 53 46 285 57 48 90 18 15 10 15 Unit ns TPLZ, t PHZ ns TPZL, t PZH ns TTLH, t THL ns CIN COUT pF pF Typical @25°C,VCC=5.0 V 40 pF Figure 1. Switching Waveforms Figure 2. Switching Waveforms SLS System Logic Semiconductor SL74HC367 Figure 3. Test Circuit Figure 4. Test Circuit EXPANDED LOGIC DIAGRAM (1/6 of the Device) SLS System Logic Semiconductor