SL74HC597D

SL74HC597 8-Bit Serial or Parallel-Input/ Serial-Output Shift Register with Input Latch High-Performance Silicon-Gate CMOS The SL74HC597 is identical in pinout to the LS/ALS597. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. This device consists of an 8 -bit input latch which feeds parallel data to an 8-bit shift register. Data can also be loaded serially (see Function Table). • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range: 2.0 to 6.0 V • Low Input Current: 1.0 µA • High Noise Immunity Characteristic of CMOS Devices ORDERING INFORMATION SL74HC597N Plastic SL74HC597D SOIC TA = -55° to 125° C for all packages LOGIC DIAGRAM PIN ASSIGNMENT PIN 16 =VCC PIN 8 = GND SLS System Logic Semiconductor SL74HC597 MAXIMUM RATINGS * Symbol VCC VIN VOUT IIN IOUT ICC PD T stg TL * Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) Value -0.5 to +7.0 -1.5 to VCC +1.5 -0.5 to VCC +0.5 ±20 ±25 ±50 750 500 -65 to +150 260 Unit V V V mA mA mA mW °C °C Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C SOIC Package: : - 7 mW/°C from 65° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT TA tr, t f Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1) VCC =2.0 V VCC =4.5 V VCC =6.0 V Min 2.0 0 -55 0 0 0 Max 6.0 VCC +125 1000 500 400 Unit V V °C ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN a nd VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V ). CC Unused outputs must be left open. SLS System Logic Semiconductor SL74HC597 DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) VCC Symbol Parameter Test Conditions V Guaranteed Limit 25 °C to -55°C 1.5 3.15 4.2 0.3 0.9 1.2 1.9 4.4 5.9 3.98 5.48 0.1 0.1 0.1 0.26 0.26 ±0.1 8.0 ≤85 °C 1.5 3.15 4.2 0.3 0.9 1.2 1.9 4.4 5.9 3.84 5.34 0.1 0.1 0.1 0.33 0.33 ±1.0 80 ≤125 °C 1.5 3.15 4.2 0.3 0.9 1.2 1.9 4.4 5.9 3.7 5.2 0.1 0.1 0.1 0.4 0.4 ±1.0 160 µA µA V Unit VIH Minimum High-Level Input Voltage Maximum Low -Level Input Voltage Minimum High-Level Output Voltage VOUT=0.1 V or VCC-0.1 V IOUT≤ 20 µA VOUT=0.1 V or VCC-0.1 V IOUT ≤ 20 µA VIN=VIH or VIL IOUT ≤ 20 µA VIN=VIH or VIL IOUT ≤ 4.0 mA IOUT ≤ 5.2 mA 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 6.0 6.0 V VIL V VOH V VOL Maximum Low-Level Output Voltage VIN=VIH or VIL IOUT ≤ 20 µA VIN=VIH or VIL IOUT ≤ 4.0 mA IOUT ≤ 5.2 mA IIN ICC Maximum Input Leakage Current Maximum Quiescent Supply Current (per Package) VIN=VCC or GND VIN=VCC or GND IOUT=0µA SLS System Logic Semiconductor SL74HC597 AC ELECTRICAL CHARACTERISTICS (CL=50pF,Input t r=t f=6.0 ns) VCC Symbol fmax Parameter Minimum Clock Frequency (50% Duty Cycle) (Figures 2 and 8) Maximum Propagation Delay, Latch Clock to QH (Figures 1 and 8) Maximum Propagation Delay , Shift Clock to QH (Figures 2 and 8) Maximum Propagation Delay , Reset to QH (Figures 3 and 8) Maximum Propagation Delay, Serial Shift/ Parallel Load to QH (Figures 4 and 8) Maximum Output Transition Time, Any Output (Figures 1 and 8) Maximum Input Capacitance Power Dissipation Capacitance (Per Package) CPD Used to determine the no-load dynamic power consumption: PD=CPDVCC2f+ICCVCC V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Guaranteed Limit 25 °C to -55°C 6.0 30 35 210 42 36 175 35 30 175 35 30 175 35 30 75 15 13 10 ≤85°C 4.8 24 28 265 53 45 220 44 37 220 44 37 220 44 37 95 19 16 10 ≤125°C 4.0 20 24 315 63 54 265 53 45 265 53 45 265 53 45 110 22 19 10 Unit MHz tPLH, t PHL ns tPLH, t PHL ns tPHL ns tPLH, t PHL ns tTLH, t THL ns CIN pF Typical @25°C,VCC=5.0 V 50 pF SLS System Logic Semiconductor SL74HC597 TIMING REQUIREMENTS (CL=50pF,Input t r=t f=6.0 ns) VCC Symbol tsu Parameter Minimum Setup Time, Parallel Data Inputs A -H to Latch Clock (Figure 5) Minimum Setup Time, Serial Data Input SA to Shift Clock (Figure 6) Minimum Setup Time, Serial Shift/Parallel Load to Shift Clock (Figure 7) Minimum Hold Time, Latch Clock to Parallel Data Inputs A-H (Figure 5) Minimum Hold Time, Shift Clock to Serial Data Input SA (Figure 6) Minimum Recovery Time, Reset Inactive to Shift Clock (Figure 3) Minimum Pulse Width, Latch Clock and Shift Clock (Figures 1 and 2) Minimum Pulse Width, Reset (Figure 3) Minimum Pulse Width, Serial Shift/Parallel Load (Figure 4) Maximum Input Rise and Fall Times (Figure 1) V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Guaranteed Limit 25 °C to -55°C 100 20 17 100 20 17 100 20 17 25 5 5 5 5 5 100 20 17 80 16 14 80 16 14 80 16 14 1000 500 400 ≤85°C 125 25 21 125 25 21 125 25 21 30 6 6 5 5 5 125 25 21 100 20 17 100 20 17 100 20 17 1000 500 400 ≤125°C 150 30 26 150 30 26 150 30 26 40 8 7 5 5 5 150 30 26 120 24 20 120 24 20 120 24 20 1000 500 400 Unit ns tsu ns tsu ns th ns th ns trec ns tw ns tw ns tw ns tr, t f ns SLS System Logic Semiconductor SL74HC597 FUNCTION TABLE Inputs Operation Reset Serial Shift/ Parallel Load X X Latch Clock L,H, Shift Clock X X Serial Input SA X X Resulting Function Parallel Latch Inputs Contents A-H X a-h U a-h Shift Register Contents L L Output QH Reset shift register Reset shift register; load parallel data into data latch Load parallel data into data latch Transfer latch contents to shift register Contents of data latch and shift register are unchanged Load parallel data into data latch and shift register Shift serial data into shift register Load parallel data into data latch and shift serial data into shift register L L L L H H H L L,H, L,H, X X X a-h X a-h U U LRN SRN U LRH H H L,H, L,H, X X U U U H L X X a-h a-h a-h h H H H H X D D X a-h * a-h SRA=D; SRN SRN+1 SRA=D; SRN SRN+1 SRG SRH SRG SRH SR = shift register contents LR = latch register contents D = data (L,H) at serial data input SA U = remains unchanged X = don’t care a-h = data at parallel data inputs A-H * = depends on Latch Clock input INPUTS: A, B, C, D, E, F, G, H - Parallel data inputs. Data on these inputs is stored in the input latch on the rising edge of the Latch Clock input. S A - Serial data input. Data on this input is shifted into the shift register on the rising edge of the Shift Clock input if Serial Shift/Parallel Load is high. Data on this input is ignored when Serial Shift/ Parallel Load is low. SERIAL SHIFT/PARALLEL LOAD - Shift register mode control. When a high level is applied to this pin, the shift register is allowed to serially shift data. When a low level is applied to this pin, the shift register accepts parallel data from the input latch, and serial shifting is inhibited. RESET - Asynchronous, Active-low shift register reset. A low level applied to this input resets the shift register to a low level, but does not change the data in the input latch. SHIFT CLOCK - Serial shift register clock. A low-tohigh transition on this input shifts data on the Serial Data Input into the shift register and data in stage H is shifted out QH, being replaced by the data previously stored in stage G. LATCH CLOCK - A low-to-high transition on this input loads the parallel data on inputs A-H into the input latch. OUTPUT: QH - Serial data output. This pin is the output from the last stage of the shift register. SLS System Logic Semiconductor SL74HC597 Figure 1. (Serial Shift/Parallel Load = L) Figure 2. (Serial Shift/Parallel Load = H) Figure 3. Switching Waveforms Figure 4. Switching Waveforms Figure 5. Switching Waveforms Figure 6. Switching Waveforms Figure 7. Test Circuit Figure 8. Test Circuit SLS System Logic Semiconductor SL74HC597 TIMING DIAGRAM SLS System Logic Semiconductor SL74HC597 EXPANDED LOGIC DIAGRAM SLS System Logic Semiconductor