SL74HCT132

SL74HCT132 Quad 2-Input NAND Gate with Schmitt-Trigger Inputs High-Performance Silicon-Gate CMOS The SL74HCT132 is identical in pinout to the LS/ALS132. The SL74HCT132 may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs. • TTL/NMOS Compatible Input Levels • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range: 4.5 to 5.5 V • Low Input Current: 1.0 µA ORDERING INFORMATION SL74HCT132N Plastic SL74HCT132D SOIC TA = -55° to 125° C for all packages LOGIC DIAGRAM PIN ASSIGNMENT FUNCTION TABLE Inputs A L L H PIN 14 =VCC PIN 7 = GND H B L H L H Output Y H H H L SLS System Logic Semiconductor SL74HCT132 MAXIMUM RATINGS * Symbol VCC VIN VOUT IIN IOUT ICC PD T stg TL * Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) Value -0.5 to +7.0 -1.5 to VCC +1.5 -0.5 to VCC +0.5 ±20 ±25 ±50 750 500 -65 to +150 260 Unit V V V mA mA mA mW °C °C Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C SOIC Package: : - 7 mW/°C from 65° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT TA tr, t f * Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1) Min 4.5 0 -55 - Max 5.5 VCC +125 no limit* Unit V V °C ns When VIN ≈ 0.5VCC, ICC> > quiescent current. This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN a nd VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V ). CC Unused outputs must be left open. SLS System Logic Semiconductor SL74HCT132 DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) VCC Symbol Parameter Test Conditions V Guaranteed Limit 25 °C to -55°C 1.9 2.1 1.2 1.4 1.2 1.4 0.5 0.6 1.4 1.5 0.4 0.4 4.4 5.4 3.98 0.1 0.1 0.26 ±0.1 1.0 ≤85 °C 1.9 2.1 1.2 1.4 1.2 1.4 0.5 0.6 1.4 1.5 0.4 0.4 4.4 5.4 3.84 0.1 0.1 0.33 ±1.0 10 ≤125 °C 1.9 2.1 1.2 1.4 1.2 1.4 0.5 0.6 1.4 1.5 0.4 0.4 4.4 5.4 3.7 0.1 0.1 0.4 ±1.0 40 µA µA V Unit VT+max Maximum PositiveGoing Input Threshold Voltage Minimum PositiveGoing Input Threshold Voltage Maximum NegativeGoing Input Threshold Voltage Minimum NegativeGoing Input Threshold Voltage Maximum Hysteresis Voltage Minimum Hysteresis Voltage Minimum High-Level Output Voltage VOUT=0.1 V IOUT≤ 20 µA VOUT=0.1 V IOUT ≤ 20 µA VOUT=VCC-0.1 V IOUT≤ 20 µA VOUT=VCC-0.1 V IOUT ≤ 20 µA VOUT=0.1 V or VCC-0.1 V IOUT ≤ 20 µA VOUT=0.1 V or VCC-0.1 V IOUT ≤ 20 µA VIN≤VT-min or VT+max Iout ≤ 20 µA VIN≤VT-min or VT+max IOUT ≤ 4.0 mA IOUT ≤ 5.2 mA 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 4.5 4.5 5.5 4.5 5.5 5.5 V VT+min V VT-max V VT-min V VHmax Note VHmin Note VOH V V V VOL Maximum Low-Level Output Voltage VIN ≥VT+max IOUT ≤ 20 µA VIN≥ VT+max IOUT ≤ 4.0 mA IOUT ≤ 5.2 mA IIN ICC Maximum Input Leakage Current Maximum Quiescent Supply Current (per Package) Additional Quiescent Supply Current VIN=VCC or GND VIN=VCC or GND IOUT=0µA VIN = 2.4 V, Any One Input VIN=VCC or GND, Other Inputs IOUT=0µA ∆ICC ≥-55°C 25°C to 125°C 2.4 mA 5.5 2.9 Note. VHmin>(VT+min)-(VT-max); VHmax=(VT+max)+(VT-min). SLS System Logic Semiconductor SL74HCT132 AC ELECTRICAL CHARACTERISTICS (VCC=5.0 V ± 10%, CL=50pF,Input t r=t f=6.0 ns) Guaranteed Limit Symbol tPLH, t PHL tTLH, t THL CIN Parameter Maximum Propagation Delay, Input A or B to Output Y (Figures 1 and 2) Maximum Output Transition Time, Any Output (Figures 1 and 2) Maximum Input Capacitance 25 °C to -55°C 25 15 10 ≤85°C 31 19 10 ≤125°C 38 22 10 Unit ns ns pF Power Dissipation Capacitance (Per Gate) CPD Used to determine the no-load dynamic power consumption: PD=CPDVCC2f+ICCVCC Typical @25°C,VCC=5.0 V 27 pF SLS System Logic Semiconductor SL74HCT132 SLS System Logic Semiconductor SL74HCT132 Figure 1. Switching Waveforms Figure 2. Test Circuit SLS System Logic Semiconductor