83C694D

Twisted-Pair Interface and Manchester Encoder/Decoder • 83C694D Data sheet 83C694D TABLE OF CONTENTS 1.0 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 DOCUMENT SCOPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.3 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.0 ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 OSCILLATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2 MANCHESTER ENCODER/DIFFERENTIAL DRIVER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.3 MANCHESTER DECODER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.4 COLLISION TRANSLATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.5 TP DIFFERENTIAL DRIVER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.6 TP DIFFERENTIAL RECEIVER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.7 LOOPBACK FUNCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.8 LINK TEST FUNCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.9 AUI/TP AUTOSELECT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.10 JABBER AND SQE TEST FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.11 STATUS INDICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.12 TEST MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.0 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.0 DC ELECTRICAL SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.1 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.2 RECOMMENDED OPERATING CONDITIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.3 DC OPERATING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.0 AC OPERATING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.1 TIMING DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.0 PACKAGE DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 i 83C694D LIST OF ILLUSTRATIONS Figure 1-1 1-2 2-1 2-2 2-3 2-4 2-5 2-6 3-1 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-10 5-11 5-11 6-1 Title Page SYSTEM BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 83C694C BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 CRYSTAL CONNECTION DIAGRAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 AUI TRANSMIT PATH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 AUI RECEIVE PATH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ZENER DIODE VOLTAGE REGULATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 TWISTED PAIR TRANSMIT PATH AND TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 TWISTED PAIR RECEIVE PATH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 83C694C PLCC PACKAGE DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 TRANSMIT TIMING - START OF TRANSMISSION. . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 TRANSMIT TIMING - END OF TRANSMISSION (LAST BIT = 0) . . . . . . . . . . . . . . . . . 21 TRANSMIT TIMING - END OF TRANSMISSION (LAST BIT = 1) . . . . . . . . . . . . . . . . . 22 TRANSMIT TIMING - LINK TEST PULSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 RECEIVE TIMING - START OF PACKET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 RECEIVE TIMING - END OF PACKET (LAST BIT = 0) . . . . . . . . . . . . . . . . . . . . . . . . . 23 RECEIVE TIMING - END OF PACKET (LAST BIT = 1) . . . . . . . . . . . . . . . . . . . . . . . . . 24 COLLISION TIMING (AUI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 COLLISION TIMING (TP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 SQE TEST TIMING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 LOOPBACK TIMING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 TEST LOADS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 44-PIN PLCC PACKAGE DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 LIST OF TABLES Table 3-1 4-1 5-1 5-2 Title Page PIN DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 DC OPERATING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 AC OPERATING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 83C694C TIMING DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 ii INTRODUCTION 83C694D 1.0 INTRODUCTION 1.3 GENERAL DESCRIPTION The 83C694D is used for applications where Twisted-Pair Interface (TPI) and/or Attachment Unit Interface (AUI) functions are required. Its two main functions are to: 1. 2. Receive a digital data stream from a low-level input signal and 1.1 DOCUMENT SCOPE This document describes the function and operation of the 83C694D Twisted-Pair Interface and Manchester Encoder/Decoder. It includes a description of external logic necessary for the efficient use of this device and its proper role in the chip set which includes the 83C690 and 83B692 as shown in Figure 1-1. Figure 1-2 provides a functional block diagram of the 83C694D chip itself. 1.2 • • FEATURES Features of the 83C694D include: Twisted-Pair interface solution for IEEE 802.3 10BaseT Standard Compatible with Ethernet II (10BASE5) and Cheapernet (10BASE2) IEEE 802.3 Standards Smart Squelch© digital noise filter at receive and collision inputs to reject noise and digital noise on twisted-pair receive inputs. Direct connection to the transceiver (AUI) cable 16V fault protection at the AUI transmitter interface 10 Mbps Manchester encoding/ decoding with receive clock recovery Low power, 1.25µ CMOS technology TTL/MOS-compatible controller interface Externally-selectable half- or full-step modes of operation at AUI TX± outputs Loopback capability for diagnostics Single station interface operation Link test generation and digital equalization for twisted-pair transmitter Automatic phase detection AUI/TP autoselect Built-in LED drivers for transmit, receive, link test and polarity status indicators Convert a digital output data stream into an analog high-current signal for transmission across a network cable. This means that the 83C694D serves as the logical link between a network cable on one end and a digital controller chip (such as the 83C690) on the other end. To accomplish these two functions, the 83C694D consists of these components: Manchester encoder/decoder, balanced drivers and receivers, onboard crystal oscillator, signal translator, diagnostic circuit, and protocol timers and state machines. The remainder of this data sheet contains the following information: Section 2 discusses the system architecture including an explanation of all chip circuits. Section 3 provides pin descriptions. Section 4 provides DC Operating Characteristics. Section 5 provides AC Operating Characteristics including Interface Timing diagrams. Section 6 provides the PLCC package diagram of this chip. • • • • • • • • • • • • • 1 83C694D INTRODUCTION TX+/RX+/CD+/- 83B692 RX+/ETHERNET TRANSCEIVER BUFFER MEMORY 83C690 802.3 ETHERNET LAN CONTROLLER CRS RXD RXC COL TXC CD+/83C694C MANCHESTER ENCODER/ DECODER TPX1+/TPX2+/10BaseT Twisted Pair Transmit Filter PC BUS INTERFACE TPR+/Receive Filter FIGURE 1-1. SYSTEM BLOCK DIAGRAM 2 10Base2 CHEAPERNET TXE TXD TX+/- AUI 10Base5 ETHERNET INTRODUCTION 83C694D AUI COLLISION RECEIVER CD+ CD- LNK COLLISION DECODER MODE1 MODE2 JABBER TP RECEIVER TPR+ TPR- COL REPEATER LOGIC COLLISION DETECT LBK COL MPE SMART SQUELCH LINK TEST RECEIVE POLARITY CORRECT LNK RXC AUI RECEIVER RX+ RXLBKCTL PLL DECODER CRS RXD LOOPBACK FUNCTIONS AUI DRIVER TX+ TX- CRYSTAL OSCILLATOR 20 MHz X1 X2 SEL LNK MODE1 LBK TXCTL LINK BEAT TP DRIVER 2 TRANSMIT CONTROL ENCODER TXC TXE TXD TPX+ TPX2 JABBER DETECT LNK LED DRIVERS TPOL RLED JABBER DIGITAL EQUALIZATION XLED FIGURE 1-2. 83C694C BLOCK DIAGRAM 3 83C694D 2.0 ARCHITECTURE • • Jabber & SQE Test Functions Status Indications ARCHITECTURE The 83C694D can be used as an AUI device or as a twisted-pair interface device. When used in combination TPI/AUI applications, the 83C694D is part of a three-device set that implements the complete IEEE 802.3-compatible network node electronics (see Figure 1-1). The 83C690 Ethernet LAN Controller (ELC) and the 83B692 Ethernet Transceiver (ET) comprise the other two devices in the set. The 83C690 provides media access protocol functions and performs buffer management tasks, while the 83B692 serves as a coaxial cable line driver/receiver and collision detector. The 83C694D Twisted-Pair Interface provides the interface between the 83C690 ELC and the 83B692 ET. When transmitting, the device converts non-return-to-zero (NRZ) data from the controller into Manchester encoded data, then sends this data to the transceiver. When receiving, the device reverses the process using an analog phase-locked loop that decodes 10 Mbit/sec signals with up to ±20 nsec of jitter. When the 83C694D is used as a twisted-pair (TP) interface, its on-chip transmitter and receiver (separate from the AUI inputs and outputs) connect to the network through a transformer and filter. In this application, the 83C694D is used with the 83C690 providing controller and protocol functions, and the 83B692 is not used. The 83C694D Twisted-Pair Interface is comprised of these functional blocks: • • • • • • • • • 4 Oscillator Manchester Encoder and Differential Driver Manchester Decoder Collision Translator Loopback Capabilities TP Differential Driver TP Differential Receiver Link Test Function AUI / TP Autoselect The rest of this section describes each of these circuits in more detail, including suggestions, where appropriate, for designing external circuits consistent with the 802.3 standard. 2.1 OSCILLATOR Control is provided either by a 20 MHz, parallel resonant crystal connected between X1 and X2, or by an external clock connected at X1. The oscillator’s 20 MHz output is divided in half to generate the 10 MHz transmit clock for the Ethernet LAN controller and to provide the internal clock signals for the encoding and decoding circuits. Figure 2-1 provides a diagram of this connection. X1 20 MHz CL - CP X2 CL = Load capacitance specified by crystal manufacturer CP = Total parasitic capacitance including: a) 83C694C input capacitance between X1 and X2 (typically 5 pF) b) PC board traces, plated through holes, socket capacitances FIGURE 2-1. CRYSTAL CONNECTION DIAGRAM ARCHITECTURE 83C694D 2.3 MANCHESTER DECODER 2.2 MANCHESTER ENCODER/ DIFFERENTIAL DRIVER Data encoding and transmission begins when the transmit enable input (TXE) goes high and continues as long as the TXE remains high. It is essential that the transmit enable and transmit data inputs meet the setup and hold time requirements for the rising edge of the transmit clock. Transmission ends when the transmit enable input goes low. The last transition occurs at the center of the bit cell if the last bit is one, or at the boundary of the bit cell if the last bit is zero. The AUI differential line driver, which has the ability to drive up to 50 meters of twisted-pair AUI/Ethernet transceiver cable, provides the emitter-coupled logic (ECL) level signals. With the SEL input, select one of two modes, fullstep or half-step. When SEL is low, TX+ is positive in relation to TX- in the idle state. When SEL is high, TX+ and TX- are equal in the idle state. Figures 5-1 through 5-3 illustrate AUI transmit timing. An external interface circuit utilizing these signals might resemble Figure 2-2. In such a configuration, the transmit interface circuit could utilize an isolation transformer leading to the 83B692 which would then drive the coax signal to the network. Another option would use the AUI connector which would go to external equipment. Decoding is accomplished by a differential input receiver circuit and an analog phase-locked loop that separates the Manchester-encoded data stream into clock signals and NRZ data. To prevent noise at the AUI RX+ or RX- input from falsely triggering the decoder, a squelch circuit rejects signals with pulse widths less than 20 nsec (negative going), or with levels less than -175 mV. When the input exceeds the squelch limits, the analog phase-locked loop locks onto the incoming signal and the 83C694D decodes a data frame. The carrier sense (CRS) is activated, and the receive data (RXD) and receive clock (RXC) become available within five bit times. At the end of a frame, when the normal mid-bit transition on the differential input ceases, carrier sense is de-activated. The receive clock remains active for an additional five bit times. Figures 5-4 through 5-6 illustrate the receive timing. An external interface circuit for RX+ and RX- might be designed like Figure 2-3. To avoid signal corruption caused by excessive voltage fluctuation on the power supply, it is desirable to externally implement a voltage regulation system consisting of a 5.1-volt zener diode. Typically, as shown in Figure 2-4, the diode’s cathode is connected to pin 20, pin 23, the VCC side of the OSR resistor, the VCC side of the BSR resistor, and a 510Ω 1⁄4-Watt resistor which goes from the zener’s cathode to the 12-volt power supply. AUI CONNECTOR 0.02µ F RX+ or CD+ +5V 39.2Ω 1% TX+ 150Ω 1% 0.02µF 83B692 39.2Ω 1% COA CABL RX- or CD- 150Ω 1% ETHERNET TRANSCEIVER TX- 0.1µF FIGURE 2-2. AUI TRANSMIT PATH FIGURE 2-3. AUI RECEIVE PATH 5 83C694D +12V (circuit board) ARCHITECTURE 510Ω (1/4 watt) cathode 0.1 µ F 5.1V zener anode 10ΚΩ 31.6ΚΩ ground (circuit board) BSR OSR VCC (pin 32) VCC (pin 35) 83C694C FIGURE 2-4. ZENER DIODE VOLTAGE REGULATION FOR 12 VOLTS It is also helpful to place a decoupling capacitor between the diode’s cathode and ground as shown in Figure 2-4. 2.4 COLLISION TRANSLATOR When the 83C694D is used as an AUI device, a separate Ethernet transceiver detects collisions on the coaxial cable and generates a 10 MHz signal, which is monitored by the 83C694D through the collision detect pins. The presence of the signal activates the collision detect (CD) pin connected to the 83C690 causing the controller to stop transmitting. The collision detect output is deactivated within 160 nsec. after the absence of the 10 MHz signal. Figure 5-7 illustrates the collision timing. An external interface circuit for CD+ and CD- is designed exactly like an external interface for RX+ and RX-. See Figure 2-3. 2.5 TP DIFFERENTIAL DRIVER The TP driver can transmit through up to 100m of unshielded twisted-pair (UTP) cable. The driver includes a circuit for transmit equalization, which attenuates low frequency components of the transmit waveform. This reduces the zero crossing jitter of the received signal and avoids the use of a receive equalizer. There are two pulse widths transmitted: 50 nsec and 100 nsec. When a pulse width of 100 nsec is sent, both drivers (TPX1+ and TPX2+) turn on and drive a high level. This provides a greater amplitude 6 at the start of the pulse; however, halfway through the pulse TPX2 turns off, thereby reducing the amplitude after 50 ns. A narrow pulse is transmitted at the same amplitude as the first half of the wide pulses. The resistor ratio is calculated to produce the best signal wave shape at the receiving end assuming a UTP cable length of 100 meters. Figure 2-6 shows the basic twisted-pair transmit path along with its timing and one possible external transmit interface design. Typical values for resistance on TPX2 pins are 261Ω, while TPX1 pins use 65Ω. The 2.4KΩ parallel resistor is used to match the output resistance of the transmitter to the twisted-pair cable. At the receive end of the cable, a 100Ω termination resistor is commonly used. To verify the operation of the circuit, measure the TPX signals differentially. In designing the external circuits to connect the 83C694D transmit outputs to the cable, use a transmit filter followed by an isolation transformer and, in the most practical applications, a common mode choke for FCC compliance. The common mode choke may not always be needed in every application; however, the isolation transformer is always needed and the transmit filter is strongly recommended; without it, high frequency radiation may exceed FCC limits. 2.6 TP DIFFERENTIAL RECEIVER ARCHITECTURE 83C694D 261Ω TPX2+ 65Ω TPX+ 2.4ΚΩ Common Mode Choke Transmit Filter TPX1+ TPX165Ω TPX- TPX2261Ω Isolation Transformer Twisted Pair Cable 100 nsec 50 nsec FIGURE 2-6. TWISTED-PAIR TRANSMIT PATH AND TIMING The signal received from the unshielded cable can be noisy, so minimum voltage and timing limits must be met before the receiver logic is enabled. A "smart squelch"© digital noise filter is used in addition to the analog squelch circuit in the receiver. The smart squelch circuit provides extra protection against false collisions and false link connections. If the input polarity is reversed, it will be automatically detected and corrected. When this happens, the TPOL output pin will go high to signal the controller or to turn off the polarity indicator LED. The phase-locked loop and Manchester decoder are the same circuits used by the AUI receiver. An external interface circuit for TPR+ and TPRmight be designed like Figure 2-5. 2.7 LOOPBACK FUNCTION When the loopback input goes high it causes the 83C694D to send serial data from the transmit data input through the encoder, and back through the phase-locked loop and decoder to the receive data output. The transmit driver is in the idle state during loopback mode and the receiver circuitry and collision detection are disabled. Loopback can be enabled during either AUI or TP (10BaseT) operation. Transmit data is always looped back during TP operation, simulating the physical broadcast characteristic of 802.3 coaxial cable networks. Common Mode Choke TP+ Receive Filter TPR+ 100Ω 1% TPR- TP- Twisted Pair Cable Isolation Transformer FIGURE 2-5. TWISTED-PAIR RECEIVE PATH 7 83C694D The 83C694D supports the IEEE 802.3 loopback design (section 14.2.1.3) which provides for continuous loopback from transmit to receive in normal operation. This means that transmitted data is always looped back during TP operation, simulating the physical broadcast characteristics of 802.3 coaxial cable networks. 2.8 LINK TEST FUNCTION Each TP driver transmits a short positive pulse periodically when it is not sending data as shown in Figure 5-4. These pulses are received at the other end of the TP cable, signalling that the link is operating correctly. The time between link test pulses is compared to the expected range at the receiver, to avoid false detection of noise pulses as link test pulses. If the link test fails (no pulses or data received in a fixed time period), then the LNK pin is set high and data transmit and receive on the TP interface is disabled. 2.9 AUI/TP AUTOSELECT The 83C694D can automatically select which media to transmit and receive on, based on the link test state. If the link test fails, the AUI transmitter and receiver are enabled while the TP transmitter, receiver, and loopback are disabled. If link test passes, the AUI operation is disabled and TP operation is re-enabled. The only exception to this is when MODE1 is set low and TP operation is enabled continuously. 2.10 JABBER AND SQE TEST FUNCTIONS 2.11 STATUS INDICATIONS ARCHITECTURE To assist in installation and management of the network, indicator LEDs can be driven by four outputs from the 83C694D. These show the result of Link Test, polarity check, and transmit or receive activity. An LED test feature is built into the 83C694D. All LEDs turn on for 2/3 second after a reset to the device. 2.12 TEST MODE Three test modes can be selected when the SEL pin is set to intermediate voltages. These modes and their corresponding voltages are: • • • Internal counter speedup (1.75 V) RXC and RXD enable (2.5 V) Output tristate (3.5 V) Internal counter speedup is used for fast boardlevel testing of timed functions such as LED powerup blink and link test pulse period. RXC and RXD enable is used to test internal VCO functions without using a full data packet receive. Output tristate is used during board-level testing to enable short/open testing. It is also used to test other devices resident on the board. This function does not tristate transmit (pins 22-27) or X2 outputs. If TXE is high for greater than 46 ms, the TP transmitter will be disabled and COL will go active high. If TXE then goes low for more than 368 ms, the TP transmitter will be re-enabled and COL will go low. In TP operation, a short pulse will be output on COL after each packet is transmitted. This is required as a test of the TP transmit/receive path, and is called SQE Test or CD Heartbeat. 8 PIN DESCRIPTION 83C694D 3.0 PIN DESCRIPTION Figure 3-1 illustrates the signal names and pin locations on the 44-pin PLCC 83C694D package. Table 3-1 lists the signal names and descriptions for the 83C694D. TPR+ TPR- RES CRS RXD COL RXC CD+ 6 SEL LNK 5 4 3 2 1 44 43 42 41 CD- 40 RX+ NC 7 8 9 10 11 12 13 14 15 16 17 18 X2 39 38 37 36 35 34 33 32 31 30 29 28 OSR RXBSR TST NC TPOL GND GND GND VCC VCC VCC VCC GND RLED XLED LBK MODE2 MODE1 CAP X1 19 TXD 20 TXC 21 TXE 22 TPX2- 23 TPX1- 24 TPX1+ 25 TPX2+ 26 TX- 27 TX+ FIGURE 3-1. 83C694C 44-PIN PLCC PACKAGE DRAWING 9 83C694D PIN NUMBER 1 MNEMONIC COL SIGNAL NAME Collision Detect I/O O PIN DESCRIPTION DESCRIPTION A 10 MHz (+25%,-15%) signal at the CD inputs (DTE mode) produces a logic high at the COL output. When no signal is present at the CD inputs, the COL output goes low. In 10BaseT operation, the COL output goes high when TPR+ and TPR- are active while a packet is being transmitted on TPX+/TPX-. COL also goes high during SQE test or jabber condition. 2 3 NC RXD No Connect Receive Data I O Do not connect any circuitry to this pin. This is the NRZ data output from the on-chip decoder and phase-locked loop. This signal should be sampled by the controller at the rising edge of receive clock. A high level is binary "one", a low level is binary "zero". CRS (DTE mode) goes high when valid data is presen t at the RX+/RX- inp uts or TPR+/TPR- inputs. It goes low after the last bit is received at the inputs. When RES is low, all internal nodes are set to a known state except for internal clock distribution. This improves testing procedures. Normal operation is enabled on the rising edge of RES and while RES is high. The RES pin includes an internal pull up resistor, so it may be left open if unused. When the phase-locked loop acquires a valid receive signal, a 10MHz clock signal (recovered from receive data) is output on RXC. RXC is low during idle (5 bit times after receive activity stops). When SEL is high, TX+ and TX- outputs are at the same voltage in idle state, providing a "zero" differential. When SEL is low, TX+ is positive with respect to TX- in idle state. Also, three test modes may be selected by setting the SEL pin to voltages between low and high levels. Refer to section 2.13 for more on test modes. 4 CRS Carrier Sense O 5 RES Reset/Synch I 6 RXC Receive Clock O 7 SEL Mode Select I TABLE 3-1. PIN DESCRIPTION 10 PIN DESCRIPTION 83C694D SIGNAL NAME TwPr Link Status I/O O DESCRIPTION If valid data or Link Test pulses are received on TPR+/TPR-, LNK is low (link status OK). When no data or Link Test pulses are received, LNK is high. The LNK pin can sink 10mA to drive an external LED. TPOL is low when positive polarity Link Test pulses or data packets are received on TPR+/TPR- (normal operation). TPOL is high when negative polarity Link Test pulses or data packets are received (link wiring polarity reversed). When TPOL is low, it can sink 10mA to drive an external LED. Pin 10 provides negative supply for analog circuits. Pin 11 provides negative supply for digital circuits. Pin 12 provides negative supply for digital/pad circuits. Pin 13 provides negative supply for VCO circuits. O When active low, RLED sinks 10 mA to drive an external LED. If no data is received, RLED is high. If data is received, RLED will go low for approximately 50ms longer than the received packet length. All LED current is controlled internally and requires no external resistors between the chip and an external LED. The external LED must be connected from +5V to the device pin. If LEDs are not used, then the four pins can be used as logic outputs. PIN NUMBER 8 MNEMONIC LNK 9 TPOL TwPr Link Polarity O 10 – 13 GND Negative Supply 14 RLED Receive LED Driver 15 XLED Transmit LED Driver O When active low, XLED sinks 10mA to drive an external LED. When there is no transmission (TXE inactive), XLED is high. When data is transmitted, XLED goes active low for approximately 50ms longer than the transmitted packet length. XLED does not go active low for Link Test pulses. TABLE 3-1. PIN DESCRIPTION cont. 11 83C694D PIN NUMBER 16 MNEMONIC LBK SIGNAL NAME Loopback I/O I PIN DESCRIPTION DESCRIPTION A high level enables loopback of TXD to RXD/RXC. A low level enables normal transmit/receive operation. The LBK pin includes an internal pull-down resistor, so it may be left open if unused. X1 is driven by an external clock frequency source or is connected to one terminal of the 20MHz crystal. The IEEE 802.3 standard requires 0.01% absolute accuracy on the transmitted signal frequency. Stray capacitance can shift the crystal’s frequency out of range, causing it to exceed the 0.01% tolerance. To remedy this, extra load capacitance may be added. To determine the amount of capacitance to add, measure the board capacitance and the capacitance between the X1 and X2 pins. Then add these values together, and subtract them from the crystal’s required load capacitance. (Refer to Figure 2-1.) 17 X1 Crystal/Ext. Input I 18 X2 Crystal Feedback O This output is connected to the other terminal of the 20MHz crystal. If X1 is driven with an external source, X2 must be left open. TXD is sampled on the rising edge of TXC when TXE is high. The NRZ data input here is encoded and transmitted on TX+/TX- or TPX+/TPX- as a differential signal. This is a 10MHz clock signal derived from the internal 20MHz oscillator. It is enabled except when RES is low and MPE is high. TXE enables encoding and transmission of the data input via TXD. It is sampled on the rising edge of TXC. TPX2- is used for 10BaseT only. It is the low current negative output pin. See TPX1+ for details. TPX1- is used for 10BaseT only. It is the high current negative output pin. See TPX1+ for details. 19 TXD Transmit Data I 20 TXC Transmit Clock O 21 TXE Transmit Enable I 22 TPX2- TwPr Transmit O 23 TPX1- TwPr Transmit O TABLE 3-1. PIN DESCRIPTION cont. 12 PIN DESCRIPTION 83C694D SIGNAL NAME TwPr Transmit I/O O DESCRIPTION In 10BaseT operation, data input via TXD is encoded and then transmitted on TPX pins. When transmit and receive are idle, Link Test pulses are periodically transmitted via TPX. The TPX pins are connected to the twistedpair medium via a transformer and filter, and use 5 external resistors for waveshaping as shown in Figure 2-6. TPX1+ is the high current positive output pin. PIN NUMBER 24 MNEMONIC TPX1+ 25 TPX2+ TwPr Transmit O TPX2+ is used for 10BaseT only. It is the low current positive output pin. See TPX1+ for details. In AUI mode, TX+ and TX- transmit Manchester encoded data differentially to an external transceiver. Each output requires an external pull-up resistor of 150Ω 1% to +5V as shown in Figure 2-2. A resistor from OSR to +5V biases the internal VCO current. Nominal value is 31.6 KΩ 1%. A capacitor (nominal value .02 µF) from CAP to ground is used as part of the filter for the internal phase-locked loop. With MODE1 low, TP mode is always selected. No Link Test pulses are transmitted or required on RX+/-. When MODE1 is high, AUI mode is selected at power on. When MODE1 is connected to RES, 10BaseT mode is selected at power on. After power on, if MODE1 is not low, 10BaseT mode is automatically selected if LNK goes low (otherwise AUI mode is selected). The MODE1 pin includes an internal pull-up resistor, so it can be left open if not used. When MODE2 is low, automatic link polarity correction is disabled (TP mode only). Autopolarity correction is enabled when MODE2 is high. The MODE2 pin includes an internal pull up resistor, so it may be left open if not used. 26 27 TXTX+ AUI Transmit O 28 29 OSR CAP VCO Bias Resistor PLL Filter Cap I I 30 MODE1 Mode Select 1 I 31 MODE2 Mode Select 2 I TABLE 3-1. PIN DESCRIPTION cont. 13 83C694D PIN NUMBER 32, 33, 34, 35 MNEMONIC VCC SIGNAL NAME Positive Supply I/O PIN DESCRIPTION DESCRIPTION Pin 32 is positive supply to the VCO. Pin 33 is positive supply for digital and transmit circuits. Pin 34 is positive supply for digital circuits. Pin 35 is positive supply for receive circuits. Do not connect to this pin. 36 37 38 NC TST BSR Not Connected Test Input Bias Resistor I I This pin must be tied low. A resistor from BSR to VCC sets the internal bias levels. Nominal value is 10KΩ 1% resistor connected externally to +5V. If BSR is tied low, a low power mode is enabled and transmit/receive is disabled. In AUI mode, the Manchester encoded data from an external transceiver is received on RX+/RX-. After timing recovery and decoding, it is output to the controller on RXD. With the standard 78Ω transceiver AUI cable, the differential input must be externally terminated. This requirement can be satisfied by connecting two 39.2Ω 1% resistors in series with an optional 0.1 µF common mode bypass capacitor as shown in Figure 2-3. Matched capacitors can also be added to protect the inputs from external faults. In AUI mode, a 10 MHz collision presence signal from an external transceiver is received on CD+/CD-. The COL pin is then output high. The collision differential inputs, CD+ and CD-, must be terminated in the same manner as the receive inputs, RX+ and RX-. See Figure 2-3 for information on this design. 39 40 RXRX+ AUI Receive I 41 42 CDCD+ AUI Collision I TABLE 3-1. PIN DESCRIPTION cont. 14 PIN DESCRIPTION 83C694D SIGNAL NAME Twisted-Pair Receive I/O I DESCRIPTION In 10BaseT mode, Manchester encoded data is received via TPR+/TPR-. After timing recovery and decoding it is output to the controller on RXD. TPR+/TPR- are connected to the twisted-pair medium through a transformer and filter. A 100Ω termination resistor is generally used before the circuit connects to the receive signal lines, TPR+ and TPR- inputs. See Figure 2-5 for information on this design. The 83C694D automatically corrects for a misconnection of the + and - interface allowing operation without having to correct the wiring. PIN NUMBER 43 44 MNEMONIC TPRTPR+ TABLE 3-1. PIN DESCRIPTION cont. 15 83C694D 4.0 DC ELECTRICAL SPECIFICATIONS DC ELECTRICAL SPECIFICATIONS 4.1 ABSOLUTE MAXIMUM RATINGS Supply Voltage (Vcc). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6V TTL Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 – 5.5V Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 – 5.5V Differential Output Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 – 16V Differential Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 mA Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C (-85°F) to 150° (302°F) Absolute maximum ratings indicate limits beyond which permanent damage may occur. Continuous operation at these limits is not recommended; operation should be limited to conditions specified under DC Operating Characteristics. 4.2 RECOMMENDED OPERATING CONDITIONS Supply Voltage (Vcc). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ±5% Ambient Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C (32°F) to 70°C (158°F) 4.3 DC OPERATING CHARACTERISTICS Ta = 0°C (32°F) to 70°C (158°F) Vcc = +5V ±5% NOTE All currents into device pins are positive. All currents out of device pins are negative. All voltages are referenced to ground unless otherwise specified. SYMBOL Vih CHARACTERISTIC Input High Voltage (TTL and X1)1 Input High Voltage (SEL) Input Low Voltage (TTL, X1, SEL) Input High Current (TTL, X1, SEL) Input High Current (RX± and CD± ) Input Low Current (TTL, X1 and SEL) Input Low Current (RX± and CD± ) Input Clamp Voltage (TTL) Output High Voltage (RXD, RXC, CRS, TXC, COL, X2 and LEDs)2 MIN 2.0 4.5 – – – – – – 3.5 – – MAX UNITS V V V µA µA µA µA V V – – – CONDITIONS Vil Iih 0.8 50 500 -50 -500 -1.2 – Vin = Vcc Iil Vin = 0.5V Vcl Voh Iin = -12mA Ioh = -100µA 16 DC ELECTRICAL SPECIFICATIONS 83C694D MIN – – – 10 -40 ±500 SYMBOL Vol CHARACTERISTIC Output Low Voltage (RXD, RXC, CRS, TXC, COL) Output Low Voltage (X2) Output Low Voltage (LEDs) Output Low Current (LEDs) Output Short Circuit Current (RXD, RXC, CRS, TXC, COL) Differential Output Voltage (TX±) Differential Output Voltage Imbalance (TX±) Output High Voltage (TPX1±) Output High Voltage (TPX2±) Output Low Voltage (TPX1±) Output Low Voltage (TPX2±) Differential Squelch Threshold (RX±, CD±) Differential Squelch Threshold (TPR±) Differential Input Common Mode Voltage (RX±, CD±) Power Supply Current MAX 0.5 0.7 0.5 25 -200 ±1200 ±40 UNITS V V V mA mA CONDITIONS Iol = 8mA Iol = 2 mA 2V ≤ Vol ≤ 4V – 78Ω termination and 150Ω from each output to Vcc 78Ω termination and 150Ω from each output to Vcc Ioh = -30mA Ioh = -14 mA Ioh = 30 mA Ioh = 14 mA – Iol Ios Vod mV Vob – mV Voh Vcc - 0.6 – V V V V mV Vcc - 0.75 – – 0.6 0.75 -175 300 0 – -300 500 5.25 100 Vol Vds mV peak – V mA – loopback active at 10 Mbit/sec Vcm Icc TABLE 4-1. DC OPERATING CHARACTERISTICS 1 2 TTL inputs are TXE, TXD, LBK, MODE1, MODE2, and RES. LED drivers are RLED, XLED, LNK, and TPOL. 17 83C694D 5.0 AC OPERATING CHARACTERISTICS AC OPERATING CHARACTERISTICS Ta = 0°C (32°F) to 70°C (158°F) Vcc = 5V ± 5% NOTE All typical values are given for Vcc = 5V and Ta = 25°C (77°F). SYMBOL tXTH tXTL tTCD tTCR tTCF tTDS tTDH tTES tTEH tTOD tTOR tTOF tTOJ tTOH tTOI tLTPW tRCD tRCR tRCF tRDR tRDF tRDS tCSON tCSOFF PARAMETER MIN 8 8 42 – – 20 0 20 0 – – – – – – 200 – TYP – – 50 – – – – – – – – 4.5 – 4.5 ±0.25 – – 100 50 – – – – – – – – – MAX 25 25 58 8 8 – – – – 60 8 – 8 – – – 350 UNITS nsec nsec % nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec % nsec nsec nsec nsec nsec nsec nsec nsec nsec Oscillator Specification X1 rising edge to Transmit Clock High X1 rising edge to Transmit Clock Low Transmit Specification Transmit Clock Duty Cycle at 50% (10 MHz) Transmit Clock Rise Time (20 to 80%) Transmit Clock Fall Time (20 to 80%) Transmit Data Setup Time to Transmit Clock Rising Edge Transmit Data Hold Time from Transmit Clock Rising Edge Transmit Enable Setup Time to Transmit Clock Rising Edge Transmit Enable Hold Time from Transmit Clock Rising Edge Transmit Output Delay from Transmit Clock Rising Edge Transmit Output Rise Time (20% to 80%) (TX±) Transmit Output Rise Time (TPX±) Transmit Output Fall Time (80% to 20%) (TX±) Transmit Output Fall Time (TPX±) Transmit Output Jitter (TX±) Transmit Output High before Idle in Half Step Mode Transmit Output Idle Time in Half Step Mode Link Test Pulse Width Receive Specification Receive Clock Duty Cycle at 50% (10 MHz) Receive Clock Rise Time (20% to 80%) Receive Clock Fall Time (20% to 80%) Receive Data Rise Time (20% to 80%) Receive Data Fall Time (80% to 20%) Receive Data Stable from Receive Clock Rising Edge Carrier Sense Turn on Delay (AUI) Carrier Sense Turn on Delay (TP) Carrier Sense Turn off Delay (AUI) Carrier Sense Turn off Delay (TP) 40 – – – – ±40 – – – – 60 8 8 8 8 – 60 300 160 160 18 AC OPERATING CHARACTERISTICS 83C694D MIN – – 8 8 – – – 100 – 0.6 0.5 35 350 SYMBOL tDAT tDREJ tRD tCOLON tCOLOFF tSQEON tSQED tLBS tLBH PARAMETER Decoder Acquisition Time (AUI) Decoder Acquisition Time (TP) Differential Inputs Rejection Pulse Width (AUI) Differential Inputs Rejection Pulse Width (TP) Receive Throughput Delay TYP – – 25 20 – – – – – 1.0 1.0 – – – – – – – MAX 700 950 35 30 200 60 900 160 160 1.6 1.5 – – 11.5 92 5.8 46 368 UNITS nsec nsec nsec nsec nsec nsec nsec nsec nsec usec usec nsec nsec msec msec msec msec msec Collision Specification Collision Turn On Delay (AUI) Collision Turn On Delay (TP) Collision Turn Off Delay (AUI) Collision Turn Off Delay (TP) SQE Test Start Delay (TP) SQE Test Duration (TP) Loopback Specification Loopback Setup Time Loopback Hold Time 10BaseT Protocol Timers Link Test Transmit Period Link Loss / Link Test Max. Link Test Min. Jabber On (transmit inhibit) Jabber Off (transmit re–enable) 9.8 78 4.9 39 314 TABLE 5-1. AC OPERATING CHARACTERISTICS 19 83C694D AC OPERATING CHARACTERISTICS 5.1 TIMING DIAGRAMS Figures 5–1 through 5–9 illustrate all timings. Table 5–2 lists all timing diagrams. Figure Number 5–1 5–2 5–3 5–4 5–5 5–6 5–7 5–8 5–9 5–10 5–11 5–12 Title Transmit Timing – Start of Transmission Transmit Timing – End of Transmission (last bit = 0) Transmit Timing – End of Transmission (last bit = 1) Transmit Timing – Link Test Pulse Receive Timing – Start of Packet Receive Timing – End of Packet (last bit = 0) Receive Timing – End of Packet (last bit = 1) Collision Timing (AUI) Collision Timing (TP) SQE Test Timing Loopback Timing Test Loads TABLE 5–2. 83C694D TIMING DIAGRAMS 20 AC OPERATING CHARACTERISTICS 83C694D TXC 1.5V t TES TXE 1.5V tTDH tTDS 1.5V 1.5V t TOD TXD TX+ TX- TPX2+ TPX1+ TPX1- TPX2- FIGURE 5-1. TX TIMING - START OF TRANSMISSION FIGURE 5-2. TX TIMING - END OF TRANSMISSION (LAST BIT=0) 21 83C694D AC OPERATING CHARACTERISTICS TXC 1.5V t TEH 1.5V TXE 1 1 0 1 TXD t TOI t TOH TX+ TX1 TPX2+ 1 1 0 1 TPX1+ TPX1- TPX2- 1 1 1 0 1 FIGURE 5-3. TX TIMING - END OF TRANSMISSION (LAST BIT=1) TXC TPX2+ TPX1+ TPX1- TPX2- t LTP FIGURE 5-4. TX TIMING - LINK TEST PULSE 22 AC OPERATING CHARACTERISTICS 83C694D FIRST BIT DECODED RX+/RXor TPRX+/TPRXt DREJ 1.5V t CSON RXC t DAT t RDS t RDS RXD 1.5V 1 0 1 0 1 0 1 0 1 0 1 1.5V 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CRS FIGURE 5-5. RECEIVE TIMING - START OF PACKET 1 RX+/RXor TPRX+/TPRX- 0 1 0 0 t CSOFF 1.5V t RD CRS RXC 5 EXTRA CLOCKS RXD 1 0 1 0 0 FIGURE 5-6. RECEIVE TIMING - END OF PACKET (LAST BIT = 0) 23 83C694D AC OPERATING CHARACTERISTICS 1 RX+ RX- 0 1 0 1 t CSOFF CRS RXC 5 EXTRA CLOCKS RXD 1 0 1 0 1 FIGURE 5-7. RECEIVE TIMING - END OF PACKET (LAST BIT = 1) CD+ CDt COLON COL 1.5V t COLOFF 1.5V FIGURE 5-8. COLLISION TIMING (AUI) 24 AC OPERATING CHARACTERISTICS 83C694D TXE TPRX+ TPRX- t COLON t COLOFF COL FIGURE 5-9. COLLISION TIMING (TP) TXE t SQEON t SQED COL FIGURE 5-10. SQE TEST TIMING 25 83C694D AC OPERATING CHARACTERISTICS 1.5V LBK t LBS 1.5V TXE t LBH 1.5V 1.5V FIGURE 5-11. LOOPBACK TIMING + 5V 150 Ohm TTL/MOS OUTPUTS TX+ + 5V 50 pF 150 Ohm R* 27 µ H** + 1% _ TX- * R = 73 Ohm + 1% and R = 83 Ohm + 1% ** 27 µ H + 1% inductor is used for test purposes. 100 µH tranformers (Valor LT 1101, or Pulse Engineering 64103) are recommended for application use. TPX2+ 237 Ohm TPX1+ 59 Ohm TPX1- 59 Ohm TPX2- 237 Ohm FIGURE 5-12. TEST LOADS 26 PACKAGE DESCRIPTION 83C694D 6.0 PACKAGE DESCRIPTION Figure 6-1 illustrates the 44-pin PLCC package for the 83C694D. Refer to Table 6-1 for the dimensions given in this figure. FIGURE 6-1. 44-PIN PLCC PACKAGE DIAGRAM 27 83C694D PACKAGE DESCRIPTION Table 6-1 provides acceptable ranges for the codes shown in Figure 6-1. All dimensions are in inches. Code A A1 B B1 B2 C D/E D1/E1 D2/E2 D3/E3 e F G J R Dimension Ranges .160 – .188 .090 – .120 .013 – .021 .026 – .032. .025 min .020 – .045 .685 – .695 .650 – .656 .600 – .630 .500 REF .050 BSC .042 – .060 .042 – .048 .000 – .028 .025 – .045 TABLE 6-1. PLCC PACKAGE DIMENSIONS Notes: 1. 2. 3. Coplanarity is .004" maximum Tolerance on the position of the leads is .007"maximum Package body dimensions D1 and E1 do not include the mold protrusion. Maximum mold protrusion is .010" 28 Index 83C694D Index ! F P Phase-locked loop, 5, 7 PLCC/PQFP package, 9 PLL filter cap, 13 Positive supply, 14 Prevention of voltage fluctuation, 5 Pulse widths transmitted, 6 R Receive clock, 10 Receive data, 10 Receive LED driver, 11 RES, 10 Reset/Synch, 10 RLED, 11 RX-/RX+, 14 RXC, 10 RXC & RXD enable, 8 RXD, 10 S SEL, 10 Smart squelch, 1, 7 SQE test functions, 8 Status indications, 8 T Test modes, 8 Timing diagrams, 20 TP differential driver, 6 design notes, 6 TP differential receiver, 7 TPOL, 11 TPR-/TPR+, 15 TPX1+, 13 TPX1-, 12 TPX2+, 13 TPX2-, 12 Transmit clock, 12 Transmit data, 12 Transmit enable, 12 Transmit LED driver, 11 TST, 14 Twisted-pair interface, 4 Twisted-pair link polarity, 11 Twisted-pair link status, 11 29 Features, 1 83B692 Ethernet transceiver, 4 83C690 Ethernet LAN controller, 4 G 83C694D functional blocks, 4 General description, 1 as twisted-pair interface, 4 GND, 11 pin package, 27 I A Indicator LEDs, 8 Absolute maximum ratings, 16 Internal counter speedup, 8 AC operating characteristics, 18 Introduction, 1 20 Architecture, 4 - 8 J AUI collision, 14 Jabber, 8 AUI differential line driver, 5 design notes, 5 L AUI receive, 14 AUI transmit, 13 LBK, 12 AUI/TP autoselect, 8 LED test functions, 8 Autoselect, 8 Link test function, 8 B Bias resistor, 14 BSR, 14 C CAP, 13 Carrier sense, 10 Carrier Sense (CRS), 5 CD-/CD+, 14 COL, 10 Collision detect, 10 Collision translator, 6 CRS, 10 Crystal accuracy, 12 Crystal feedback, 12 Crystal/ext. input, 12 D DC electrical specifications, 16 - 17 recommended operating conditions, 16 DC operating characteristics, 16 Decoding, 5 Differential driver, 5 LNK, 11 Loopback, 12 Loopback function, 7 M Main functions, 1 Manchester decoder, 5 Manchester encoder, 5 Manchester encoding, 4 Mode select, 10 Mode select 1, 13 Mode select 2, 13 MODE1, 13 MODE2, 13 N Negative supply, 11 NRZ data conversion, 4 O Oscillator, 4 OSR, 13 Output tristate, 8 83C694D Twisted-pair receive, 15 Twisted-pair transmit, 12 - 13 TX-/TX+, 13 TXC, 12 TXD, 12 TXE, 12 Typical TPX pin values, 6 U UTP, 6 V VCC, 14 VCO bias resistor, 13 X X1, 12 X2O, 12 XLED, 11 Z Zener diode 5-volt supply, 5 Index 30