FDC37B78X

FDC37B78x Super I/O Controller with ACPI Support, Real Time Clock and Consumer IR FEATURES 5 Volt Operation PC98/99 and ACPI 1.0 Compliant Battery Back-up for Wake-Events ISA Plug-and-Play Compatible Register Set 12 IRQ Options 15 Serial IRQ Options 16 Bit Address Qualification Four DMA Options 12mA AT Bus Drivers BIOS Buffer 20 GPI/O Pins 32KHz Standby Clock Output Soft Power Management ACPI/PME Support SCI/SMI Support Watchdog timer Power Button Override Event Either Edge Triggered Interrupts Intelligent Auto Power Management Shadowed Write-only Registers Programmable Wake-up Event Interface 8042 Keyboard Controller 2K Program ROM 256 Bytes Data RAM Asynchronous Access to Two Data Registers and One Status Register Supports Interrupt and Polling Access 8 Bit Timer/Counter Port 92 Support Fast Gate A20 and Hardware Keyboard Reset Real Time Clock Day of Month Alarm, Century Byte MC146818 and DS1287 Compatible 256 Bytes of Battery Backed CMOS in Two Banks of 128 Bytes 128 Bytes of CMOS RAM Lockable in 4x32 Byte Blocks 12 and 24 Hour Time Format Binary and BCD Format 5μA Standby Battery Current (max)1 2.88MB Super I/O Floppy Disk Controller Relocatable to 480 Different Addresses Licensed CMOS 765B Floppy Disk Controller Advanced Digital Data Separator SMSC's Proprietary 82077AA Compatible Core Sophisticated Power Control Circuitry (PCC) Including Multiple Powerdown Modes for Reduced Power Consumption Supports Two Floppy Drives Directly Software Write Protect FDC on Parallel Port Low Power CMOS Design Supports Vertical Recording Format 16 Byte Data FIFO 100% IBM Compatibility Detects All Overrun and Underrun Conditions 24mA Drivers and Schmitt Trigger Inputs Enhanced FDC Digital Data Separator Low Cost Implementation No Filter Components Required 2 Mbps, 1 Mbps, 500 Kbps, 300 Kbps, 250 Kbps Data Rates Programmable Precompensation Modes - 1 Serial Ports Relocatable to 480 Different Addresses Two High Speed NS16C550 Compatible UARTs with Send/Receive 16 Byte FIFOs Programmable Baud Rate Generator Modem Control Circuitry Including 230K and 460K Baud IrDA 1.0, Consumer IR, HP-SIR, ASKIR Support Ring Wake Filter Multi-Mode Parallel Port with ChiProtect Relocatable to 480 Different Addresses Standard Mode IBM PC/XT, PC/AT, and PS/2 Compatible Bidirectional ParallelPort Enhanced Mode Enhanced Parallel Port (EPP) Compatible EPP 1.7 and EPP 1.9 (IEEE 1284 Compliant) High Speed Mode Microsoft and Hewlett Packard Extended Capabilities Port (ECP) Compatible (IEEE 1284 Compliant) Incorporates ChiProtect Circuitry for Protection Against Damage Due to Printer Power-On 14 mA Output Drivers 128 Pin QFP package, lead-free RoHS compliant package also available - Note 1: Please contact SMSC for the latest value. ORDERING INFORMATION Order Numbers: FDC37B787QFP for 128 pin QFP package FDC37B787-NS for 128 pin QFP lead-free RoHS compliant package 2 TABLE OF CONTENTS FEATURES ........................................................................................................................................... 1 GENERAL DESCRIPTION ................................................................................................................. 6 DESCRIPTION OF PIN FUNCTIONS ............................................................................................... 7 BUFFER TYPE DESCRIPTIONS .................................................................................................... 11 REFERENCE DOCUMENTS ........................................................................................................... 13 FUNCTIONAL DESCRIPTION......................................................................................................... 14 SUPER I/O REGISTERS ............................................................................................................... 14 HOST PROCESSOR INTERFACE .............................................................................................. 14 FLOPPY DISK CONTROLLER....................................................................................................... 16 FDC INTERNAL REGISTERS ................................................................................................. 16 COMMAND SET/DESCRIPTIONS .......................................................................................... 41 Force Write Protect .................................................................................................................. 70 SERIAL PORT (UART) ..................................................................................................................... 70 REGISTER DESCRIPTION ...................................................................................................... 70 INFRARED INTERFACE .................................................................................................................. 88 PARALLEL PORT ............................................................................................................................. 88 IBM XT/AT COMPATIBLE, BI-DIRECTIONAL AND EPP MODES........................................ 90 EXTENDED CAPABILITIES PARALLEL PORT .......................................................................... 96 PARALLEL PORT FLOPPY DISK CONTROLLER .................................................................. 108 POWER MANAGEMENT................................................................................................................ 110 FDC Power Management ...................................................................................................... 110 UART Power Management ................................................................................................... 115 Parallel Port.............................................................................................................................. 115 VBAT Support ............................................................................................................................ 115 VTR Support .............................................................................................................................. 115 Internal PWRGOOD ................................................................................................................ 116 CIRCC PLL Power Control ................................................................................................... 116 32.768 kHz Standby Clock Output...................................................................................... 116 BIOS BUFFER .................................................................................................................................. 121 GENERAL PURPOSE I/O .............................................................................................................. 123 3 Description ............................................................................................................................... 123 RUN STATE GPIO DATA REGISTER ACCESS ................................................................ 123 GPIO OPERATION .................................................................................................................. 127 8042 KEYBOARD CONTROLLER DESCRIPTION ................................................................... 130 RTC INTERFACE............................................................................................................................. 138 SOFT POWER MANAGEMENT .................................................................................................... 148 ACPI/PME/SMI FEATURES ........................................................................................................... 152 ACPI Features.......................................................................................................................... 152 Wake Events ............................................................................................................................. 153 PME SUPPORT ........................................................................................................................ 154 ACPI/PME/SMI REGISTERS ...................................................................................................... 154 Register Description ................................................................................................................. 154 Wakeup Event Configuration is Retained by Battery Power ...................................... 156 Register Block ......................................................................................................................... 156 ACPI REGISTERS ................................................................................................................... 157 CONFIGURATION ........................................................................................................................... 168 SYSTEM ELEMENTS .................................................................................................................. 168 Entering the Configuration State........................................................................................ 149 Exiting the Configuration State .......................................................................................... 149 CONFIGURATION SEQUENCE ............................................................................................ 149 CONFIGURATION REGISTERS ................................................................................................... 172 Chip Level (Global) Control/Configuration Registers [0x00-0x2F] ............................ 176 Logical Device Configuration/Control Registers [0x30-0xFF] .................................... 179 Logical Device Registers ...................................................................................................... 179 I/O Base Address Configuration Register........................................................................ 181 Interrupt Select Configuration Register ........................................................................... 183 DMA Channel Select Configuration Register .................................................................. 184 SMSC Defined Logical Device Configuration Registers .............................................. 185 Parallel Port, Logical Device 3 ............................................................................................ 188 Serial Port 1, Logical Device 4 ............................................................................................ 189 Serial Port 2, Logical Device 5 ............................................................................................ 191 RTC, Logical Device 6 ........................................................................................................... 192 KYBD, Logical Device 7 ........................................................................................................ 193 Auxiliary I/O, Logical Device 8 ............................................................................................ 194 ACPI, Logical Device A ......................................................................................................... 212 OPERATIONAL DESCRIPTION ................................................................................................... 218 MAXIMUM GUARANTEED RATINGS ...................................................................................... 218 DC ELECTRICAL CHARACTERISTICS ................................................................................... 218 4 AC TIMING DIAGRAMS .............................................................................................................. 223 CAPACITIVE LOADING ......................................................................................................... 223 IOW Timing Port 92 ................................................................................................................ 224 POWER-UP TIMING ................................................................................................................ 225 Button Timing .......................................................................................................................... 226 ROM INTERFACE.................................................................................................................... 227 ISA WRITE ................................................................................................................................ 228 ISA READ .................................................................................................................................. 229 8042 CPU .................................................................................................................................. 231 CLOCK TIMING........................................................................................................................ 232 Burst Transfer DMA Timing ................................................................................................. 235 DISK DRIVE TIMING ............................................................................................................... 237 SERIAL PORT .......................................................................................................................... 238 Parallel Port.............................................................................................................................. 239 EPP 1.9 Data or Address Write Cycle................................................................................ 240 EPP 1.9 Data or Address Read Cycle ................................................................................ 242 EPP 1.7 Data Or Address Write Cycle ............................................................................... 244 EPP 1.7 Data or Address Read Cycle ................................................................................ 246 ECP PARALLEL PORT TIMING ........................................................................................... 249 Serial Port Infrared Timing ................................................................................................... 254 5 GENERAL DESCRIPTION The FDC37B78x with advanced Consumer IR and IrDA v1.0 support incorporates a keyboard interface, real-time clock, SMSC's true CMOS 765B floppy disk controller, advanced digital data separator, 16 byte data FIFO, two 16C550 compatible UARTs, one Multi-Mode parallel port which includes ChiProtect circuitry plus EPP and ECP support, on-chip 12 mA AT bus drivers, and two floppy direct drive support, soft power management and SMI support and Intelligent Power Management including PME and SCI/ACPI support. The true CMOS 765B core provides 100% compatibility with IBM PC/XT and PC/AT architectures in addition to providing data overflow and underflow protection. The SMSC advanced digital data separator incorporates SMSC's patented data separator technology, allowing for ease of testing and use. Both on-chip UARTs are compatible with the NS16C550. The parallel port, the IDE interface, and the game port select logic are compatible with IBM PC/AT architecture, as well as EPP and ECP. The FDC37B78x incorporates sophisticated power control circuitry (PCC) which includes support for keyboard, mouse, modem ring, power button support and consumer infrared wake-up events. The PCC supports multiple low power down modes. The FDC37B78x provides features for compliance with the “Advanced Configuration and Power Interface Specification” (ACPI). These features include support of both legacy and ACPI power management models through the selection of SMI or SCI. It implements a power button override event (4 second button hold to turn off the system) and either edge triggered interrupts. The FDC37B78x provides support for the ISA Plug-and-Play Standard (Version 1.0a) and provides for the recommended functionality to support Windows '95, PC97 and PC98. Through internal configuration registers, each of the FDC37B78x 's logical device's I/O address, DMA channel and IRQ channel may be programmed. There are 480 I/O address location options, 12 IRQ options or Serial IRQ option, and four DMA channel options for each logical device. The FDC37B78x Floppy Disk Controller and separator do not require any external components and are therefore easy to use, lower system cost and reduced board area. FDC is software and register compatible SMSC's proprietary 82077AA core. data filter offer The with 6 PD7 VSS SLCT PE BUSY nACK nERROR nALF nSTROBE RXD1 TXD1 nDSR1 nRTS1/SYSOP nCTS1 nDTR1 nRI1 nDCD1 nRI2 VCC nDCD2 RXD2/IRRX TXD2/IRTX nDSR2 nRTS2 nCTS2 nDTR2 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 DRVDEN0 DRVDEN1/GP52/IRQ8/nSMI nMTR0 nMTR1/GP16 nDS0 nDS1/GP17 VSS nDIR nSTEP nWDATA nWGATE nHDSEL nINDEX nTRK0 nWRTPRT 1 2 3 4 5 6 7 8 9 10 11 12 13 FDC37B78x 128 Pin QFP FIGURE 1 - FDC37B78x PIN CONFIGURATION 6 nRDATA nDSKCHG CLK32OUT nPOWERON BUTTON_IN nPME/SCI/IRQ9 CLOCKI SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 IOCHRDY TC VCC DRQ3 nDACK3 DRQ2 nDACK2 DRQ1 nDACK1 DRQ0 nDACK0 RESET_DRV SD7 SD6 SD5 SD4 VSS SD3 SD2 SD1 SD0 AEN nIOW nIOR SER_IRQ/IRQ15 PCI_CLK/IRQ14/GP50 PD6 PD5 PD4 PD3 PD2 PD1 PD0 nSLCTIN nINIT VCC nROMOE/IRQ12/GP54/EETI nROMCS/IRQ11/GP53/EETI RD7/IRQ10/GP67 RD6/IRQ8/GP66 RD5/IRQ7/GP65 RD4/IRQ6/GP64/P17 RD3/IRQ5/GP63/WDT RD2/IRQ4/GP62/nRING RD1/IRQ3/GP61/LED RD0/IRQ1/GP60/nSMI GP15/IRTX2 GP14/IRRX2 GP13/LED GP12/WDT/P17/EETI GP11/nRING/EETI GP10/nSMI A20M KBDRST VSS MCLK MDAT KCLK KDAT VTR XTAL2 AVSS XTAL1 VBAT DESCRIPTION OF PIN FUNCTIONS PIN No./QFP NAME TOTAL SYMBOL BUFFER TYPE PROCESSOR/HOST INTERFACE (40) 44-47, 49-52 23-38 43 64 53 40 39 55 57 59 61 54 56 58 60 63 41 42 16-bit System Address Bus Address Enable I/O Channel Ready ISA Reset Drive Serial IRQ/IRQ15 PCI Clock/IRQ14/GP50 DMA Request 0 DMA Request 1 DMA Request 2 DMA Request 3 DMA Acknowledge 0 DMA Acknowledge 1 DMA Acknowledge 2 DMA Acknowledge 3 Terminal Count I/O Read I/O Write CLOCKS (4) 22 66 68 18 14.318MHz Clock Input 32.768kHz Crystal Input 32.768kHz Crystal Driver 32.768kHz Clock Out POWER PINS (10) 62, 93, 121 +5V Supply Voltage 3 VCC 1 1 1 1 CLOCKI XTAL1 XTAL2 CLK32OUT I ICLK OCLK O8 16 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 SA[0:15] AEN IOCHRDY RESET_DRV SER_IRQ PCI_CLK DRQ0 DRQ1 DRQ2 DRQ3 nDACK0 nDACK1 nDACK2 nDACK3 TC nIOR nIOW I I OD12 IS IO12 IO12 O12 O12 O12 O12 I I I I I I I System Data Bus 8 SD[0:7] IO12 7 PIN No./QFP 7, 48, 74, 104 67 69 65 Analog Ground Digital Ground NAME TOTAL 4 SYMBOL VSS BUFFER TYPE 1 1 1 POWER MANAGEMENT (3) AVSS VTR VBAT Trickle Supply Voltage Battery Voltage 19 20 21 Power On Button In Power Management Event/SCI/IRQ9 FDD INTERFACE (16) 1 1 1 nPOWERON BUTTON_IN nPME OD24 I O12 16 11 10 12 8 9 17 5 6 3 4 15 14 13 1 2 Read Disk Data Write Gate Write Disk Data Head Select Step Direction Step Pulse Disk Change Drive Select 0 Drive Select 1/GP17 Motor On 0 Motor On 1/GP16 Write Protected Track 0 Index Pulse Input Drive Density Select 0 Drive Density Select 1/GP52/IRQ8/nSMI 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 nRDATA nWGATE nWDATA nHDSEL nDIR nSTEP nDSKCHG nDS0 nDS1 nMTR0 nMTR1 nWRTPRT nTRKO nINDEX DRVDEN0 DRVDEN1 IS O24 O24 O24 O24 O24 IS O24 IO24 O24 IO24 IS IS IS O24 IO24 GENERAL PURPOSE I/O (6) 77 78 General Purpose 10/nSMI General Purpose 11/nRING/EETI 1 1 GP10 GP11 IO12 IO4 8 PIN No./QFP 79 80 81 82 NAME General Purpose 12/WDT/P17/EETI General Purpose 13/LED Driver General Purpose 14/Infrared Rx General Purpose 15/Infrared Tx (Note 3) TOTAL 1 1 1 1 SYMBOL GP12 GP13 GP14 GP15 BUFFER TYPE IO4 IO24 IO4 IO24 BIOS INTERFACE (10) 83 84 85 86 87 88 89 90 91 92 ROM Bus 0/IRQ1/GP60/nSMI ROM Bus 1/IRQ3/GP61/LED ROM Bus 2/IRQ4/GP62/nRING ROM Bus 3/IRQ5/GP63/WDT ROM Bus 4/IRQ6/GP64/P17 ROM Bus 5/IRQ7/GP65 ROM Bus 6/IRQ8/GP66 ROM Bus 7/IRQ10/GP67 nROMCS/IRQ11/GP53/EETI nROMOE/IRQ12/GP54/EETI 1 1 1 1 1 1 1 1 1 1 RD0 RD1 RD2 RD3 RD4 RD5 RD6 RD7 nROMCS nROMOE IO12 IO24 IO12 IO12 IO12 IO12 IO12 IO12 IO12 IO12 SERIAL PORT 1 INTERFACE (8) 112 113 115 116 117 114 119 118 Receive Serial Data 1 Transmit Serial Data 1 Request to Send 1 Clear to Send 1 Data Terminal Ready 1 Data Set Ready 1 Data Carrier Detect 1 Ring Indicator 1 1 1 1 1 1 1 1 1 SERIAL PORT 2 INTERFACE (8) 123 124 126 Receive Serial Data 2/Infrared Rx Transmit Serial Data 2/Infrared Tx (Note 3) Request to Send 2 1 1 1 RXD2/IRRX TXD2/IRTX nRTS2 I O24 O4 RXD1 TXD1 nRTS1/ SYSOP nCTS1 nDTR1 nDSR1 nDCD1 nRI1 I O4 IO4 I O4 I I I 9 PIN No./QFP 127 128 125 122 120 Clear to Send 2 NAME TOTAL 1 1 1 1 1 SYMBOL nCTS2 nDTR2 nDSR2 nDCD2 nRI2 BUFFER TYPE I O4 I I I Data Terminal Ready Data Set Ready 2 Data Carrier Detect 2 Ring Indicator 2 PARALLEL PORT INTERFACE (17) 96-103 95 94 110 111 107 108 106 105 109 Parallel Port Data Bus Printer Select Initiate Output Auto Line Feed Strobe Signal Busy Signal Acknowledge Handshake Paper End Printer Selected Error at Printer 8 1 1 1 1 1 1 1 1 1 KEYBOARD/MOUSE INTERFACE (6) 70 71 72 73 75 76 Note 1 Note 2 Note 3 Keyboard Data Keyboard Clock Mouse Data Mouse Clock Keyboard Reset Gate A20 1 1 1 1 1 1 KDAT KCLK MDAT MCLK KBDRST (Note 2) A20M IOD16 IOD16 IOD16 IOD16 O4 O4 PD[0:7] nSLCTIN nINIT nALF nSTROBE BUSY nACK PE SLCT nERROR IOP14 OP14 OP14 OP14 OP14 I I I I I The “n” as the first letter of a signal name indicates an “Active Low” signal. KBDRST is active low. This pin defaults to an output and low. 10 BUFFER TYPE DESCRIPTIONS SYMBOL I IS ICLK OCLK IO4 O4 O8 IO12 O12 OD12 IOP14 OD14 OP14 IOD16 O24 OD24 IO24 TABLE 1 - BUFFER TYPES DESCRIPTION Input, TTL compatible. Input with Schmitt trigger. RTC 32.768 kHz crystal input. RTC 32.768 kHz crystal output. Input/Output, 4mA sink, 2mA source. Output, 4mA sink, 2mA source. Output, 8mA sink, 4mA source. Input/Output, 12mA sink, 6mA source. Output, 12mA sink, 6mA source. Output, Open Drain, 12 mA sink. Input/Output, 14mA sink, 14mA source. Backdrive Protected. Output, Open Drain, 14mA sink. Output, 14mA sink, 14mA source. Backdrive Protected. Input/Output, Open Drain, 16mA sink Output, 24mA sink, 12mA source. Output, Open Drain, 24mA sink. Input/Output, 24mA sink, 12mA source. 11 PME#/SCI nSMI* nROMOE* nROMCS* RD[0:7]* MULTI-MODE PARALLEL PORT/FDC MUX nPowerOn Button_In SOFT POWER MANAGEMENT PME/ ACPI nSMI BIOS BUFFER PD0-7 BUSY, SLCT, PE, nERROR, nACK nSTB, nSLCTIN, nINIT, nALF POWER MANAGEMENT DATA BUS SER_IRQ PCI_CLK SERIAL IRQ ADDRESS BUS GENERAL PURPOSE I/O GP1[0:7]* GP5[0,2:4]* GP6[0:7]* nIOR CONFIGURATION nIOW REGISTERS 16C550 COMPATIBLE SERIAL PORT 1 TXD1 RXD1 nDSR1, nDCD1, nRI1, nDTR1 nCTS1, nRTS1 AEN CONTROL BUS SA[0:15] SD[O:7] HOST IRTX IRRX WDATA DRQ[0:3] CPU INTERFACE nDACK[0:3] SMSC PROPRIETARY TC 82077 COMPATIBLE VERTICAL FLOPPYDISK CONTROLLER CORE RCLOCK IOCHRDY RDATA RTC DIGITAL DATA SEPARATOR WITH WRITE PRECOMPENSATION 8042 WCLOCK 16C550 COMPATIBLE SERIAL PORT 2 WITH INFRARED TXD2(IRTX) RXD2(IRRX) nDSR2, nDCD2, nRI2, nDTR2 nCTS2, nRTS2 IRQ[1,3-12,14] KCLK KDATA MCLK MDATA P20, P21 P17* XTAL1,2 VBAT RESET_DRV CLK32OUT nINDEX nTRK0 nDSKCHG nWRPRT nWGATE Vcc Vtr Vss nSTEP nHDSEL DENSEL nDIR nDS0,1 nMTR0,1 DRVDEN0 DRVDEN1 nWDATA nRDATA CLOCK GEN CLOCKI (14.318) *Multi-Function I/O Pin - Optional FIGURE 2 - FDC37B78x BLOCK DIAGRAM 12 GENERAL PURPOSE I/O PINS TABLE 2 - GENERAL PURPOSE I/O PIN FUNCTIONS DEFAULT ALT ALT ALT BUFFER FUNCT FUNCT 1 FUNCT 2 FUNCT 3 TYPE PIN NO. QFP 77 GPIO nSMI IO12 GP10 78 GPIO nRING EETI1 IO4 GP11 79 GPIO WDT P17 EETI1 IO4 GP12 80 GPIO LED IO24 GP13 81 GPIO IRRX2 IO4 GP14 82 GPIO IRTX2 IO24 GP15 4 nMTR1 GPIO IO24 GP16 6 nDS1 GPIO IO24 GP17 IO12 39 PCI_CLK IRQ14 GPIO GP50 2 DRVDEN1 GPIO IRQ8 nSMI IO24 GP52 IO12 91 nROMCS2 IRQ11 GPIO EETI1 GP53 2 IO12 92 nROMOE IRQ12 GPIO EETI1 GP54 IO12 83 RD02,3 IRQ1 GPIO nSMI GP60 IO24 84 RD12,3 IRQ3 GPIO LED GP61 IO12 85 RD22,3 IRQ4 GPIO nRING GP62 IO12 86 RD32,3 IRQ5 GPIO WDT GP63 IO12 87 RD42,3 IRQ6 GPIO P17 GP64 IO12 88 RD52,3 IRQ7 GPIO GP65 IO12 89 RD62,3 IRQ8 GPIO GP66 IO12 90 RD72,3 IRQ10 GPIO GP67 Note 1 Either Edge Triggered Interrupt Inputs. Note 2 At power-up, RD0-7, nROMCS and nROMOE function as the XD Bus. To use RD0-7 for alternate functions, nROMCS must stay high until those pins are finished being programmed. Note 3 These pins cannot be programmed as open drain pins in their original function. INDEX REGISTE R GP1 GP1 GP1 GP1 GP1 GP1 GP1 GP1 GP5 GP5 GP5 GP5 GP6 GP6 GP6 GP6 GP6 GP6 GP6 GP6 GPIO REFERENCE DOCUMENTS SMSC Consumer Infrared Communications Controller (CIrCC) V1.X IEEE 1284 Extended Capabilities Port Protocol and ISA Standard, Rev. 1.14, July 14, 1993. Hardware Description of the 8042, Intel 8 bit Embedded Controller Handbook. PCI Bus Power Management Interface Specification, Rev. 1.0, Draft, March 18, 1997. 13 FUNCTIONAL DESCRIPTION SUPER I/O REGISTERS The address map, shown below in Table 4, shows the addresses of the different blocks of the Super I/O immediately after power up. The base addresses of the FDC, serial and parallel ports can be moved via the configuration registers. Some addresses are used to access more than one register. HOST PROCESSOR INTERFACE The host processor communicates with the FDC37B78x through a series of read/write registers. The port addresses for these registers are shown in Table 4. Register access is accomplished through programmed I/O or DMA transfers. All registers are 8 bits wide. All host interface output buffers are capable of sinking a minimum of 12 mA. TABLE 3 - SUPER I/O BLOCK ADDRESSES LOGICAL ADDRESS BLOCK NAME DEVICE Base+(0-5) and +(7) Floppy Disk 0 3 Parallel Port SPP Base+(0-3) EPP Base+(0-7) ECP Base+(0-3), +(400-402) ECP+EPP+SPP Base+(0-7), +(400-402) Base+(0-7) Serial Port Com 1 4 Base1+(0-7) Serial Port Com 2 5 Base2+(0-7) 70,71, Base, Base+(1) RTC 6 60, 64 KYBD 7 Base + (0-17h) ACPI, PME, SMI A Base + (0-1) Configuration NOTES IR Support Consumer IR Note 1: Refer to the configuration register descriptions for setting the base address. 14 FLOPPY DISK CONTROLLER The Floppy Disk Controller (FDC) provides the interface between a host microprocessor and the floppy disk drives. The FDC integrates the functions of the Formatter/Controller, Digital Data Separator, Write Precompensation and Data Rate Selection logic for an IBM XT/AT compatible FDC. The true CMOS 765B core guarantees 100% IBM PC XT/AT compatibility in addition to providing data overflow and underflow protection. The FDC is compatible to the 82077AA using SMSC's proprietary floppy disk controller core. FDC INTERNAL REGISTERS The Floppy Disk Controller contains eight internal registers that facilitate the interfacing between the host microprocessor and the disk drive. TABLE 4 shows the addresses required to access these registers. Registers other than the ones shown are not supported. The rest of the description assumes that the primary addresses have been selected. TABLE 4 - STATUS, DATA AND CONTROL REGISTERS (Shown with base addresses of 3F0 and 370) PRIMARY SECONDARY ADDRESS ADDRESS R/W REGISTER Status Register A (SRA) R 370 3F0 Status Register B (SRB) R 371 3F1 Digital Output Register (DOR) R/W 372 3F2 Tape Drive Register (TSR) R/W 373 3F3 Main Status Register (MSR) R 374 3F4 Data Rate Select Register (DSR) W 374 3F4 Data (FIFO) R/W 375 3F5 Reserved 376 3F6 Digital Input Register (DIR) R 377 3F7 Configuration Control Register (CCR) W 377 3F7 16 STATUS REGISTER A (SRA) Address 3F0 READ ONLY This register is read-only and monitors the state of the FINTR pin and several disk interface pins in PS/2 and Model 30 modes. The SRA can be accessed at any time when in PS/2 mode. In the PC/AT mode the data bus pins D0 - D7 are held in a high impedance state for a read of address 3F0. PS/2 Mode 7 INT PENDING 0 6 nDRV2 1 5 STEP 0 4 3 2 nTRK0 HDSEL nINDX N/A 0 N/A 1 nWP N/A 0 DIR 0 RESET COND. BIT 0 DIRECTION Active high status indicating the direction of head movement. A logic "1" indicates inward direction; a logic "0" indicates outward direction. BIT 1 nWRITE PROTECT Active low status of the WRITE PROTECT disk interface input. A logic "0" indicates that the disk is write protected. (See also Force Write Protect Function) BIT 2 nINDEX Active low status of the INDEX disk interface input. BIT 3 HEAD SELECT Active high status of the HDSEL disk interface input. A logic "1" selects side 1 and a logic "0" selects side 0. BIT 4 nTRACK 0 Active low status of the TRK0 disk interface input. BIT 5 STEP Active high status of the STEP output disk interface output pin. BIT 6 nDRV2 Active low status of the DRV2 disk interface input pin, indicating that a second drive has been installed. Note: This function is not supported in this chip. (Always 1, indicating 1 drive) BIT 7 INTERRUPT PENDING Active high bit indicating the state of the Floppy Disk Interrupt output. 17 PS/2 Model 30 Mode 7 INT PENDING 0 6 DRQ 0 5 STEP F/F 0 4 TRK0 N/A 3 nHDSEL 1 2 INDX N/A 1 WP N/A 0 nDIR 1 RESET COND. BIT 0 nDIRECTION Active low status indicating the direction of head movement. A logic "0" indicates inward direction; a logic "1" indicates outward direction. BIT 1 WRITE PROTECT Active high status of the WRITE PROTECT disk interface input. A logic "1" indicates that the disk is write protected. (See also Force Write Protect Function) BIT 2 INDEX Active high status of the INDEX disk interface input. BIT 3 nHEAD SELECT Active low status of the HDSEL disk interface input. A logic "0" selects side 1 and a logic "1" selects side 0. BIT 4 TRACK 0 Active high status of the TRK0 disk interface input. BIT 5 STEP Active high status of the latched STEP disk interface output pin. This bit is latched with the STEP output going active, and is cleared with a read from the DIR register, or with a hardware or software reset. BIT 6 DMA REQUEST Active high status of the DRQ output pin. BIT 7 INTERRUPT PENDING Active high bit indicating the state of the Floppy Disk Interrupt output. 18 STATUS REGISTER B (SRB) Address 3F1 READ ONLY This register is read-only and monitors the state of several disk interface pins in PS/2 and Model 30 modes. The SRB can be accessed at any time when in PS/2 mode. In the PC/AT mode the data bus pins D0 - D7 are held in a high impedance state for a read of address 3F1. PS/2 Mode 7 1 RESET COND. 1 6 1 1 5 4 3 2 DRIVE WDATA RDATA WGATE SEL0 TOGGLE TOGGLE 0 0 0 0 1 MOT EN1 0 0 MOT EN0 0 BIT 0 MOTOR ENABLE 0 Active high status of the MTR0 disk interface output pin. This bit is low after a hardware reset and unaffected by a software reset. BIT 1 MOTOR ENABLE 1 Active high status of the MTR1 disk interface output pin. This bit is low after a hardware reset and unaffected by a software reset. BIT 2 WRITE GATE Active high status of the WGATE disk interface output. BIT 3 READ DATA TOGGLE Every inactive edge of the RDATA input causes this bit to change state. BIT 4 WRITE DATA TOGGLE Every inactive edge of the WDATA input causes this bit to change state. BIT 5 DRIVE SELECT 0 Reflects the status of the Drive Select 0 bit of the DOR (address 3F2 bit 0). This bit is cleared after a hardware reset and it is unaffected by a software reset. BIT 6 RESERVED Always read as a logic "1". BIT 7 RESERVED Always read as a logic "1". 19 PS/2 Model 30 Mode 7 nDRV2 RESET COND. N/A 6 nDS1 1 5 nDS0 1 4 WDATA F/F 0 3 RDATA F/F 0 2 WGATE F/F 0 1 nDS3 1 0 nDS2 1 BIT 0 nDRIVE SELECT 2 The DS2 disk interface is not supported. (Always 1) BIT 1 nDRIVE SELECT 3 The DS3 disk interface is not supported. (Always 1) BIT 2 WRITE GATE Active high status of the latched WGATE output signal. This bit is latched by the active going edge of WGATE and is cleared by the read of the DIR register. BIT 3 READ DATA Active high status of the latched RDATA output signal. This bit is latched by the inactive going edge of RDATA and is cleared by the read of the DIR register. BIT 4 WRITE DATA Active high status of the latched WDATA output signal. This bit is latched by the inactive going edge of WDATA and is cleared by the read of the DIR register. This bit is not gated with WGATE. BIT 5 nDRIVE SELECT 0 Active low status of the DS0 disk interface output. BIT 6 nDRIVE SELECT 1 Active low status of the DS1 disk interface output. BIT 7 nDRV2 Active low status of the DRV2 disk interface input, this is not supported. (Always 1) 20 DIGITAL OUTPUT REGISTER (DOR) Address 3F2 READ/WRITE The DOR controls the drive select and motor enables of the disk interface outputs. It also contains the enable for the DMA logic and a software reset bit. The contents of the DOR are unaffected by a software reset. The DOR can be written to at any time. 7 MOT EN3 0 6 MOT EN2 0 5 MOT EN1 0 4 MOT EN0 0 3 DMAEN 0 2 1 0 nRESE DRIVE DRIVE T SEL1 SEL0 0 0 0 RESET COND. BIT 0 and 1 DRIVE SELECT These two bits are binary encoded for the drive selects, thereby allowing only one drive to be selected at one time. BIT 2 nRESET A logic "0" written to this bit resets the Floppy disk controller. This reset will remain active until a logic "1" is written to this bit. This software reset does not affect the DSR and CCR registers, nor does it affect the other bits of the DOR register. The minimum reset duration required is 100ns, therefore toggling this bit by consecutive writes to this register is a valid method of issuing a software reset. BIT 3 DMAEN PC/AT and Model 30 Mode: Writing this bit to logic "1" will enable the DRQ, nDACK, TC and FINTR outputs. This bit being a logic "0" will disable the nDACK and TC inputs, and hold the DRQ and FINTR outputs in a high impedance state. This bit is a logic "0" after a reset and in these modes. PS/2 Mode: In this mode the DRQ, nDACK, TC and FINTR pins are always enabled. During a reset, the DRQ, nDACK, TC, and FINTR pins will remain enabled, but this bit will be cleared to a logic "0". BIT 4 MOTOR ENABLE 0 This bit controls the MTR0 disk interface output. A logic "1" in this bit will cause the output pin to go active. BIT 5 MOTOR ENABLE 1 This bit controls the MTR1 disk interface output. A logic "1" in this bit will cause the output pin to go active. BIT 6 MOTOR ENABLE 2 The MTR2 disk interface output is not. (Always 0) BIT 7 MOTOR ENABLE 3 The MTR3 disk interface output is not. (Always 0) Table 6 - Drive Activation Values DRIVE DOR VALUE 0 1CH 1 2DH 21 TAPE DRIVE REGISTER (TDR) Address 3F3 READ/WRITE TABLE 7 - TAPE SELECT BITS TAPE SEL1 (TDR.1) 0 0 1 1 TAPE SEL0 (TDR.0) 0 1 0 1 DRIVE SELECTED None 1 2 3 The Tape Drive Register (TDR) is included for 82077 software compatibility and allows the user to assign tape support to a particular drive during initialization. Any future references to that drive automatically invokes tape support. The TDR Tape Select bits TDR.[1:0] determine the tape drive number. TABLE 7 illustrates the Tape Select Bit encoding. Note that drive 0 is the boot device and cannot be assigned tape support. The remaining Tape Drive Register bits TDR.[7:2] are tristated when read. The TDR is unaffected by a software reset. 22 TABLE 8 - INTERNAL 2 DRIVE DECODE - NORMAL DRIVE SELECT OUTPUTS MOTOR ON OUTPUTS DIGITAL OUTPUT REGISTER (ACTIVE LOW) (ACTIVE LOW) Bit 7 Bit 6 Bit 5 Bit 4 Bit1 Bit 0 nDS1 nDS0 nMTR1 nMTR0 X X X 1 0 X X 1 X 0 X 1 X X 0 1 X X X 0 0 0 1 1 X 0 1 0 1 X 1 0 1 1 1 0 1 1 1 1 nBIT 5 nBIT 5 nBIT 5 nBIT 5 nBIT 5 nBIT 4 nBIT 4 nBIT 4 nBIT 4 nBIT 4 TABLE 9 - INTERNAL 2 DRIVE DECODE - DRIVES 0 AND 1 SWAPPED DRIVE SELECT MOTOR ON OUTPUTS DIGITAL OUTPUT REGISTER OUTPUTS (ACTIVE LOW) (ACTIVE LOW) Bit 7 Bit 6 Bit 5 Bit 4 Bit1 Bit 0 nDS1 nDS0 nMTR1 nMTR0 X X X 1 0 X X 1 X 0 X 1 X X 0 1 X X X 0 0 0 1 1 X 0 1 0 1 X 0 1 1 1 1 1 0 1 1 1 nBIT 4 nBIT 4 nBIT 4 nBIT 4 nBIT 4 nBIT 5 nBIT 5 nBIT 5 nBIT 5 nBIT 5 23 Normal Floppy Mode Normal mode. Register 3F3 contains only bits 0 and 1. When this register is read, bits 2 - 7 are a high impedance. DB7 REG 3F3 Tri-state DB6 Tri-state DB5 Tri-state DB4 Tri-state DB3 Tri-state DB2 Tri-state DB1 tape sel1 DB0 tape sel0 Enhanced Floppy Mode 2 (OS2) Register 3F3 for Enhanced Floppy Mode 2 operation. DB7 DB6 DB5 DB4 DB3 DB2 DB1 tape sel1 DB0 tape sel0 REG 3F3 Reserved Reserved Drive Type ID Floppy Boot Drive TABLE 10 - DRIVE TYPE ID DIGITAL OUTPUT REGISTER REGISTER 3F3 - DRIVE TYPE ID Bit 1 0 0 1 1 Bit 0 0 1 0 1 Bit 5 L0-CRF2 - B1 L0-CRF2 - B3 L0-CRF2 - B5 L0-CRF2 - B7 Bit 4 L0-CRF2 - B0 L0-CRF2 - B2 L0-CRF2 - B4 L0-CRF2 - B6 Note:L0-CRF2-Bx = Logical Device 0, Configuration Register F2, Bit x. 24 DATA RATE SELECT REGISTER (DSR) Address 3F4 WRITE ONLY This register is write only. It is used to program the data rate, amount of write precompensation, power down status, and software reset. The data rate is programmed using the Configuration Control Register (CCR) not the DSR, for PC/AT and PS/2 Model 30 and Microchannel applications. Other applications can set the data rate in the DSR. The data rate of the floppy controller is the most recent write of either the DSR or CCR. The DSR is unaffected by a software reset. A hardware reset will set the DSR to 02H, which corresponds to the default precompensation setting and 250 Kbps. RESET COND. 7 6 S/W POWER RESET DOWN 0 0 5 0 0 4 PRECOMP2 0 3 PRECOMP1 0 2 1 0 PREDRATE DRATE COMP0 SEL1 SEL0 0 1 0 BIT 0 and 1 DATA RATE SELECT These bits control the data rate of the floppy controller. See Table 11 for the settings corresponding to the individual data rates. The data rate select bits are unaffected by a software reset, and are set to 250 Kbps after a hardware reset. BIT 2 through 4 PRECOMPENSATION SELECT These three bits select the value of write precompensation that will be applied to the WDATA output signal. Table 10 shows the precompensation values for the combination of these bits settings. Track 0 is the default starting track number to start precompensation. this starting track number can be changed by the configure command. BIT 5 UNDEFINED Should be written as a logic "0". BIT 6 LOW POWER A logic "1" written to this bit will put the floppy controller into manual low power mode. The floppy controller clock and data mode after a software reset or access to the Data Register or Main Status Register. BIT 7 SOFTWARE RESET This active high bit has the same function as the DOR RESET (DOR bit 2) except that this bit is self clearing. Note: The DSR is Shadowed in the Floppy Data Rate Select Shadow Register, LD8:CRC2[7:0]. separator circuits will be turned off. The controller will come out of manual low power. 25 TABLE 11 - PRECOMPENSATION DELAYS PRECOMPENSATION PRECOMP DELAY (nsec) 432 111 001 010 011 100 101 110 000 4V, and the FDC37B78x host interface is active. When the internal PWRGOOD signal is “0” (inactive), Vcc is ≤ 4V, and the FDC37B78x host interface is inactive; that is, ISA bus reads and writes will not be decoded. The FDC37B78x device pins nPME, KCLK, MCLK, IRRX, nRI1, nRI2, RXD1, RXD2, nRING, Button_In and GP53 are part of the PME interface and remain active when the internal PWRGOOD signal has gone inactive, provided VTR is powered. In addition, the nPowerOn and CLK32OUT pins remain active when the internal PWRGOOD is inactive and VTR is powered. When the internal PWRGOOD is inactive, and VTR is powered, the GPIOs (excluding GP53) become tri-state (input) and are able to generate wake-up events. The internal PWRGOOD signal is also used to determine the clock source for the CIrCC CIR and to disable the IR Half Duplex Timeout. Note: If VTR is to be used for programmable wake-up events when VCC is removed, VTR must be at its full minimum potential at least 10 μs before Vcc begins a power-on cycle. When VTR and Vcc are fully powered, the potential difference between the two supplies must not exceed 500mV. CIRCC PLL Power Control The FDC37B78x uses the 32.768 kHz RTC clock and a clock multiplier (PLL) to drive the CIrCC Wakeup function when Vcc has been removed. The CIR PLL Power bit, located in the Sleep/Wake Configuration Register, is used to enable (power-up) the 32.768 kHz clock PLL. When the CIR PLL Power bit is set to “1” (active), the 32.768 kHz clock PLL is running and can replace the 14.318 MHz clock source for the CIR Wake Event, depending upon the state of the internal PWRGOOD signal (TABLE 51). When the CIR PLL Power bit is reset to “0” (inactive/default), the 32.768 kHz clock PLL is unpowered. PLL CONTROL BIT (CR24.1) 1 0 0 0 0 TABLE 51 - FDC37B78x PLL CONTROLS AND SELECTS CIR PLL INTERNAL POWER BIT PWRGOOD DESCRIPTION X X All PLLs Powered Down 0 0 0 1 32KHz PLL Unpowered, Not Selected, 14MHz PLL Powered, Selected. 1 0 32KHz PLL Powered, Selected, 14MHz PLL Unpowered, Not Selected. 1 1 32KHz PLL Powered, Not Selected, 14MHz PLL Powered, Selected. 32.768 kHz Standby Clock Output The FDC37B78x provides a 32.768 kHz trickle clock output pin. This output is active as long as VTR is present. SERIAL INTERRUPTS The FDC37B78x will support the serial interrupt to transmit interrupt information to the host system. The serial interrupt scheme adheres to the Serial IRQ Specification for PCI Systems, Version 6.0. 116 Timing Diagrams For IRQSER Cycle PCICLK = 33Mhz_IN pin IRQSER = SIRQ pin A) Start Frame timing with source sampled a low pulse on IRQ1 SL or START FRAME H R T IRQ0 FRAME IRQ1 FRAME IRQ2 FRAME S R T S R T S R T H PCICLK IRQSER Drive Source IRQ1 START1 Host Controller None R=Recovery T=Turn-around IRQ1 None H=Host Control SL=Slave Control S=Sample 1) Start Frame pulse can be 4-8 clocks wide. 118 B) Stop Frame Timing with Host using 17 IRQSER sampling period IRQ14 FRAME SRT PCICLK IRQSER Driver None IRQ15 FRAME SRT IOCHCK# FRAME SRT STOP FRAME NEXT CYCLE T I 2 H R STOP1 IRQ15 None H=Host Control R=Recovery I= Idle. START3 Host Controller T=Turn-around S=Sample 1) 2) 3) Stop pulse is 2 clocks wide for Quiet mode, 3 clocks wide for Continuous mode. There may be none, one or more Idle states during the Stop Frame. The next IRQSER cycle’s Start Frame pulse may or may not start immediately after the turn-around clock of the Stop Frame. Any IRQSER Device (i.e., The FDC37B78x) which detects any transition on an IRQ/Data line for which it is responsible must initiate a Start Frame in order to update the Host Controller unless the IRQSER is already in an IRQSER Cycle and the IRQ/Data transition can be delivered in that IRQSER Cycle. 2) Continuous (Idle) Mode: Only the Host controller can initiate a Start Frame to update IRQ/Data line information. All other IRQSER agents become passive and may not initiate a Start Frame. IRQSER will be driven low for four to eight clocks by Host Controller. This mode has two functions. It can be used to stop or idle the IRQSER or the Host Controller can operate IRQSER in a continuous mode by initiating a Start Frame at the end of every Stop Frame. An IRQSER mode transition can only occur during the Stop Frame. Upon reset, IRQSER bus is defaulted to Continuous mode, therefore only the Host controller can initiate the first Start Frame. Slaves must continuously sample the Stop Frames pulse width to determine the next IRQSER Cycle’s mode. IRQSER Cycle Control There are two modes of operation for the IRQSER Start Frame. 1) Quiet (Active) Mode: Any device may initiate a Start Frame by driving the IRQSER low for one clock, while the IRQSER is Idle. After driving low for one clock the IRQSER must immediately be tri-stated without at any time driving high. A Start Frame may not be initiated while the IRQSER is Active. The IRQSER is Idle between Stop and Start Frames. The IRQSER is Active between Start and Stop Frames. This mode of operation allows the IRQSER to be Idle when there are no IRQ/Data transitions which should be most of the time. Once a Start Frame has been initiated the Host Controller will take over driving the IRQSER low in the next clock and will continue driving the IRQSER low for a programmable period of three to seven clocks. This makes a total low pulse width of four to eight clocks. Finally, the Host Controller will drive the IRQSER back high for one clock, then tri-state. 119 IRQSER Data Frame Once a Start Frame has been initiated, the FDC37B78x will watch for the rising edge of the Start Pulse and start counting IRQ/Data Frames from there. Each IRQ/Data Frame is three clocks: Sample phase, Recovery phase, and Turn-around phase. During the Sample phase the FDC37B78x must drive the IRQSER (SIRQ pin) low, if and only if, its last detected IRQ/Data value was low. If its detected IRQ/Data value is high, IRQSER must be left tri-stated. During the Recovery phase the FDC37B78x must drive the SERIRQ high, if and only if, it had driven the IRQSER low during the previous Sample Phase. During the Turn-around Phase the FDC37B78x must tri-state the SERIRQ. The FDC37B78x will drive the IRQSER line low at the appropriate sample point if its associated IRQ/Data line is low, regardless of which device initiated the Start Frame. The Sample Phase for each IRQ/Data follows the low to high transition of the Start Frame pulse by a number of clocks equal to the IRQ/Data Frame times three, minus one. (e.g. The IRQ5 Sample clock is the sixth IRQ/Data Frame, (6 x 3) - 1 = 17th clock after the rising edge of the Start Pulse). 119 IRQSER PERIOD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Note: IRQSER Sampling Periods SIGNAL SAMPLED Not Used IRQ1 nSMI/IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 # OF CLOCKS PAST START 2 5 8 11 14 17 20 23 26 29 32 35 38 41 44 47 It is the responsibility of the software to ensure that two IRQ’s are not set to the same IRQ number. IRQSER Period 14 is used to transfer IRQ13. Logical devices 0 (FDC), 3 (Par Port), 4 (Ser Port The SIRQ data frame will now support IRQ2 from 1), 5 (Ser Port 2), 6 (RTC), and 7 (KBD) shall a logical device, previously IRQSER Period 3 have IRQ13 as a choice for their primary was reserved for use by the System interrupt. Management Interrupt (nSMI). When using Period 3 for IRQ2 the user should mask off the SMI via the SMI Enable Register. Likewise, Note: When Serial IRQs are used, the RTC when using Period 3 for nSMI the user should IRQ, nSCI and nSMI may be output on one of not configure any logical devices as using IRQ2. their respective pin options. See the IRQ MUX Configuration Register. 120 Stop Cycle Control Once all IRQ/Data Frames have completed the Host Controller will terminate IRQSER activity by initiating a Stop Frame. Only the Host Controller can initiate the Stop Frame. A Stop Frame is indicated when the IRQSER is low for two or three clocks. If the Stop Frame’s low time is two clocks then the next IRQSER Cycle’s sampled mode is the Quiet mode; and any IRQSER device may initiate a Start Frame in the second clock or more after the rising edge of the Stop Frame’s pulse. If the Stop Frame’s low time is three clocks then the next IRQSER Cycle’s sampled mode is the Continuos mode; and only the Host Controller may initiate a Start Frame in the second clock or more after the rising edge of the Stop Frame’s pulse. Latency Latency for IRQ/Data updates over the IRQSER bus in bridge-less systems with the minimum IRQ/Data Frames of seventeen, will range up to 96 clocks (3.84μS with a 25MHz PCI Bus or 2.88uS with a 33MHz PCI Bus). If one or more PCI to PCI Bridge is added to a system, the latency for IRQ/Data updates from the secondary or tertiary buses will be a few clocks longer for synchronous buses, and approximately double for asynchronous buses. EOI/ISR Read Latency Any serialized IRQ scheme has a potential implementation issue related to IRQ latency. IRQ latency could cause an EOI or ISR Read to precede an IRQ transition that it should have followed. This could cause a system fault. The host interrupt controller is responsible for ensuring that these latency issues are mitigated. The recommended solution is to delay EOIs and ISR Reads to the interrupt controller by the same amount as the IRQSER Cycle latency in order to ensure that these events do not occur out of order. AC/DC Specification Issue All IRQSER agents must drive / sample IRQSER synchronously related to the rising edge of PCI bus clock. IRQSER (SIRQ) pin uses the electrical specification of PCI bus. Electrical parameters will follow PCI spec. section 4, sustained tri-state. Reset and Initialization The IRQSER bus uses RESET_DRV as its reset signal. The IRQSER pin is tri-stated by all agents while RESET_DRV is active. With reset, IRQSER Slaves are put into the (continuous) IDLE mode. The Host Controller is responsible for starting the initial IRQSER Cycle to collect system’s IRQ/Data default values. The system then follows with the Continuous/Quiet mode protocol (Stop Frame pulse width) for subsequent IRQSER Cycles. It is Host Controller’s responsibility to provide the default values to 8259’s and other system logic before the first IRQSER Cycle is performed. For IRQSER system suspend, insertion, or removal application, the Host controller should be programmed into Continuous (IDLE) mode first. This is to guarantee IRQSER bus is in IDLE state before the system configuration changes. BIOS BUFFER The chip contains one 245 type buffer that can be used for a BIOS Buffer. If the BIOS buffer is not used, then nROMCS must be tied high or pulled up to Vcc with a resistor so as not to interfere with the boot ROM. This function allows data nROMCS L L H nROMOE L H X transmission from the RD bus to the SD bus or from the SD bus to the RD bus. The direction of the transfer is controlled by nROMOE. The enable input, nROMCS, can be used to disable the transfer and isolate the buses. DESCRIPTION RD[0:7] data to SD[0:7] bus SD[0:7] data to RD[0:7] Isolation 121 RD Bus Functionality The following cases described below illustrate the use of the RD Bus. Case 1: nROMCS and nROMOE as original function. The RD bus can be used as the RD bus or one or more RD pins can be programmed as alternate function. These alternate functions behave as follows: if in RD to SD mode, any value on RDx will appear on SDx; if in SD to RD mode, SDx will not appear on RDx, RDx gets the alternate function value. Note: In this case, nROMCS=0, nROMOE=1. Case 2: nROMOE as GPIO function. (nROMOE internally tied to ground). In this case, the RD bus is a unidirectional bus (read only) controlled by nROMCS. If nROMCS = 0, the values on RD0-7 appear on SD0-7. If nROMCS = 1, the RD bus is disabled, and nothing appears on the SD bus. Note: any RD bus pin can be programmed as an alternate function, however, if nROMCS=0, then anything on the RD bus will appear on the SD bus. Case 3: nROMCS as GPIO function. (nROMCS internally tied to VDD.) The RD bus floats - cannot use as a bus. Any pin can be programmed as an alternate function. Case 4: nROMCS and nROMOE as GPIO function. Same as Case 3. Case 5: Parallel IRQ enabled; RD Bus pins, nROMOE, nROMCS are used as IRQ pins. 107 GENERAL PURPOSE I/O The FDC37B78x provides a set of flexible Input/Output control functions to the system designer through the 21 dedicated independently programmable General Purpose I/O pins (GPIO). The GPIO pins can perform simple I/O or can be individually configured to provide predefined alternate functions. VBAT Power-On-Reset configures all GPIO pins as non-inverting inputs. Description Each GPIO port requires a 1-bit data register TABLE 52 - GENERAL PURPOSE I/O PORT ASSIGNMENTS PIN NO. QFP 77 78 79 80 81 82 4 6 39 2 91 92 83 84 85 86 87 88 89 90 DEFAULT FUNCTION GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO PCI_CLK 5 DRVDEN1 2 nROMCS 2 nROMOE 2,3 RD0 2,3 RD1 2,3 RD2 2,3 RD3 2,3 RD4 2,3 RD5 2,3 RD6 2,3 RD7 ALT. FUNC. 1 nSMI nRING WDT LED IRRX2 IRTX2 nMTR1 nDS1 IRQ14 GPIO IRQ11 IRQ12 IRQ1 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ10 ALT. FUNC. 2 1 EETI P17 GPIO IRQ8 GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO ALT. FUNC. 3 1 EETI nSMI 1 EETI 1 EETI nSMI LED nRING WDT P17 DATA REGISTER 4 (HEX) GP1 (CRF6) DATA REGISTER BIT NO. 0 1 2 3 4 5 6 7 0 2 3 4 0 1 2 3 4 5 6 7 CONFIG. 4 REGISTER (HEX) CRE0 CRE1 CRE2 CRE3 CRE4 CRE5 CRE6 CRE7 CRC8 CRCA CRCB CRCC CRD0 CRD1 CRD2 CRD3 CRD4 CRD5 CRD6 CRD7 and an 8-bit configuration control register. The data register for each GPIO port is represented as a bit in one of three 8-bit GPIO DATA Registers, GP1, GP5, and GP6. All of the GPIO registers are located in Logical Device Block No. 8 in the FDC37B78x device configuration space. The GPIO DATA Registers are also optionally available at different addresses when the FDC37B78x is in the Run state. The GPIO ports with their alternate functions and configuration state register addresses are listed in. Note: three bits 5-7 of GP5 are not implemented. GP5 (CRF9) GP6 (CRFA) Note 1. Refer to the section on Either Edge Triggered Interrupt Inputs. Note 2. At power-up, RD0-7, nROMCS and nROMOE function as the XD Bus. To use RD0-7 for alternate functions, nROMCS must stay high until those pins are finished being programmed. Note 3. These pins cannot be programmed as open drain pins in their original function. Note 4. The GPIO Data and Configuration Registers are located in Logical Device 8. Note 5: This pin defaults to its GPIO function. See Configuration Registers. when the chip is in the run state if CR03 Bit[7] = 1. RUN STATE GPIO DATA REGISTER ACCESS The host uses an Index and Data port to access these registers. The Index and Data port powerThe GPIO data registers as well as the Watchdog on default addresses are 0xEA and 0xEB Timer Control, and the Soft Power Enable and respectively. In the configuration state the Index Status registers can be accessed by the host 123 port address may be re-programmed to 0xE0, 0xE2, 0xE4 or 0xEA; the Data port address is automatically set to the Index port address + 1. Upon exiting the configuration state the new Index and Data port addresses are used to access the GPIO data, Soft Power Status and Enable, and the Watchdog Timer Control registers. For example, to access the GP1 data register when in the run state, the host should perform an I/O Write of 0x01 to the Index port address (0xEX) to select GP1 and then read or write the Data port (at Index+1) to access the GP1 register. Generally, to access any GPIO data register GPx the host should perform an I/O Write of 0x0X to the Index port address and then access GPX through the Data port. The Soft Power and Watchdog Timer Control registers are accessed similarly. PORT NAME Index Data TABLE 53 - INDEX AND DATA PORTS PORT ADDRESS RUN STATE ACCESS 0xE0, E2, E4, EA 0x01-0x0F Index address + 1 Access to GP1, Watchdog Timer Control, GP5, GP6, and the Soft Power Status and Enable registers (see TABLE 54). TABLE 54 - RUN STATE ACCESSABLE CONFIGURATION REGISTERS RUN STATE REGISTER 1 ADDRESS (INDEX) REGISTER (CONFIGURATION STATE ADDRESSING ) 0x01 GP1 (L8 - CRF6) 0x03 0x05 0x06 0x08 0x09 0x0A 0x0B Note 1: Watchdog Timer Control (L8 - CRF4) GP5 (L8 - CRF9) GP6 (L8 - CRFA) Soft Power Enable Register 1 (L8-CRB0) Soft Power Enable Register 2 (L8-CRB1) Soft Power Status Register 1 (L8-CRB2) Soft Power Status Register 2 (L8-CRB3) These registers can also be accessed through the configuration registers L8 - CRxx, as shown, when the FDC37B78x is in the configuration state. 125 GPIO CONFIGURATION Each GPIO port has an 8-bit configuration register that controls the behavior of the pin. The GPIO configuration registers are only accessible when the FDC37B78x is in the Configuration state; more information can be found in the Configuration section of this specification. Each GPIO port may be configured as either an input or an output. If the pin is configured as an output, it can be programmed as open-drain or push-pull. Inputs and outputs can be configured as non-inverting or inverting and can be programmed to generate an interrupt. GPIO ports can also be configured as a pre-defined alternate function. Bit[0] of each GPIO Configuration Register determines the port direction, bit[1] determines the signal polarity, bits[4:3] select the port function, bit[5] enables the interrupt, and bit[7] determines the output driver type select. The GPIO configuration register Output Type select bit[7] applies to GPIO functions, the Watchdog Timer WDT, the LED and the nSMI Alternate functions. The basic GPIO configuration options are summarized in TABLE 55. For Alternate functions, the pin direction is set and controlled internally, regardless of the state of the GPIO Direction bit[0]. Also, selected Alternate INPUT functions cannot be inverted, regardless of The state of the GPIO polarity bit[1], except for the EETI function. The interrupt channel for the group Interrupts is selected by the GP_INT[2:1] configuration registers defined in the FDC37B78x Configuration Register Section. The group interrupts are the "ORed" function of the group interrupt enabled GPIO ports and will represent a standard ISA interrupt (edge high). GPIO Group 1 and 2 Interrupts can generate SMI events, wake-up events through the Soft Power Management logic, and SCI/PME events. See the ACPI, PME and SMI section for details. When the group interrupt is enabled on a GPIO input port, the interrupt circuitry contains a selectable digital debounce filter so that switches or push-buttons may be directly connected to the chip. The debounce filters reject signals with pulse widths ≤1ms and are enabled per interrupt group in the GP_INT[2:1] configuration registers. The state of unconnected GPIO alternate input functions is inactive. For example, if bits[4:3] in LD8 -CRCB are not “00”, i.e. nROMCS is not the selected function for GP53, internally the state of nROMCS is inactive, “1”. 126 TABLE 55 - GPIO CONFIGURATION SUMMARY GROUP INT. SELECTED DIRECTION POLARITY ENABLE FUNCTION BIT BIT BIT DESCRIPTION B0 B1 B5 GPIO 0 0 0 Pin is a non-inverted output with the Interrupt disabled. 0 0 1 Pin is a non-inverted output with the Interrupt enabled. 0 1 0 Pin is an inverted output with the Interrupt disabled. 0 1 1 Pin is a inverted output with the Interrupt enabled. 1 0 0 Pin is a non-inverted input with the Interrupt disabled. 1 0 1 Pin is a non-inverted input with the Interrupt enabled. 1 1 0 Pin is an inverted input with the Interrupt disabled. 1 1 1 Pin is a inverted input with the Interrupt enabled. ALT. X1 0 0 Non-inverted alternate function with Interrupt disabled. 0 1 Non-inverted alternate function with Interrupt enabled. 12 0 Alternate OUTPUT functions are inverted, Alternate INPUT functions are non-inverted; Interrupts are disabled. 1 Alternate OUTPUT functions are inverted, Alternate INPUT functions are non-inverted; Interrupts are enabled. Note 1. For alternate function selects, the pin direction is set and controlled internally; i.e., regardless of the state of the GPIO configuration register Direction bit. Note 2. For alternate function selects, INPUT functions cannot be inverted, regardless of the state of the GPIO polarity bit, except for the EETI function. 126 GPIO OPERATION The operation of the GPIO ports is illustrated in FIGURE 3. Note: FIGURE 3 is for illustration purposes only and is not intended to suggest specific implementation details. GPIO Configuration Register bit-1 (Polarity) GPIO Configuration Register bit-0 (Input/Output) SD-bit GPx_nIOW D-TYPE D Q 0 Transparent Q GPx_nIOR D 1 1 0 GPIO PIN GPIO Data Register Bit-n GPIO Configuration Register bit-2 or 5 (GROUP INT. ENABLE) GP Group Interrupts (1 or 2) FIGURE 3 - GPIO FUNCTION ILLUSTRATION 127 When a GPIO port is programmed as an input, reading it through the GPIO data register latches either the inverted or non-inverted logic value present at the GPIO pin. Writing to a GPIO port that is programmed as an input has no effect. When a GPIO port is programmed as an output, the logic value or the inverted logic value that has been written into the GPIO data register is output to the GPIO pin. Reading from a GPIO port that is programmed as an output returns the last value written to the data register. TABLE 56 - GPIO READ/WRITE BEHAVIOR HOST OPERATION READ WRITE GPIO INPUT PORT GPIO OUTPUT PORT LATCHED VALUE OF GPIO PIN LAST WRITE TO GPIO DATA REGISTER NO EFFECT BIT PLACED IN GPIO DATA REGISTER 128 8042 KEYBOARD CONTROLLER DESCRIPTION A Universal Keyboard Controller designed for intelligent keyboard management in desktop computer applications is implemented. The Universal Keyboard Controller uses an 8042 microcontroller CPU core. This section concentrates on the enhancements to the 8042. For general information about the 8042, refer to the "Hardware Description of the 8042" in the 8-Bit Embedded Controller Handbook. 8042A P27 P10 P26 TST0 P23 TST1 P22 P11 LS05 KDAT KCLK MCLK MDAT Keyboard and Mouse Interface KIRQ is the Keyboard IRQ MIRQ is the Mouse IRQ Port 21 is used to create a GATEA20 signal from the FDC37B78x. 130 KEYBOARD ISA INTERFACE The FDC37B78x ISA interface is functionally compatible with the 8042-style host interface. It consists of the D0-7 data bus; the nIOR, nIOW and the Status register, Input Data register, and Output Data register. TABLE 57 shows how the interface decodes the control signals. In addition to the above signals, the host interface includes keyboard and mouse IRQs. TABLE 57 - ISA I/O ADDRESS MAP nIOW nIOR BLOCK FUNCTION (NOTE 1) 0 1 KDATA Keyboard Data Write (C/D=0) 1 0 KDATA Keyboard Data Read 0x64 0 1 KDCTL Keyboard Command Write (C/D=1) 1 0 KDCTL Keyboard Status Read Note 1:These registers consist of three separate 8 bit registers. Status, Data/Command Write and Data Read. ISA ADDRESS 0x60 Keyboard Data Write This is an 8 bit write only register. When written, the C/D status bit of the status register is cleared to zero and the IBF bit is set. Keyboard Data Read This is an 8 bit read only register. If enabled by "ENABLE FLAGS", when read, the KIRQ output is cleared and the OBF flag in the status register is cleared. If not enabled, the KIRQ and/or AUXOBF1 must be cleared in software. Keyboard Command Write This is an 8 bit write only register. When written, the C/D status bit of the status register is set to one and the IBF bit is set. Keyboard Status Read This is an 8 bit read only register. Refer to the description of the Status Register for more information. CPU-to-Host Communication The FDC37B78x CPU can write to the Output Data register via register DBB. A write to this register automatically sets Bit 0 (OBF) in the Status register. See Table 58. Table 58 - Host Interface Flags FLAG Set OBF, and, if enabled, the KIRQ output signal goes high 8042 INSTRUCTION OUT DBB 130 Host-to-CPU Communication The host system can send both commands and data to the Input Data register. The CPU differentiates between commands and data by reading the value of Bit 3 of the Status register. When bit 3 is "1", the CPU interprets the register contents as a command. When bit 3 is "0", the CPU interprets the register contents as data. During a host write operation, bit 3 is set to "1" if SA2 = 1 or reset to "0" if SA2 = 0. KIRQ If "EN FLAGS" has been executed and P24 is set to a one: the OBF flag is gated onto KIRQ. The KIRQ signal can be connected to system interrupt to signify that the FDC37B78x CPU has written to the output data register via "OUT DBB,A". If P24 is set to a zero, KIRQ is forced low. On power-up, after a valid RST pulse has been delivered to the device, KIRQ is reset to 0. KIRQ will normally reflects the status of writes "DBB". (KIRQ is normally selected as IRQ1 for keyboard support.) If "EN FLAGS” has not been executed: KIRQ can be controlled by writing to P24. Writing a zero to P24 forces KIRQ low; a high forces KIRQ high. MIRQ If "EN FLAGS" has been executed and P25 is set to a one:; IBF is inverted and gated onto MIRQ. The MIRQ signal can be connected to system interrupt to signify that the FDC37B78x CPU has read the DBB register. If "EN FLAGS” has not been executed, MIRQ is controlled by P25, Writing a zero to P25 forces MIRQ low, a high forces MIRQ high. (MIRQ is normally selected as IRQ12 for mouse support). Gate A20 A general purpose P21 is used as a software controlled Gate A20 or user defined output. EXTERNAL INTERFACE KEYBOARD AND MOUSE PS/2 mouse products that employ the same type of interface. To facilitate system expansion, the FDC37B78x provides four signal pins that may be used to implement this interface directly for an external keyboard and mouse. The FDC37B78x has four high-drive, open-drain output, bidirectional port pins that can be used for external serial interfaces, such as ISA external keyboard and PS/2-type mouse interfaces. They are KCLK, KDAT, MCLK, and MDAT. P26 is inverted and output as KCLK. The KCLK pin is connected to TEST0. P27 is inverted and output as KDAT. The KDAT pin is connected to P10. P23 is inverted and output as MCLK. The MCLK pin is connected to TEST1. P22 is inverted and output as MDAT. The MDAT pin is connected to P11. NOTE: External pull-ups may be required. KEYBOARD POWER MANAGEMENT The keyboard provides support for two powersaving modes: soft powerdown mode and hard powerdown mode. In soft powerdown mode, the clock to the ALU is stopped but the timer/counter and interrupts are still active. In hard power down mode the clock to the 8042 is stopped. Soft Power Down Mode This mode is entered by executing a HALT instruction. The execution of program code is halted until either RESET is driven active or a data byte is written to the DBBIN register by a master CPU. If this mode is exited using the interrupt, and the IBF interrupt is enabled, then program execution resumes with a CALL to the interrupt routine, otherwise the next instruction is executed. If it is exited using RESET then a normal reset sequence is initiated and program execution starts from program memory location 0. Hard Power Down Mode Hard Power Down Mode is entered by executing a STOP instruction. Disabling the oscillator driver cell stops the oscillator. When either RESET is driven active or a data byte is written to the DBBIN register by a master CPU, this mode will be exited Industry-standard PC-AT-compatible keyboards employ a two-wire, bidirectional TTL interface for data transmission. Several sources also supply 131 (as above). However, as the oscillator cell will require an initialization time, either RESET must be held active for sufficient time to allow the oscillator to stabilize. Program execution will resume as above. INTERRUPTS The FDC37B78x provides the two 8042 interrupts, the IBF and the Timer/Counter Overflow. MEMORY CONFIGURATIONS The FDC37B78x provides 2K of on-chip ROM and 256 bytes of on-chip RAM. Register Definitions Host I/F Data Register The Input Data and Output Data registers are each 8 bits wide. A write to this 8 bit register will load the Keyboard Data Read Buffer, set the OBF flag and set the KIRQ output if enabled. A read of this register will read the data from the Keyboard Data or Command Write Buffer and clear the IBF flag. Refer to the KIRQ and Status register descriptions for more information. Host I/F Status Register The Status register is 8 bits wide. TABLE 59 shows the contents of the Status register. D7 UD D6 UD D5 UD TABLE 59 - STATUS REGISTER D4 D3 D2 UD C/D UD D1 IBF D0 OBF 132 Status Register This register is cleared on a reset. This register is read-only for the Host and read/write by the FDC37B78x CPU. UDWritable by FDC37B78x CPU. These bits are user-definable. C/D(Command Data)-This bit specifies whether the input data register contains data or a command (0 = data, 1 = command). During a host data/command write operation, this bit is set to "1" if SA2 = 1 or reset to "0" if SA2 = 0. IBF(Input Buffer Full)- This flag is set to 1 whenever the host system writes data into the input data register. Setting this flag activates the FDC37B78x CPU's nIBF (MIRQ) interrupt if enabled. When the FDC37B78x CPU reads the input data register (DBB), this bit is automatically reset and the interrupt is cleared. There is no output pin associated with this internal signal. OBF(Output Buffer Full) - This flag is set to whenever the FDC37B78x CPU write to the output data register (DBB). When the host system reads the output data register, this bit is automatically reset. EXTERNAL CLOCK SIGNAL The FDC37B78x Keyboard Controller clock source is a 12 MHz clock generated from a 14.318 MHz clock. The reset pulse must last for at least 24 16 MHz clock periods. The pulse-width requirement applies to both internally (Vcc POR) and externally generated reset signals. In powerdown mode, the external clock signal is not loaded by the chip. DEFAULT RESET CONDITIONS The FDC37B78x has one source of reset: an external reset via the RESET_DRV pin. Refer to TABLE 60 for the effect of each type of reset on the internal registers. TABLE 60 - RESETS DESCRIPTION HARDWARE RESET (RESET) KCLK Input KDAT Input MCLK Input MDAT Input Host I/F Data Reg N/A Host I/F Status Reg 00H N/A: Not Applicable 133 GATEA20 AND KEYBOARD RESET The FDC37B78x provides two options for GateA20 and Keyboard Reset: 8042 Software Generated GateA20 and KRESET and Port 92 Fast GateA20 and KRESET. PORT 92 FAST GATEA20 AND KEYBOARD RESET Port 92 Register This port can only be read or written if Port 92 has been enabled via bit 2 of the KRST_GA20 Register (Logical Device 7, 0xF0) set to 1. This register is used to support the alternate reset (nALT_RST) and alternate A20 (ALT_A20) functions. Name Location Default Value Attribute Size Port 92 92h 24h Read/Write 8 bits Bit 7:6 5 4 3 2 1 0 Port 92 Register Function Reserved. Returns 00 when read Reserved. Returns a 1 when read Reserved. Returns a 0 when read Reserved. Returns a 0 when read Reserved. Returns a 1 when read ALT_A20 Signal control. Writing a 0 to this bit causes the ALT_A20 signal to be driven low. Writing a 1 to this bit causes the ALT_A20 signal to be driven high. Alternate System Reset. This read/write bit provides an alternate system reset function. This function provides an alternate means to reset the system CPU to effect a mode switch from Protected Virtual Address Mode to the Real Address Mode. This provides a faster means of reset than is provided by the Keyboard controller. This bit is set to a 0 by a system reset. Writing a 1 to this bit will cause the nALT_RST signal to pulse active (low) for a minimum of 1 µs after a delay of 500 ns. Before another nALT_RST pulse can be generated, this bit must be written back to a 0. 134 nGATEA20 8042 P21 0 0 1 1 ALT_A20 0 1 0 1 System nA20M 0 1 1 1 Bit 0 of Port 92, which generates the nALT_RST signal, is used to reset the CPU under program control. This signal is AND’ed together externally with the reset signal (nKBDRST) from the keyboard controller to provide a software means of resetting the CPU. This provides a faster means of reset than is provided by the keyboard controller. Writing a 1 to bit 0 in the Port 92 Register causes this signal to pulse low for a minimum of 6µs, after a delay of a minimum of 14µs. Before another nALT_RST pulse can be generated, bit 0 must be set to 0 either by a system reset of a write to Port 92. Upon reset, this signal is driven inactive high (bit 0 in the Port 92 Register is set to 0). If Port 92 is enabled, i.e., bit 2 of KRST_GA20 is set to 1, then a pulse is generated by writing a 1 to bit 0 of the Port 92 Register and this pulse is AND’ed with the pulse generated from the 8042. This pulse is output on pin KRESET and its polarity is controlled by the GPI/O polarity configuration. 135 14us ~ ~ 6us 8042 P20 KRST KBDRST P92 KRST_GA20 Bit 2 nALT_RST Bit 0 Pulse Gen 14us Note: When Port 92 is disabled, writes are ignored and reads return undefined values. KRESET Generation Bit 1 of Port 92, the ALT_A20 signal, is used to force nA20M to the CPU low for support of real mode compatible software. This signal is externally OR’ed with the A20GATE signal from the keyboard controller and CPURST to control the nA20M input of the CPU. Writing a 0 to bit 1 of the Port 92 Register forces ALT_A20 low. ALT_A20 low drives nA20M to the CPU low, if A20GATE from the keyboard controller is also low. Writing a 1 to bit 1 of the Port 92 Register forces ALT_A20 high. ALT_A20 high drives nA20M to the CPU high, regardless of the state of A20GATE from the keyboard controller. Upon reset, this signal is driven low. 8042 P17 Functions 8042 function P17 is implemented as in a true 8042 part. Reference the 8042 spec for all timing. A port signal of 0 drives the output to 0. A port signal of 1 causes the port enable signal to drive the output to 1 within 20-30nsec. After several (# TBD) clocks, the port enable goes away and the internal 90µA pull-up maintains the output signal as 1. In 8042 mode, the pins can be programmed as open drain. When programmed in open drain mode, the port enables do not come into play. If the port signal is 0 the output will be 0. If the port signal is 1, the output tristates: an external pull-up can pull the pin high, and the pin can be shared i.e., P17 and nSMI can be externally tied together. In 8042 mode, the pins cannot be programmed as input nor inverted through the GP configuration registers. ~ ~ 6us 136 0ns 250ns 500ns CLK AEN nAEN 64=I/O Addr n64 nIOW nA DD1 nDD1 nCNTL nIOW' nIOW+n64 AfterD1 nAfterD1 60=I/O Addr n60 nIOW+n60=B nAfterD1+B D[1] GA20 Gate A20 Turn-On Sequence Timing When writing to the command and data port with hardware speedup, the IOW timing shown in the figure titled “IOW Timing for Port 92” in the Timing Diagrams Section is used. This setup time is only required to be met when using hardware speedup; the data must be valid a minimum of 0 nsec from the leading edge of the write and held throughout the entire write cycle. 112 RTC INTERFACE The ISA interface is functionally compatible with the 8042-style host interface. It consists of the D07 data bus, the nIOR, nIOW and the Status register, Input Data register, and Output Data register. Table 61 shows how the interface decodes the control signals. In addition to the above signals, the host interface includes keyboard and mouse IRQs. Table 61 - ISA I/O Address Map Addresses 0x60, 0x64, 0x70 and 0x71 are qualified by AEN ISA ADDRESS* BLOCK FUNCTION 0x70 (R/W) RTC Address Register 0x71 (R/W) RTC Data Register Base* RTC Bank 1 Address Register Base* + 1 RTC Bank 1 Data Register *Bank 0 is at 70h. Bank 1 is relocatable via the RTC Mode Register and the Secondary Base Address for RTC Bank 1 (CR62 and CR63). See Configuration section. RTC Address Register Writing to this register sets the CMOS address that will be read or written. RTC Data Register A read of this register will read the contents of the selected CMOS register. A write to this register will write to the selected CMOS register. REAL TIME CLOCK The Real Time Clock is a complete time of day clock with a day of month alarm, calendar (up to the year 9999), a programmable periodic interrupt, and a programmable square wave generator. Features Counts seconds, minutes, and hours of the day. Counts days of the week, date, month, year and century. Day of Month Wake-Up Alarm Binary or BCD representation of time, calendar and alarms. Three interrupts - each is separately software maskable. (No daylight savings time) 256 Bytes of CMOS RAM. Port Definition and Description OSCILLATOR Crystal Oscillator input. A 32.768 kHz crystal connected externally on the XTAL1 and XTAL2 pins generates the 32.768 kHz RTC input clock. Maximum clock frequency is 32.768 KHz. RTC Reset The clock, calendar, or RAM functions are not affected by the system reset (RESET_DRV active). When the RESET_DRV pin is active (i.e., system reset) and the battery voltage is above 1 volt nominal, the following occurs: 1) 2) 3) 4) 5) 6) 7) 8) 9) Periodic Interrupt Enable (PIE) is cleared to 0. Alarm Interrupt Enable (AIE) bit is cleared to 0. Update Ended Interrupt Enable (UIE) bit is cleared to 0. Update Ended Interrupt Flag (UF) bit is cleared to 0. Interrupt Request Status Flag (IRQF) bit is cleared to 0. Periodic Interrupt Flag (PIF) is cleared to 0. The RTC and CMOS registers are not accessible. Alarm Interrupt Flag (AF) is cleared to 0. nIRQ pin is in high impedance state. When RESET_DRV is active and the battery voltage is below 1-volt nominal, the following occurs: 138 1. 2. Registers 00-0D are initialized to 00h. Access to all registers from the host are blocked. RTC Interrupt The interrupt generated by the RTC is an active high output. The RTC interrupt output remains high as long as the status bit causing the interrupt is present and the corresponding interrupt-enable bit is set. Activating RESET_DRV or reading register C clears the RTC interrupt. The RTC Interrupt is brought out by programming the RTC Primary Interrupt Select to a non-zero value. If IRQ 8 is selected then the polarity of this IRQ 8 output is programmable through a bit in the OSC Global Configuration Register. Internal Registers Table 62 shows the address map for bank 0 of the RTC; time, calendar, alarm, control, status bytes and 114 bytes of "CMOS" registers. ADDRESS 0 1 2 3 4 5 6 7 8 9 A B C D 0E-7Ch 7Dh 7Eh 7Fh Table 62 - Real Time Clock Address Map, Bank 0 REGISTER TYPE REGISTER FUNCTION R/W Register 0: Seconds R/W Register 1: Seconds Alarm R/W Register 2: Minutes R/W Register 3: Minutes Alarm R/W Register 4: Hours R/W Register 5: Hours Alarm R/W Register 6: Day of Week R/W Register 7: Date of Month R/W Register 8: Month R/W Register 9: Year R/W Register A: R/W Register B: (Bit 0 is Read Only) R Register C: R/W Register D:VRT and Day of Month Alarm R/W Register E-7C: General Purpose R/W Register 7D: Century Byte R/W Register 7E: Control Register 1 R/W Register 7F:General Purpose All 14 bytes are directly writable and readable by the host with the following exceptions: a. b. c. Register C is read only Bit 7 of Register A and Bit 7 of Register D are read only Bit 0 of Register B is read only 139 Table 63 shows Bank 1, the second bank of CMOS registers which contains an additional 128 bytes of general purpose CMOS registers. All 128 bytes are directly writeable and readable by the host. ADDRESS 0-7F Table 63 - Real Time Clock Address Map, Bank 1 REGISTER TYPE REGISTER FUNCTION R/W Register 0-7F: General Purpose Note: CMOS Bank 1 is relocatable via the RTC Mode Register and the Secondary Base Address (CR62 and CR63). See Configuration Section. Time, Calendar and Alarm The processor program obtains time and calendar information by reading the appropriate locations. The program may initialize the time, calendar and alarm by writing to these locations. The contents of the time, calendar, century and alarm bytes can be in binary or BCD as shown in Table 64. Before initializing the internal registers, the SET bit in Register B should be set to a "1" to prevent time/calendar updates from occurring. The program initializes the ten locations in the binary or BCD format as defined by the DM bit in Register B. The SET bit may now be cleared to allow updates. The 12/24 bit in Register B establishes whether the hour locations represent 1 to 12 or 0 to 23. The 12/24 bit cannot be changed without reinitializing the hour locations. When the 12 hour format is selected, the high order bit of the hours byte represents PM when it is a "1". Once per second, the time, calendar and alarm bytes, as well as the century byte switched to the update logic to be advanced by one second and to check for an alarm condition. If any of these bytes are read at this time, the data outputs are undefined. The update cycle time is shown in Table 65. The update logic contains circuitry for automatic end-of-month recognition as well as automatic leap year compensation. An alarm can be generated for day of month, day, hour, minute, or seconds. The alarm may be used in two ways. First, when the program inserts an alarm time in the appropriate date, hours, minutes and seconds alarm locations, the alarm interrupt is initiated at the specified time each day if the alarm enable bit is high. The second usage is to insert a "don't care" state in one or more of three alarm bytes. The "don't care" code is any hexadecimal byte from C0 to FF inclusive. That is the two most significant bits of each byte, when set to "1", create a "don't care" situation. An alarm interrupt each hour is created with a "don't care" code in the hours and date alarm location. Similarly, an alarm is generated every minute with "don't care" codes in the hours, date and minutes alarm bytes. The "don't care" codes in all three alarm bytes create an interrupt every second. 140 ADD 0h 1h 2h 3h 4h 5h 6h 7h 8h 9h Dh 7Dh 7Eh Table 64 - Time, Calendar and Alarm Bytes REGISTER FUNCTION BCD RANGE Register 0: Seconds 00-59 Register 1: Seconds Alarm 00-59 Register 2: Minutes 00-59 Register 3: Minutes Alarm 00-59 Register 4: Hours 01-12 am (12 hour mode) 81-92 pm (24 hour mode) 00-23 Register 5: Hours Alarm 01-12 am (12 hour mode) 81-92 pm (24 hour mode) 00-23 Register 6: Day of Week 01-07 Register 7: Day of Month 01-31 Register 8: Month 01-12 Register 9: Year 00-99 Date of Month Alarm 1-31 Century Byte 00-99 Control Register 1 Update Cycle BINARY RANGE 00-3B 00-3B 00-3B 00-3B 01-0C 81-8C 00-17 01-0C 81-8C 00-17 01-07 01-1F 01-0C 00-63 01-1F 00-63 Wake-up Alarm Function The Alarm can be used as a wake-up alarm to turn on power to the system when the system is powered off. There are two bits used to control alarm. The Alarm wake-up function is enabled via the Alarm Enable bit, AIE. The Alarm Remember Enable bit, AL_REM_EN, in the RTC Control Register 1, is used to power-up the system upon return of power if the Alarm time has passed during loss of power. These bits function as follows: If VTR is present: AIE controls whether or not the alarm is enabled as a wake-up function. If AIE is set and VTR=5V, the nPowerOn pin will go active (low) when the date/time is equal to the alarm date/time and the power supply will turn on the machine. If VTR is not present: AL_REM_EN controls whether or not the alarm will power-up the system upon the return of VTR, regardless of the value of AIE. If AL_REM_EN is set and VTR=0 at the date/time that alarm 2 is set for, the nPowerOn pin will go active (low) as soon as VTR comes back and the machine will power-up. An update cycle is executed once per second if the SET bit in Register B is clear and the DV0-DV2 divider is not clear. The SET bit in the "1" state permits the program to initialize the time and calendar bytes by stopping an existing update and preventing a new one from occurring. The primary function of the update cycle is to increment the seconds’ byte, check for overflow, and increment the minute’s byte when appropriate and so forth through to the year of the century byte. The update cycle also compares each alarm byte with the corresponding time byte and issues an alarm if a match or if a "don't care" code is present. The length of an update cycle is shown in Table 65. During the update cycle, the time, calendar and alarm bytes are not accessible by the processor program. If the processor reads these locations before the update cycle is complete, the output will be undefined. The UIP (update in progress) status bit is set during the interval. When the UIP bit goes high, the update cycle will begin 244 μs later. Therefore, if a low is read on the UIP bit, the user has at least 244 μs before time/calendar data will be changed. 141 Table 65 - Update Cycle Time INPUT CLOCK FREQUENCY 32.768 kHz 32.768 kHz UIP BIT 1 0 UPDATE CYCLE TIME 1948 μs MINIMUM TIME UPDATE CYCLE 244 μs CONTROL AND STATUS REGISTERS, BANK 0 Bank 0 of the RTC has five registers that are accessible to the processor program at all times REGISTER A (AH) MSB b7 UIP when Bank 0 is enabled, even during the update cycle. Note Register D, Bits[6:0] are not accessible during an update cycle. b6 DV2 b5 DV1 b4 DV0 b3 RS3 b2 RS2 b1 RS1 LSB b0 RS0 UIP The update in progress bit is a status flag that may be monitored by the program. When UIP is a "1" the update cycle is in progress or will soon begin. When UIP is a "0" the update cycle is not in progress and will not be for at least 244 μs. The time, calendar, and alarm information is fully available to the program when the UIP bit is zero. The UIP bit is a read- only bit and is not affected by RESET_DRV. Writing the SET bit in Register B to a "1" inhibits any update cycle and then clears the UIP status bit. The UIP bit is only valid when the RTC is enabled. Refer to Table 66. DV2-0 Three bits are used to permit the program to select various conditions of the 22-stage divider chain. Table 66 shows the allowable combinations. The divider selection bits are also used to reset the divider chain. When the time/calendar is first initialized, the program may start the divider chain at the precise time stored in the registers. When the divider reset is removed the first update begins one-half second later. These three read/write bits are not affected by RESET_DRV. RS3-0 The four rate selection bits select one of 15 taps on the divider chain or disable the divider output. The selected tap determines rate or frequency of the periodic interrupt. The program may enable or disable the interrupt with the PIE bit in Register B. Table 67 lists the periodic interrupt rates and equivalent output frequencies that may be chosen with the RS0-RS3 bits. These four bits are read/write bits, which are not affected by RESET_DRV. 111 OSCILLATOR FREQUENCY 32.768 KHz 32.768 KHz 32.768 KHz 32.768 KHz 32.768 KHz Table 66 - Divider Selection Bits REGISTER A BITS DV2 DV1 DV0 MODE Reset Divider 0 0 0 Reset Divider 1 0 0 Normal Operate 0 1 0 Test 1 1 0 Test X 0 1 Reset Divider X 1 1 RATE SELECT RS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 RS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 RS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Table 67 - Periodic Interrupt Rates 32.768 KHz TIME BASE PERIOD RATE OF FREQUENCY OF RS0 INTERRUPT INTERRUPT 0 0.0 1 3.90625 ms 256 Hz 0 7.8125 ms 128 Hz 1 8.192 KHz 122.070 μs 0 4.096 KHz 244.141 μs 1 2.048 KHz 488.281 μs 0 1.024 KHz 976.562 μs 1 1.953125 ms 512 Hz 0 3.90625 ms 256 Hz 1 7.8125 ms 128 Hz 0 15.625 ms 64 Hz 1 31.25 ms 32 Hz 0 62.5 ms 16 Hz 1 125 ms 8 Hz 0 250 ms 4 Hz 1 500 ms 2 Hz REGISTER B (BH) MSB b7 b6 SET PIE SET b5 AIE b4 UIE b3 RES b2 DM2 b1 24/12 LSB b0 DSE When the SET bit is a "0", the update functions normally by advancing the counts once per second. When the SET bit is a "1", an update PIE The periodic interrupt enable bit is a read/write bit which allows the periodic-interrupt flag (PF) bit in Register C to cause the IRQB port to be driven cycle in progress is aborted and the program may initialize the time and calendar bytes without an update occurring in the middle of initialization. SET is a read/write bit which is not modified by RESET_DRV or any internal functions. low. The program writes a "1" to the PIE bit in order to receive periodic interrupts at the rate specified by the RS3-RS0 bits in Register A. A zero in PIE blocks IRQB from being initiated by a 143 periodic interrupt, but the periodic flag (PF) is still set at the periodic rate. PIE is not modified by any internal function, but is cleared to "0" by a RESET_DRV. AIE The alarm interrupt enable bit is a read/write bit, which when set to a "1" permits the alarm flag (AF) bit in Register C to assert IRQB. An alarm interrupt occurs for each second that the three time Bytes equal the three alarm bytes (including a "don't care" alarm code of binary 11XXXXXX). When the AIE bit is a "0", the AF bit does not initiate an IRQB signal. The RESET_DRV port clears AIE to "0". The AIE bit is not affected by any internal functions. UIE The update-ended interrupt enable bit is a read/write bit which enables the update-end flag (UF) bit in Register C to assert IRQB. The RESET_DRV port or the SET bit going high clears the UIE bit. RES Reserved - read as “0”. DM The data mode bit indicates whether time and calendar updates are to use binary or BCD formats. The DM bit is written by the processor program and may be read by the program, but is not modified by any internal functions or by RESET_DRV. A "1" in DM signifies binary data, while a "0" in DM specifies BCD data. 24/12 The 24/12 control bit establishes the format of the hours byte as either the 24 hour mode if set to a "1", or the 12 hour mode if cleared to a "0". This is a read/write bit which is not affected by RESET_DRV or any internal function. DSE The daylight savings enable bit is read only and is always set to a "0" to indicate that the daylight savings time option is not available. REGISTER C (CH) - READ ONLY REGISTER MSB b7 IRQF LSB b0 0 b6 PF b5 AF b4 UF b3 0 b2 0 b1 0 IRQF The interrupt request flag is set to a "1" when one or more of the following are true: PF = PIE = 1 AF = AIE = 1 UF = UIE = 1 Any time the IRQF bit is a "1", the IRQB signal is driven low. All flag bits are cleared after Register C is read or by the RESET_DRV port. PF The periodic interrupt flag is a read-only bit which is set to a "1" when a particular edge is detected on the selected tap of the divider chain. The RS3-RS0 bits establish the periodic rate. PF is set to a "1" independent of the state of the PIE bit. PF being a "1" sets the IRQF bit and initiates an IRQB signal when PIE is also a "1". The PF bit is cleared by RESET_DRV or by a read of Register C. AF The alarm interrupt flag when set to a "1" indicates that the current time has matched the alarm time. A "1" in AF causes a "1" to appear in IRQF and the IRQB port to go low when the AIE bit is also a "1". A RESET_DRV or a read of Register C clears the AF bit. 145 UF b3-0 The update-ended interrupt flag bit is set after each update cycle. When the UIE bit is also a "1", the "1" in UF causes the IRQF bit to be set and asserts IRQB. A RESET_DRV or a read of Register C causes UF to be cleared. The unused bits of Register C are read as zeros and cannot be written. REGISTER D (DH) - BITS[7,6] ARE READ-ONLY, BITS[5:0] ARE READ/WRITE MSB b7 VRT VRT When a "1", this bit indicates that the contents of the RTC are valid. A "0" appears in the VRT bit when the battery voltage is low. The VRT bit is a read-only bit, which can only be set by a read of Register D. Refer to Power Management for the conditions when this bit is reset. The processor program can set the VRT bit when the time and calendar are initialized to indicate that the time is valid. b6 REGISTER 7E (7Eh) CONTROL REGISTER 1 Read as zero and cannot be written. Default is 0; cleared upon Vbat POR. This register is battery backed-up. D7 XTAL_ CAP D6 0 D5 0 D4 0 D3 0 D2 VTR_POR _EN D1 VTR_POR _OFF D0 AL_REM_ EN b6 0 b5 b4 b3 b2 Date Alarm b5:b0 Date Alarm; These bits store the date of month alarm value. If set to 000000b, then a don’t care state is assumed. The host must configure the date alarm for these bits to do anything, yet they can be written at any time. If the date alarm is not enabled, these bits will return zeros. These bits are not affected by RESET_DRV. Note: Bits[6:0] are not accessible during an update cycle. b1 LSB b0 145 BIT 0 - AL_REM_EN One of the two control bits for the alarm wakeup function; it is the “remember” enable bit for the second alarm. This bit, if set to 1, wil cause the system to power-up upon return of power if the alarm 2 time has passed during loss of power. It is only applicable when VTR=0. This bit is independent of the other control bit for the alarm wake-up function, AlE. If AL_REM_EN is set and VTR=0 at the date/time that the alarm is set for, the nPowerOn pin will go active (low) and the machine will power-up as soon as VTR comes back. Bit 1 – VTR_POR_OFF If VTR_POR_OFF is set, the nPowerOn pin will go inactive (float) and the main power (Vcc) will remain off when the VTR POR occurs. The software must not set VTR_POR_OFF and VTR_POR_EN at the same time. BIT 2 - VTR_POR_EN The enable bit for VTR POR. If VTR_POR_EN is set, the nPowerOn pin will go active (low) and the machine will power-up as soon as a VTR POR occurs. The software must not set VTR_POR_OFF and VTR_POR_EN at the same time. Bits 3:6 - Reserved Read as zero, ignore writes Bit 7 - XTAL_CAP This bit is used to specify the 32Khz XTAL load capacitance (12pF vs. 6pF): 0=12pF, 1=6pF. Registers 0Eh-7Ch, 7Fh in Bank 0 and 00h-7Fh in Bank 1: General Purpose Registers 0Eh-7Ch, 7Fh in Bank 0 and 00h-7Fh in Bank 1 are general purpose CMOS registers. These registers can be used by the host and are fully available during the time update cycle. The contents of these registers are preserved by the battery power. Interrupts The RTC includes three separate fully- automatic sources of interrupts to the processor. The alarm interrupt may be programmed to occur at rates from one-per-second to one-a-day. The periodic interrupt may be selected for rates from half-a-second to 122.070 μs. The update ended interrupt may be used to indicate to the program that an update cycle is completed. Each of these independent interrupts are described in greater detail in other sections. The processor program selects which interrupts, if any, it wishes to receive by writing a "1" to the appropriate enable bits in Register B. A "0" in an enable bit prohibits the IRQB port from being asserted due to that interrupt cause. When an interrupt event occurs a flag bit is set to a "1" in Register C. Each of the three interrupt sources have separate flag bits in Register C, which are set independent of the state of the corresponding enable bits in Register B. The flag bits may be used with or without enabling the corresponding enable bits. The flag bits in Register C are cleared (record of the interrupt event is erased) when Register C is read. Double latching is included in Register C to ensure the bits that are set are stable throughout the read cycle. All bits which are high when read by the program are cleared, and new interrupts are held until after the read cycle. If an interrupt flag is already set when the interrupt becomes enabled, the IRQB port is immediately activated, though the interrupt initiating the event may have occurred much earlier. When an interrupt flag bit is set and the corresponding interrupt-enable bit is also set, the IRQB port is driven low. IRQB is asserted as long as at least one of the three interrupt sources has its flag and enable bits both set. The IRQF bit in Register C is a "1" whenever the IRQB port is being driven low. Frequency Divider The RTC has 22 binary divider stages following the clock input. The output of the divider is a 1 Hz signal to the update-cycle logic. The divider is controlled by the three divider bits (DV3-DV0) in Register A. As shown in Table 146 66 the divider control bits can select the operating mode, or be used to hold the divider chain reset which allows precision setting of the time. When the divider chain is changed from reset to the operating mode, the first update cycle is one-half second later. The divider control bits are also used to facilitate testing of the RTC. Periodic Interrupt Selection The periodic interrupt allows the IRQB port to be triggered from once every 500 ms to once every 122.07 μs. As Table 67 shows, the periodic interrupt is selected with the RS0-RS3 bits in Register A. The periodic interrupt is enabled with the PIE bit in Register B. 147 SOFT POWER MANAGEMENT This chip employs soft power management to allow the chip to enter low power mode and to provide a variety of wakeup events to power up the chip. This technique allows for software control over powerdown and wakeup events. In low power mode, the chip runs off of the trickle voltage, VTR. In this mode, the chip is ready to power up from either the power button or from one of a number of wakeup events including pressing a key, touching the mouse or receiving data from one of the UARTs. The alarm can also be set to power up the system at a predetermined time to perform one or more tasks. The implementation of Soft Power Management is illustrated in Figure 11. A high to low transition on the Button input or on any of the enabled wakeup events (SPx) causes the nPowerOn output to go active low which turns on the main power supply. Even if the power supply is completely lost (i.e., VTR is not present) the power supply can still be turned on upon the return of VTR. This is accomplised by an alarm event that has already passed (if the alarm remember bit is enabled) or by a VTR power on reset (if the VTR POR bit is enabled). These bits are described in the RTC section. The chip can also be programmed to always stay off when the AC power returns. (See VTR_POR_OFF in the RTC section.) The Button input can be used to turn off the power supply after a debounce delay. The power supply can also be turned off under software control (via a write to register WDT_CTRL with bit 7 set). Configuration registers L8-CR_B0 and L8CR_B1 select the wakes-up events (SPx). The Configuration registers L8-CR_B2 and L8CR_B3 indict the wake-up event status. The possible wake-events are: • • • • • • • • • • UART1 and UART 2 Ring Indicator Pin Keyboard and Mouse clock Pin Group Interrupt 1, Group Interrupt 2 IRRX2 input pin RTC Alarm UART 1 and UART 2 Receive Data Pin nRING pin Consumer IR (CIR) Power Button input pin VTR_POR 148 FIGURE 3 - SOFT POWER MANAGEMENT FUNCTIONAL DIAGRAM nBINT OFF_EN OFF_DLY Delay2 Logic nSPOFF VTR_POR_EN VTR POR AL_REM_EN ED; PG Alarm Delay1 VTR ED; L EN1 nSPOFF1 VTR_POR_OFF VTR POR VBAT POR Soft Power Off nSPOFF1 VTR POR With Vbat+Dh PME_EN 1 8 < PM1_BLK>+Eh PME_EN 2 8 < PM1_BLK>+Fh PME_STS 8 < PM1_BLK>+10h PME_EN 8 < PM1_BLK>+11h SMI_STS 1 8 < PM1_BLK>+12h SMI_STS 2 8 < PM1_BLK>+13h SMI_EN 1 8 < PM1_BLK>+14h SMI_EN 2 8 < PM1_BLK>+15h MSC_STS 8 < PM1_BLK>+16h Reserved 8 < PM1_BLK>+17h TABLE 70 shows the block size and range of base addresses for each block. TABLE 70 - REGISTER BLOCK ATTRIBUTES Block Name Block Size Base Address Range PM1_BLK 24-bytes 0-FFF 156 ACPI REGISTERS In the FDC37B78x, the PME wakeup events can be enabled as SCI events through the SCI_STS1 and SCI_EN1 bits in the GPE status and enable registers. See PME Interface and SMI/PME/SCI logic sections. Power Management 1 Status Register 1 (PM1_STS 1) Register Location: System I/O Space Default Value: 00h on Vbat POR Attribute: Read/Write (Note 0) Size: 8-bits BIT NAME DESCRIPTION 0-7 Reserved Reserved. These bits always return a value of zero. Note 0: All bits described as "reserved" in writeable registers must be written with the value 0 when the register is written. Note 1: This bit is set by hardware and can only be cleared by software writing a one to this bit position and by Vbat POR. Writing a 0 has no effect. Power Management 1 Status Register 2 (PM1_STS 2) Register Location: +1h System I/O Space Default Value: 00h on Vbat POR Attribute: Read/Write (Note 0) Size: 8-bits BIT 0 NAME PWRBTN_STS DESCRIPTION This bit is set when the Button_In signal is asserted. In the system working state, while PWRBTN_EN and PWRBTN_STS are both set an SCI interrupt event is raised. In the sleeping or soft off state, a wake-up event is generated (regardless of the setting of PWRBTN_EN) (Note 2). This bit is only set by hardware and is reset by software writing a one to this bit position, and by Vbat POR. Writing a 0 has no effect. It is also reset as follows: If PWRBTNOR_EN is set, and if the Button_In signal is held asserted for more than four seconds, then this bit is cleared, the PWRBTNOR_STS bit is set and the system will transition into the soft off state (nPowerOn floats). Reserved. This bit is set when the RTC generates an alarm. Additionally if the RTC_EN bit is set then the setting of the RTC_STS bit will generate an SCI. When the AL_REM_EN bit is set in the RTC control register 1, then the RTC_STS bit is set due to an RTC alarm event occurring when Vtr is not present. This will indicate to the OS the cause of the wakeup event (nPowerOn pin asserted when Vtr returns) caused by the “alarm remember” logic in the Soft Power Management block. (Note 1) This bit is set when the power switch over-ride function is set: If PWRBTNOR_EN is set, and if the Button_In signal is held asserted for more than four seconds. Hardware is also required to reset the PWRBTN_STS when issuing a power switch over-ride function. 1 2 Reserved RTC_STS 3 PWRBTNOR_STS 157 DESCRIPTION (Note 1) 4-6 Reserved Reserved. These bits always return a value of zero. 7 WAK_STS This bit is set when the system is in the sleeping state and an enabled wakeup event occurs. This bit is set on the high-to-low transition of nPowerOn, if the WAK_CTRL bit in the sleep / wake configuration register (0xF0 in Logical Device A) is cleared. If the WAK_CTRL bit is set, then any enabled wakeup event will also set the WAK_STS bit in addition to the high-to-low transition of nPowerOn. It is cleared by writing a 1 to its bit location when nPowerOn is active (low). Upon setting this bit, the system will transition to the working state. (Note 1) Note 1: This bit is set by hardware and can only be cleared by software writing a one to this bit position and by Vbat POR. Writing a 0 has no effect. Note 2: In the present implementation of Button_In, pressing the button will always wake the machine (i.e., activate nPowerOn). Power Management 1 Enable Register 1 (PM1_EN 1) Register Location: +2 System I/O Space Default Value: 00h on Vbat POR Attribute: Read/Write (Note 0) Size: 8-bits BIT 0-7 NAME Reserved DESCRIPTION Reserved. These bits always return a value of zero. BIT NAME Power Management 1 Enable Register 2 (PM1_EN 2) Register Location: +3 System I/O Space Default Value: 00h on Vbat POR Attribute: Read/Write (Note 0) Size: 8-bits DESCRIPTION This bit is used to enable the assertion of the Button_In to generate an SCI event. The PWRBTN_STS bit is set anytime the Button_In signal is asserted. The enable bit does not have to be set to enable the setting of the PWRBTN_STS bit by the assertion of the Button_In signal. 1 Reserved Reserved. 2 RTC_EN This bit is used to enable the setting of the RTC_STS bit to generate an SCI. The RTC_STS bit is set anytime the RTC generates an alarm. 3-7 Reserved Reserved. These bits always return a value of zero. Power Management 1 Control Register 1 (PM1_CNTRL 1) Register Location: +4 System I/O Space Default Value: 00h on Vbat POR Attribute: Read/Write (Note 0) Size: 8-bits 0 BIT 0 NAME SCI_EN DESCRIPTION When this bit is set, then the SCI enabled power management events will BIT NAME PWRBTN_EN 158 BIT NAME 1-7 Reserved DESCRIPTION generate an SCI interrupt. When this bit is reset power management events will not generate an SCI interrupt. Reserved. These bits always return a value of zero. Power Management 1 Control Register 2 (PM1_CNTRL 2) Register Location: +5 System I/O Space Default Value: 00h on Vbat POR Attribute: Read/Write (Note 0) Size: 8-bits BIT 0 1 NAME Reserved PWRBTNOR_EN DESCRIPTION Reserved. This field always returns zero. This bit controls the power button over-ride function. When set, then anytime the Button_In signal is asserted for more than four seconds the system will transition to the off state. When a power button over-ride event occurs, the logic should clear the PWRBTN_STS bit, and set the PWRBTNOR_STS bit. This 3-bit field defines the type of hardware sleep state the system enters when the SLP_EN bit is set to one. When this field is 000 the FDC37B78x will transition the machine to the off state when the SLP_EN bit is set to one. That is, with this field set to 000, nPowerOn will go inactive (float) after a 1-2 RTC clock delay when SLP_EN is set. This delay is a minimum of one 32kHz clock and a maximum of two 32kHz clocks (31.25μsec-62.5μsec). When this field is any other value, there is no effect. This is a write-only bit and reads to it always return a zero. Writing ‘1’ to this bit causes the system to sequence into the sleeping state associated with the SLP_TYPx fields after a 1-2 RTC clock delay, if the SLP_CTRL bit in the sleep / wake configuration register (0xF0 in Logical Device A) is cleared. If the SLP_CTRL bit is set, do not sequence into the sleeping state associated with the SLP_TYPx field, but generate an SMI. Note: the SLP_EN_SMI bit in the SMI Status Register 2 is always set upon writing ‘1’ to the SLP_EN bit. Writing ‘0’ to this bit has no effect. Reserved. This field always returns zero. 2-4 SLP_TYPx 5 SLP_EN 6-7 Reserved 159 General Purpose Event Status Register 1 (GPE_STS1) Register Location: +8 System I/O Space Default Value: 00h on Vbat POR Attribute: Read/Write (Note 0) Size: 8-bits DESCRIPTION This bit is set when the device power management events (PME events) occur. When enabled, the setting of this bit will generate an SCI Interrupt (Note 1). Writing a “1” to this bit will clear it if there are no pending PME events. See Figure 5. 1-7 Reserved Reserved. These bits always return a value of zero. Note 1: This bit is set by hardware and can only be cleared by software writing a one to this bit position and by Vbat POR. Writing a 0 has no effect. General Purpose Event Enable Register 1 (GPE_EN1) Register Location: +9 System I/O Space Default Value: 00h on Vbat POR Attribute: Read/Write (Note 0) Size: 8-bits BIT 0 NAME SCI_EN1 DESCRIPTION When this bit is set, then the enabled device power management events (PME events) will generate an SCI interrupt. When this bit is reset, device power management events will not generate an SCI interrupt. Reserved. These bits always return a value of zero. BIT 0 NAME SCI_STS1 1-7 Reserved Note 0: all bits described as "reserved" in writeable registers must be written with the value 0 when the register is written. PME Registers The power management event function has a PME_Status bit and a PME_En bit. These bits are defined in the PCI Bus Power Management Interface Specification, Revision 1.0, Draft, Copyright © 1997, PCI Special Interest Group, Mar. 18, 1997. The default states for the PME_Status and PME_En bits are controlled by Vbat Power-On-Reset. PME Status Register (PME_STS) Register Location: +10h System I/O Space Default Value: 00h on Vbat POR Attribute: Read/Write (Note 0) Size: 8-bits D7 • D6 D5 D4 D3 RESERVED D2 D1 D0 PME_Status DEFAULT 0x00 The PME_Status bit is set when the FDC37B78x would normally assert the PCI nPME signal, independent of the state of the PME_En bit. Only active transitions on the PME Wake sources can set the PME_Status bit. 160 • • • The PME_Status bit is read/write-clear. Writing a “1” to the PME_Status bit will clear it (if there are no pending PME events) and cause the FDC37C78X to stop asserting the nPME, if enabled. See Figure 5. Writing a “0” has no effect on the PME_Status bit. The PME_Status bit is reset to “0” during VBAT Power-On-Reset. PME Enable Register (PME_EN) Register Location: +11h System I/O Space Default Value: 00h on Vbat POR Attribute: Read/Write (Note 0) Size: 8-bits D7 • • • D6 D5 D4 D3 RESERVED D2 D1 D0 PME_En DEFAULT 0x00 Setting the PME_En bit to “1” enables the FDC37B78x to assert the nPME signal. When the PME_En bit is reset to “0”, nPME signal assertion is disabled. The PME_En bit is reset to “0” during VBAT Power-On-Reset. PME Status Register 1 (PME_STS 1) Register Location: +Ch System I/O Space Default Value: 00h on Vbat POR Attribute: Read/Write (Note 0) Size: 8-bits D7 DEVINT _STS D6 RTC_PME _STS D5 nRING D4 MOUSE D3 KBD D2 RI1 D1 RI2 D0 CIR DEFAULT 0x00 PME Status Register 2 (PME_STS2) Register Location: +Dh System I/O Space Default Value: 00h on Vbat POR Attribute: Read/Write (Note 0) Size: 8-bits D7 GP17 • • D6 GP16 D5 GP15 D4 GP14 D3 GP13 D2 GP12 D1 GP11 D0 GP10 DEFAUL T 0x00 The PME Status registers indicate the state of the individual FDC37B78x PME wake sources, independent of the state of the individual source enables or the PME_En bit. If the wake source has asserted a wake event, the associated PME Status bit will be “1”. The wake source bits in the PME Status registers are read/write-clear: an active (“1”) PME Status bit can only be cleared by writing a “1” to the bit. Writing a “0” to bits in the PME Wake Status register has no effect. PME Enable Register 1 (PME_EN1) Register Location: +Eh System I/O Space Default Value: 00h on Vbat POR Attribute: Read/Write (Note 0) 161 Size: 8-bits D7 DEVINT_ EN D6 RTC_PME _EN D5 nRING D4 MOUSE D3 KBD D2 RI1 D1 RI2 D0 CIR DEFAULT 0x00 PME Enable Register 2 (PME_EN2) Register Location: +Fh System I/O Space Default Value: 00h on Vbat POR Attribute: Read/Write (Note 0) Size: 8-bits D7 GP17 • • • D6 GP16 D5 GP15 D4 GP14 D3 GP13 D2 GP12 D1 GP11 D0 GP10 DEFAULT 0x00 The PME Enable registers enable the individual FDC37B78x wake sources onto the nPME bus. When the PME Enable register bit for a wake source is active (“1”), if the source asserts a wake event and the PME_En bit is “1”, the source will assert the PCI nPME signal. When the PME Enable register bit for a wake source is inactive (“0”), the PME Status register will indicate the state of the wake source but will not assert the PCI nPME signal. SMI Registers The FDC37B78x implements a group nSMI output pin. The nSMI group interrupt output consists of the enabled interrupts from each of the functional blocks in the chip plus other SMI events. The interrupts are enabled onto the group nSMI output via the SMI Enable Registers 1 and 2. The nSMI output is then enabled onto the group nSMI output pin or Serial IRQ Frame (IRQ2) via bit[7] in the SMI Enable Register 2. These SMI events can also be enabled as nPME/SCI events by setting the EN_SMI_PME bit, bit[6] of SMI Enable Register 2. This register is also used to enable the group nSMI output onto the nSMI Serial/Parallel IRQ pin and the routing of 8042 P12 internally to nSMI. The IRQ mux Register Bit 7 is used to select the SMI on the SMI pin or the Serial IRQ frame. 162 SMI Status Register 1 (SMI_STS1) Register Location: +12h System I/O Space Default Value: 00h on Vbat POR Attribute: Read/Write Size: 8-bits NAME SMI Status Register 1 Default = 0x00 on Vbat POR DESCRIPTION This register is used to read the status of the SMI inputs. The following bits must be cleared at their source. Bit[0] Reserved Bit[1] PINT (Parallel Port Interrupt) Bit[2] U2INT (UART 2 Interrupt) Bit[3] U1INT (UART 1 Interrupt) Bit[4] FINT (Floppy Disk Controller Interrupt) Bit[5] GPINT2 (Group Interrupt 2) Bit[6] GPINT1 (Group Interrupt 1) Bit[7] WDT (Watch Dog Timer) SMI Status Register 2 (SMI_STS2) Register Location: +13h System I/O Space Default Value: 00h on Vbat POR Attribute: Read/Write Size: 8-bits NAME SMI Status Register 2 Default = 0x00 on Vbat POR DESCRIPTION This register is used to read the status of the SMI inputs. Bit[0] MINT: Mouse Interrupt. Cleared at source. Bit[1] KINT: Keyboard Interrupt. Cleared at source. Bit[2] IRINT: This bit is set by a transition on the IR pin (RXD2 or IRRX2 as selected by Bit 6 of Configuration Register 0xF1 in Logical Device 5, i.e., after the MUX). Cleared by a read of this register. Bit[3] BINT: Cleared by a read of this register. Bit[4] P12: 8042 P1.2. Cleared at source Bits[5:6] Reserved Bit[7] SLP_EN_SMI. The SLP_EN SMI status bit. Cleared by a read of this register. (See Sleep Enable Config Reg.) 0=no SMI due to setting SLP_EN bit 1=SMI generated due to setting SLP_EN bit. 163 SMI Enable Register 1 (SMI_EN1) Register Location: < PM1_BLK >+14h System I/O Space Default Value: 00h on Vbat POR Attribute: Read/Write Size: 8-bits NAME SMI Enable Register 1 Default = 0x00 on Vbat POR DESCRIPTION This register is used to enable the different interrupt sources onto the group nSMI output. 1=Enable 0=Disable Bit[0] EN_RING Note: the PME status bit for RING is used as the SMI status bit for RING (see PME Status Register). Bit[1] EN_PINT Bit[2] EN_U2INT Bit[3] EN_U1INT Bit[4] EN_FINT Bit[5] EN_GPINT2 Bit[6] EN_GPINT1 Bit[7] EN_WDT 164 SMI Enable Register 2 (SMI_EN2) Register Location: < PM1_BLK >+15h System I/O Space Default Value: 00h on Vbat POR Attribute: Read/Write Size: 8-bits NAME SMI Enable Register 2 Default = 0x00 on Vbat POR DESCRIPTION This register is used to enable the different interrupt sources onto the group nSMI output, and the group nSMI output onto the nSMI GPI/O pin. Unless otherwise noted, 1=Enable 0=Disable Bit[0] EN_MINT Bit[1] EN_KINT Bit[2] EN_IRINT Bit[3] EN_BINT Bit[4] EN_P12: Enable 8042 P1.2 to route internally to nSMI 0=Do not route to nSMI 1=Enable routing to nSMI. Bit [5] EN_CIR Note: the PME status bit for CIR is used as the SMI status bit for CIR (see PME Status Register). Bit[6] EN_SMI_PME: Enable the group nSMI output into the PME interface logic. 0= Group SMI output does not go to PME interface logic 1= Enable group SMI output to PME interface logic Bit[7] EN_SMI: Enable the group nSMI output onto the nSMI pin or Serial IRQ frame (IRQ2). 0=SMI pin floats 1=Enable group nSMI output onto nSMI pin or serial IRQ frame Note: the selection of either the nSMI pin or serial IRQ frame is done via bit 7 of the IRQ Mux Control Register (0xC0 in Logical Device 8). 165 EITHER EDGE TRIGGERED INTERRUPTS Four GPIO pins are implemented that allow an interrupt to be generated on both a high-to-low and a low-to-high edge transition, instead of one or the other as selected by the polarity bit. The either edge triggered interrupts function as follows: Selecting the Either Edge Triggered Interrupt (EETI) function for these GPIO pins is applicable when the combined interrupt is enabled for the GPIO pin (GPINT1 for GP10GP17, and GPINT2 for GP50-GP54 and GP60GP67). Otherwise, selection of the EETI function will produce no function for the pin. If the EETI Miscellaneous Status Register function is selected for the GPIO pin, then the bits that control input/output, polarity and open collector/push-pull have no effect on the function of the pin. However, the polarity bit does affect the value of the GP bit (i.e., register GP1, bit 2 for GP12). An interrupt occurs if the status bit is set and the interrupt is enabled. The status bits indicate which of the EETI interrupts transitioned. These status bits are located in the MSC_STS register. The status is valid whether or not the interrupt is enabled and whether or not the EETI function is selected for the pin. The MSC_STS register is implemented as follows to hold the status bits of these four GPIOs. Miscellaneous Status Register (PM1_STS) Register Location: +16h System I/O Space Default Value: 00h on Vbat POR Attribute: Read/Write (Note 0) Size: 8-bits BIT 0 NAME EETI1_STS DEFINITION Either Edge Triggered Interrupt Input 1 Status. This bit is set when an edge occurs on the GP11 pin. This bit is cleared by writing a 1 to this bit position (writing a 0 has no effect). Either Edge Triggered Interrupt Input 2 Status. This bit is set when an edge occurs on the GP12 pin. This bit is cleared by writing a 1 to this bit position (writing a 0 has no effect). Either Edge Triggered Interrupt Input 3 Status. This bit is set when an edge occurs on the GP53 pin. This bit is cleared by writing a 1 to this bit position (writing a 0 has no effect). Either Edge Triggered Interrupt Input 4 Status. This bit is set when an edge occurs on the GP54 pin. This bit is cleared by writing a 1 to this bit position (writing a 0 has no effect). This bit is set upon VTR POR. This bit is cleared by writing a 1 to this bit position (writing a 0 has no effect). Additionally, when the system turns on (nPowerOn active low) due to a VTR POR, then an SCI is generated. Reserved. This bit always returns zero. 1 EETI2_STS 2 EETI3_STS 3 EETI4_STS 4 VTRPOR_STS 5-7 Reserved SMI/PME/SCI Logic The logic for the SMI, PME and SCI signals is shown in the figures that follow. 166 FIGURE 5 - PME/SCI LOGIC PME_EN Registers PME_EN1 Register EN_CIR EN_RI2 EN_RI1 MUX 00 01 10 Bit[6] Bits[6:5] of IRQ Mux Control Register EN_KBD PME_STS Registers PME_STS1 Register CIR RI2 RI1 KBD MOUSE RING RTC DEV_INT From SMI/PME Device Interrupt Block nPME pin nPME nSCI IRQ9 EN_MOUSE EN_RING EN_RTC EN_DEVINT PME_EN2 Register PME_STS Bit[5] PME_STS2 Register GP10 PME_EN GPE_STS Register GPE_EN Register SCI_STS1 GPE_STS.0 EN_GP10 EN_GP11 GP11 GP12 GP13 GP14 GP15 GP16 GP17 nSCI on IRQx pin EN_GP12 EN_GP13 EN_GP14 EN_GP15 EN_GP16 EN_GP17 nSCI on Serial IRQx Bit[2] of IRQ Mux Control Register SCI_EN1 GPE_EN.0 SCI_EN PM1_BLK PWRBTN_STS PWRBTN_EN RTC_EN RTC_STS nPowerOn WAK_STS Key to Symbols Enable bit Sticky Status bit: Cleared by software writing a ‘1’ to its bit location WAK_CTRL 167 FIGURE 6 - SMI/PME LOGIC SMI_EN Registers SMI_EN1 Register EN_RING SMI_STS Registers SMI_STS1 Register PINT EVENT RING Bit, PME_STS1 Register nRING CONFIGURATION The Configuration of the FDC37B78x is very flexible and is based on the configuration architecture implemented inGroup Plug-and-Play typical SMI components. The FDC37B78x is designed for nSMI out to pin motherboard applications in which the resources EN_SMI or Serial requiredIRQ2 their components are known. With its by Bit 7 of SMI_EN2 flexible resource allocation architecture, the Register FDC37B78x allows the BIOS to assign resources at POST. DEV_INT to nPME Interface SYSTEM ELEMENTS EN_SMI_PME Logic Bit 6 of SMI_EN2 Register configuration ports to initialize thePINT logical devices EN_PINT U2INT U2INT EN_U2INT U1INT at POST. The INDEX and DATA ports are only U1INT EN_U1INT FINT FINT valid EN_FINT the FDC37B78x is in Configuration when GPINT2 GPINT2 Mode. EN_GPINT2 GPINT1 GPINT1 EN_GPINT1 EN_WDT WDT WDT Primary Configuration Address Decoder After a hard reset (RESET_DRV pin asserted) or Vcc Power On Reset the FDC37B78x is in the Run Mode with all logical devices disabled. The logical devices may be configured through two standard Configuration I/O Ports (INDEX and DATA) by placing the FDC37B78x into Configuration Mode. The BIOS uses these The SYSOPT pin is latched on the falling edge of SMI_STS2 Register SMI_EN2 Register the RESET_DRV or on Vcc Power On Reset to MINT MINT EN_MINT KINT determine the configuration register's base KINT EN_KINT IRINT IRINT address. The SYSOPT pin is used to select the EN_IRINT BINT CONFIG PORT's I/O address at BINT power-up. Once EN_BINT P12 P12 EN_P12 CIR Bit, PME_STS1 Register powered up the configuration port base address CIR EN_CIR SLP_EN_SMI can be changed through configuration registers SLP_EN CR26 and CR27. The SYSOPT pin is a SLP_CTRL hardware configuration pin which is shared Bit 0 of the Sleep Enable with the nRTS1 signalto Symbols 115. During reset Key on pin Configuration Register 0xF0 of Logical Device A. this pin is a weak active low signal which sinks Enable bit 30µA. Note: All I/O addresses areCleared at qualified with Interrupt Status bit: source AEN. The INDEX and DATA ports are effective only when the chip is in the Configuration State. Interrupt Status bit: Cleared by a read of register Sticky Status bit: Cleared by a write of ‘1’ to this bit PORT NAME CONFIG PORT (Note 2) INDEX PORT (Note 2) DATA PORT SYSOPT= 0 (Pull-down resistor) Refer to Note 1 0x03F0 0x03F0 INDEX PORT + 1 SYSOPT= 1 (10K Pull-up resistor) 0x0370 0x0370 TYPE Write Read/Write Read/Write Note 1:If using TTL RS232 drivers use 1K pull-down. If using CMOS RS232 drivers use 10K pull-down. Note 2: The configuration port base address can be relocated through CR26 and CR27. 168 Entering the Configuration State The device enters the Configuration State when the following Config Key is successfully written to the CONFIG PORT. Config Key = < 0x55> When in configuration mode, all logical devices function properly. Entering and exiting configuration mode has no effect on the devices. Exiting the Configuration State The device exits the Configuration State when the following Config Key is successfully written to the CONFIG PORT. Config Key = < 0xAA> Configuration Mode The system sets the logical device information and activates desired logical devices through the INDEX and DATA ports. In configuration mode, the INDEX PORT is located at the CONFIG PORT address and the DATA PORT is at INDEX PORT address + 1. The desired configuration registers are accessed in two steps: a. Write the index of the Logical Device Number Configuration Register (i.e., 0x07) to the INDEX PORT and then write the number of the desired logical device to the DATA PORT. b. Write the address of the desired configuration register within the logical device to the INDEX PORT and then write or read the configuration register through the DATA PORT. Note: if accessing the Global Configuration Registers, step (a) is not required. Exit Configuration Mode To exit the Configuration State the system writes 0xAA to the CONFIG PORT. The chip returns to the RUN State. Note: Only two states are defined (Run and Configuration). In the Run State the chip will always be ready to enter the Configuration State. CONFIGURATION SEQUENCE To program the configuration registers, the following sequence must be followed: 1. Enter Configuration Mode 2. Configure the Configuration Registers 3. Exit Configuration Mode. Enter Configuration Mode To place the chip into the Configuration State the Config Key is sent to the chip's CONFIG PORT. The config key consists of a write of 0x55 data to the CONFIG PORT. Once the initiation key is received correctly the chip enters into the Configuration State (The auto Config ports are enabled). 149 Programming Example The following is an example of a configuration program in Intel 8086 assembly language. ;----------------------------. ; ENTER CONFIGURATION MODE | ;----------------------------' MOV DX,3F0H MOV AX,055H CLI; disable interrupts OUT DX,AL STI; enable interrupts ;-------------------------------. ; CONFIGURE REGISTER CRE0, | ; LOGICAL DEVICE 8 | ;-------------------------------' MOV DX,3F0H MOV AL,07H OUT DX,AL ; Point to LD# Config Reg MOV DX,3F1H MOV AL, 08H OUT DX,AL ; Point to Logical Device 8 ; MOV DX,3F0H MOV AL,E0H OUT DX,AL; Point to CRE0 MOV DX,3F1H MOV AL,02H OUT DX,AL; Update CRE0 ;-------------------------------. ; EXIT CONFIGURATION MODE | ;-------------------------------' MOV DX,3F0H MOV AX,0AAH OUT DX,AL Notes: 1. HARD RESET: RESET_DRV pin asserted 2. SOFT RESET: Bit 0 of Configuration Control register set to one 3. All host accesses are blocked for 500µs after Vcc POR (see Power-up Timing Diagram) 171 CONFIGURATION REGISTERS INDEX TYPE HARD RESET Vbat SOFT Vcc POR Vtr POR POR RESET GLOBAL CONFIGURATION REGISTERS CONFIGURATION REGISTER 0x02 0x03 0x07 0x20 0x21 0x22 0x23 0x24 0x26 W R/W R/W R R R/W R/W R/W R/W 0x00 0x03 0x00 0x44 0x00 0x00 (Note 0) 0x00 0x03 0x00 0x44 0x00 0x00 (Note 0) 0x00 0x03 0x00 0x44 0x00 0x00 (Note 0) - 0x00 0x44 0x00 0x00 0) (Note Config Control Index Address Logical Device Number Device ID - hard wired Device Rev - hard wired Power Control Power Mgmt OSC Configuration Port Address Byte 0 0x00 0x04 Sysopt=0: 0xF0 Sysopt=1: 0x70 Sysopt=0: 0x03 Sysopt=1: 0x03 0x00 0x00 0x03, 0xF0 0x06 0x02 0x0E 0x00 0xFF 0x00 0x00 0x00 0x04 Sysopt=0: 0xF0 Sysopt=1: 0x70 Sysopt=0: 0x03 Sysopt=1: 0x03 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x03, 0xF0 0x06 0x02 0x0E 0x00 0xFF 0x00 0x00 0x00 0x04 - - 0x27 R/W - - - Configuration Port Address Byte 1 0x28 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x60, 0x61 0x70 0x74 0xF0 0xF1 0xF2 0xF4 0xF5 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0x00 0x00 0x00 0x00 0x00 0x00 0x03, 0xF0 0x06 0x02 0x0E 0x00 0xFF 0x00 0x00 - 0x00 0x00 0x03, 0xF0 0x06 0x02 - Clock Mask Register TEST 4 TEST 5 TEST 1 TEST 2 TEST 3 Activate Primary Base I/O Address Primary Interrupt Select DMA Channel Select FDD Mode Register FDD Option Register FDD Type Register FDD0 FDD1 LOGICAL DEVICE 0 CONFIGURATION REGISTERS (FDD) LOGICAL DEVICE 1 CONFIGURATION REGISTERS (Reserved) LOGICAL DEVICE 2 CONFIGURATION REGISTERS (Reserved) LOGICAL DEVICE 3 CONFIGURATION REGISTERS (Parallel Port) 172 INDEX 0x30 TYPE R/W HARD RESET 0x00 Vcc POR 0x00 Vtr POR 0x00 Vbat POR - SOFT RESET 0x00 CONFIGURATION REGISTER Activate 0x60, 0x61 0x70 0x74 0xF0 0xF1 R/W R/W R/W R/W R/W 0x00, 0x00 0x00 0x04 0x3C 0x00 0x00, 0x00 0x00 0x04 0x3C 0x00 0x00, 0x00 0x00 0x04 0x3C 0x00 - 0x00, 0x00 0x00 0x04 - Primary Base I/O Address Primary Interrupt Select DMA Channel Select Parallel Port Mode Register Parallel Port Mode Register 2 Activate Primary Base I/O Address Primary Interrupt Select Serial Port 1 Mode Register Activate Primary Base I/O Address CIR Base I/O Address Primary Interrupt Select DMA Channel Select Serial Port 2 Mode Register IR Options Register IR Half Duplex Timeout Activate Secondary Base Address for RTC Bank 1 Primary Interrupt Select Real Time Clock Mode Register Activate Primary Interrupt Select Second Interrupt Select KRESET and GateA20 Select LOGICAL DEVICE 4 CONFIGURATION REGISTERS (Serial Port 1) 0x30 0x60, 0x61 0x70 0xF0 R/W R/W R/W R/W 0x00 0x00, 0x00 0x00 0x00 0x00 0x00, 0x00 0x00 0x00 0x00 0x00, 0x00 0x00 0x00 - 0x00 0x00, 0x00 0x00 - LOGICAL DEVICE 5 CONFIGURATION REGISTERS (Serial Port 2) 0x30 0x60, 0x61 0x62, 0x63 0x70 0x74 0xF0 0xF1 0xF2 0x30 0x62, 0x63 0x70 0xF0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0x00, 0x00 0x00, 0x00 0x00 0x04 0x00 0x02 0x03 0x00 0x00, 0x70 0x00 0x00 0x00, 0x00 0x00, 0x00 0x00 0x04 0x00 0x02 0x03 0x00 0x00, 0x70 0x00 0x00 0x00 0x00, 0x00 0x00, 0x00 0x00 0x04 0x00 0x02 0x03 0x00 0x00, 0x70 0x00 n/a - 0x00, 0x00 0x00, 0x00 0x00 0x04 0x00 0x00, 0x70 0x00 n/a LOGICAL DEVICE 6 CONFIGURATION REGISTERS (RTC) LOGICAL DEVICE 7 CONFIGURATION REGISTERS (Keyboard) 0x30 0x70 0x72 0xF0 R/W R/W R/W R/W 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 - 0x00 0x00 0x00 - 173 INDEX TYPE HARD Vbat SOFT RESET Vcc POR Vtr POR POR RESET LOGICAL DEVICE 8 CONFIGURATION REGISTERS (Aux I/O) CONFIGURATION REGISTER 0x30 0xB0 0xB1 0xB2 0xB3 0xB8 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC8 0xCA 0xCB 0xCC 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xE0 0xE1 0xE2 0xE3 0xE4 R/W R/W R/W R/W R/W R/W R/W R/W R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0x00 0x01 0x00 - 0x00 0x01 0x00 - 0x00 0x00 - 0x00 0x80 0x00 0x00 0x00 0x00 0x01 0x09 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x00 - Activate Soft Power Enable 3 Register 1 Soft Power Enable 3 Register 2 Soft Power Status 3 Register 1 Soft Power Status 3 Register 2 Delay 2 Time Set Register IRQ Mux Control 3 Force Disk Change Floppy Data Rate Select Shadow UART1 FIFO Control Shadow UART2 FIFO Control Shadow FDC Force Write Protect Ring Filter Select GP50 GP52 GP53 GP54 GP60 GP61 GP62 GP63 GP64 GP65 GP66 GP67 GP10 GP11 GP12 GP13 GP14 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 174 INDEX 0xE5 TYPE R/W HARD RESET - Vcc POR - Vtr POR - Vbat POR 0x00 SOFT RESET - CONFIGURATION REGISTER 3 GP15 0xE6 0xE7 0xEF 0xF0 0xF1 0xF2 0xF3 0xF4 0xF6 0xF9 0xFA 0x30 0x60, (2) 0x61 0x70 0xF0 R/W R/W R/W R/W R/W R/W R/W R/W (1) 0x00 0x00 0x00 0x00 0x00 0x00, 0x00 - 0x00 0x00 0x00 0x00 0x00 0x00, 0x00 - 0x00 0x00 0x00 0x00 0x00 0x00, 0x00 - 0x01 0x01 0x00 0x00 0x00 0x00 0x00 - 0x00 0x00, 0x00 - GP16 GP17 3 3 3 3 GP_INT2 GP_INT1 WDT_UNITS WDT_VAL WDT_CFG WDT_CTRL GP1 GP5 GP6 3 3 3 R/W R/W R/W R/W R/W LOGICAL DEVICE A CONFIGURATION REGISTERS (ACPI) Activate 4 Primary Base I/O Address PM1_BLK Primary Interrupt Select Sleep/Wake 3 Configuration 3 R/W R/W 0x00 0x00 Notes 0) CR22 Bit 5 is reset on Vtr POR only 1) This register contains some bits which are read or write only. 2) Register 60 is the high byte; 61 is the low byte. For example to set the primary base address to 1234h, write 12h into 60, and 34h into 61. 3) These configuration registers are powered by Vtr and battery backed up. 4) The Activate bit for Logical Device A does not effect the generation of an interrupt (SCI). 175 Chip Level (Global) Control/Configuration Registers [0x00-0x2F] The chip-level (global) registers lie in the address range [0x00-0x2F]. The design MUST use all 8 bits of the ADDRESS Port for register selection. All unimplemented registers and bits ignore writes and return zero when read. The INDEX PORT is used to select a configuration register in the chip. The DATA PORT is then used to access the selected register. These registers are accessable only in the Configuration Mode. TABLE 71 - CHIP LEVEL REGISTERS DESCRIPTION Chip (Global) Control Registers 0x00 0x01 Config Control Default = 0x00 on Vcc POR or Reset_Drv Index Address Default = 0x03 on Vcc POR or Reset_Drv 0x03 R/W 0x02 W Reserved - Writes are ignored, reads return 0. The hardware automatically clears this bit after the write, there is no need for software to clear the bits. Bit 0 = 1: Soft Reset. Refer to the "Configuration Registers" table for the soft reset value for each register. Bit[7] = 1 Enable GP1, WDT_CTRL, GP5, GP6, Soft Power Enable and Status Register access when not in configuration mode = 0 Disable GP1, WDT_CTRL, GP5, GP6, Soft Power Enable and Status Register access when not in configuration mode (Default) Bits [6:2] Reserved - Writes are ignored, reads return 0. Bits[1:0] Sets GP1 etc. selection register used when in Run mode (not in Configuration Mode). = 11 0xEA (Default) = 10 0xE4 = 01 0xE2 = 00 0xE0 0x04 - 0x06 Logical Device # Default = 0x00 on Vcc POR or Reset_Drv 0x07 R/W Reserved - Writes are ignored, reads return 0. A write to this register selects the current logical device. This allows access to the control and configuration registers for each logical device. Note: the Activate command operates only on the selected logical device. Reserved - Writes are ignored, reads return 0. Chip Level, SMSC Defined C C REGISTER ADDRESS STATE Card Level Reserved 0x08 - 0x1F 176 REGISTER Device ID Hard wired = 0x44 Device Rev Hard wired = 0x00 PowerControl Default = 0x00. on Vcc POR or Reset_Drv hardware signal. ADDRESS 0x20 R DESCRIPTION A read only register which provides identification. Bits[7:0] = 0x44 when read device STATE C 0x21 R A read only register which provides device revision information. Bits[7:0] = 0x00 when read C 0x22 R/W Bit[0] FDC Power Bit[1] Reserved Bit[2] Reserved Bit[3] Parallel Port Power Bit[4] Serial Port 1 Power Bit[5] Serial Port 2 Power Bit[6] Reserved Bit[7] Reserved = 0 Power off or disabled = 1 Power on or enabled Bit[0] FDC Bit[1] Reserved Bit[2] Reserved Bit[3] Parallel Port Bit[4] Serial Port 1 Bit[5] Serial Port 2 Bit[6] Reserved (read as 0) Bit[7] Reserved (read as 0) = 0 Intelligent Pwr Mgmt off = 1 Intelligent Pwr Mgmt on Bit[0] Reserved Bit [1] PLL Control = 0 PLL is on (backward Compatible) = 1 PLL is off Bits[3:2] OSC = 01 Osc is on, BRG clock is on. = 10 Same as above (01) case. = 00 Osc is on, BRG Clock Enabled. = 11 Osc is off, BRG clock is disabled. Bit [6:4] Reserved, set to zero Bit[7] IRQ8 Polarity = 0 IRQ8 is active high = 1 IRQ8 is active low C Power Mgmt Default = 0x00. on Vcc POR or Reset_Drv hardware signal 0x23 R/W C OSC Default = 0x04, on Vcc POR or Reset_Drv hardware signal. 0x24 R/W C Chip Level Vendor Defined 0x25 Reserved - Writes are ignored, reads return 0. 177 REGISTER Configuration Address Byte 0 Default=0xF0 (Sysopt=0) =0x70 (Sysopt=1) on Vcc POR or Reset_Drv Configuration Address Byte 1 Default = 0x03 on Vcc POR or Reset_Drv Chip Level Vendor Defined TEST 4 TEST 5 TEST 1 TEST 2 ADDRESS 0x26 DESCRIPTION Bit[7:1] Configuration Address Bits [7:1] Bit[0] = 0 See Note 1 Below STATE C 0x27 Bit[7:0] Configuration Address Bits [15:8] See Note 1 Below C 0x28 -0x2A 0x2B R/W 0x2C R/W 0x2D R/W 0x2E R/W Reserved - Writes are ignored, reads return 0. Test Modes: Reserved for SMSC. Users should not write to this register, may produce undesired results. Test Modes: Reserved for SMSC. Users should not write to this register, may produce undesired results. Test Modes: Reserved for SMSC. Users should not write to this register, may produce undesired results. Test Modes: Reserved for SMSC. Users should not write to this register, may produce undesired results. Test Modes: Reserved for SMSC. Users should not write to this register, may produce undesired results. C C C C TEST 3 Default = 0x00, on Vcc POR or Reset_Drv hardware signal. 0x2F R/W C Note 1: To allow the selection of the configuration address to a user defined location, these Configuration Address Bytes are used. There is no restriction on the address chosen, except that A0 is 0, that is, the address must be on an even byte boundary. As soon as both bytes are changed, the configuration space is moved to the specified location with no delay (Note: Write byte 0, then byte 1; writing CR27 changes the base address). The configuration address is only reset to its default address upon a Hard Reset or Vcc POR. Note: the default configuration address is either 3F0 or 370, as specified by the SYSOPT pin. This change affects SMSC Mode only. 178 Logical Device Configuration/Control Registers [0x30-0xFF] Used to access the registers that are assigned to each logical unit. This chip supports eight logical units and has eight sets of logical device registers. The eight logical devices are Floppy, Parallel Port, Serial Port 1 and Serial Port 2, Real Time Clock, Keyboard Controller, Auxiliary I/O and ACPI. A separate set (bank) of control and configuration register exists for each logical device and is selected with the Logical Device # Register (0x07). The INDEX PORT is used to select a specific logical device register. These registers are then accessed through the DATA PORT. The Logical Device registers are accessible only when the device is in the Configuration State. The logical register addresses are: Logical Device Registers TABLE 72 - CHIP LEVEL REGISTERS LOGICAL DEVICE REGISTER Activate Note1 ADDRESS (0x30) DESCRIPTION Bits[7:1] Reserved, set to zero. Bit[0] = 1 Activates the logical device currently selected through the Logical Device # register. = 0 Logical device currently selected is inactive Reserved - Writes are ignored, reads return 0. Vendor Defined - Reserved - Writes are ignored, reads return 0. Reserved - Writes are ignored, reads return 0. Registers 0x60 and 0x61 set the base address for the device. If more than one base address is required, the second base address is set by registers 0x62 and 0x63. Unused registers will ignore writes and return zero when read. STATE C Default = 0x00 on Vcc POR or Reset_Drv Note 2 Logical Device Control Logical Device Control Mem Base Addr I/O Base Addr. (see Device Base I/O Address Table) Default = 0x00 on Vcc POR or Reset_Drv Interrupt Select Defaults : 0x70 = 0x00, on Vcc POR or Reset_Drv 0x72 = 0x00, on Vcc POR or Reset_Drv (0x31-0x37) (0x38-0x3f) (0x40-0x5F) (0x60-0x6F) 0x60,2,... = addr[15:8] 0x61,3,... = addr[7:0] C C C C (0x70,072) 0x70 is implemented for each logical device. Refer to Interrupt Configuration Register description. Only the keyboard controller uses Interrupt Select register 0x72. Unused register (0x72) will ignore writes and return zero when read. Interrupts default to edge high (ISA compatible). C 179 LOGICAL DEVICE REGISTER ADDRESS (0x71,0x73) DESCRIPTION Reserved - not implemented. These register locations ignore writes and return zero when read. Only 0x74 is implemented for FDC, Serial Port 2 and Parallel port. 0x75 is not implemented and ignores writes and returns zero when read. Refer to DMA Channel Configuration. Reserved - not implemented. These register locations ignore writes and return zero when read. Reserved - not implemented. These register locations ignore writes and return zero when read. Reserved - Vendor Defined (see SMSC defined Logical Device Configuration Registers) Reserved STATE DMA Channel Select Default = 0x04 on Vcc POR or Reset_Drv 32-Bit Memory Space Configuration Logical Device Logical Device Config. Reserved (0x74,0x75) C (0x76-0xA8) (0xA9-0xDF) (0xE0-0xFE) 0xFF C C C Note 1:A logical device will be active and powered up according to the following equation: DEVICE ON (ACTIVE) = (Activate Bit SET or Pwr/Control Bit SET). The Logical device's Activate Bit and its Pwr/Control Bit are linked such that setting or clearing one sets or clears the other. Note: If the I/O Base Addr of the logical device is not within the Base I/O range as shown in the Logical Device I/O map, then read or write is not valid and is ignored. Note 2. The activate bit for Logical Device 5 (Serial Port 2) is reset on Vtr POR only. 180 I/O Base Address Configuration Register TABLE 73 - I/O BASE ADDRESS CONFIGURATION REGISTER DESCRIPTION BASE I/O FIXED RANGE LOGICAL REGISTER INDEX BASE OFFSETS (NOTE3) DEVICE +0 : SRA FDC 0x60,0x61 [0x100:0x0FF8] +1 : SRB (Note 4) ON 8 BYTE BOUNDARIES +2 : DOR +3 : TSR +4 : MSR/DSR +5 : FIFO +7 : DIR/CCR Parallel Port 0x60,0x61 [0x100:0x0FFC] ON 4 BYTE BOUNDARIES (EPP Not supported) or [0x100:0x0FF8] ON 8 BYTE BOUNDARIES (all modes supported, EPP is only available when the base address is on an 8byte boundary) +0 : Data|ecpAfifo +1 : Status +2 : Control +3 : EPP Address +4 : EPP Data 0 +5 : EPP Data 1 +6 : EPP Data 2 +7 : EPP Data 3 +400h : cfifo|ecpDfifo|tfifo |cnfgA +401h : cnfgB +402h : ecr +0 : RB/TB|LSB div +1 : IER|MSB div +2 : IIR/FCR +3 : LCR +4 : MSR +5 : LSR +6 : MSR +7 : SCR +0 : RB/TB|LSB div +1 : IER|MSB div +2 : IIR/FCR +3 : LCR +4 : MSR +5 : LSR +6 : MSR +7 : SCR LOGICAL DEVICE NUMBER 0x00 0x03 0x04 Serial Port 1 0x60,0x61 [0x100:0x0FF8] ON 8 BYTE BOUNDARIES 0x05 Serial Port 2 0x60,0x61 [0x100:0x0FF8] ON 8 BYTE BOUNDARIES 181 LOGICAL DEVICE NUMBER LOGICAL DEVICE REGISTER INDEX 0x62,0x63 BASE I/O RANGE (NOTE3) [0x100:0x0FF8] ON 8 BYTE BOUNDARIES 0x06 RTC n/a Not Relocatable Fixed Base Address: 70,71 [0x00:0xFFE] ON 2 BYTE BOUNDARIES Not Relocatable Fixed Base Address: 60,64 [0x00:0x0FE7] ON 24 BYTE BOUNDARIES FIXED BASE OFFSETS +0 : CIR Registers +1 : CIR Registers +2 : CIR Registers +3 : CIR Registers +4 : CIR Registers +5 : CIR Registers +6 : CIR Registers +7 : CIR Registers +0: Index Register +1: Data Register +0: Index Register +1: Data Register +0 : Data Register +4 : Command/Status Reg. 0x62, 0x63 0x07 KYBD n/a 0x0A ACPI 0x60,0x61 Note 3:This chip uses ISA address bits [A11:A0] to decode the base address of each of its logical devices. 182 Interrupt Select Configuration Register TABLE 74 - INTERRUPT SELECT CONFIGURATION REGISTER DESCRIPTION NAME REG INDEX DEFINITION STATE Interrupt Request Level Select 0 Default = 0x00 on Vcc POR or Reset_Drv 0x70 (R/W) Bits[3:0] selects which interrupt level is used for Interrupt 0. 0x00=no interrupt selected. 0x01=IRQ1 0x02=IRQ2 • • • 0x0E=IRQ14 0x0F=IRQ15 Note: All interrupts are edge high (except ECP/EPP) C Note: It is the responsibility of the software to ensure that two IRQ’s are not set to the same IRQ number. An Interrupt is activated by setting the Interrupt Request Level Select 0 register to a non-zero value AND: for the FDC logical device by setting DMAEN, bit D3 of the Digital Output Register. for the PP logical device by setting IRQE, bit D4 of the Control Port and in addition for the PP logical device in ECP mode by clearing serviceIntr, bit D2 of the ecr. for the Serial Port logical device by setting any combination of bits D0-D3 in the IER and by setting the OUT2 bit in the UART's Modem Control (MCR) Register. for the RTC by (refer to the RTC section of this spec.) for the KYBD by (refer to the KYBD controller section of this spec.) Note: IRQ pins must tri-state if not used/selected by any Logical Device. Refer to Note A. Note: 183 DMA Channel Select Configuration Register TABLE 75 - DMA CHANNEL SELECT CONFIGURATION REGISTER DESCRIPTION NAME REG INDEX DEFINITION STATE DMA Channel Select Default = 0x04 on Vcc POR or Reset_Drv 0x74 (R/W) Bits[2:0] select the DMA Channel. 0x00=DMA0 0x01=DMA1 0x02=DMA2 0x03=DMA3 0x04-0x07= No DMA active C Note: A DMA channel is activated by setting the DMA Channel Select register to [0x00-0x03] AND : for the FDC logical device by setting DMAEN, bit D3 of the Digital Output Register. for the PP logical device in ECP mode by setting dmaEn, bit D3 of the ecr. for the UART 2 logical device, by setting the DMA Enable bit. Refer to the IRCC specification. Note:DMAREQ pins must tri-state if not used/selected by any Logical Device. Refer to Note A. Note A. Logical Device IRQ and DMA Operation 1) IRQ and DMA Enable and Disable: Any time the IRQ or DACK for a logical block is disabled by a register bit in that logical block, the IRQ and/or DACK must be disabled. This is in addition to the IRQ and DACK disabled by the Configuration Registers (active bit or address not valid). FDC: For the following cases, the IRQ and DACK used by the FDC are disabled (high impedance). Will not respond to the DREQ. a) Digital Output Register (Base+2) bit D3 (DMAEN) set to "0". b) The FDC is in power down (disabled). Serial Port 1 and 2: Modem Control Register (MCR) Bit D2 (OUT2) - When OUT2 is a logic "0", the serial port interrupt is forced to a high impedance state - disabled. Parallel Port: SPP and EPP modes: Control Port (Base+2) bit D4 (IRQE) set to "0", IRQ is disabled (high impedance). 2) 3) 4) 184 a) ECP Mode: i) (DMA) dmaEn from ecr register. See table. ii) IRQ - See table. MODE (FROM ECR REGISTER) 000 001 010 011 100 101 110 111 5) PRINTER SPP FIFO ECP EPP RES TEST CONFIG IRQ PIN CONTROLLED BY IRQE IRQE (on) (on) IRQE IRQE (on) IRQE PDREQ PIN CONTROLLED BY dmaEn dmaEn dmaEn dmaEn dmaEn dmaEn dmaEn dmaEn Real Time Clock and Keyboard Controller: Refer to the RTC and KBD section of this spec. SMSC Defined Logical Device Configuration Registers The SMSC Specific Logical Device Configuration Registers reset to their default values only on hard resets generated by Vcc POR or VTR POR or VBAT POR (as shown) or the RESET_DRV signal. 185 These registers are not affected by soft resets. TABLE 76 - FLOPPY DISK CONTROLLER, LOGICAL DEVICE 0 [LOGICAL DEVICE NUMBER = 0X00] NAME REG INDEX DEFINITION STATE FDD Mode Register Default = 0x0E on Vcc POR or Reset_Drv 0xF0 R/W Bit[0] Floppy Mode = 0Normal Floppy Mode (default) = 1 Enhanced Floppy Mode 2 (OS2) Bit[1] FDC DMA Mode = 0 Burst Mode is enabled = 1 Non-Burst Mode (default) Bit[3:2] Interface Mode = 11 AT Mode (default) = 10 (Reserved) = 01 PS/2 = 00 Model 30 Bit[4] Swap Drives 0,1 Mode = 0 No swap (default) = 1 Drive and Motor sel 0 and 1 are swapped. Bits[5] Reserved, set to zero. Bit [6] Output Type Control: 0= FDC outputs are OD24 open drain (default) 1= FDC outputs are O24 push-pull. Bit [7] FDC output Control: 0= FDC outputs active (default) 1= FDC outputs tristated Note: these bits do not affect the parallel port FDC pins. FDD Option Register Default = 0x00 on Vcc POR or Reset_Drv 0xF1 R/W Bits[1:0] Reserved, set to zero Bits[3:2] Density Select = 00 Normal (default) = 01 Normal (reserved for users) = 10 1 (forced to logic "1") = 11 0 (forced to logic "0") Bit[5:4] Reserved, set to zero Bits[7:6] Boot Floppy = 00 FDD 0 (default) = 01 FDD 1 = 10 Reserved (neither drive A or B is a boot drive). = 11 Reserved (neither drive A or B is a boot drive). Bits[1:0] Bits[3:2] Bits[5:4] type) Bits[7:6] type) Floppy Drive A Type Floppy Drive B Type Reserved (could be used to store Floppy Drive C Reserved (could be used to store Floppy Drive D Note: The FDC37B78x supports two floppy drives 0xF3 R Reserved, Read as 0 (read only) C C C FDD Type Register Default = 0xFF on Vcc POR or Reset_Drv 0xF2 R/W C 186 NAME FDD0 Default = 0x00 on Vcc POR or Reset_Drv REG INDEX 0xF4 R/W DEFINITION Bits[1:0] Drive Type Select: DT1, DT0 Bits[2] Read as 0 (read only) Bits[4:3] Data Rate Table Select: DRT1, DRT0 Bits[5] Read as 0 (read only) Bits[6] Precompensation Disable PTS =0 Use Precompensation =1 No Precompensation Bits[7] Read as 0 (read only) Refer to definition and default for 0xF4 STATE C FDD1 0xF5 R/W C 187 Parallel Port, Logical Device 3 TABLE 77 - PARALLEL PORT, LOGICAL DEVICE 3 [LOGICAL DEVICE NUMBER = 0X03] NAME REG INDEX DEFINITION STATE PP Mode Register Default = 0x3C on Vcc POR or Reset_Drv 0xF0 R/W Bits[2:0] Parallel Port Mode = 100 Printer Mode (default) = 000 Standard and Bi-directional (SPP) Mode = 001 EPP-1.9 and SPP Mode = 101 EPP-1.7 and SPP Mode = 010 ECP Mode = 011 ECP and EPP-1.9 Mode = 111 ECP and EPP-1.7 Mode Bit[6:3] ECP FIFO Threshold 0111b (default) Bit[7] PP Interupt Type Not valid when the parallel port is in the Printer Mode (100) or the Standard & Bi-directional Mode (000). = 1 Pulsed Low, released to high-Z. = 0 IRQ follows nACK when parallel port in EPP Mode or [Printer,SPP, EPP] under ECP. IRQ level type when the parallel port is in ECP, TEST, or Centronics FIFO Mode. PP Mode Register 2 Default = 0x00 on Vcc POR or Reset_Drv 0xF1 R/W Bits[1:0] PPFDC - muxed PP/FDC control = 00 Normal Parallel Port Mode = 01 PPFD1:Drive 0 is on the FDC pins Drive 1 is on the Parallel port pins Drive 2 is on the FDC pins Drive 3 is on the FDC pins = 10 PPFD2:Drive 0 is on the Parallel port pins Drive 1 is on the Parallel port pins Drive 2 is on the FDC pins Drive 3 is on the FDC pins Bits[7:2] Reserved. Set to zero. C 188 Serial Port 1, Logical Device 4 TABLE 78 - SERIAL PORT 1, LOGICAL DEVICE 4 [LOGICAL DEVICE NUMBER = 0X04] NAME REG INDEX DEFINITION STATE Serial Port 1 Mode Register Default = 0x00 on Vcc POR or Reset_Drv 0xF0 R/W Bit[0] MIDI Mode = 0 MIDI support disabled (default) = 1 MIDI support enabled Bit[1] High Speed = 0 High Speed Disabled(default) = 1 High Speed Enabled Bit[6:2] Reserved, set to zero Bit[7]: Share IRQ =0 UARTS use different IRQs =1 UARTS share a common IRQ See Note 1 below. Note 1: To properly share and IRQ, 1. Configure UART1 (or UART2) to use the desired IRQ pin. 2. Configure UART2 (or UART1) to use No IRQ selected. 3. Set the share IRQ bit. Note: If both UARTs are configured to use different IRQ pins and the share IRQ bit is set, then both of the UART IRQ pins will assert when either UART generates an interrupt. C 189 TABLE 79 - UART INTERRUPT OPERATION UART2 IRQ PINS UART2 UART2 Share UART1 UART2 IRQ OUT2 bit IRQ State Pin State Pin State Bit This part of the table is based on the assumption that both UARTS have selected different IRQ pins 0 Z 0 Z 0 Z Z 1 asserted 0 Z 0 1 Z 1 de-asserted 0 Z 0 0 Z 0 Z 1 asserted 0 Z 1 0 Z 1 de-asserted 0 Z 0 1 asserted 1 asserted 0 1 1 1 asserted 1 de-asserted 0 1 0 1 de-asserted 1 asserted 0 0 1 1 de-asserted 1 de-asserted 0 0 0 0 Z 0 Z 1 Z Z 1 asserted 0 Z 1 1 1 1 de-asserted 0 Z 1 0 0 0 Z 1 asserted 1 1 1 0 Z 1 de-asserted 1 0 0 1 asserted 1 asserted 1 1 1 1 asserted 1 de-asserted 1 1 1 1 de-asserted 1 asserted 1 1 1 1 de-asserted 1 de-asserted 1 0 0 It is the responsibility of the software to ensure that two IRQ’s are not set to the same IRQ number. However, if they are set to the same number then no damage to the chip will result. UART1 UART1 UART1 OUT2 bit IRQ State 190 Serial Port 2, Logical Device 5 TABLE 80 - SERIAL PORT 2, LOGICAL DEVICE 5 [LOGICAL DEVICE NUMBER = 0X05] NAME REG INDEX DEFINITION STATE Serial Port 2 Mode Register Default = 0x00 on Vcc POR or Reset_Drv IR Option Register Default = 0x02 on Vcc POR or Reset_Drv 0xF1 R/W (EN 1) 0xF0 R/W Bit[0] MIDI Mode = 0MIDI support disabled (default) = 1MIDI support enabled Bit[1] High Speed = 0High Speed disabled(default) = 1High Speed enabled Bit[7:2] Reserved, set to zero Bit[0] Receive Polarity = 0 Active High (Default) = 1 Active Low Bit[1] Transmit Polarity = 0 Active High = 1 Active Low (Default) Bit[2] Duplex Select = 0 Full Duplex (Default) = 1 Half Duplex Bits[5:3] IR Mode = 000 Standard (Default) = 001 IrDA = 010 ASK-IR = 011 Reserved = 1xx Reserved Bit[6] IR Location Mux = 0 Use Serial port TXD2 and RXD2 (Default) = 1Use alternate IRRX2 (pin 81) and IRTX2 (pin 82) Bit[7] Reserved, write 0 Bits [7:0] These bits set the half duplex time-out for the IR port. This value is 0 to 10msec in 100usec increments. 0= blank during transmit/receive 1= blank during transmit/receive + 100usec ... C C IR Half Duplex Timeout Default = 0x03 on Vcc POR or Reset_Drv 0xF2 191 RTC, Logical Device 6 TABLE 81 - RTC, LOGICAL DEVICE 6 [LOGICAL DEVICE NUMBER = 0X06] NAME REG INDEX DEFINITION STATE RTC Mode Register Default = 0x00 on Vcc POR or Reset_Drv 0xF0 R/W Bit[0] = 1 : Lock CMOS RAM 00-1Fh in Bank 1 Bit[1] = 1 : Lock CMOS RAM 20-3Fh in Bank 1 Bit[2] = 1 : Lock CMOS RAM 40-5Fh in Bank 1 Bit[3] = 1 : Lock CMOS RAM 60-7Fh in Bank 1 Bits[5:4] RTC Bank Selection =00 Bank 1 at Secondary Base Address, Bank 0 Off (Default) =01 Bank 0 at 70h and Bank 1 at Secondary Base Address (Note 1) =10 No Bank Selected =11 Bank 0 at 70h, Bank 1 Off Bit[7:6] Reserved Note: Once set, bits[3:0] can not be cleared by a write; bits[3:0] are cleared only on Vcc Power On Reset or upon a Hard Reset. Note 1: The secondary base address must be set to a value other than 70h prior to selecting this option. C 192 KYBD, Logical Device 7 TABLE 82 - KYBD, LOGICAL DEVICE 7 [LOGICAL DEVICE NUMBER = 0X07] NAME REG INDEX DEFINITION STATE KRST_GA20 Default = 0x00 on Vcc POR or Reset_Drv 0xF0 R/W KRESET and GateA20 Select Bit[7] Polarity Select for P12 = 0 P12 active low (default) = 1 P12 active high Bits[6:3] Reserved Bit[2] Port 92 Select = 0 Port 92 Disabled = 1 Port 92 Enabled Bit[1] GATEA20 Select = 0 Software Control = 1 Hardware Speed-up Bit[0] KRESET Select = 0 Software Control = 1 Hardware Speed-up Reserved - read as ‘0’ 0xF1 0xFF 193 Auxiliary I/O, Logical Device 8 TABLE 83 - AUXILLIARY I/O, LOGICAL DEVICE 8 [LOGICAL DEVICE NUMBER = 0X08] NAME REG INDEX DEFINITION STATE C 0xB0 R/W The following bits are the enables for the wake-up Soft Power Enable function of the nPowerOn bit. When enabled, Register 1 these bits allow their corresponding function to turn on power to the system. Default = 0x00 on Vbat POR 1 = ENABLED 0 = DISABLED Bit[0] SP_RI1: UART 1 Ring Indicator Pin Bit[1] SP_RI2: UART 2 Ring Indicator Pin Bit[2] SP_KCLK: Keyboard Clock pin Bit[3] SP_MCLK: Mouse Clock pin Bit[4] SP_GPINT1: Group Interrupt 1 Bit[5] SP_GPINT2: Group Interrupt 2 Bit[6] SP_IRRX2: IRRX2 input pin Bit[7] SP_RTC ALARM: RTC Alarm C 0xB1 R/W The following bits are the enables for the wake-up Soft Power Enable function of the nPowerOn bit. When enabled, Register 2 these bits allow their corresponding function to turn on power to the system. Default = 0x80 on Vbat POR 1 = ENABLED 0 = DISABLED Bit[0] SP_RXD1: UART 1 Receive Data Pin Bit[1] SP_RXD2: UART 2 Receive Data Pin Bit[2] Reserved Bit[3] RING Enable bit “RING_EN” 0=Disable. 1=Enable ring indicator on nRING pin as wakeup function to activate nPowerOn. Bit[4] Reserved Bit[5] CIR Enable bit “CIR_EN” 0=Disable. 1=Enable CIR wakeup event to activate nPowerOn Bit[6] Reserved Bit[7] OFF_EN: After power up, this bit defaults to 1, i.e., enabled. This bit allows the software to enable or disable the button control of power off. 194 NAME Soft Power Status Register 1 Default = 0x00 on Vbat POR REG INDEX 0xB2 R/W DEFINITION The following bits are the status for the wake-up function of the nPowerOn bit. These indicate which of the enabled wakeup functions caused the power up. 1 = Occured 0 = Did not occur since last cleared The following signals are latched to detect and hold the soft power event (Type 1) (Note 1) Bit[0] RI1: UART 1 Ring Indicator; high to low transition on the pin, cleared by a read of this register Bit[1] RI2: UART 2 Ring Indicator; high to low transition on the pin, cleared by a read of this register Bit[2] KCLK: Keyboard clock; high to low transition on the pin, cleared by a read of this register Bit[3] MCLK: Mouse clock; high to low transition on the pin, cleared by a read of this register Bit[6] IRRX2: IRRX2 input; high to low transition on the pin, cleared by a read of this register Bit[7] RTC ALARM: RTC Alarm; status of the RTC Alarm internal signal. Cleared by a read of the status register. The following signals are not latched to detect and hold the soft power event (Type 2) (Note 1) Bit[4] GPINT1: Group Interrupt 1; status of the GPINT1 internal signal. Cleared at the source Bit[5] GPINT2: Group Interrupt 2; status of the GPINT2 internal signal. Cleared at the source STATE C 195 NAME Soft Power Status Register 2 Default = 0x00 on Vbat POR REG INDEX 0xB3 R/W DEFINITION The following bits are the status for the wake-up function of the nPowerOn bit. These indicate which of the enabled wakeup functions caused the power up. 1 = Occured 0 = Did not occur since last cleared The following signals are latched to detect and hold the soft power event (Type 1) (Note 1) Bit[0] RXD1: UART 1 Receive Data; high to low transition on the pin, cleared by a read of this register Bit[1] RXD2: UART 2 Receive Data; high to low transition on the pin, cleared by a read of this register Bit[3] RING Status bit “RING_STS”; Latched, cleared on read. 0= nRING input did not occur. 1= Ring indicator input occurred on the nRING pin and, if enabled, caused the wakeup (activated nPowerOn) Bit[4] Reserved Bit[5] CIR Status bit “CIR_STS”; latched, cleared on read. 0= CIR wakeup event did not occur. 1= CIR wakeup event occurred and, if enabled, caused the wakeup (activated nPowerOn). The following signal is latched to detect and hold the soft power event (Type 3) (Note 1) but the output of the latch does not feed into the power down circuitry: Bit[2] Button: Button pressed, Cleared by a read of this register Bits[7:6] Reserved STATE C 196 NAME Delay 2 Time Set Register Default = 0x00 on VTR POR REG INDEX 0xB8 R/W DEFINITION This register is used to set Delay 2 (for Soft Power Management) to a value from 500 msec to 32 sec. The default value is 500msec. Engineering Note: this delay is started if OFF_EN is enabled and OFF_DLY was set and a Button Input comes in. Bits[5:0] The value of these bits correspond to the delay time as follows: 000000= 500msec min to 510msec max 000001= 1sec min to 1.01sec max 000010= 1.5sec min to 1.51sec max 000011= 2sec min to 2.01sec max ... 111111 = 32sec min to 32.01sec max Bits[7:6] Reserved STATE C 197 NAME IRQ Mux Control Register Default = 0x00 on Vbat POR REG INDEX 0XC0 R/W DEFINITION This register is used to configure the IRQs, including PME, SCI and SMI. Bit[0] Serial/Parallel IRQs 0=Serial IRQs are used 1=Parallel IRQS are used Note 1: This bit does not control the RTC IRQ, SCI or SMI interrupts. See bits 1,2,7 of this register. Note 2: If set, the BIOS buffer is disabled. Also, the SER_IRQ and PCI_CLK pins are disabled, and these pins function as IRQ15 and IRQ14, respectively. Note 3: Select IRQ9 below. Select RTC IRQ and SCI below. Select nSMI through the SMI register. Bit[1] RTC IRQ Select. 0=RTC IRQ on serial IRQ frame 1=RTC IRQ on IRQx pin Bit[2] SCI Select 0=SCI is on serial IRQ frame 1=SCI is on IRQx pin Note: Serial IRQs are not available under VTR power. Bit[3] SCI Polarity Select (EN1) 0=SCI active low 1=SCI active high Bit[4] SCI Buffer Type (EN1) 0=Push-pull 1=Open drain Bit[6:5] SCI/PME/IRQ9 Pin select 00=Pin 21 is used for nPME signal. 01=Pin 21 is used for SCI. 10=Pin 21 is used for IRQ9. 11=Reserved Engineering Note: If bit 5 is set, this overrides the setting of the IRQ for SCI in Config Register 0x70 of Logical Device A. See the logic in the SCI section. Enginreering Note: This bit selects the buffer type of the pin as follows: if nPME is selected, it is active low OD; if SCI is selected, the buffer type and polarity are selected through bits 3 and 4 of this register; if IRQ9 is selected, it is an active high push-pull output. Bit[7] SMI Select 0=SMI is on serial IRQ frame (IRQ2) 1=SMI is on nSMI pin Engineering Note: the polarity and buffer type of the SMI pin is selected through the GPIO registers (default is active low open drain). STATE 198 NAME Forced Disk Change Default = 0x03 on VTR POR REG INDEX 0xC1 R/W DEFINITION Force Change 1 and Force Change 0 can be written to 1 are not clearable by software. Force Change 1 is cleared on (nSTEP AND nDS1) Force Change 0 is cleared on (nSTEP AND nDS0). DSK CHG (Floppy DIR Register, Bit 7) = (nDS0 AND Force Change 0) OR (nDS1 AND Force Change 1) OR nDSKCHG. Setting either of the Force Disk Change bits active (1) forces the FDD nDSKCHG input active when the appropriate drive has been selected. Bit[0] Force Change for FDC0 0=Inactive 1=Active Bit[1] Force Change for FDC1 0=Inactive 1=Active Bit[2:7] Reserved, Reads 0 Floppy Data Rate Select Shadow Register Bit[7] Soft Reset Bit[6] Power Down Bit[5] Reserved Bit[4] PRECOMP 2 Bit[3] PRECOMP 1 Bit[2] PRECOMP 0 Bit[1] Data Rate Select 1 Bit[0] Data Rate Select 0 UART1 FIFO Control Shadow Register Bit[7] RCVR Trigger MSB Bit[6] RCVR Trigger LSB Bit[5] Reserved Bit[4] Reserved Bit[3] DMA Mode Select Bit[2] XMIT FIFO Reset Bit[1] RCVR FIFO Reset Bit[0] FIFO Enable UART2 FIFO Control Shadow Register Bit[7] RCVR Trigger MSB Bit[6] RCVR Trigger LSB Bit[5] Reserved Bit[4] Reserved Bit[3] DMA Mode Select Bit[2] XMIT FIFO Reset Bit[1] RCVR FIFO Reset Bit[0] FIFO Enable STATE Floppy Data Rate Select Shadow 0xC2 R UART1 FIFO Control Shadow 0xC3 R UART2 FIFO Control Shadow 0xC4 R 199 NAME Forced Write Protect Default = 0x00 on VTR POR REG INDEX 0xC5 R/W DEFINITION Force Write Protect function forces the FDD nWRTPRT input active if the FORCE WRTPRT bit is active. The Force Write Protect function applies to the nWRTPRT pin in the FDD Interface as well as the nWRTPRT pin in the Parallel Port FDC. Bit[0] Force Write Protect bit FDD0 0 = Inactive (Default) 1 = Active “forces the FDD nWRTPRT input active when the drive has been selected” Note 2 Bit[1:7] Reserved, reads 0. This register is used to select the operation of the ring indicator on the nRI1, nRI2 and nRING pins. Bit[0]: 1=Enable detection of pulse train of frequency 15Hz or higher for 200msec and generate an active low pulse for its duration to use as the ring indicator function on nRING pin. The leading high-to-low edge is the trigger for the ring indication. 0=Ring indicate function is high-to-low transition on the nRING pin. Bit[1]: 1=Enable detection of pulse train of frequency 15Hz or higher and generate an active low pulse for its duration to use for 200msec as the ring indicator function on nRI1 pin. The leading high-to-low edge is the trigger for the ring indication. 0=Ring indicate function is high-to-low transition on the nRI1 pin. Bit[2]: 1=Enable detection of pulse train of frequency 15Hz or higher and generate an active low pulse for its duration to use for 200msec as the ring indicator function on nRI2 pin. The leading high-to-low edge is the trigger for the ring indication. 0=Ring indicate function is high-to-low transition on the nRI2 pin. Bits[7:3] Reserved STATE Ring Filter Select Register Default = 0x00 on Vbat POR Note 3 0xC6 R/W C Note 1: There are three types of events Type 1, Type 2 and Type 3. Type 1: This is an event that comes from a pin or internal signal to the chip. This needs to be edge detected and latched until cleared by a read of the register. The output of the latch is used to turn on the power supply through the “or” logic. Type 2:This is an event that comes from a pin or internal signal to the chip. This does not need to be edge detected and latched. Cleared at the source. Type 3: This is an event that comes from a pin or internal signal to the chip. This needs to be edge detected and latched until cleared by a read of the register. The output of the latch is not used to turn on the power supply through the “or” logic. 200 Note 2: nWRTPRT (to the FDC Core) = (nDS0 AND FORCE WRTPRT 0) OR nWRTPRT (from the FDD Interface). The Force Write Protect 0 bit also applies to the Parallel Port FDC. This bit applies to both drives. Note 3: The ring wakeup filter will produce an active low pulse for the period of time that nRING, nRI1 and/or nRI2, nRI1 and/or nRI2 is toggling. 201 TABLE 84 - AUXILLIARY I/O, LOGICAL DEVICE 8 [LOGICAL DEVICE NUMBER = 0X08] NAME REG INDEX DEFINITION STATE GP10 Default = 0x01 on Vbat POR 0xE0 General Purpose I/0 bit 1.0 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Group Interrupt Enable =1 Enable Combined IRQ 1 =0 Disable Combined IRQ 1 Bit[3] Function Select =1 nSMI =0 GPI/O Bits[6:4] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/0 bit 1.1 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Group Interrupt Enable =1 Enable Combined IRQ 1 =0 Disable Combined IRQ 1 Bit[4:3] Function Select =00 GPI/O =01 nRING =10 Either Edge Triggered Interrupt 1 =11 Reserved Bits[6:5] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull Bit General Purpose I/0 bit 1.2 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity :=1 Invert, =0 No Invert Bit[2] Group Interrupt Enable =1 Enable Combined IRQ 1 =0 Disable Combined IRQ 1 Bit[4:3] Function Select =00 GPI/O =01 WDT =10 P17 =11 Either Edge Triggered Interupt 2 Bits[6:5] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull Bit General Purpose I/0 bit 1.3 Bit[0] In/Out : =1 Input, =0 Output C GP11 Default = 0x01 on Vbat POR 0xE1 C GP12 Default = 0x01 on Vbat POR 0xE2 C GP13 0xE3 C 202 NAME Default = 0x01 on Vbat POR REG INDEX DEFINITION Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Group Interrupt Enable =1 Enable Combined IRQ 1 =0 Disable Combined IRQ 1 Bit[3] Function Select =1 LED =0 GPI/O Bits[6:4] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull Bit General Purpose I/0 bit 1.4 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Group Interrupt Enable =1 Enable Combined IRQ 1 =0 Disable Combined IRQ 1 Bit[3] Function Select =1 IRRX2 =0 GPI/O Bits[6:4] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull Bit General Purpose I/0 bit 1.5 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Group Interrupt Enable =1 Enable Combined IRQ 1 =0 Disable Combined IRQ 1 Bit[3] Function Select =1 IRTX2 =0 GPI/O Bits[6:4] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/0 bit 1.6 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Group Interrupt Enable =1 Enable Combined IRQ 1 =0 Disable Combined IRQ 1 Bit[3] Function Select =1 nMTR1 =0 GPI/O Bits[6:4] Reserved STATE GP14 Default = 0x01 on Vbat POR 0xE4 C GP15 Default = 0x00 on Vbat POR 0xE5 C GP16 Default = 0x01 on Vbat POR 0xE6 C 203 NAME REG INDEX DEFINITION Bit[7] Output Type Select 1=Open Drain 0=Push Pull Bit STATE GP17 Default = 0x01 on Vbat POR 0xE7 General Purpose I/0 bit 1.7 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Group Interrupt Enable =1 Enable Combined IRQ 1 =0 Disable Combined IRQ 1 Bit[3] Function Select =1 nDS1 =0 GPI/O Bits[6:4] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/0 bit 5.0 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Reserved Bit[4:3] Function Select =00 PCI Clock =01 IRQ14 =10 GPI/O =11 Reserved Bit[5] Group Interrupt Enable =1 Enable Combined IRQ 2 =0 Disable Combined IRQ 2 Bit[6] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/0 bit 5.2 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Reserved Bit[4:3] Function Select =00 DRVDEN1 =01 GPIO =10 IRQ8 =11 nSMI Bit[5] Group Interrupt Enable =1 Enable Combined IRQ 2 =0 Disable Combined IRQ 2 Bit[6] Reserved Bit[7] Output Type Select 1=Open Drain C GP50 Default = 0x01 on Vbat POR 0xC8 GP52 Default =0x09 on Vbat POR 0xCA 204 NAME GP53 Default =0x01 on Vbat POR REG INDEX 0xCB DEFINITION 0=Push Pull General Purpose I/0 bit 5.3 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Reserved Bit[4:3] Function Select =00 nROMCS =01 IRQ11 =10 GPI/O =11 Either Edge Triggered Interrupt 3 Bit[5] Group Interrupt Enable =1 Enable Combined IRQ 2 =0 Disable Combined IRQ 2 Bit[6] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/0 bit 5.4 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Reserved Bit[4:3] Function Select =00 nROMOE =01 IRQ12 =10 GPI/O =11 Either Edge Triggered Interrupt 4 Bit[5] Group Interrupt Enable =1 Enable Combined IRQ 2 =0 Disable Combined IRQ 2 Bit[6] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/0 bit 6.0 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Reserved Bit[4:3] Function Select =00 RD0 =01 IRQ1 =10 GPI/O =11 nSMI Bit[5] Group Interrupt Enable =1 Enable Combined IRQ 2 =0 Disable Combined IRQ 2 Bit[6] Reserved Bit[7] Output Type Select STATE GP54 Default = 0x01 on Vbat POR 0xCC GP60 Default = 0x01 on Vbat POR 0xD0 205 NAME REG INDEX DEFINITION 1=Open Drain 0=Push Pull General Purpose I/0 bit 6.1 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Reserved Bit[4:3] Function Select =00 RD1 =01 IRQ3 =10 GPI/O =11 LED Bit[5] Group Interrupt Enable =1 Enable Combined IRQ 2 =0 Disable Combined IRQ 2 Bit[6] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/0 bit 6.2 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Reserved Bit[4:3] Function Select =00 RD2 =01 IRQ4 =10 GPI/O =11 nRING Bit[5] Group Interrupt Enable =1 Enable Combined IRQ 2 =0 Disable Combined IRQ 2 Bit[6] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/0 bit 6.3 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Reserved Bit[4:3] Function Select =00 RD3 =01 IRQ5 =10 GPI/O =11 WDT Bit[5] Group Interrupt Enable =1 Enable Combined IRQ 2 =0 Disable Combined IRQ 2 Bit[6] Reserved STATE GP61 Default = 0x01 on Vbat POR 0xD1 GP62 Default = 0x01 on Vbat POR 0xD2 GP63 Default = 0x01 on Vbat POR 0xD3 206 NAME REG INDEX DEFINITION Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/0 bit 6.4 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Reserved Bit[4:3] Function Select =00 RD4 =01 IRQ6 =10 GPI/O =11 P17 Bit[5] Group Interrupt Enable =1 Enable Combined IRQ 2 =0 Disable Combined IRQ 2 Bit[6] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/0 bit 6.5 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Reserved Bit[4:3] Function Select =00 RD5 =01 IRQ7 =10 GPI/O =11 Reserved Bit[5] Group Interrupt Enable =1 Enable Combined IRQ 2 =0 Disable Combined IRQ 2 Bit[6] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/0 bit 6.6 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Reserved Bit[4:3] Function Select =00 RD6 =01 IRQ8 =10 GPI/O =11 Reserved Bit[5] Group Interrupt Enable =1 Enable Combined IRQ 2 =0 Disable Combined IRQ 2 STATE GP64 Default = 0x01 on Vbat POR 0xD4 GP65 Default = 0x01 on Vbat POR 0xD5 GP66 Default = 0x01 on Vbat POR 0xD6 207 NAME REG INDEX DEFINITION Bit[6] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/0 bit 6.7 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Reserved Bit[4:3] Function Select =00 RD7 =01 IRQ10 =10 GPI/O =11 Reserved Bit[5] Group Interrupt Enable =1 Enable Combined IRQ 2 =0 Disable Combined IRQ 2 Bit[6] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/O Combined Interrupt 2 Bits[2:0] Reserved, = 000 Bit[3] GP IRQ Filter Select 0 = Debounce Filter Bypassed 1 = Debounce Filter Enabled Bits[7:4] Combined IRQ mapping 1111 = IRQ15 ......... 0011 = IRQ3 0010 = Invalid 0001 = IRQ1 0000 = Disable General Purpose I/O Combined Interrupt 1 Bits[2:0] Reserved, = 000 Bit[3] GP IRQ Filter Select 0 = Debounce Filter Bypassed 1 = Debounce Filter Enabled Bits[7:4] Combined IRQ mapping 1111 = IRQ15 ......... 0011 = IRQ3 0010 = Invalid 0001 = IRQ1 0000 = Disable Watch Dog Timer Units Bits[6:0] Reserved, = 00000 Bit[7] WDT Time-out Value Units Select STATE GP67 Default = 0x01 on Vbat POR 0xD7 GP_INT2 Default = 0x00 on Vbat POR 0xEF GP_INT1 Default = 0x00 on Vbat POR 0xF0 C WDT_UNITS 0xF1 C 208 NAME Default = 0x00 on Vcc POR or Reset_Drv REG INDEX DEFINITION = 0 Minutes (default) = 1 Seconds Note: if the logical device's activate bit is not set then bits 0 and 1 have no effect. STATE WDT_VAL Default = 0x00 on Vcc POR or Reset_Drv 0xF2 Watch-dog Timer Time-out Value Binary coded, units = minutes(default) or seconds, selectable via Bit[7] of Reg 0xF1, LD 8. 0x00 Time out disabled 0x01 Time-out = 1 minute/second ......... 0xFF Time-out = 255 minutes/seconds Watch-dog timer Configuration Bit[0] Joy-stick Enable =1WDT is reset upon an I/O read or write of the Game Port =0WDT is not affected by I/O reads or writes to the Game Port. Bit[1] Keyboard Enable =1WDT is reset upon a Keyboard interrupt. =0WDT is not affected by Keyboard interrupts. Bit[2] Mouse Enable =1WDT is reset upon a Mouse interrupt =0WDT is not affected by Mouse interrupts. Bit[3] PWRLED Time-out enable =1Enables the Power LED to toggle at a 1Hz rate with 50 percent duty cycle while the Watch-dog Status bit is set. =0Disables the Power LED toggle during Watch-dog timeout status. Bits[7:4] WDT Interrupt Mapping 1111 = IRQ15 ......... 0011 = IRQ3 0010 = Invalid 0001 = IRQ1 0000 = Disable Watch-dog timer Control Bit[0] Watch-dog Status Bit, R/W =1WD timeout occured =0WD timer counting Bit[1] Power LED Toggle Enable, R/W =1Toggle Power LED at 1Hz rate with 50 percent duty cycle. (1/2 sec. on, 1/2 sec. off) =0Disable Power LED Toggle Bit[2] Force Timeout, W =1Forces WD timeout event; this bit is self-clearing Bit[3] P20 Force Timeout Enable, R/W C WDT_CFG Default = 0x00 on Vcc POR or Reset_Drv 0xF3 C WDT_CTRL Default = 0x00 Cleared by VTR POR 0xF4 C 209 NAME REG INDEX DEFINITION = 1Allows rising edge of P20, from the Keyboard Controller, to force the WD timeout event. A WD timeout event may still be forced by setting the Force Timeout Bit, bit 2. = 0P20 activity does not generate the WD timeout event. Note: The P20 signal will remain high for a minimum of 1us and can remain high indefinitely. Therefore, when P20 forced timeouts are enabled, a self-clearing edge-detect circuit is used to generate a signal which is ORed with the signal generated by the Force Timeout Bit. Bit[4] Reserved. Set to 0. Bit[5] Stop_Cnt: This is used to terminate Delay 2 (Note 1) without generating a power down. This is used if the software determines that the power down should be aborted. When read, this bit indicates the following: Stop_Cnt = 0; Counter running Stop_Cnt = 1; Counter Stopped. Note: The write is self clearing. Bit[6] Restart_Cnt: This is used to restart Delay 2 (Note 1) from the button input to the generation of the power down. When restarted, the count will start over and delay the power down for the time that Delay 2 is set for (Default=500msec). The software can continue to do this indefinately with out allowing a powerdown. This bit is self clearing. 1=Restart; Automatically cleared. Bit[7] SPOFF: This is used to force a software power down. This bit is self clearing. Note 1: This delay is programmable via the Delay 2 Time Set Register at Logical Device 8, 0xB8. This register is used to read the value of the GPIO pins. Bit[0]: GP10 Bit[1]: GP11 Bit[2]: GP12 Bit[3]: GP13 Bit[4]: GP14 Bit[5]: GP15 Bit[6]: GP16 Bit[7]: GP17 This register is used to read the value of the GPIO pins. Bit[0]: GP50 Bit[1]: Reserved Bit[2]: GP52 STATE GP1 Default = 0x00 on Vbat POR 0xF6 GP5 Default = 0x00 on Vbat POR 0xF9 210 NAME REG INDEX DEFINITION STATE Bit[3]: GP53 Bit[4]: GP54 Bit[7:5]: Reserved 0xFA This register is used to read the value of the GPIO GP6 pins. Bit[0]: GP60 Default = 0x00 Bit[1]: GP61 on Vbat POR Bit[2]: GP62 Bit[3]: GP63 Bit[4]: GP64 Bit[5]: GP65 Bit[6]: GP66 Bit[7]: GP67 Note:Registers GP1, WDT_CTRL, GP5-6, Soft Power Enable and Status Registers are also available at index 01-0F when not in configuration mode. Note: GP10-17 can be enabled onto GPINT1; GP50-54 and GP60-67 can be enabled onto GPINT2. 211 ACPI, Logical Device A TABLE 85 - ACPI, LOGICAL DEVICE A [LOGICAL DEVICE NUMBER = 0X0A] NAME REG INDEX DEFINITION STATE Sleep/Wake Configuration Default = 0x00 on Vbat POR 0xF0 This register is used to configure the functionality of the SLP_EN bit and its associated logic, and the WAK_STS bit bit and its associated logic. It also contains the CIR PLL Power bit. Bit[0] SLP_CTRL. SLP_EN Bit Function. 0=Default. Writing ‘1’ to the SLP_EN bit causes the system to sequence into the sleeping state associated with the SLP_TYPx fields. 1=Writing ‘1’ to the SLP_EN bit does not cause the system to sequence into the sleeping state associated with the SLP_TYPx fields; instead an SMI is generated. Note: the SLP_EN_SMI bit in the SMI Status Register 2 is set whenever ‘1’ is written to the SLP_EN bit; it is enabled to generate an SMI through bit[0] of this register. Bit[1] WAK_CTRL. WAK_STS Bit Function 0=Default. The WAK_STS bit is set on the high-to-low transition of nPowerOn. 1=The WAK_STS bit is set upon any enabled wakeup event and the high-to-low transition of nPowerOn. Bits[2:6] Reserved Bit[7]: CIR PLL Power. 0=Default. The 32KHz clock PLL is unpowered 1=The 32KHz clock PLL is running and can replace the 14.318MHz clock source for the CIR wakeup event. C 212 OPERATIONAL DESCRIPTION MAXIMUM GUARANTEED RATINGS Operating Temperature Range.....................................................................................................0oC to +70oC Storage Temperature Range ..................................................................................................... -55o to +150oC Lead Temperature Range (soldering, 10 seconds) ...............................................................................+325oC Positive Voltage on any pin, with respect to Ground ...........................................................................Vcc+0.3V Negative Voltage on any pin, with respect to Ground............................................................................... -0.3V Maximum Vcc ............................................................................................................................................... +7V *Stresses above those listed above could cause permanent damage to the device. This is a stress rating only and functional operation of the device at any other condition above those indicated in the operation sections of this specification is not implied. Note: When powering this device from laboratory or system power supplies, it is important that the Absolute Maximum Ratings not be exceeded or device failure can result. Some power supplies exhibit voltage spikes on their outputs when the AC power is switched on or off. In addition, voltage transients on the AC power line may appear on the DC output. If this possibility exists, it is suggested that a clamp circuit be used. DC ELECTRICAL CHARACTERISTICS (TA = 0°C - 70°C, Vcc = +5 V ± 10%) PARAMETER SYMBOL I Type Input Buffer Low Input Level High Input Level IS Type Input Buffer Low Input Level High Input Level Schmitt Trigger Hysteresis ICLK Input Buffer Low Input Level High Input Level Input Leakage (All I and IS buffers) Low Input Leakage High Input Leakage IIL IIH -10 -10 +10 +10 μA μA VIN = 0 VIN = VCC VILCK VIHCK 2.2 0.4 V V VILIS VIHIS VHYS 2.2 250 0.8 V V mV Schmitt Trigger Schmitt Trigger VILI VIHI 2.0 0.8 V V TTL Levels MIN TYP MAX UNITS COMMENTS 218 PARAMETER IO4 Type Buffer Low Output Level High Output Level Output Leakage O4 Type Buffer Low Output Level High Output Level Output Leakage O8 Type Buffer Low Output Level High Output Level Output Leakage IO12 Type Buffer Low Output Level High Output Level Output Leakage O12 Type Buffer Low Output Level High Output Level Output Leakage OD12 Type Buffer Low Output Level Output Leakage SYMBOL MIN TYP MAX UNITS COMMENTS VOL VOH IOL 2.4 -10 0.4 V V IOL = 4 mA IOH = -2 mA VIN = 0 to VCC (Note 1) +10 μA VOL VOH IOL 2.4 -10 0.4 V V IOL = 4 mA IOH = -2 mA VIN = 0 to VCC (Note 1) +10 μA VOL VOH IOL 2.4 -10 0.4 V V IOL = 8 mA IOH = -4 mA VIN = 0 to VCC (Note 1) +10 μA VOL VOH IOL 2.4 -10 0.4 V V IOL = 12 mA IOH = -6 mA VIN = 0 to VCC (Note 1) +10 μA VOL VOH IOL 2.4 -10 0.4 V V IOL = 12 mA IOH = -6 mA VIN = 0 to VCC (Note 1) +10 μA VOL IOL -10 0.4 +10 V μA IOL = 12 mA VIN = 0 to VCC (Note 1) 219 PARAMETER IOP14 Type Buffer Low Output Level High Output Level Output Leakage Backdrive Protected OD14 Type Buffer Low Output Level Output Leakage OP14 Type Buffer Low Output Level High Output Level Output Leakage Backdrive Protected IOD16 Type Buffer Low Output Level Output Leakage O24 Type Buffer Low Output Level High Output Level Output Leakage SYMBOL MIN TYP MAX UNITS COMMENTS VOL VOH IOL IIL 2.4 -10 0.4 V V IOL = 14 mA IOH = -14 mA VIN = 0 to VCC (Note 1) VCC=0V; VCC=VTR =0V VIN = 6V Max +10 ± 10 μA μA VOL IOL -10 0.4 +10 V μA IOL = 14 mA VIN = 0 to VCC (Note 1) VOL VOH IOL IIL 2.4 -10 0.4 V V IOL = 14 mA IOH = -14 mA VIN = 0 to VCC VCC=0V; VCC=VTR =0V VIN = 6V Max +10 ± 10 μA μA VOL IOL -10 0.4 V μA IOL = 16 mA VIN = 0 to VCC VOL VOH IOL 2.4 -10 0.4 V V IOL = 24 mA IOH = -12 mA VIN = 0 to VCC (Note 1) +10 μA 220 PARAMETER IO24 Type Buffer Low Output Level High Output Level Output Leakage OD24 Type Buffer Low Output Level Output Leakage ChiProtect (SLCT, PE, BUSY, nACK, nERROR, GP10-GP17, GP50GP54, GP60-GP67,) Backdrive (nSTROBE, nAUTOFD, nINIT, nSLCTIN, PD0-PD7, GP10GP17, GP50-GP54, GP60GP67, nSMI, IRQ8) VCC Suppy Current Active Trickle Supply Voltage SYMBOL MIN TYP MAX UNITS COMMENTS VOL VOH IOL 2.4 -10 0.4 V V IOL = 24 mA IOH = -12 mA VIN = 0 to VCC (Note 1) +10 μA VOL IOL IIL 0.4 +10 ± 10 V μA μA IOL = 24 mA VIN = 0 to VCC (Note 1) VCC=0V; VCC=VTR =0V VIN = 6V Max VCC=0V; VCC=VTR =0V VIN = 6V Max IIL ± 10 μA ICCI VTR 4.5 VCC min -.5V 70 90 VCC max 25 mA V All outputs open. VCC must not be greater than .5V above VTR All outputs driven VTR Supply Current Active3 Battery Supply Voltage VBAT Supply Current Standby Input Leakage 3 3 IVRI VBAT 2.4 3.0 mA V μA nA 4.0 5 100 VCC=VTR=VSS =0V VCC=5V, VBAT=3V Note 1: Output leakage is are measured with the current pins in high impedance. Note 2: Output leakage is measured with the low driving output off, either for a high level output or a high impedance state. Note 3: Please contact SMSC for the latest values. 221 CAPACITANCE TA = 25°C; fc = 1MHz; VCC = 5V PARAMETER Clock Input Capacitance Input Capacitance Output Capacitance SYMBOL CIN CIN COUT MIN LIMITS TYP MAX 20 10 20 UNIT pF pF pF TEST CONDITION All pins except pin under test tied to AC ground 222 AC TIMING DIAGRAMS CAPACITIVE LOADING For the Timing Diagrams shown, the following capacitive loads are used. TABLE 86 - CAPACITIVE LOADING NAME SD[0:7] IOCHRDY IRQ[1,3-12,14,15] DRQ[1:3] nWGATE nWDATA nHDSEL nDIR nSTEP nDS[1:0] nMTR[1:0] DRVDEN[1:0] TXD1 nRTS1 nDTR1 TXD2 nRTS2 nDTR2 PD[0:7] nSLCTIN nINIT nALF nSTB KDAT KCLK MDAT MCLK CAPACITANCE TOTAL (pF) 120 120 60 60 240 240 240 240 240 240 240 240 100 100 100 100 100 100 240 240 240 240 240 240 240 240 240 223 IOW Timing Port 92 t3 SAx t4 SD nIOW t1 t2 t5 FIGURE 7 - IOW TIMING FOR PORT 92 TABLE 87 - IOW TIMING FOR PORT 92 NAME t1 t2 t3 t4 t5 DESCRIPTION SAx Valid to nIOW Asserted SDATA Valid to nIOW Asserted nIOW Asserted to SAx Invalid nIOW Deasserted to DATA Invalid nIOW Deasserted to nIOW or nIOR Asserted MIN 40 0 10 0 100 TYP MAX UNITS ns ns ns ns ns 224 POWER-UP TIMING t1 Vcc t2 t3 A ll H o s t Accesses FIGURE 8 - POWER-UP TIMING TABLE 88 - POWER-UP TIMING NAME t1 t2 t3 DESCRIPTION Vcc Slew from 4.5V to 0V Vcc Slew from 0V to 4.5V All Host Accesses After Powerup (Note 1) MIN 300 100 125 500 TYP MAX UNITS μs μs μs Note 1: Internal write-protection period after Vcc passes 4.5 volts on power-up 225 Button Timing B u tto n _ In tF tR FIGURE 9 - BUTTON INPUT TIMING TABLE 89 - BUTTON INPUT TIMING NAME tR, tF DESCRIPTION Button_In Rise/Fall Time MIN TYP MAX 0.5 UNITS μs B u tto n _ In t1 R e le a s e n P o w e rO n t2 B la n k in g P e r io d t3 V cc FIGURE 10 - BUTTON OVERRIDE TIMING TABLE 90 - BUTTON OVERRIDE TIMING NAME t1 t2 t3 DESCRIPTION Button_In Hold Time For Override Event Button _In Low To nPowerOn Tristate and Vcc Low and Start of Blanking Period Blanking Period After Release of Button_In MIN 4 TYP 4 4 MAX UNITS s s s 226 ROM INTERFACE nR O M C S nRO M O E t2 t1 R D [x] N o te 1 t5 S D [x] FIGURE 11 - ROM INTERFACE TIMING Note 1: RD[x] driven by FDC37B78x, SD[x] driven by system Note 2: RD[x] driven by ROM, SD[x] driven by FDC37B78x t7 N o te 2 t3 t2 t8 t3 t4 t6 TABLE 91 - ROM INTERFACE TIMING NAME t1 t2 t3 t4 t5 t6 t7 t8 DESCRIPTION SD[x] Valid to RD[x] Valid nROMCS Active to RD[X] Driven nROMCS Inactive to RD[X] Float RD[x] Valid to SD[x] Valid nROMCS Active to SD[X] Driven nROMCS Inactive to SD[X] Float nROMOE Active to RD[x] Float nROMOE Inactive to RD[x] Driven MIN TYP MAX 25 25 25 25 25 25 25 25 UNITS ns ns ns ns ns ns ns ns Note 1: Outputs have a 50 pf load. 227 ISA WRITE t10 AEN t3 SA[x], t2 t1 nIOW t5 SD[x] DATA t7 FINTR t8 PINTR t9 IBF t4 t6 FIGURE 13 - ISA WRITE TIMING TABLE 92 - ISA WRITE TIMING NAME t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 DESCRIPTION SA[x], nCS and AEN valid to nIOW asserted nIOW asserted to nIOW deasserted nIOW asserted to SA[x], nCS invalid SD[x] Valid to nIOW deasserted SD[x] Hold from nIOW deasserted nIOW deasserted to nIOW asserted nIOW deasserted to FINTR deasserted (Note 1) nIOW deasserted to PINTER deasserted (Note 2) IBF (internal signal) asserted from nIOW deasserted nIOW deasserted to AEN invalid 10 25 55 260 40 MIN 10 80 10 45 0 TYP MAX UNITS ns ns ns ns ns ns ns ns ns ns Note 1: FINTR refers to the IRQ used by the floppy disk Note 2: PINTR refers to the IRQ used by the parallel port 228 ISA READ t13 AEN t3 SA[x], nCS t1 t7 nIOR t4 SD[x] PD[x], nERROR, PE, SLCT, ACK, BUSY t10 FINTER t9 PINTER t11 PCOBF t12 AUXOBF1 t8 nIOR/nIOW DATA VALID t5 t2 t6 FIGURE 14 - ISA READ TIMING See timing parameters on next page. 229 TABLE 93 - ISA READ TIMING NAME t1 t2 t3 t4 t5 t6 t8 t8 t7 t9 t10 t11 t12 t13 Note 1: Note 2: Note 3: Note 4: Note 5: DESCRIPTION SA[x], nCS and AEN valid to nIOR asserted nIOR asserted to nIOR deasserted nIOR asserted to SA[x], nCS invalid nIOR asserted to Data Valid Data Hold/float from nIOR deasserted nIOR deasserted nIOR asserted after nIOW deasserted nIOR/nIOR, nIOW/nIOW transfers from/to ECP FIFO Parallel Port setup to nIOR asserted nIOR asserted to PINTER deasserted nIOR deasserted to FINTER deasserted nIOR deasserted to PCOBF deasserted (Notes 3,5) nIOR deasserted to AUXOBF1 deasserted (Notes 4,5) nIOW deasserted to AEN invalid FINTR refers to the IRQ used by the floppy disk. PINTR refers to the IRQ used by the parallel port. PCOBF is used for the Keyboard IRQ. AUXOBF1 is used for the Mouse IRQ. Applies only if deassertion is performed in hardware. 10 10 25 80 150 20 55 260 80 80 MIN 10 50 10 50 25 TYP MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns 230 8042 CPU t2 PCOBF t1 AUXOBF1 nWRT t3 IBF nRD FIGURE 15 - INTERNAL 8042 CPU TIMING TABLE 94 - INTERNAL 8042 CPU TIMING NAME t1 t2 t3 DESCRIPTION nWRT deasserted to AUXOBF1 asserted (Notes 1,2) nWRT deasserted to PCOBF asserted (Notes 1,3) nRD deasserted to IBF deasserted (Note 1) MIN TYP MAX 40 40 40 UNITS ns ns ns Note 1: IBF, nWRT and nRD are internal signals. Note 2: PCOBF is used for the Keyboard IRQ. Note 3 AUXOBF1 is used for the Mouse IRQ. 231 CLOCK TIMING t2 CLOCKI t2 FIGURE 16 - INPUT CLOCK TIMING TABLE 95 - INPUT CLOCK TIMING NAME t1 t2 t1 t2 DESCRIPTION Clock Cycle Time for 14.318MHZ Clock High Time/Low Time for 14.318MHz Clock Cycle Time for 32KHZ Clock High Time/Low Time for 32KHz Clock Rise Time/Fall Time (not shown) MIN TYP 70 35 31.25 16.53 5 MAX UNITS ns ns μs μs ns FIGURE 17 - RESET TIMING t4 RESET_DRV TABLE 96 - RESET TIMING NAME t4 DESCRIPTION RESET width (Note 1) MIN 1.5 TYP MAX UNITS μs Note 1: The RESET width is dependent upon the processor clock. The RESET must be active while the clock is running and stable. 232 Single Transfer DMA t15 AEN t16 t3 t2 FDRQ, PDRQ t1 nDACK t12 t14 t11 t6 t5 nIOR or nIOW t7 DATA (DO-D7) t13 TC DATA VALID t8 t4 t10 t9 FIGURE 18 - SINGLE TRANSFER DMA TIMING See timing parameters on next page. 233 TABLE 97 - SINGLE TRANSFER DMA TIMING NAME t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 DESCRIPTION nDACK Delay Time from FDRQ High DRQ Reset Delay from nIOR or nIOW FDRQ Reset Delay from nDACK Low nDACK Width nIOR Delay from FDRQ High nIOW Delay from FDRQ High Data Access Time from nIOR Low Data Set Up Time to nIOW High Data to Float Delay from nIOR High Data Hold Time from nIOW High nDACK Set Up to nIOW/nIOR Low nDACK Hold after nIOW/nIOR High TC Pulse Width AEN Set Up to nIOR/nIOW AEN Hold from nDACK TC Active to PDRQ Inactive 40 10 10 5 10 60 40 10 100 60 150 0 0 100 MIN 0 100 100 TYP MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 234 Burst Transfer DMA Timing t15 AEN t16 t3 t2 FDRQ, PDRQ t1 nDACK t12 t14 t11 t6 nIOR or nIOW t5 t8 t4 t7 DATA (DO-D7) DATA VALID t13 TC t10 t9 DATA VALID FIGURE 19 - BURST TRANSFER DMA TIMING See timing parameters on next page. 235 TABLE 98 - BURST TRANSFER DMA TIMING NAME t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 DESCRIPTION nDACK Delay Time from FDRQ High DRQ Reset Delay from nIOR or nIOW FDRQ Reset Delay from nDACK Low nDACK Width nIOR Delay from FDRQ High nIOW Delay from FDRQ High Data Access Time from nIOR Low Data Set Up Time to nIOW High Data to Float Delay from nIOR High Data Hold Time from nIOW High nDACK Set Up to nIOW/nIOR Low nDACK Hold after nIOW/nIOR High TC Pulse Width AEN Set Up to nIOR/nIOW AEN Hold from nDACK TC Active to PDRQ Inactive 40 10 10 5 10 60 40 10 100 60 150 0 0 100 MIN 0 100 100 TYP MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 236 DISK DRIVE TIMING t3 nDIR t4 t1 nSTEP t2 t5 nDS0-3 t6 nINDEX t7 nRDATA t8 nWDATA nIOW t9 nDS0-1, MTR0-1 t9 FIGURE 20 - DISK DRIVE TIMING (AT MODE ONLY) TABLE 99 - DISK DRIVE TIMING (AT MODE ONLY) NAME t1 t2 t3 t4 t5 t6 t7 t8 t9 DESCRIPTION nDIR Set Up to STEP Low nSTEP Active Time Low nDIR Hold Time after nSTEP nSTEP Cycle Time nDS0-1 Hold Time from nSTEP Low nINDEX Pulse Width nRDATA Active Time Low nWDATA Write Data Width Low nDS0-1, MTRO-1 from End of nIOW MIN TYP 4 24 96 132 20 2 40 .5 25 MAX UNITS X* X* X* X* X* X* ns Y* ns *X specifies one MCLK period and Y specifies one WCLK period. MCLK = 16 x Data Rate (at 500 kb/s MCLK = 8 MHz) WCLK = 2 x Data Rate (at 500 kb/s WCLK = 1 MHz) 237 SERIAL PORT nIOW t1 nRTSx, nDTRx t5 IRQx nCTSx, nDSRx, nDCDx t2 IRQx nIOW t4 t6 t3 IRQx nIOR nRIx FIGURE 21 - SERIAL PORT TIMING TABLE 100 - SERIAL PORT TIMING NAME t1 t2 t3 t4 t5 t6 DESCRIPTION nRTSx, nDTRx Delay from nIOW IRQx Active Delay from nCTSx, nDSRx, nDCDx IRQx Inactive Delay from nIOR (Leading Edge) IRQx Inactive Delay from nIOW (Trailing Edge) IRQx Inactive Delay from nIOW IRQx Active Delay from nRIx 10 MIN TYP MAX 200 100 120 125 100 100 UNITS ns ns ns ns ns ns 238 Parallel Port PD0- PD7 t6 nIOW nINIT, nSTROBE. nAUTOFD, SLCTIN nACK t2 nPINTR (SPP) t1 PINTR (ECP or EPP Enabled) nFAULT (ECP) nERROR (ECP) t5 t2 PINTR t3 t4 t3 FIGURE 22 - PARALLEL PORT TIMING TABLE 101 - PARALLEL PORT TIMING NAME t1 t2 t3 t4 t5 t6 Note DESCRIPTION PD0-7, nINIT, nSTROBE, nAUTOFD Delay from nIOW PINTR Delay from nACK, nFAULT PINTR Active Low in ECP and EPP Modes PINTR Delay from nACK nERROR Active to PINTR Active PD0 - PD7 Delay from IOW Active PINTR refers to the IRQ used by the parallel port. 200 MIN TYP MAX 100 60 300 105 105 100 UNITS ns ns ns ns ns ns 239 EPP 1.9 Data or Address Write Cycle t18 A0-A10 t9 SD nIOW IOCHRDY t13 t22 t20 t1 PD t14 t16 t3 t4 t17 t8 t10 t11 t12 t19 nWRITE t2 t5 nDATAST nADDRSTB t6 nWAIT PDIR t21 t15 t7 FIGURE 23 - EPP 1.9 DATA OR ADDRESS WRITE CYCLE See timing parameters on next page. 240 TABLE 102 - EPP 1.9 DATA OR ADDRESS WRITE CYCLE TIMING NAME t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 DESCRIPTION nIOW Asserted to PDATA Valid nWAIT Asserted to nWRITE Change (Note 1) nWRITE to Command Asserted nWAIT Deasserted to Command Deasserted (Note 1) nWAIT Asserted to PDATA Invalid (Note 1) Time Out Command Deasserted to nWAIT Asserted SDATA Valid to nIOW Asserted nIOW Deasserted to DATA Invalid nIOW Asserted to IOCHRDY Asserted nWAIT Deasserted to IOCHRDY Deasserted (Note 1) IOCHRDY Deasserted to nIOW Deasserted nIOW Asserted to nWRITE Asserted nWAIT Asserted to Command Asserted (Note 1) Command Asserted to nWAIT Deasserted PDATA Valid to Command Asserted Ax Valid to nIOW Asserted nIOW Asserted to Ax Invalid nIOW Deasserted to nIOW or nIOR Asserted nWAIT Asserted to nWRITE Asserted (Note 1) nWAIT Asserted to PDIR Low PDIR Low to nWRITE Asserted MIN 0 60 5 60 0 10 0 10 0 0 60 10 0 60 0 10 40 10 40 60 0 0 185 70 210 10 24 160 12 TYP MAX 50 185 35 190 UNITS ns ns ns ns ns s ns ns ns ns ns ns ns ns s ns ns ns ns ns ns ns Note 1: nWAIT must be filtered to compensate for ringing on the parallel bus cable. WAIT is considered to have settled after it does not transition for a minimum of 50 nsec. 241 EPP 1.9 Data or Address Read Cycle t20 A0-A10 IOR t19 t13 SD t8 t24 t23 PDIR t9 t21 nWRITE t2 t25 PD t28 t26 t1 DATASTB ADDRSTB t15 t7 nWAIT t6 t14 t3 t5 PData bus driven by peripheral t11 t12 t18 t10 t22 IOCHRDY t27 t17 t4 t16 FIGURE 24 - EPP 1.9 DATA OR ADDRESS READ CYCLE See timing parameters on next page 242 NAME t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 t26 t27 t28 Note 1 Note 2 Note 3 TABLE 103 - EPP 1.9 DATA OR ADDRESS READ CYCLE TIMING DESCRIPTION MIN TYP MAX PDATA Hi-Z to Command Asserted nIOR Asserted to PDATA Hi-Z nWAIT Deasserted to Command Deasserted (Note 1) Command Deasserted to PDATA Hi-Z Command Asserted to PDATA Valid PDATA Hi-Z to nWAIT Deasserted PDATA Valid to nWAIT Deasserted nIOR Asserted to IOCHRDY Asserted nWRITE Deasserted to nIOR Asserted (Note 2) nWAIT Deasserted to IOCHRDY Deasserted (Note 1) IOCHRDY Deasserted to nIOR Deasserted nIOR Deasserted to SDATA Hi-Z (Hold Time) PDATA Valid to SDATA Valid nWAIT Asserted to Command Asserted Time Out nWAIT Deasserted to PDATA Driven (Note 1) nWAIT Deasserted to nWRITE Modified (Notes 1,2) SDATA Valid to IOCHRDY Deasserted (Note 3) Ax Valid to nIOR Asserted nIOR Deasserted to Ax Invalid nWAIT Asserted to nWRITE Deasserted nIOR Deasserted to nIOW or nIOR Asserted nWAIT Asserted to PDIR Set (Note 1) PDATA Hi-Z to PDIR Set nWAIT Asserted to PDATA Hi-Z (Note 1) PDIR Set to Command nWAIT Deasserted to PDIR Low (Note 1) 0 0 60 0 0 0 0 0 0 60 0 0 0 0 10 60 60 0 40 10 0 40 60 0 60 0 60 180 20 180 185 10 185 40 75 195 12 190 190 85 160 24 30 50 180 UNITS ns ns ns ns ns s ns ns ns ns ns ns ns ns s ns ns ns ns ns ns ns ns ns ns ns ns ns nWRITE Deasserted to Command 1 nWAIT is considered to have settled after it does not transition for a minimum of 50 ns. When not executing a write cycle, EPP nWRITE is inactive high. 85 is true only if t7 = 0. 243 EPP 1.7 Data Or Address Write Cycle t18 A0-A10 t9 SD t17 t8 t6 t12 t10 t20 t19 nIOW IOCHRDY t13 nWRITE t1 PD t11 t2 t5 t16 t3 nDATAST nADDRSTB t4 t21 nWAIT PDIR FIGURE 25 - EPP 1.7 DATA OR ADDRESS WRITE CYCLE See timing parameters on next page. 244 NAME t1 t2 t3 t4 t5 t6 t8 t9 t10 t11 t12 t13 t16 t17 t18 t19 t20 t21 Note 1 Note 2 TABLE 104 - EPP 1.7 DATA OR ADDRESS WRITE CYCLE TIMING DESCRIPTION MIN TYP MAX nIOW Asserted to PDATA Valid Command Deasserted to nWRITE Change nWRITE to Command nIOW Deasserted to Command Deasserted (Note 2) Command Deasserted to PDATA Invalid Time Out SDATA Valid to nIOW Asserted nIOW Deasserted to DATA Invalid nIOW Asserted to IOCHRDY Asserted nWAIT Deasserted to IOCHRDY Deasserted IOCHRDY Deasserted to nIOW Deasserted nIOW Asserted to nWRITE Asserted PDATA Valid to Command Asserted Ax Valid to nIOW Asserted nIOW Deasserted to Ax Invalid nIOW Deasserted to nIOW or nIOR Asserted nWAIT Asserted to IOCHRDY Deasserted Command Deasserted to nWAIT Deasserted 0 10 0 10 40 10 100 45 50 35 50 10 10 0 0 24 40 12 0 0 5 50 40 35 50 UNITS ns ns ns ns ns s ns ns ns ns ns ns ns ns s ns ns ns nWRITE is controlled by clearing the PDIR bit to "0" in the control register before performing an EPP Write. The number is only valid if nWAIT is active when IOW goes active. 245 EPP 1.7 Data or Address Read Cycle t20 A0-A10 t15 t19 nIOR t13 SD t8 t3 IOCHRDY t10 t11 t22 t12 nWRITE t5 PD t23 nDATASTB nADDRSTB t2 t4 t21 nWAIT PDIR FIGURE 26 - EPP 1.7 DATA OR ADDRESS READ CYCLE See timing parameters on next page. 246 TABLE 105 - EPP 1.7 DAT OR ADDRESS READ CYCLE TIMING NAME t2 t3 t4 t5 t8 t10 t11 t12 t13 t15 t19 t20 t21 t22 t23 Note: DESCRIPTION nIOR Deasserted to Command Deasserted nWAIT Asserted to IOCHRDY Deasserted Command Deasserted to PDATA Hi-Z Command Asserted to PDATA Valid nIOR Asserted to IOCHRDY Asserted nWAIT Deasserted to IOCHRDY Deasserted IOCHRDY Deasserted to nIOR Deasserted nIOR Deasserted to SDATA High-Z (Hold Time) PDATA Valid to SDATA Valid Time Out Ax Valid to nIOR Asserted nIOR Deasserted to Ax Invalid Command Deasserted to nWAIT Deasserted nIOR Deasserted to nIOW or nIOR Asserted nIOR Asserted to Command Asserted 10 40 10 0 40 55 0 0 40 40 12 0 0 0 24 50 MIN TYP MAX 50 40 UNITS ns ns ns ns ns ns ns ns ns s ns ns ns ns ns WRITE is controlled by setting the PDIR bit to "1" in the control register before performing an EPP Read. 247 ECP PARALLEL PORT TIMING Parallel Port FIFO (Mode 101) The standard parallel port is run at or near the peak 500KBytes/sec allowed in the forward direction using DMA. The state machine does not examine nACK and begins the next transfer based on Busy. Refer to FIGURE 28. ECP Parallel Port Timing Reverse Data Transfer Phase The timing is designed to allow operation at approximately 2.0 Mbytes/sec over a 15ft cable. If a shorter cable is used then the bandwidth will increase. Forward-Idle When the host has no data to send it keeps HostClk (nStrobe) high and the peripheral will leave PeriphClk (Busy) low. Forward Data Transfer Phase The interface transfers data and commands from the host to the peripheral using an interlocked PeriphAck and HostClk. The peripheral may indicate its desire to send data to the host by asserting nPeriphRequest. The Forward Data Transfer Phase may be entered from the Forward-Idle Phase. While in the Forward Phase the peripheral may asynchronously assert the nPeriphRequest (nFault) to request that the channel be reversed. When the peripheral is not busy it sets PeriphAck (Busy) low. The host then sets HostClk (nStrobe) low when it is prepared to send data. The data must be stable for the specified setup time prior to the falling edge of HostClk. The peripheral then sets PeriphAck (Busy) high to acknowledge the handshake. The host then sets HostClk (nStrobe) high. The peripheral then accepts the data and sets PeriphAck (Busy) low, completing the transfer. This sequence is shown in FIGURE 28. The interface transfers data and commands from the peripheral to the host using an interlocked HostAck and PeriphClk. The Reverse Data Transfer Phase may be entered from the ReverseIdle Phase. After the previous byte has beed accepted the host sets HostAck (nALF) low. The peripheral then sets PeriphClk (nACK) low when it has data to send. The data must be stable for the specified setup time prior to the falling edge of PeriphClk. When the host is ready to accept a byte it sets HostAck (nALF) high to acknowledge the handshake. The peripheral then sets PeriphClk (nACK) high. After the host has accepted the data it sets HostAck (nALF) low, completing the transfer. This sequence is shown in FIGURE 29. Output Drivers To facilitate higher performance data transfer, the use of balanced CMOS active drivers for critical signals (Data, HostAck, HostClk, PeriphAck, PeriphClk) are used ECP Mode. Because the use of active drivers can present compatibility problems in Compatible Mode (the control signals, by tradition, are specified as open-collector), the drivers are dynamically changed from open-collector to totem-pole. The timing for the dynamic driver change is specified in the IEEE 1284 Extended Capabilities Port Protocol and ISA Interface Standard, Rev. 1.14, July 14, 1993, available from Microsoft. The dynamic driver change must be implemented properly to prevent glitching the outputs. The timing is designed to provide 3 cable round-trip times for data setup if Data is driven simultaneously with HostClk (nStrobe). Reverse-Idle Phase The peripheral has no data to send and keeps PeriphClk high. The host is idle and keeps HostAck low. 249 t6 t3 PDATA t1 t2 t5 nSTROBE t4 BUSY FIGURE 27 - PARALLEL PORT FIFO TIMING TABLE 106 - PARALLEL PORT FIFO TIMING NAME t1 t2 t3 t4 t5 t6 DESCRIPTION DATA Valid to nSTROBE Active nSTROBE Active Pulse Width DATA Hold from nSTROBE Inactive (Note 1) nSTROBE Active to BUSY Active BUSY Inactive to nSTROBE Active BUSY Inactive to PDATA Invalid (Note 1) 680 80 MIN 600 600 450 500 TYP MAX UNITS ns ns ns ns ns ns Note 1: The data is held until BUSY goes inactive or for time t3, whichever is longer. This only applies if another data transfer is pending. If no other data transfer is pending, the data is held indefinitely. 251 t3 nAUTOFD t4 PDATA t2 t1 t7 nSTROBE BUSY t6 t5 t6 t8 FIGURE 28 - ECP PARALLEL PORT FORWARD TIMING TABLE 107 - ECP PARALLEL PORT FORWARD TIMING NAME t1 t2 t3 t4 t5 t6 t7 t8 Note 1 Note 2 DESCRIPTION nAUTOFD Valid to nSTROBE Asserted PDATA Valid to nSTROBE Asserted BUSY Deasserted to nAUTOFD Changed (Notes 1,2) BUSY Deasserted to PDATA Changed (Notes 1,2) nSTROBE Deasserted to Busy Asserted nSTROBE Deasserted to Busy Deasserted BUSY Deasserted to nSTROBE Asserted (Notes 1,2) BUSY Asserted to nSTROBE Deasserted (Note 2) MIN 0 0 80 80 0 0 80 80 200 180 TYP MAX 60 60 180 180 UNITS ns ns ns ns ns ns ns ns Maximum value only applies if there is data in the FIFO waiting to be written out. BUSY is not considered asserted or deasserted until it is stable for a minimum of 75 to 130 ns. 252 t2 PDATA t1 t5 nACK t4 nAUTOFD t3 t4 t6 FIGURE 29 - ECP PARALLEL PORT REVERSE TIMING TABLE 108 - ECP PARALLEL PORT REVERSE TIMING NAME t1 t2 t3 t4 t5 t6 Note 1 Note 2 DESCRIPTION PDATA Valid to nACK Asserted nAUTOFD Deasserted to PDATA Changed nACK Asserted to nAUTOFD Deasserted (Notes 1,2) nACK Deasserted to nAUTOFD Asserted (Note 2) nAUTOFD Asserted to nACK Asserted nAUTOFD Deasserted to nACK Deasserted MIN 0 0 80 80 0 0 200 200 TYP MAX UNITS ns ns ns ns ns ns Maximum value only applies if there is room in the FIFO and terminal count has not been received. ECP can stall by keeping nAUTOFD low. nACK is not considered asserted or deasserted until it is stable for a minimum of 75 to 130 ns. 253 Serial Port Infrared Timing IRDA SIR RECEIVE DATA 0 t2 t1 1 0 1 0 0 1 1 0 1 1 t2 t1 IRRX n IRRX Parameter t1 t1 t1 t1 t1 t1 t1 t2 t2 t2 t2 t2 t2 t2 Pulse Width at Pulse Width at Pulse Width at Pulse Width at Pulse Width at Pulse Width at Pulse Width at Bit Time at Bit Time at Bit Time at Bit Time at Bit Time at Bit Time at Bit Time at min 1.4 1.4 1.4 1.4 1.4 1.4 1.4 typ 1.6 3.22 4.8 9.7 19.5 39 78 8.68 17.4 26 52 104 208 416 max 2.71 3.69 5.53 11.07 22.13 44.27 88.55 units µs µs µs µs µs µs µs µs µs µs µs µs µs µs 1. Receive Pulse Detection Criteria: A received pulse is considered received pulse is a minimum of 1 41µs 2. IRRX: L5, CRF1 Bit 0 nIRRX: L5, CRF1 Bit 0 = 0 FIGURE 30 - IRDA SIR RECEIVE TIMING 254 IRDA SIR TRANSMIT DAT A 0 t2 t1 1 0 1 0 0 1 1 0 1 1 t2 t1 IRT X n IRT X Parameter t1 t1 t1 t1 t1 t1 t1 t2 t2 t2 t2 t2 t2 t2 Pulse Width at 115kbaud Pulse Widt h at 57. 6kbaud Pulse Widt h at 38. 4kbaud Pulse Widt h at 19. 2kbaud Pulse Widt h at 9. 6kbaud Pulse Widt h at 4. 8kbaud Pulse Widt h at 2. 4kbaud Bit T ime at 115kbaud Bit Time at 57.6kbaud Bit Time at 38.4kbaud Bit Time at 19.2kbaud Bit Tim e at 9.6kbaud Bit Tim e at 4.8kbaud Bit Tim e at 2.4kbaud mi n 1.41 1.41 1.41 1.41 1.41 1.41 1.41 typ 1.6 3.22 4.8 9.7 19.5 39 78 8.68 17.4 26 52 104 208 416 max 2.71 3.69 5.53 11.07 22.13 44.27 88.55 u nits µs µs µs µs µs µs µs µs µs µs µs µs µs µs Notes: 1. IrDA @ 115k i s HPSIR com pati ble. IrDA @ 2400 wi ll al low compatibilit y with HP95LX and 48SX. 2. IRT X: L5, CRF 1 Bit 1 = 1 (default) nI RT X: L5, CRF1 Bit 1 = 0 FIGURE 31 - IRDA SIR TRANSMIT TIMING 255 ASK IR Receive DA A T 0 t1 IRRX n IRRX 1 t2 0 1 0 0 1 1 0 1 1 t3 M IRRX t5 nM IRRX t4 t6 Pa ramet er t1 t2 t3 t4 t5 t6 M odu lated Out put Bit T ime Off Bit Time M odu lated Outp ut " On" M odu lated Out put " Off" M odu lated Outp ut " On" M odu lated Out put " Off" min typ max units µs µs 0.8 0.8 0.8 0.8 1 1 1 1 1.2 1.2 1.2 1.2 µs µs µs µs Note s: 1 . IRRX: L 5, CRF 1 Bit 0 = 1 n IRRX: L5 , CRF 1 Bit 0 = 0 (de fault) M IRRX, nMI RRX are the mod ulate d ou tpu ts FIGURE 32 - AMPLITUDE SHIFT KEYED IR RECEIVE TIMING 256 ASK IR Transmit DATA 0 1 0 1 0 0 1 1 0 1 1 t1 IRTX n IRTX t2 t3 MIRTX t5 nMIRTX t4 t6 Parameter t1 t2 t3 t4 t5 t6 Modulated Output Bit Time Off Bit Time Modulated Output "On" Modulated Output "Off" Modulated Output "On" Modulated Output "Off" min typ max units µs µs 0.8 0.8 0.8 0.8 1 1 1 1 1.2 1.2 1.2 1.2 µs µs µs µs Notes: 1. IRTX: L5, CRF1 Bit 1 = 1 (default) nIRTX: L5, CRF1 Bit 1 = 0 MIRTX, nMIRTX are the modulated outputs FIGURE 33 - ASK IR TRANSMIT TIMING 257 D D1 102 3 65 103 DETAIL "A" R1 R2 0 L 4 3 64 L1 E E1 D1/4 5 e W E1/4 39 128 38 2 1 A A2 H 1 0.10 -CA1 0 SEE DETAIL "A" MIN A A1 A2 D D1 E E1 H 0.05 2.55 23.65 19.9 17.65 13.9 NOM 23.9 20 17.9 14 MAX 3.4 0.5 3.05 24.15 20.1 18.15 14.1 L L1 e 0 W R1 R2 MIN 0.65 NOM 0.8 1.95 0.5BSC MAX 0.95 0 0.1 0.13 0.13 7 0.3 0.3 Notes: 1) Coplanarity is 0.08 mm or 3.2 mils maximum. 2) Tolerance on the position of the leads is 0.080 mm maximum. 3) Package body dimensions D1 and E1 do not include the mold protrusion. Maximum mold protrusion is 0.25 mm. 4) Dimensions for foot length L measured at the gauge plane 0.25 mm above the seating plane. 5) Details of pin 1 identifier are optional but must be located within the zone indicated. 6) Controlling dimension: millimeter FIGURE 34 - 128 PIN QFP PACKAGE OUTLINE 257 80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123 Copyright © 2007 SMSC or its subsidiaries. All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. 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IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. FDC37B78x Rev. 02-09-07