FDC37B80X

FDC37B80x ADVANCE INFORMATION PC98/99 Compliant Enhanced Super I/O Controller with Keyboard/Mouse Wake-Up FEATURES • • • • 5 Volt Operation PC98, PC99 Compliant ISA Plug-and-Play Compatible Register Set Intelligent Auto Power Management Shadowed Write-Only Registers Programmable Wake-up Event Interface System Management Interrupt, Watchdog Timer 2.88MB Super I/O Floppy Disk Controller Licensed CMOS 765B Floppy Disk Controller Software and Register Compatible with SMSC's Proprietary 82077AA Compatible Core Supports One Floppy Drive Configurable Open Drain/Push-Pull Output Drivers Supports Vertical Recording Format 16-Byte Data FIFO 100% IBM® Compatibility Detects All Overrun and Underrun Conditions Sophisticated Power Control Circuitry (PCC) Including Multiple Powerdown Modes for Reduced Power Consumption DMA Enable Logic Data Rate and Drive Control Registers 480 Address, Up to 15 IRQ and Three DMA Options • • Floppy Disk Available on Parallel Port Pins Enhanced Digital Data Separator 2 Mbps, 1 Mbps, 500 Kbps, 300 Kbps, 250 Kbps Data Rates Programmable Precompensation Modes Keyboard Controller 8042 Software Compatible 8 Bit Microcomputer 2k Bytes of Program ROM 256 Bytes of Data RAM Four Open Drain Outputs Dedicated for Keyboard/Mouse Interface Asynchronous Access to Two Data Registers and One Status Register Supports Interrupt and Polling Access 8 Bit Counter Timer Port 92 Support Fast Gate A20 and KRESET Outputs 8042 P12, P16 and P17 Outputs Serial Ports Two Full Function Serial Ports High Speed NS16C550A Compatible UARTs with Send/Receive 16-Byte FIFOs Supports 230k and 460k Baud Programmable Baud Rate Generator Modem Control Circuitry 480 Address and 15 IRQ Options IrDA 1.0, HP-SIR, ASK IR Support • • • • • Multi-Mode™ Parallel Port with ChiProtect™ Standard Mode IBM PC/XT®, PC/AT®, and PS/2™ Compatible Bidirectional Parallel Port Enhanced Parallel Port (EPP) Compatible - EPP 1.7 and EPP 1.9 (IEEE 1284 Compliant) IEEE 1284 Compliant Enhanced Capabilities Port (ECP) ChiProtect Circuitry for Protection Against Damage Due to Printer PowerOn • • 480 Address, Up to 15 IRQ and Three DMA Options ISA Host Interface 16 Bit Address Qualification 8 Bit Data Bus IOCHRDY for ECP and IrCC Three 8 Bit DMA Channels Serial IRQ Interface Compatible with Serialized IRQ Support for PCI Systems PME Interface 100 Pin QFP Package 2 TABLE OF CONTENTS FEATURES ....................................................................................................................................... 1 GENERAL DESCRIPTION................................................................................................................. 4 DESCRIPTION OF PIN FUNCTIONS ................................................................................................ 6 DESCRIPTION OF MULTIFUNCTION PINS .................................................................................... 10 REFERENCE DOCUMENTS ........................................................................................................... 10 FUNCTIONAL DESCRIPTION ......................................................................................................... 12 SUPER I/O REGISTERS ................................................................................................................. 12 HOST PROCESSOR INTERFACE................................................................................................... 12 FLOPPY DISK CONTROLLER ........................................................................................................ 13 FDC INTERNAL REGISTERS.......................................................................................................... 13 COMMAND SET/DESCRIPTIONS ................................................................................................... 36 INSTRUCTION SET ........................................................................................................................ 39 INFRARED INTERFACE.................................................................................................................. 80 PARALLEL PORT............................................................................................................................ 81 IBM XT/AT COMPATIBLE, BI-DIRECTIONAL AND EPP MODES .................................................... 83 EXTENDED CAPABILITIES PARALLEL PORT ................................................................................ 89 PARALLEL PORT FLOPPY DISK CONTROLLER...........................................................................102 POWER MANAGEMENT................................................................................................................104 VTR SUPPORT ................................................................................................................................104 SERIAL IRQ ...................................................................................................................................110 GP INDEX REGISTERS .................................................................................................................115 WATCH DOG TIMER .....................................................................................................................117 8042 KEYBOARD CONTROLLER DESCRIPTION ..........................................................................118 SYSTEM MANAGEMENT INTERRUPT (SMI) .................................................................................127 PME SUPPORT..............................................................................................................................127 CONFIGURATION..........................................................................................................................128 OPERATIONAL DESCRIPTION......................................................................................................158 MAXIMUM GUARANTEED RATINGS .............................................................................................158 DC ELECTRICAL CHARACTERISTICS ..........................................................................................158 TIMING DIAGRAMS .......................................................................................................................163 ECP PARALLEL PORT TIMING......................................................................................................184 80 Arkay Drive Hauppauge, NY 11788 (516) 435-6000 FAX (516) 273-3123 3 GENERAL DESCRIPTION The FDC37B80x with IrDA v1.0 support incorporates a keyboard interface, SMSC's true CMOS 765B floppy disk controller, advanced digital data separator, two 16C550A compatible UARTs, one Multi-Mode parallel port which includes ChiProtect circuitry plus EPP and ECP, on-chip 12 mA AT bus drivers, one floppy direct drive support, and Intelligent Power Management including PME support. The true CMOS 765B core provides 100% compatibility with IBM PC/XT and PC/AT architectures in addition to providing data overflow and underflow protection. The SMSC advanced digital data separator incorporates SMSC's patented data separator technology, allowing for ease of testing and use. Both on-chip UARTs are compatible with the NS16C550A. The parallel port is compatible with IBM PC/AT architecture, as well as IEEE 1284 EPP and ECP. The FDC37B80x incorporates sophisticated power control circuitry (PCC) which includes support for keyboard, mouse, and modem ring wake-up events. The PCC supports multiple low power-down modes. The FDC37B80x supports the ISA Plug-andPlay Standard (Version 1.0a) and provides the recommended functionality to support Windows '95. The I/O Address, DMA Channel and hardware IRQ of each logical device in the FDC37B80x may be reprogrammed through the internal configuration registers. There are 480 I/O address location options, a Serialized IRQ interface, and three DMA channels. The FDC37B80x does not require any external filter components and is therefore easy to use and offers lower system costs and reduced board area. The FDC37B80x is software and register compatible with SMSC's proprietary 82077AA core. IBM, PC/XT and PC/AT are registered trademarks and PS/2 is a trademark of International Business Machines Corporation SMSC is a registered trademark and Ultra I/O, ChiProtect, and Multi-Mode are trademarks of Standard Microsystems Corporation 4 PIN CONFIGURATION DRVDEN0 DRVDEN1 nMTR0 nPME nDS0 P17 VSS nDIR nSTEP nWDATA nWGATE nHDSEL nINDEX nTRK0 nWPRT nRDATA nDSKCHG VTR CLOCKI nCS/SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 nDTR2/SA14 nCTS2/SA13 nRTS2/SA12 nDSR2/SA15 TXD2/IRTX RXD2/IRRX nDCD2/P12 VCC nRI2/P16 nDCD1 nRI1 nDTR1 nCTS1 nRTS1/SYSOP nDSR1 TXD1 RXD1 nALF nSTROBE BUSY FDC37B80x 100 PIN QFP 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PE SLCT nERROR nACK VSS PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 nINIT nSLCTIN VCC KBRST A20M IRTX2 IRRX2 VSS KDAT KCLK MDAT MCLK IOCHRDY TC VCC DRQ3/P12 nDACK3/P16 SA0 PCICLK SERIRQ AEN nIOR nIOW SD7 SD6 SD5 SD4 VSS SD3 SD2 SD1 SD0 RESET 5 nDACK1 DRQ1 nDACK2 DRQ2 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 DESCRIPTION OF PIN FUNCTIONS PIN No./QFP NAME System Data Bus 11-bit System Address Bus Chip Select/SA11 (Note 1) Address Enable I/O Channel Ready ISA Reset Drive Serial IRQ PCI Clock for Serial IRQ (33MHz/30MHz) DMA Request 1 DMA Request 2 DMA Request 3/8042 P12 DMA Acknowledge 1 DMA Acknowledge 2 DMA Acknowledge 3/8042 P16 Terminal Count I/O Read I/O Write Power Management Event 8042 - P17 (Note 5) CLOCKS (1) 19 61 62 53,65, 93 7,41, 60,76 14.318MHz Clock Input Infrared Rx Infrared Tx (Note 4) POWER PINS (8) Power Ground VCC VSS 1 1 1 CLOCKI IRRX IRTX ICLK I O24PD INFRARED INTERFACE (2) TOTAL 8 11 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 SYMBOL SD[0:7] SA[0:10] nCS/SA11 AEN IOCHRDY RESET_DRV SER_IRQ PCI_CLK DRQ1 DRQ2 DRQ3/P12 nDACK1 nDACK2 nDACK3/ P16 TC nIOR nIOW nPME P17 BUFFER TYPE PROCESSOR/HOST INTERFACE (36) 45:42, 40:37 31:21 20 34 55 46 33 32 48 50 52 47 49 51 54 35 36 4 6 IO12 I I I OD12 IS IO12 ICLK O12 O12 O12/IO12 I I I/IO12 I I I OD24 IO8 6 DESCRIPTION OF PIN FUNCTIONS PIN No./QFP 18 16 11 10 12 8 9 17 5 3 15 14 13 1 2 84 85 87 88 89 86 91 90 95 96 98 99 100 97 94 Trickle Voltage FDD INTERFACE (14) Read Disk Data 1 Write Gate 1 Write Disk Data 1 Head Select 1 Step Direction 1 Step Pulse 1 Disk Change 1 Drive Select 0 1 Motor On 0 1 Write Protected 1 Track 0 1 Index Pulse Input 1 Drive Density Select 0 1 Drive Density Select 1 1 SERIAL PORT 1 INTERFACE (8) Receive Serial Data 1 1 Transmit Serial Data 1 1 Request to Send 1 1 Clear to Send 1 1 Data Terminal Ready 1 1 Data Set Ready 1 1 Data Carrier Detect 1 1 Ring Indicator 1 1 SERIAL PORT 2 INTERFACE (8) Receive Serial Data 2/Infrared Rx 1 Transmit Serial Data 2/Infrared Tx (Note 4) 1 Request to Send 2/Sys Addr 12 1 Clear to Send 2/Sys Addr 13 1 Data Terminal Ready/Sys Addr 14 1 Data Set Ready 2/Sys Addr 15 Data Carrier Detect 2/8042 P12 7 1 1 nRDATA nWGATE nWDATA nHDSEL nDIR nSTEP nDSKCHG nDS0 nMTR0 nWRTPRT nTRKO nINDEX DRVDEN0 DRVDEN1 RXD1 TXD1 nRTS1/ SYSOP nCTS1 nDTR1 nDSR1 nDCD1 nRI1 RXD2/IRRX TXD2/IRTX nRTS2/SA12 nCTS2/SA13 nDTR2/ SA14 nDSR2/ SA15 nDCD2/P12 IS O24/OD24 O24/OD24 O24/OD24 O24/OD24 O24/OD24 IS O24/OD24 O24/OD24 IS IS IS O24/OD24 O24/OD24 I O4 O4/I I O4 I I I I O24PD O4/I I/I O4/I I/I I/IO24 NAME TOTAL SYMBOL VTR BUFFER TYPE DESCRIPTION OF PIN FUNCTIONS PIN No./QFP 92 75:68 66 67 83 82 81 77 80 79 78 59 58 57 56 64 63 Note 1: NAME Ring Indicator 2/8042 P16 TOTAL 1 SYMBOL nRI2/P16 PD[0:7] nSLCTIN nINIT nALF nSTROBE BUSY nACK PE SLCT nERROR KDAT KCLK MDAT MCLK KBDRST (Note 3) A20M BUFFER TYPE I/IO24 IO24 OD24/O24 OD24/O24 OD24/O24 OD24/O24 I I I I I IOD16 IOD16 IOD16 IOD16 O4 O4 PARALLEL PORT INTERFACE (17) Parallel Port Data Bus 8 Printer Select 1 Initiate Output 1 Auto Line Feed 1 Strobe Signal 1 Busy Signal 1 Acknowledge Handshake 1 Paper End 1 Printer Selected 1 Error at Printer 1 KEYBOARD/MOUSE INTERFACE (6) Keyboard Data 1 Keyboard Clock 1 Mouse Data 1 Mouse Clock 1 Keyboard Reset 1 Gate A20 1 Note 2: Note 3: Note 4: Note 5: For 12 bit addressing, SA0:SA11 only, nCS should be tied to GND. For 16 bit external address qualification, address bits SA11:SA15 can be "ORed" together and applied to nCS. The nCS pin functions as SA11 in full 16 bit Internal Address Qualification Mode. CR24.6 controls the FDC37B80x addressing modes. The "n" as the first letter of a signal name indicates an "Active Low" signal. KBDRST is active low. The pull-down on this pin is always active including when the output driver is tristated and regardless of the state of internal PWRGOOD. Requires external pull-up resistor. 8 Buffer Type Descriptions I IS IOD16 IO24 IO4 O4 O24 OD24 IO8 ICLK IO12 O12 OD12 O24PD Input, TTL compatible Input with Schmitt trigger Input/Output, 16mA sink Input/Output, 24mA sink, 12mA source Input/Output, 4mA sink, 2mA source Output, 4mA sink, 2mA source Output, 24mA sink, 12mA source Output, Open Drain, 24mA sink Input/Output, 8mA sink, 4mA source Clock Input Input/Output, 12mA sink, 6mA source Output, 12mA sink, 6mA source Output, Open Drain, 12 mA sink Output, 12mA sink, 6mA source with 30 µA pull-down 9 DESCRIPTION OF MULTIFUNCTION PINS PIN ORIGINAL ALTERNATE NO./QFP FUNCTION FUNCTION 1 DEFAULT nDACK3 8042 P16 nDACK3 51 DRQ3 8042 P12 DRQ3 52 nRI2 8042 P16 nRI2 92 nDCD2 8042 P12 nDCD2 94 RXD2 IRRX RXD2 95 TXD2 IRTX TXD2 96 nDSR2 SA15 nDSR2 97 nRTS2 SA12 nRTS2 98 nCTS2 SA13 nCTS2 99 nDTR2 SA14 nDTR2 100 Controlled by DMA3SEL(LD8:CRC0.1) Controlled by 8042COMSEL(LD8:CRC0.3) Controlled by IR Option Register( LD5:CRF1.6) Controlled by 16 bit Address Qualification (CR24.6) NOTE 1 1 2 2 3 3 4 4 4 4 Note 1: Note 2: Note 3: Note 4: For more information, refer to tables 63 through 73. REFERENCE DOCUMENTS 1. 2. 3. IEEE 1284 Extended Capabilities Port Protocol and ISA Standard, Rev. 1.14, July 14, 1993. Hardware Description of the 8042, Intel 8 bit Embedded Controller Handbook. PCI Bus Power Management Interface Specification, Rev. 1.0, Draft, March 18, 1997. 10 nPME SMI PME WDT MULTI-MODE PARALLEL PORT/FDC MUX PD0-7 BUSY, SLCT, PE, nERROR, nACK nSTB, nSLCTIN, nINIT, nALF ADDRESS BUS DATA BUS SER_IRQ PCI_CLK SERIAL IRQ nIOR nIOW AEN * CONFIGURATION REGISTERS 16C550 COMPATIBLE SERIAL PORT 1 TXD1, nCTS1, nRTS1 RXD1 nDSR1, nDCD1, nRI1, nDTR1 SA[0:12] (nCS) * CONTROL BUS HOST CPU INTERFACE WDATA WCLOCK SA[13-15] SD[O:7] * DRQ[1:3] nDACK[1:3] TC RESET_DRV IOCHRDY RDATA * 16C550 COMPATIBLE SERIAL PORT 2 WITH INFRARED IRRX, IRTX * TXD2(IRTX), nCTS2, nRTS2 * RXD2(IRRX) * nDSR2, nDCD2, nRI2, nDTR2 SMSC PROPRIETARY DIGITAL DATA 82077 SEPARATOR COMPATIBLE WITH WRITE VERTICAL PRECOMFLOPPYDISK PENSATION CONTROLLER CORE RCLOCK 8042 CLOCK GEN nINDEX DENSEL nDS0 nTRK0 nDIR nMTR0 nWDATAnRDATA nDSKCHG nSTEP DRVDEN0 nWRPRT * nHDSEL DRVDEN1 nWGATE KCLK KDATA MCLK MDATA GATEA20, KRESET P12*, P16* VTR Vcc Vss *Denotes Multifunction Pins CLOCKI 14MHz FIGURE 1 - FDC37B80x BLOCK DIAGRAM 11 FUNCTIONAL DESCRIPTION SUPER I/O REGISTERS The address map, shown below in Table 1, shows the addresses of the different blocks of the Super I/O immediately after power up. The base addresses of the FDC, serial and parallel ports can be moved via the configuration registers. Some addresses are used to access more than one register. HOST PROCESSOR INTERFACE The host processor communicates with the FDC37B80x through a series of read/write registers. The port addresses for these registers are shown in Table 1. Register access is accomplished through programmed I/O or DMA transfers. All registers are 8 bits wide. All host interface output buffers are capable of sinking a minimum of 12 mA. Table 1 - Super I/O Block Addresses LOGICAL ADDRESS BLOCK NAME DEVICE Base+(0-5) and +(7) Floppy Disk 0 Base+(0-7) Base1+(0-7) Base+(0-3) Base+(0-7) Base+(0-3), +(400-402) Base+(0-7), +(400-402) 60, 64 Serial Port Com 1 Serial Port Com 2 Parallel Port SPP EPP ECP ECP+EPP+SPP KYBD 4 5 3 NOTES IrDA 1.0 7 Note 1: Refer to the configuration register descriptions for setting the base address 12 FLOPPY DISK CONTROLLER The Floppy Disk Controller (FDC) provides the interface between a host microprocessor and the floppy disk drive. The FDC integrates the functions of the Formatter/Controller, Digital Data Separator, Write Precompensation and Data Rate Selection logic for an IBM XT/AT compatible FDC. The true CMOS 765B core guarantees 100% IBM PC XT/AT compatibility in addition to providing data overflow and underflow protection. The FDC is compatible to the 82077AA using SMSC's proprietary floppy disk controller core. FDC INTERNAL REGISTERS The Floppy Disk Controller contains eight internal registers which facilitate the interfacing between the host microprocessor and the disk drive. Table 2 shows the addresses required to access these registers. Registers other than the ones shown are not supported. The rest of the description assumes that the primary addresses have been selected. PRIMARY ADDRESS 3F0 3F1 3F2 3F3 3F4 3F4 3F5 3F6 3F7 3F7 Table 2 - Status, Data and Control Registers (Shown with base addresses of 3F0 and 370) SECONDARY ADDRESS R/W REGISTER 370 R Status Register A (SRA) 371 R Status Register B (SRB) 372 R/W Digital Output Register (DOR) 373 R/W Tape Drive Register (TSR) 374 R Main Status Register (MSR) 374 W Data Rate Select Register (DSR) 375 R/W Data (FIFO) 376 Reserved 377 R Digital Input Register (DIR) 377 W Configuration Control Register (CCR) 13 STATUS REGISTER A (SRA) Address 3F0 READ ONLY This register is read-only and monitors the state of the FINTR pin and several disk interface pins in PS/2 and Model 30 modes. The SRA can be accessed at any time when in PS/2 mode. In the PC/AT mode the data bus pins D0 - D7 are held in a high impedance state for a read of address 3F0. PS/2 Mode 7 INT PENDING 0 6 nDRV2 1 5 STEP 0 4 3 2 nTRK0 HDSEL nINDX N/A 0 N/A 1 nWP N/A 0 DIR 0 RESET COND. BIT 0 DIRECTION Active high status indicating the direction of head movement. A logic "1" indicates inward direction; a logic "0" indicates outward direction. BIT 1 nWRITE PROTECT Active low status of the WRITE PROTECT disk interface input. A logic "0" indicates that the disk is write protected. BIT 2 nINDEX Active low status of the INDEX disk interface input. BIT 3 HEAD SELECT Active high status of the HDSEL disk interface input. A logic "1" selects side 1 and a logic "0" selects side 0. BIT 4 nTRACK 0 Active low status of the TRK0 disk interface input. BIT 5 STEP Active high status of the STEP output disk interface output pin. BIT 6 nDRV2 Active low status of the DRV2 disk interface input pin, indicating that a second drive has been installed. Note: This function is not supported in the FDC37B80x. BIT 7 INTERRUPT PENDING Active high bit indicating the state of the Floppy Disk Interrupt output. 14 PS/2 Model 30 Mode 7 INT PENDING 0 6 DRQ 0 5 STEP F/F 0 4 3 TRK0 nHDSEL N/A 1 2 INDX N/A 1 WP N/A 0 nDIR 1 RESET COND. BIT 0 nDIRECTION Active low status indicating the direction of head movement. A logic "0" indicates inward direction; a logic "1" indicates outward direction. BIT 1 WRITE PROTECT Active high status of the WRITE PROTECT disk interface input. A logic "1" indicates that the disk is write protected. BIT 2 INDEX Active high status of the INDEX disk interface input. BIT 3 nHEAD SELECT Active low status of the HDSEL disk interface input. A logic "0" selects side 1 and a logic "1" selects side 0. BIT 4 TRACK 0 Active high status of the TRK0 disk interface input. BIT 5 STEP Active high status of the latched STEP disk interface output pin. This bit is latched with the STEP output going active, and is cleared with a read from the DIR register, or with a hardware or software reset. BIT 6 DMA REQUEST Active high status of the DRQ output pin. BIT 7 INTERRUPT PENDING Active high bit indicating the state of the Floppy Disk Interrupt output. 15 STATUS REGISTER B (SRB) Address 3F1 READ ONLY This register is read-only and monitors the state of several disk interface pins in PS/2 andModel 30 modes. The SRB can be accessed at any time when in PS/2 mode. In the PC/AT mode the data bus pins D0 - D7 are held in a high impedance state for a read of address 3F1. PS/2 Mode 7 1 RESET COND. 1 6 1 1 5 4 3 2 DRIVE WDATA RDATA WGATE SEL0 TOGGLE TOGGLE 0 0 0 0 1 MOT EN1 0 0 MOT EN0 0 BIT 0 MOTOR ENABLE 0 Active high status of the MTR0 disk interface output pin. This bit is low after a hardware reset and unaffected by a software reset. BIT 1 MOTOR ENABLE 1 Active high status of the MTR1 disk interface output pin. This bit is low after a hardware reset and unaffected by a software reset. Note: In the FDC37B80x only one drive is available at the FDD interface. BIT 2 WRITE GATE Active high status of the WGATE disk interface output. BIT 3 READ DATA TOGGLE Every inactive edge of the RDATA input causes this bit to change state. BIT 4 WRITE DATA TOGGLE Every inactive edge of the WDATA input causes this bit to change state. BIT 5 DRIVE SELECT 0 Reflects the status of the Drive Select 0 bit of the DOR (address 3F2 bit 0). This bit is cleared after a hardware reset and it is unaffected by a software reset. BIT 6 RESERVED Always read as a logic "1". BIT 7 RESERVED Always read as a logic "1". 16 PS/2 Model 30 Mode 7 nDRV2 RESET COND. N/A 6 nDS1 1 5 nDS0 1 4 WDATA F/F 0 3 RDATA F/F 0 2 WGATE F/F 0 1 nDS3 1 0 nDS2 1 BIT 0 nDRIVE SELECT 2 The DS2 disk interface is not supported in the FDC37B80x. BIT 1 nDRIVE SELECT 3 The DS3 disk interface is not supported in the FDC37B80x. BIT 2 WRITE GATE Active high status of the latched WGATE output signal. This bit is latched by the active going edge of WGATE and is cleared by the read of the DIR register. BIT 3 READ DATA Active high status of the latched RDATA output signal. This bit is latched by the inactive going edge of RDATA and is cleared by the read of the DIR register. BIT 4 WRITE DATA Active high status of the latched WDATA output signal. This bit is latched by the inactive going edge of WDATA and is cleared by the read of the DIR register. This bit is not gated with WGATE. BIT 5 nDRIVE SELECT 0 Active low status of the DS0 disk interface output. BIT 6 nDRIVE SELECT 1 Active low status of the DS1 disk interface output. BIT 7 nDRV2 Active low status of the DRV2 disk interface input. Note: This function is not supported in the FDC37B80x. 17 DIGITAL OUTPUT REGISTER (DOR) Address 3F2 READ/WRITE The DOR controls the drive select and motor enables of the disk interface outputs. It also contains the enable for the DMA logic and a software reset bit. The contents of the DOR are unaffected by a software reset. The DOR can be written to at any time. RESET COND. 7 MOT EN3 0 6 MOT EN2 0 5 MOT EN1 0 4 MOT EN0 0 3 2 1 0 DMAEN nRESE DRIVE DRIVE T SEL1 SEL0 0 0 0 0 BIT 0 and 1 DRIVE SELECT These two bits are binary encoded for the drive selects, thereby allowing only one drive to be selected at one time. BIT 2 nRESET A logic "0" written to this bit resets the Floppy disk controller. This reset will remain active until a logic "1" is written to this bit. This software reset does not affect the DSR and CCR registers, nor does it affect the other bits of the DOR register. The minimum reset duration required is 100ns, therefore toggling this bit by consecutive writes to this register is a valid method of issuing a software reset. BIT 3 DMAEN PC/AT and Model 30 Mode: Writing this bit to logic "1" will enable the DRQ, nDACK, TC and FINTR outputs. This bit being a logic "0" will disable the nDACK and TC inputs, and hold the DRQ and FINTR outputs in a high impedance state. This bit is a logic "0" after a reset and in these modes. PS/2 Mode: In this mode the DRQ, nDACK, TC and FINTR pins are always enabled. During a reset, the DRQ, nDACK, TC, and FINTR pins will remain enabled, but this bit will be cleared to a logic "0". BIT 4 MOTOR ENABLE 0 This bit controls the MTR0 disk interface output. A logic "1" in this bit will cause the output pin to go active. BIT 5 MOTOR ENABLE 1 This bit controls the MTR1 disk interface output. A logic "1" in this bit will cause the output pin to go active. BIT 6 MOTOR ENABLE 2 The MTR2 disk interface output is not supported in the FDC37B80x. BIT 7 MOTOR ENABLE 3 The MTR3 disk interface output is not supported in the FDC37B80x. Table 3 - Drive Activation Values DRIVE 0 1 DOR VALUE 1CH 2DH 18 TAPE DRIVE REGISTER (TDR) Address 3F3 READ/WRITE The Tape Drive Register (TDR) is included for 82077 software compatibility and allows the user to assign tape support to a particular drive during initialization. Any future references to that drive automatically invokes tape support. The TDR Tape Select bits TDR.[1:0] determine the tape drive number. Table 4 illustrates the Tape Select Bit encoding. Note that drive 0 is the boot device and cannot be assigned tape support. The remaining Tape Drive Register bits TDR.[7:2] are tristated when read. The TDR is unaffected by a software reset. TAPE SEL1 (TDR.1) 0 0 1 1 Table 4 - Tape Select Bits TAPE SEL0 DRIVE SELECTED (TDR.0) None 0 1 1 2 0 3 1 Table 5 - Internal 2 Drive Decode - Normal DRIVE SELECT MOTOR ON OUTPUTS DIGITAL OUTPUT REGISTER OUTPUTS (ACTIVE LOW) (ACTIVE LOW) Bit 7 Bit 6 Bit 5 Bit 4 Bit1 Bit 0 nDS1 nDS0 nMTR1 nMTR0 X X X 1 0 X X 1 X 0 X 1 X X 0 1 X X X 0 0 0 1 1 X 0 1 0 1 X 1 0 1 1 1 0 1 1 1 1 nBIT 5 nBIT 5 nBIT 5 nBIT 5 nBIT 5 nBIT 4 nBIT 4 nBIT 4 nBIT 4 nBIT 4 Table 6 - Internal 2 Drive Decode - Drives 0 and 1 Swapped DRIVE SELECT OUTPUTS MOTOR ON OUTPUTS DIGITAL OUTPUT REGISTER (ACTIVE LOW) (ACTIVE LOW) Bit 7 Bit 6 Bit 5 Bit 4 Bit1 Bit 0 nDS1 nDS0 nMTR1 nMTR0 X X X 1 0 X X 1 X 0 X 1 X X 0 1 X X X 0 0 0 1 1 X 0 1 0 1 X 0 1 1 1 1 1 0 1 1 1 nBIT 4 nBIT 4 nBIT 4 nBIT 4 nBIT 4 nBIT 5 nBIT 5 nBIT 5 nBIT 5 nBIT 5 19 Normal Floppy Mode Normal mode. Register 3F3 contains only bits 0 and 1. When this register is read, bits 2 - 7 are a high impedance. DB7 REG 3F3 Tri-state DB6 Tri-state DB5 Tri-state DB4 Tri-state DB3 Tri-state DB2 Tri-state DB1 tape sel1 DB0 tape sel0 Enhanced Floppy Mode 2 (OS2) Register 3F3 for Enhanced Floppy Mode 2 operation. DB7 DB6 DB5 DB4 DB3 DB2 DB1 tape sel1 DB0 tape sel0 REG 3F3 Reserved Reserved Drive Type ID Floppy Boot Drive Table 7 - Drive Type ID DIGITAL OUTPUT REGISTER REGISTER 3F3 - DRIVE TYPE ID Bit 1 0 0 1 1 Note: Bit 0 0 1 0 1 Bit 5 L0-CRF2 - B1 L0-CRF2 - B3 L0-CRF2 - B5 L0-CRF2 - B7 Bit 4 L0-CRF2 - B0 L0-CRF2 - B2 L0-CRF2 - B4 L0-CRF2 - B6 L0-CRF2-Bx = Logical Device 0, Configuration Register F2, Bit x. 20 DATA RATE SELECT REGISTER (DSR) Address 3F4 WRITE ONLY This register is write only. It is used to program the data rate, amount of write precompensation, power down status, and software reset. The data rate is programmed using the Configuration Control Register (CCR) not the DSR, for PC/AT and PS/2 Model 30 and Microchannel applications. Other applications can set the data rate in the DSR. The data rate of the floppy controller is the most recent write of either the DSR or CCR. The DSR is unaffected by a software reset. A hardware reset will set the DSR to 02H, which corresponds to the default precompensation setting and 250 Kbps. RESET COND. 7 6 S/W POWER RESET DOWN 0 0 5 0 0 4 PRECOMP2 0 3 PRECOMP1 0 2 1 0 PRE- DRATE DRATE COMP0 SEL1 SEL0 0 1 0 BIT 0 and 1 DATA RATE SELECT These bits control the data rate of the floppy controller. See Table 11 for the settings corresponding to the individual data rates. The data rate select bits are unaffected by a software reset, and are set to 250 Kbps after a hardware reset. BIT 2 through 4 PRECOMPENSATION SELECT These three bits select the value of write precompensation that will be applied to the WDATA output signal. Table 10 shows the precompensation values for the combination of these bits settings. Track 0 is the default starting track number to start precompensation. this starting track number can be changed by the configure command. BIT 5 UNDEFINED Should be written as a logic "0". BIT 6 LOW POWER A logic "1" written to this bit will put the floppy controller into manual low power mode. The floppy controller clock and data mode after a software reset or access to the Data Register or Main Status Register. BIT 7 SOFTWARE RESET This active high bit has the same function as the DOR RESET (DOR bit 2) except that this bit is self clearing. Note: The DSR is Shadowed in the Floppy Data Rate Select Shadow Register, LD8:CRC2[7:0]. separator circuits will be turned off. The controller will come out of manual low power. 21 Table 8 - Precompensation Delays PRECOMP 432 111 001 010 011 100 101 110 000 PRECOMPENSATION DELAY (nsec)