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FDC37M817-MS

FDC37M817-MS

  • 厂商:

    SMSC

  • 封装:

  • 描述:

    FDC37M817-MS - PC98/99 Compliant Enhanced Super I/O Controller with Keyboard/Mouse Wake-Up - SMSC Co...

  • 数据手册
  • 价格&库存
FDC37M817-MS 数据手册
FDC37M81x PC98/99 Compliant Enhanced Super I/O Controller with Keyboard/Mouse Wake-Up FEATURES • • • • 5 Volt Operation PC98, PC99 Compliant ISA Plug-and-Play Compatible Register Set Intelligent Auto Power Management Shadowed Write-Only Registers Programmable Wake-up Event Interface System Management Interrupt, Watchdog Timer 2.88MB Super I/O Floppy Disk Controller Licensed CMOS 765B Floppy Disk Controller Software and Register Compatible with SMSC's Proprietary 82077AA Compatible Core Supports One Floppy Drive Configurable Open Drain/Push-Pull Output Drivers Supports Vertical Recording Format 16-Byte Data FIFO 100% IBM Compatibility Detects All Overrun and Underrun Conditions Sophisticated Power Control Circuitry (PCC) Including Multiple Powerdown Modes for Reduced Power Consumption DMA Enable Logic Data Rate and Drive Control Registers 480 Address, Up to 15 IRQ and Three DMA Options • • Floppy Disk Available on Parallel Port Pins Enhanced Digital Data Separator 2 Mbps, 1 Mbps, 500 Kbps, 300 Kbps, 250 Kbps Data Rates Programmable Precompensation Modes Keyboard Controller 8042 Software Compatible 8 Bit Microcomputer 2k Bytes of Program ROM 256 Bytes of Data RAM Four Open Drain Outputs Dedicated for Keyboard/Mouse Interface Asynchronous Access to Two Data Registers and One Status Register Supports Interrupt and Polling Access 8 Bit Counter Timer Port 92 Support Fast Gate A20 and KRESET Outputs 8042 P12, P16 and P17 Outputs Serial Ports Two Full Function Serial Ports High Speed NS16C550A Compatible UARTs with Send/Receive 16-Byte FIFOs Supports 230k and 460k Baud Programmable Baud Rate Generator Modem Control Circuitry 480 Address and 15 IRQ Options IrDA 1.0, HP-SIR, ASK IR Support • • • • • Multi-Mode Parallel Port with ChiProtect Standard Mode IBM PC/XT PC/AT, and PS/2 Compatible Bidirectional Parallel Port Enhanced Parallel Port (EPP) Compatible - EPP 1.7 and EPP 1.9 (IEEE 1284 Compliant) IEEE 1284 Compliant Enhanced Capabilities Port (ECP) ChiProtect Circuitry for Protection Against Damage Due to Printer PowerOn • • 480 Address, Up to 15 IRQ and Three DMA Options ISA Host Interface 16 Bit Address Qualification 8 Bit Data Bus IOCHRDY for ECP and IrCC Three 8 Bit DMA Channels Serial IRQ Interface Compatible with Serialized IRQ Support for PCI Systems PME Interface 100 Pin QFP Lead-free RoHS Compliant Package Order Number: FDC37M817-MS for 100 pin, QFP Lead-free RoHS Compliant Package GENERAL DESCRIPTION The FDC37M81x* with IrDA v1.0 support incorporates a keyboard interface, SMSC's true CMOS 765B floppy disk controller, advanced digital data separator, two 16C550A compatible UARTs, one Multi-Mode parallel port which includes ChiProtect circuitry plus EPP and ECP, on-chip 12 mA AT bus drivers, one floppy direct drive support, and Intelligent Power Management including PME support. The true CMOS 765B core provides 100% compatibility with IBM PC/XT and PC/AT architectures in addition to providing data overflow and underflow protection. The SMSC advanced digital data separator incorporates SMSC's patented data separator technology, allowing for ease of testing and use. Both on-chip UARTs are compatible with the NS16C550A. The parallel port is compatible with IBM PC/AT architecture, as well as IEEE 1284 EPP and ECP. The FDC37M81x incorporates sophisticated power control circuitry (PCC) which includes support for keyboard, mouse, and modem ring wake-up events. The PCC supports multiple low power-down modes. The FDC37M81x supports the ISA Plug-and-Play Standard (Version 1.0a) and provides the recommended functionality to support Windows '95/’98. The I/O Address, DMA Channel and hardware IRQ of each logical device in the FDC37M81x may be reprogrammed through the internal configuration registers. There are 480 I/O address location options, a Serialized IRQ interface, and three DMA channels. The FDC37M81x does not require any external filter components and is therefore easy to use and offers lower system costs and reduced board area. The FDC37M81x is software and register compatible with SMSC's proprietary 82077AA core. *The “x” in the part number is a designator that changes depending upon the particular BIOS used inside the specific chip. “2” denotes AMI Keyboard BIOS and “7” denotes Phoenix 42i Keyboard BIOS. 2 TABLE OF CONTENTS FEATURES.............................................................................................................................................. 1 GENERAL DESCRIPTION ...................................................................................................................... 2 PIN CONFIGURATION............................................................................................................................ 5 DESCRIPTION OF PIN FUNCTIONS ..................................................................................................... 6 Buffer Type Descriptions ..................................................................................................................... 9 Description of Multifunction Pins ........................................................................................................10 REFERENCE DOCUMENTS..................................................................................................................10 POWER FUNCTIONALITY ....................................................................................................................12 VCC Power ........................................................................................................................................12 VTR Support ......................................................................................................................................12 Internal PWRGOOD...........................................................................................................................12 Trickle Power Functionality ................................................................................................................13 Maximum Current Values...................................................................................................................13 Power Management Events (PME/SCI) .............................................................................................13 FUNCTIONAL DESCRIPTION ...............................................................................................................14 Super I/O Registers............................................................................................................................14 Host Processor Interface....................................................................................................................14 FLOPPY DISK CONTROLLER ..............................................................................................................15 FDC Internal Registers.......................................................................................................................15 Command Set/Descriptions................................................................................................................38 Instruction Set ....................................................................................................................................41 SERIAL PORT (UART)...........................................................................................................................68 INFRARED INTERFACE ........................................................................................................................82 PARALLEL PORT ..................................................................................................................................83 IBM XT/AT Compatible, Bi-Directional And Epp Modes .......................................................................85 Extended Capabilities Parallel Port......................................................................................................91 PARALLEL PORT FLOPPY DISK CONTROLLER .............................................................................104 POWER MANAGEMENT .....................................................................................................................106 SERIAL IRQ .........................................................................................................................................112 GP INDEX REGISTERS .......................................................................................................................116 WATCH DOG TIMER ...........................................................................................................................118 8042 KEYBOARD CONTROLLER DESCRIPTION .............................................................................119 Latches On Keyboard And Mouse IRQs ..........................................................................................128 Keyboard and Mouse PME Generation............................................................................................129 3 SYSTEM MANAGEMENT INTERRUPT (SMI) .....................................................................................131 PME SUPPORT....................................................................................................................................132 CONFIGURATION................................................................................................................................133 OPERATIONAL DESCRIPTION ..........................................................................................................164 Maximum Guaranteed Ratings.........................................................................................................164 DC Electrical Characteristics............................................................................................................164 TIMING DIAGRAMS .............................................................................................................................169 4 PIN CONFIGURATION nDTR2/SA14 nCTS2/SA13 nRTS2/SA12 nDSR2/SA15 TXD2/IRTX RXD2/IRRX nDCD2/P12 VCC nRI2/P16 nDCD1 nRI1 nDTR1 nCTS1 nRTS1/SYSOPT nDSR1 TXD1 RXD1 nALF nSTROBE BUSY 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 DRVDEN0 DRVDEN1 nMTR0 nIO_PME nDS0 P17 VSS nDIR nSTEP nWDATA nWGATE nHDSEL nINDEX nTRK0 nWPRT nRDATA nDSKCHG VTR CLOCKI nCS/SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 FDC37M81x 100 PIN QFP 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PE SLCT nERROR nACK VSS PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 nINIT nSLCTIN VCC KBRST A20M IRTX2 IRRX2 VSS KDAT KCLK MDAT MCLK IOCHRDY TC VCC DRQ3/P12 nDACK3/P16 SA0 PCI_CLK SER_IRQ AEN nIOR nIOW SD7 SD6 SD5 SD4 VSS SD3 SD2 SD1 SD0 RESET_DRV nDACK1 DRQ1 nDACK2 DRQ2 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 5 DESCRIPTION OF PIN FUNCTIONS PIN No./QFP 45:42, 40:37 31:21 20 34 55 46 33 32 48 50 52 47 49 51 54 35 36 4 6 19 61 62 53,65, 93 BUFFER TYPE PER FUNCTION (NOTE 1) IO12 I I/I I OD12 IS IO12 ICLK O12 O12 O12/IO12 I I I/IO12 I I I OD24 IO8 ICLK I O24PD NAME TOTAL SYMBOL PROCESSOR/HOST INTERFACE (36) System Data Bus 11-bit System Address Bus Chip Select/SA11 (Note 2) Address Enable I/O Channel Ready ISA Reset Drive Serial IRQ PCI Clock for Serial IRQ (33MHz/30MHz) DMA Request 1 DMA Request 2 DMA Request 3/8042 P12 DMA Acknowledge 1 DMA Acknowledge 2 DMA Acknowledge 3/8042 P16 Terminal Count I/O Read I/O Write Power Management Event 8042 - P17 (Note 5) 14.318MHz Clock Input Infrared Rx Infrared Tx (Note 4) +5 Volt Supply Voltage 8 11 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 CLOCKS (1) 1 1 1 CLOCKI IRRX IRTX VCC INFRARED INTERFACE (2) SD[0:7] SA[0:10] nCS/SA11 AEN IOCHRDY RESET_DR V SER_IRQ PCI_CLK DRQ1 DRQ2 DRQ3/P12 nDACK1 nDACK2 nDACK3/ P16 TC nIOR nIOW nIO_PME P17 POWER PINS (8) 6 DESCRIPTION OF PIN FUNCTIONS PIN No./QFP 7,41, 60,76 18 BUFFER TYPE PER FUNCTION (NOTE 1) NAME Ground +5 Volt Standby Supply Voltage (Note 7) TOTAL SYMBOL VSS VTR 16 11 10 12 8 9 17 5 3 15 14 13 1 2 84 85 87 88 89 86 91 90 95 96 98 FDD INTERFACE (14) Read Disk Data 1 nRDATA Write Gate 1 nWGATE Write Disk Data 1 nWDATA Head Select 1 nHDSEL Step Direction 1 nDIR Step Pulse 1 nSTEP Disk Change 1 nDSKCHG Drive Select 0 1 nDS0 Motor On 0 1 nMTR0 Write Protected 1 nWRTPRT Track 0 1 nTRKO Index Pulse Input 1 nINDEX Drive Density Select 0 1 DRVDEN0 Drive Density Select 1 1 DRVDEN1 SERIAL PORT 1 INTERFACE (8) Receive Serial Data 1 1 RXD1 Transmit Serial Data 1 1 TXD1 Request to Send 1/System 1 nRTS1/ Option (Note 6) SYSOPT Clear to Send 1 1 nCTS1 Data Terminal Ready 1 1 nDTR1 Data Set Ready 1 1 nDSR1 Data Carrier Detect 1 1 nDCD1 Ring Indicator 1 1 nRI1 SERIAL PORT 2 INTERFACE (8) Receive Serial Data 2/Infrared 1 RXD2/IRRX Rx Transmit Serial Data 2/Infrared 1 TXD2/IRTX Tx (Note 4) Request to Send 2/Sys Addr 12 1 nRTS2/ SA12 7 IS (O24/OD24) (O24/OD24) (O24/OD24) (O24/OD24) (O24/OD24) IS (O24/OD24) (O24/OD24) IS IS IS (O24/OD24) (O24/OD24) I O4 O4/I I O4 I I I I/I O24PD/ O24PD O4/I DESCRIPTION OF PIN FUNCTIONS PIN No./QFP 99 100 97 94 92 75:68 66 67 83 82 81 77 80 79 78 59 58 57 56 64 63 BUFFER TYPE PER FUNCTION (NOTE 1) I/I O4/I I/I I/IO24 I/IO24 IO24 OD24/O24 OD24/O24 OD24/O24 OD24/O24 I I I I I IOD16 IOD16 IOD16 IOD16 O4 O4 SYMBOL nCTS2/ SA13 Data Terminal Ready/Sys Addr 1 nDTR2/ 14 SA14 Data Set Ready 2/Sys Addr 15 1 nDSR2/ SA15 Data Carrier Detect 2/8042 P12 1 nDCD2/P12 Ring Indicator 2/8042 P16 1 nRI2/P16 PARALLEL PORT INTERFACE (17) Parallel Port Data Bus 8 PD[0:7] Printer Select 1 nSLCTIN Initiate Output 1 nINIT Auto Line Feed 1 nALF Strobe Signal 1 nSTROBE Busy Signal 1 BUSY Acknowledge Handshake 1 nACK Paper End 1 PE Printer Selected 1 SLCT Error at Printer 1 nERROR KEYBOARD/MOUSE INTERFACE (6) Keyboard Data 1 KDAT Keyboard Clock 1 KCLK Mouse Data 1 MDAT Mouse Clock 1 MCLK Keyboard Reset 1 KBDRST (Note 3) Gate A20 1 A20M NAME Clear to Send 2/Sys Addr 13 TOTAL 1 Note: The "n" as the first letter of a signal name indicates an "Active Low" signal. Note 1: Buffered types per function on multiplexed pins are separated by a slash “/”. Buffer types in parenthesis represent multiple buffer types for a single pin function. Note 2: For 12 bit addressing, SA0:SA11 only, nCS should be tied to GND. For 16 bit external address qualification, address bits SA11:SA15 can be "ORed" together and applied to nCS. The nCS pin functions as SA11 in full 16 bit Internal Address Qualification Mode. CR24.6 controls the FDC37M81x addressing modes. Note 3: KBDRST is active low. Note 4: The pull-down on this pin is always active including when the output driver is tristated and regardless of the state of internal PWRGOOD. 8 Note 5: Note 6: Note 7: Requires external pull-up resistor. When SYSOPT function is used on nRTS1/SYSOPT pin, an external pulldown register is required to put the base I/O address for configuration at 0x3F0. An external pullup resistor is required to move the base I/O address for configuration to 0x370. VTR can be connected to VCC if no wakeup functionality is required. Buffer Type Descriptions I IS IOD16 IO24 IO4 O4 O24 OD24 IO8 ICLK IO12 O12 OD12 O24PD Input, TTL compatible Input with Schmitt trigger Input/Output, 16mA sink Input/Output, 24mA sink, 12mA source Input/Output, 4mA sink, 2mA source Output, 4mA sink, 2mA source Output, 24mA sink, 12mA source Output, Open Drain, 24mA sink Input/Output, 8mA sink, 4mA source Clock Input Input/Output, 12mA sink, 6mA source Output, 12mA sink, 6mA source Output, Open Drain, 12 mA sink Output, 12mA sink, 6mA source with 30 μA pull-down 9 Description of Multifunction Pins PIN ORIGINAL ALTERNATE NO./QFP FUNCTION FUNCTION 1 nDACK3 8042 P16 51 DRQ3 8042 P12 52 nRI2 8042 P16 92 nDCD2 8042 P12 94 RXD2 IRRX 95 TXD2 IRTX 96 nDSR2 SA15 97 nRTS2 SA12 98 nCTS2 SA13 99 nDTR2 SA14 100 Controlled by DMA3SEL(LD8:CRC0.1) Controlled by 8042COMSEL(LD8:CRC0.3) Controlled by IR Option Register( LD5:CRF1.6) Controlled by 16 bit Address Qualification (CR24.6) DEFAULT nDACK3 DRQ3 nRI2 nDCD2 RXD2 TXD2 nDSR2 nRTS2 nCTS2 nDTR2 NOTE 1 1 2 2 3 3 4 4 4 4 Note 1: Note 2: Note 3: Note 4: For more information, refer to tables 63 through 73. REFERENCE DOCUMENTS 1. 2. 3. IEEE 1284 Extended Capabilities Port Protocol and ISA Standard, Rev. 1.14, July 14, 1993. Hardware Description of the 8042, Intel 8 bit Embedded Controller Handbook. PCI Bus Power Management Interface Specification, Rev. 1.0, Draft, March 18, 1997. 10 nPME SMI PME WDT MULTI-MODE PARALLEL PORT/FDC MUX PD0-7 BUSY, SLCT, PE, nERROR, nACK nSTB, nSLCTIN, nINIT, nALF ADDRESS BUS DATA BUS SER_IRQ PCI_CLK SERIAL IRQ nIOR nIOW AEN SA[0:12] (nCS) SA[13-15] SD[O:7] DRQ[1:3] nDACK[1:3] TC RESET_DRV IOCHRDY RDATA * * CONFIGURATION REGISTERS 16C550 COMPATIBLE SERIAL PORT 1 TXD1, nCTS1, nRTS1 RXD1 nDSR1, nDCD1, nRI1, nDTR1 CONTROL BUS HOST CPU INTERFACE WCLOCK WDATA * 16C550 COMPATIBLE SERIAL PORT 2 WITH INFRARED IRRX, IRTX * TXD2(IRTX), nCTS2, nRTS2 * RXD2(IRRX) * nDSR2, nDCD2, nRI2, nDTR2 * SMSC PROPRIETARY DIGITAL DATA 82077 SEPARATOR COMPATIBLE WITH WRITE VERTICAL PRECOMFLOPPYDISK PENSATION CONTROLLER CORE RCLOCK 8042 CLOCK GEN nINDEX DENSEL nDS0 nTRK0 nDIR nMTR0 nWDATAnRDATA nDSKCHG nSTEP DRVDEN0 nWRPRT * nHDSEL DRVDEN1 nWGATE KCLK KDATA MCLK MDATA GATEA20, KRESET P12*, P16* VTR Vcc Vss *Denotes Multifunction Pins CLOCKI 14MHz FIGURE 1 - FDC37M81x BLOCK DIAGRAM 11 POWER FUNCTIONALITY The FDC37M81x has two power planes: VCC and VTR. VCC Power The FDC37M81x is a 5 Volt part. The VCC supply is 5 Volts (nominal). See the Operational Description sections and the Maximum Current Values subsection. VTR SUPPORT The FDC37M81x requires a 25 mA max trickle supply (VTR) to provide sleep current for the programmable wake-up events in the PME interface when VCC is removed. If the FDC37M81x is not intended to provide wake-up capabilities on standby current, VTR can be connected to VCC. VTR powers the PME configuration registers, and the PME interface. The VTR pin generates a VTR Power-on-Reset signal to initialize these components. Note: If VTR is to be used for programmable wake-up events when VCC is removed, VTR must be at its full minimum potential at least 10 μs before Vcc begins a power-on cycle. When VTR and Vcc are fully powered, the potential difference between the two supplies must not exceed 500mV. Internal PWRGOOD An internal PWRGOOD logical control is included to minimize the effects of pin-state uncertainty in the host interface as Vcc cycles on and off. When the internal PWRGOOD signal is “1” (active), Vcc is > 3.7V, and the FDC37M81x host interface is active. When the internal PWRGOOD signal is “0” (inactive), Vcc is ≤ 3.7V, and the FDC37M81x host interface is inactive; that is, ISA bus reads and writes will not be decoded. The FDC37M81x device pins nIO_PME, KDAT, MDAT, IRRX, nRI1, nRI2 and RXD2 are part of the PME interface and remain active when the internal PWRGOOD signal has gone inactive, provided VTR is powered. PLL CONTROL (CR24.1) 1 0 0 0 0 FDC37M81x PLL CONTROLS AND SELECTS PME POWER INTERNAL (CR22.7) PWRGOOD DESCRIPTION X 0 0 1 1 X 0 1 0 1 14 MHz PLL Powered Down Reserved 14MHz PLL Powered, Selected. Reserved Reserved 12 Trickle Power Functionality When the FDC37M81x is running under VTR only, the PME wakeup events are active and (if enabled) able to assert and nIO_PME pin active low. The following lists the wakeup events. • UART1 Ring Indicator • UART2 Ring Indicator • Keyboard data • Mouse data Maximum Current Values Refer to the “Operational Description” section for the maximum current values. The maximum VTR current, ITR, is given with all outputs open. The total maximum current for the part is the unloaded value PLUS the maximum current sourced by all pins that are driven by VTR. The maximum VCC current, ICC, is given with all outputs open (not loaded). Power Management Events (PME/SCI) The FDC37M81x offers support for Power Management Events (PMEs), also referred to as System Control Interrupts (SCI) events. The terms PME and SCI are used synonymously throughout this document to refer to the indication of an event to the chipset via the assertion of the nIO_PME output signal on pin 4. See the “PME Support” section. 13 FUNCTIONAL DESCRIPTION SUPER I/O REGISTERS The address map, shown below in Table 1, shows the addresses of the different blocks of the Super I/O immediately after power up. The base addresses of the FDC, serial and parallel ports can be moved via the configuration registers. Some addresses are used to access more than one register. HOST PROCESSOR INTERFACE The host processor communicates with the FDC37M81x through a series of read/write registers. The port addresses for these registers are shown in Table 1. Register access is accomplished through programmed I/O or DMA transfers. All registers are 8 bits wide. All host interface output buffers are capable of sinking a minimum of 12 mA. ADDRESS Base+(0-5) and +(7) Base+(0-7) Base1+(0-7) Base+(0-3) Base+(0-7) Base+(0-3), +(400-402) Base+(0-7), +(400-402) 60, 64 Table 1 - Super I/O Block Addresses LOGICAL BLOCK NAME DEVICE Floppy Disk 0 Serial Port Com 1 Serial Port Com 2 Parallel Port SPP EPP ECP ECP+EPP+SPP KYBD 4 5 3 NOTES IrDA 1.0 7 Note 1: Refer to the configuration register descriptions for setting the base address 14 FLOPPY DISK CONTROLLER The Floppy Disk Controller (FDC) provides the interface between a host microprocessor and the floppy disk drive. The FDC integrates the functions of the Formatter/Controller, Digital Data Separator, Write Precompensation and Data Rate Selection logic for an IBM XT/AT compatible FDC. The true CMOS 765B core guarantees 100% IBM PC XT/AT compatibility in addition to providing data overflow and underflow protection. The FDC is compatible to the 82077AA using SMSC's proprietary floppy disk controller core. FDC INTERNAL REGISTERS The Floppy Disk Controller contains eight internal registers which facilitate the interfacing between the host microprocessor and the disk drive. Table 2 shows the addresses required to access these registers. Registers other than the ones shown are not supported. The rest of the description assumes that the primary addresses have been selected. PRIMARY ADDRESS 3F0 3F1 3F2 3F3 3F4 3F4 3F5 3F6 3F7 3F7 Table 2 - Status, Data and Control Registers (Shown with base addresses of 3F0 and 370) SECONDARY ADDRESS R/W REGISTER Status Register A (SRA) R 370 Status Register B (SRB) R 371 Digital Output Register (DOR) R/W 372 Tape Drive Register (TDR) R/W 373 Main Status Register (MSR) R 374 Data Rate Select Register (DSR) W 374 Data (FIFO) R/W 375 Reserved 376 Digital Input Register (DIR) R 377 Configuration Control Register (CCR) W 377 15 STATUS REGISTER A (SRA) Address 3F0 READ ONLY This register is read-only and monitors the state of the internal interrupt signal and several disk interface pins in PS/2 and Model 30 modes. The SRA can be accessed at any time when in PS/2 mode. In the PC/AT mode the data bus pins D0 - D7 are held in a high impedance state for a read of address 3F0. PS/2 Mode 7 INT PENDING 0 6 nDRV2 1 5 STEP 0 4 3 2 nTRK0 HDSEL nINDX N/A 0 N/A 1 nWP N/A 0 DIR 0 RESET COND. BIT 0 DIRECTION Active high status indicating the direction of head movement. A logic "1" indicates inward direction; a logic "0" indicates outward direction. BIT 1 nWRITE PROTECT Active low status of the WRITE PROTECT disk interface input. A logic "0" indicates that the disk is write protected. BIT 2 nINDEX Active low status of the INDEX disk interface input. BIT 3 HEAD SELECT Active high status of the HDSEL disk interface input. A logic "1" selects side 1 and a logic "0" selects side 0. BIT 4 nTRACK 0 Active low status of the TRK0 disk interface input. BIT 5 STEP Active high status of the STEP output disk interface output pin. BIT 6 nDRV2 This function is not supported. This bit is always read as ‘1’. BIT 7 INTERRUPT PENDING Active high bit indicating the state of the Floppy Disk Interrupt output. 16 PS/2 Model 30 Mode 7 INT PENDING 0 6 DRQ 0 5 STEP F/F 0 4 TRK0 N/A 3 nHDSEL 1 2 INDX N/A 1 WP N/A 0 nDIR 1 RESET COND. BIT 0 nDIRECTION Active low status indicating the direction of head movement. A logic "0" indicates inward direction; a logic "1" indicates outward direction. BIT 1 WRITE PROTECT Active high status of the WRITE PROTECT disk interface input. A logic "1" indicates that the disk is write protected. BIT 2 INDEX Active high status of the INDEX disk interface input. BIT 3 nHEAD SELECT Active low status of the HDSEL disk interface input. A logic "0" selects side 1 and a logic "1" selects side 0. BIT 4 TRACK 0 Active high status of the TRK0 disk interface input. BIT 5 STEP Active high status of the latched STEP disk interface output pin. This bit is latched with the STEP output going active, and is cleared with a read from the DIR register, or with a hardware or software reset. BIT 6 DMA REQUEST Active high status of the DRQ output pin. BIT 7 INTERRUPT PENDING Active high bit indicating the state of the Floppy Disk Interrupt output. 17 STATUS REGISTER B (SRB) Address 3F1 READ ONLY This register is read-only and monitors the state of several disk interface pins in PS/2 andModel 30 modes. The SRB can be accessed at any time when in PS/2 mode. In the PC/AT mode the data bus pins D0 - D7 are held in a high impedance state for a read of address 3F1. PS/2 Mode 7 1 RESET COND. 1 6 1 1 5 4 3 2 DRIVE WDATA RDATA WGATE SEL0 TOGGLE TOGGLE 0 0 0 0 1 MOT EN1 0 0 MOT EN0 0 BIT 0 MOTOR ENABLE 0 Active high status of the MTR0 disk interface output pin. This bit is low after a hardware reset and unaffected by a software reset. BIT 1 MOTOR ENABLE 1 Active high status of the MTR1 disk interface output pin. This bit is low after a hardware reset and unaffected by a software reset. Note: In the FDC37M81x only one drive is available at the FDD interface. BIT 2 WRITE GATE Active high status of the WGATE disk interface output. BIT 3 READ DATA TOGGLE Every inactive edge of the RDATA input causes this bit to change state. BIT 4 WRITE DATA TOGGLE Every inactive edge of the WDATA input causes this bit to change state. BIT 5 DRIVE SELECT 0 Reflects the status of the Drive Select 0 bit of the DOR (address 3F2 bit 0). This bit is cleared after a hardware reset and it is unaffected by a software reset. BIT 6 RESERVED Always read as a logic "1". BIT 7 RESERVED Always read as a logic "1". 18 PS/2 Model 30 Mode 7 nDRV2 RESET COND. N/A 6 nDS1 1 5 nDS0 1 4 WDATA F/F 0 3 RDATA F/F 0 2 WGATE F/F 0 1 nDS3 1 0 nDS2 1 BIT 0 nDRIVE SELECT 2 The DS2 disk interface is not supported in the FDC37M81x. BIT 1 nDRIVE SELECT 3 The DS3 disk interface is not supported in the FDC37M81x. BIT 2 WRITE GATE Active high status of the latched WGATE output signal. This bit is latched by the active going edge of WGATE and is cleared by the read of the DIR register. BIT 3 READ DATA Active high status of the latched RDATA output signal. This bit is latched by the inactive going edge of RDATA and is cleared by the read of the DIR register. BIT 4 WRITE DATA Active high status of the latched WDATA output signal. This bit is latched by the inactive going edge of WDATA and is cleared by the read of the DIR register. This bit is not gated with WGATE. BIT 5 nDRIVE SELECT 0 Active low status of the DS0 disk interface output. BIT 6 nDRIVE SELECT 1 Active low status of the DS1 disk interface output. BIT 7 nDRV2 Active low status of the DRV2 disk interface input. Note: This function is not supported in the FDC37M81x. 19 DIGITAL OUTPUT REGISTER (DOR) Address 3F2 READ/WRITE The DOR controls the drive select and motor enables of the disk interface outputs. It also contains the enable for the DMA logic and a software reset bit. The contents of the DOR are unaffected by a software reset. The DOR can be written to at any time. 7 MOT EN3 0 6 MOT EN2 0 5 MOT EN1 0 4 MOT EN0 0 3 DMAEN 0 2 1 0 nRESE DRIVE DRIVE T SEL1 SEL0 0 0 0 RESET COND. BIT 0 and 1 DRIVE SELECT These two bits are binary encoded for the drive selects, thereby allowing only one drive to be selected at one time. BIT 2 nRESET A logic "0" written to this bit resets the Floppy disk controller. This reset will remain active until a logic "1" is written to this bit. This software reset does not affect the DSR and CCR registers, nor does it affect the other bits of the DOR register. The minimum reset duration required is 100ns, therefore toggling this bit by consecutive writes to this register is a valid method of issuing a software reset. BIT 3 DMAEN PC/AT and Model 30 Mode: Writing this bit to logic "1" will enable the DRQ, nDACK, TC pins and interrupt functions. This bit being a logic "0" will disable the nDACK, TC inputs and interrupt functions, and hold the DRQ output in a high impedance state. This bit is a logic "0" after a reset and in these modes. PS/2 Mode: In this mode the DRQ, nDACK, TC pins and interrupt functions are always enabled. During a reset, the DRQ, nDACK, TC, and FINTR pins will remain enabled, but this bit will be cleared to a logic "0". BIT 4 MOTOR ENABLE 0 This bit controls the MTR0 disk interface output. A logic "1" in this bit will cause the output pin to go active. BIT 5 MOTOR ENABLE 1 This bit controls the MTR1 disk interface output. A logic "1" in this bit will cause the output pin to go active. BIT 6 MOTOR ENABLE 2 The MTR2 disk interface output is not supported in the FDC37M81x. BIT 7 MOTOR ENABLE 3 The MTR3 disk interface output is not supported in the FDC37M81x. Table 3 - Drive Activation Values DRIVE 0 1 DOR VALUE 1CH 2DH 20 TAPE DRIVE REGISTER (TDR) Address 3F3 READ/WRITE The Tape Drive Register (TDR) is included for 82077 software compatibility and allows the user to assign tape support to a particular drive during initialization. Any future references to that drive automatically invokes tape support. The TDR Tape Select bits TDR.[1:0] determine the tape drive number. Table 4 illustrates the Tape Select Bit encoding. Note that drive 0 is the boot device and cannot be assigned tape support. The remaining Tape Drive Register bits TDR.[7:2] are tristated when read. The TDR is unaffected by a software reset. TAPE SEL1 (TDR.1) 0 0 1 1 Table 4 - Tape Select Bits TAPE SEL0 DRIVE SELECTED (TDR.0) None 0 1 1 2 0 3 1 Table 5 - Internal 2 Drive Decode - Normal DIGITAL OUTPUT DRIVE SELECT OUTPUTS MOTOR ON OUTPUTS REGISTER (ACTIVE LOW) (ACTIVE LOW) Bit 5 Bit 4 Bit1 Bit 0 nDS1 nDS0 nMTR1 nMTR0 X 1 0 0 1 0 nBIT 5 nBIT 4 1 X 0 1 0 1 nBIT 5 nBIT 4 0 0 X X 1 1 nBIT 5 nBIT 4 Table 6 - Internal 2 Drive Decode - Drives 0 and 1 Swapped DIGITAL OUTPUT DRIVE SELECT OUTPUTS MOTOR ON OUTPUTS REGISTER (ACTIVE LOW) (ACTIVE LOW) Bit 5 X 1 0 Bit 4 1 X 0 Bit1 0 0 X Bit 0 0 1 X nDS1 0 1 1 nDS0 1 0 1 nMTR1 nBIT 4 nBIT 4 nBIT 4 nMTR0 nBIT 5 nBIT 5 nBIT 5 21 Normal Floppy Mode Normal mode. Register 3F3 contains only bits 0 and 1. When this register is read, bits 2 - 7 are a high impedance. DB7 REG 3F3 Tri-state DB6 Tri-state DB5 Tri-state DB4 Tri-state DB3 Tri-state DB2 Tri-state DB1 tape sel1 DB0 tape sel0 Enhanced Floppy Mode 2 (OS2) Register 3F3 for Enhanced Floppy Mode 2 operation. DB7 DB6 DB5 DB4 DB3 DB2 DB1 tape sel1 DB0 tape sel0 REG 3F3 Reserved Reserved Drive Type ID Floppy Boot Drive Table 7 - Drive Type ID DIGITAL OUTPUT REGISTER REGISTER 3F3 - DRIVE TYPE ID Bit 1 0 0 1 1 Note: Bit 0 0 1 0 1 Bit 5 L0-CRF2 - B1 L0-CRF2 - B3 L0-CRF2 - B5 L0-CRF2 - B7 Bit 4 L0-CRF2 - B0 L0-CRF2 - B2 L0-CRF2 - B4 L0-CRF2 - B6 L0-CRF2-Bx = Logical Device 0, Configuration Register F2, Bit x. 22 DATA RATE SELECT REGISTER (DSR) Address 3F4 WRITE ONLY This register is write only. It is used to program the data rate, amount of write precompensation, power down status, and software reset. The data rate is programmed using the Configuration Control Register (CCR) not the DSR, for PC/AT and PS/2 Model 30. Other applications can set the data rate in the DSR. The data rate of the floppy controller is the most recent write of either the DSR or CCR. The DSR is unaffected by a software reset. A hardware reset will set the DSR to 02H, which corresponds to the default precompensation setting and 250 Kbps. RESET COND. 7 6 S/W POWER RESET DOWN 0 0 5 0 0 4 PRECOMP2 0 3 PRECOMP1 0 2 1 0 PREDRATE DRATE COMP0 SEL1 SEL0 0 1 0 BIT 0 and 1 DATA RATE SELECT These bits control the data rate of the floppy controller. See Table 9 for the settings corresponding to the individual data rates. The data rate select bits are unaffected by a software reset, and are set to 250 Kbps after a hardware reset. BIT 2 through 4 PRECOMPENSATION SELECT These three bits select the value of write precompensation that will be applied to the WDATA output signal. Table 11 shows the precompensation values for the combination of these bits settings. Track 0 is the default starting track number to start precompensation. this starting track number can be changed by the configure command. BIT 5 UNDEFINED Should be written as a logic "0". BIT 6 LOW POWER A logic "1" written to this bit will put the floppy controller into manual low power mode. The floppy controller clock and data mode after a software reset or access to the Data Register or Main Status Register. BIT 7 SOFTWARE RESET This active high bit has the same function as the DOR RESET (DOR bit 2) except that this bit is self clearing. Note: The DSR is Shadowed in the Floppy Data Rate Select Shadow Register, LD8:CRC2[7:0]. separator circuits will be turned off. The controller will come out of manual low power. 23 Table 8 - Precompensation Delays PRECOMP 432 111 001 010 011 100 101 110 000 PRECOMPENSATION DELAY (nsec) The device exits the Configuration State when the following Config Key is successfully written to the CONFIG PORT. Config Key = < 0xAA> 133 CONFIGURATION SEQUENCE To program the configuration registers, the following sequence must be followed: 1. Enter Configuration Mode 2. Configure the Configuration Registers 3. Exit Configuration Mode. Enter Configuration Mode To place the chip into the Configuration State the Config Key is sent to the chip's CONFIG PORT. The config key consists of 0x55 written to the CONFIG PORT. Once the configuration key is received correctly the chip enters into the Configuration State (The auto Config ports are enabled). Configuration Mode The system sets the logical device information and activates desired logical devices through the INDEX and DATA ports. In configuration mode, the INDEX PORT is located at the CONFIG PORT address and the DATA PORT is at INDEX PORT address + 1. The desired configuration registers are accessed in two steps: a. Write the index of the Logical Device Number Configuration Register (i.e., 0x07) to the INDEX PORT and then write the number of the desired logical device to the DATA PORT b. Write the address of the desired configuration register within the logical device to the INDEX PORT and then write or read the configuration register through the DATA PORT. Note: If accessing the Global Configuration Registers, step (a) is not required. Exit Configuration Mode To exit the Configuration State the system writes 0xAA to the CONFIG PORT. The chip returns to the RUN State. Note: Only two states are defined (Run and Configuration). In the Run State the chip will always be ready to enter the Configuration State. 134 Programming Example The following is an example of a configuration program in Intel 8086 assembly language. ;----------------------------. ; ENTER CONFIGURATION MODE | ;----------------------------' MOV DX,3F0H MOV AX,055H OUT DX,AL ;----------------------------. ; CONFIGURE REGISTER CRE0, | ; LOGICAL DEVICE 8 | ;----------------------------' MOV DX,3F0H MOV AL,07H OUT DX,AL ;Point to LD# Config Reg MOV DX,3F1H MOV AL, 08H OUT DX,AL;Point to Logical Device 8 ; MOV DX,3F0H MOV AL,E0H OUT DX,AL ; Point to CRE0 MOV DX,3F1H MOV AL,02H OUT DX,AL ; Update CRE0 ;-----------------------------. ; EXIT CONFIGURATION MODE | ;-----------------------------' MOV DX,3F0H MOV AX,0AAH OUT DX,AL 135 Notes: 1. HARD RESET: RESET_DRV pin asserted 2. SOFT RESET: Bit 0 of Configuration Control register set to one 3. All host accesses are blocked for 500µs after Vcc POR (see Power-up Timing Diagram) Table 51 – FDC37M81x Configuration Registers Summary HARD VCC SOFT VTR RESET POR RESET POR TYPE CONFIGURATION REGISTER GLOBAL CONFIGURATION REGISTERS W 0x00 0x00 0x00 Configuration Control R/W 0x03 0x03 0x03 Index Address R/W 0x00 0x00 0x00 0x00 Logical Device Number R 0x4D Device ID - hard wired R Current Revision Device Rev - hard wired R/W 0x00 0x00 0x00 0x00 Power Control R/W 0x00 0x00 0x00 Power Mgmt R/W 0x04 0x04 0x04 OSC R/W Sysopt Sysopt Configuration Port Address Byte 0 =0: 0xF0 =0: 0xF0 Sysopt Sysopt =1: 0x70 =1: 0x70 R/W Sysopt Sysopt Configuration Port Address Byte 1 =0: 0x03 =0: 0x03 Sysopt Sysopt =1: 0x03 =1: 0x03 R/W 0x00 0x00 TEST 4 R/W 0x00 0x00 TEST 5 R/W 0x00 0x00 TEST 1 R/W 0x00 0x00 TEST 2 R/W 0x00 0x00 TEST 3 LOGICAL DEVICE 0 CONFIGURATION REGISTERS (FDD) R/W 0x00 0x00 0x00 0x00 Activate R/W 0x03, 0x03, 0x03, 0x03, Primary Base I/O Address 0xF0 0xF0 0xF0 0xF0 R/W 0x06 0x06 0x06 0x06 Primary Interrupt Select R/W 0x02 0x02 0x02 0x02 DMA Channel Select R/W 0x0E 0x0E 0x0E FDD Mode Register R/W 0x00 0x00 0x00 FDD Option Register R/W 0xFF 0xFF 0xFF FDD Type Register R/W 0x00 0x00 0x00 FDD0 R/W 0x00 0x00 0x00 FDD1 INDEX 0x02 0x03 0x07 0x20 0x21 0x22 0x23 0x24 0x26 0x27 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x60, 0x61 0x70 0x74 0xF0 0xF1 0xF2 0xF4 0xF5 136 INDEX TYPE HARD RESET VCC POR SOFT RESET VTR POR CONFIGURATION REGISTER LOGICAL DEVICE 1 CONFIGURATION REGISTERS (RESERVED) LOGICAL DEVICE 2 CONFIGURATION REGISTERS (RESERVED) LOGICAL DEVICE 3 CONFIGURATION REGISTERS (Parallel Port) R/W 0x00 0x00 0x00 0x00 Activate R/W 0x00, 0x00, 0x00, 0x00, Primary Base I/O Address 0x00 0x00 0x00 0x00 R/W 0x00 0x00 0x00 0x00 Primary Interrupt Select R/W 0x04 0x04 0x04 0x04 DMA Channel Select R/W 0x3C 0x3C 0x3C Parallel Port Mode Register R/W 0x00 0x00 0x00 Parallel Port Mode Register 2 LOGICAL DEVICE 4 CONFIGURATION REGISTERS (Serial Port 1) R/W 0x00 0x00 0x00 0x00 Activate R/W 0x00, 0x00, 0x00, 0x00, Primary Base I/O Address 0x00 0x00 0x00 0x00 R/W 0x00 0x00 0x00 0x00 Primary Interrupt Select R/W 0x00 0x00 0x00 Serial Port 1 Mode Register LOGICAL DEVICE 5 CONFIGURATION REGISTERS (Serial Port 2) R/W 0x00 0x00 0x00 0x00 Activate R/W 0x00, 0x00, 0x00, 0x00, Primary Base I/O Address 0x00 0x00 0x00 0x00 R/W 0x00, 0x00, 0x00, 0x00, Reserved 0x00 0x00 0x00 0x00 R/W 0x00 0x00 0x00 0x00 Primary Interrupt Select R/W 0x00 0x00 0x00 Serial Port 2 Mode Register R/W 0x02 0x02 0x02 IR Options Register R/W 0x03 0x03 0x03 IR Half Duplex Timeout LOGICAL DEVICE 6 CONFIGURATION REGISTERS (RESERVED) LOGICAL DEVICE 7 CONFIGURATION REGISTERS (KEYBOARD) R/W 0x00 0x00 0x00 0x00 Activate R/W 0x00 0x00 0x00 0x00 Primary Interrupt Select (Keyboard) R/W 0x00 0x00 0x00 0x00 Second Interrupt Select (Mouse) R/W 0x00 0x00 0x00 KRESET and GateA20 Select LOGICAL DEVICE 8 CONFIGURATION REGISTERS (Aux I/O) R/W 0x00 0x00 0x00 0x00 Activate R/W 0x00 0x00 SMI Enable Register 1 R/W 0x00 0x00 SMI Enable Register 2 0x30 0x60, 0x61 0x70 0x74 0xF0 0xF1 0x30 0x60, 0x61 0x70 0xF0 0x30 0x60, 0x61 0x62, 0x63 0x70 0xF0 0xF1 0xF2 0x30 0x70 0x72 0xF0 0x30 0xB4 0xB5 137 INDEX 0xB6 0xB7 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xF1 0xF2 0xF3 0xF4 0xF6 : FB Note 1: Note 2: Note 3: TYPE R/W R/W R/W R/W R R R R/W R/WCLEAR R/WCLEAR R/W R/W R/W R/W R/W1 HARD RESET VCC POR SOFT RESET VTR POR 0x02 0x01 0x00 0x00 0x00 0x002 - 0x00 0x00 0x02 0x01 0x00 0x00 0x00 0x00 - - 0x00 0x00 0x02 0x01 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 - CONFIGURATION REGISTER SMI Status Register 1 SMI Status Register 2 Pin Multiplex Controls Force Disk Change Floppy Data Rate Select Shadow UART1 FIFO Control Shadow UART2 FIFO Control Shadow PME Control Register PME Status Register PME Wake Status Register PME Wake Enable Register WDT_TIME_OUT WDT_VAL WDT_CFG WDT_CTRL Reserved This register contains some bits that are read or write only. Bit 0 is not cleared by HARD RESET. The Parallel Port interrupt defaults to ‘1’ when the Parallel Port activate bit is cleared. When the Parallel Port is activated, PINT follows the nACK input. 138 Chip Level (Global) Registers[0x00-0x2F] Control/Configuration ignore writes and return zero when read. The INDEX PORT is used to select a configuration register in the chip. The DATA PORT is then used to access the selected register. These registers are accessible only in the Configuration Mode. The chip-level (global) registers lie in the address range [0x00-0x2F]. The design MUST use all 8 bits of the ADDRESS Port for register selection. All unimplemented registers and bits Table 52 - Chip Level Registers REGISTER ADDRESS DESCRIPTION Chip (Global) Control Registers STATE 0x00 0x01 Config Control Default = 0x00 on VCC POR, VTR POR and HARD RESET Index Address Default = 0x03 on VCC POR, VTR POR and HARD RESET 0x03 R/W 0x02 W Reserved - Writes are ignored, reads return 0. The hardware automatically clears this bit after the write, there is no need for software to clear the bits. Bit 0 = 1: Soft Reset. Refer to the "Configuration Registers" table for the soft reset value for each register. Bit[7] =1 C =0 Enable WDT_CTRL and SMI Enable and SMI Status Register access when not in configuration mode Disable WDT_CTRL and SMI Enable and SMI Status Register access when not in configuration mode (Default) Bits [6:2] Reserved - Writes are ignored, reads return 0. Bits[1:0] Sets GP index register address when in Run mode (not in Configuration Mode). = 11 0xEA (Default) = 10 0xE4 = 01 0xE2 = 00 0xE0 0x04 - 0x06 Logical Device # Default = 0x00 on VCC POR, VTR POR and HARD RESET 0x07 R/W Reserved - Writes are ignored, reads return 0. A write to this register selects the current logical device. This allows access to the control and configuration registers for each logical device. Note: The Activate command operates only on the selected logical device. 139 C Table 52 - Chip Level Registers REGISTER ADDRESS DESCRIPTION STATE Card Level Reserved Device ID Hard wired = 0x4D Device Rev Hard wired = Current Revision PowerControl Default = 0x00. on VCC POR, VTR POR, SOFT RESET and HARD RESET 0x08 - 0x1F 0x20 R Reserved - Writes are ignored, reads return 0. Chip Level, SMSC Defined A read only register which provides identification. Bits[7:0] = 0x4D when read. device C 0x21 R A read only register which provides device revision information. Bits[7:0] = current revision when read. C 0x22 R/W Bit[0] FDC Power Bit[1] Reserved Bit[2] Reserved Bit[3] Parallel Port Power Bit[4] Serial Port 1 Power Bit[5] Serial Port 2 Power Bit[6] Reserved Bit[7] Reserved Bit[0] FDC Bit[1] Reserved Bit[2] Reserved Bit[3] Parallel Port Bit[4] Serial Port 1 Bit[5] Serial Port 2 Bit[6:7] Reserved (read as 0) =0 Intelligent Pwr Mgmt off =1 Intelligent Pwr Mgmt on C Power Mgmt Default = 0x00. on VCC POR, VTR POR and HARD RESET 0x23 R/W C 140 Table 53 - Chip Level Registers REGISTER ADDRESS DESCRIPTION STATE OSC Default = 0x04, on VCC POR, VTR POR and HARD RESET 0x24 R/W Bit[0] Reserved Bit [1] PLL Control =0 PLL is on (backward Compatible) =1 PLL is off Bits[3:2] OSC = 01 Osc is on, BRG clock is on. = 10 Same as above (01) case. = 00 Osc is on, BRG Clock Enabled. = 11 Osc is off, BRG clock is disabled. Bit [5:4] Reserved, set to zero Bit [6] 16-Bit Address Qualification =0 12-Bit Address Qualification =1 16-Bit Address Qualification Note: For normal operation, bit 6 should be set. Bit[7] Reserved C Chip Level Vendor Defined Configuration Address Byte 0 Default =0xF0 (Sysopt=0) =0x70 (Sysopt=1) on VCC POR and HARD RESET Configuration Address Byte 1 Default = 0x03 on VCC POR and HARD RESET Default = 0x00 on VCC POR and Hard Reset Chip Level Vendor Defined 0x25 0x26 Reserved - Writes are ignored, reads return 0. Bit[7:1] Configuration Address Bits [7:1] Bit[0] = 0 See Note 1 C 0x27 Bit[7:0] Configuration Address Bits [15:8] See Note 1 C 0x28 Bits[7:0] Reserved - Writes are ignored, reads return 0. Reserved - Writes are ignored, reads return 0. 0x29 -0x2A 141 Table 53 - Chip Level Registers REGISTER ADDRESS DESCRIPTION STATE TEST 4 Default = 0x00, on VCC POR and VTR POR TEST 5 Default = 0x00, on VCC POR and VTR POR 0x2B R/W Test Modes: Reserved for SMSC. Users should not write to this register, may produce undesired results. C 0x2C R/W TEST 1 Default = 0x00, on VCC POR and VTR POR TEST 2 Default = 0x00, on VCC POR and VTR POR TEST 3 Default = 0x00, on VCC POR and VTR POR 0x2D R/W Bit[7] Test Mode: Reserved for SMSC. Users should not write to this bit, may produce undesired results. Bit[6] 8042 Reset: 1 = Put the 8042 into reset 0 = Take the 8042 out of reset Bits[5:0] Test Mode: Reserved for SMSC. Users should not write to this bit, may produce undesired results. Test Modes: Reserved for SMSC. Users should not write to this register, may produce undesired results. C C 0x2E R/W Test Modes: Reserved for SMSC. Users should not write to this register, may produce undesired results. C 0x2F R/W Test Modes: Reserved for SMSC. Users should not write to this register, may produce undesired results. C Note 1: To allow the selection of the configuration address to a user defined location, these Configuration Address Bytes are used. There is no restriction on the address chosen, except that A0 is 0, that is, the address must be on an even byte boundary. As soon as both bytes are changed, the configuration space is moved to the specified location with no delay (Note: Write byte 0, then byte 1; writing CR27 changes the base address). The configuration address is only reset to its default address upon a Hard Reset or Vcc POR. Note: The default configuration address is either 3F0 or 370, as specified by the SYSOPT pin. 142 Logical Device Registers [0x30-0xFF] Configuration/Control each logical device and is selected with the Logical Device # Register (0x07). The INDEX PORT is used to select a specific logical device register. These registers are then accessed through the DATA PORT. The Logical Device registers are accessible only when the device is in the Configuration State. The logical register addresses are shown in the table below. Used to access the registers that are assigned to each logical unit. This chip supports six logical units and has six sets of logical device registers. The six logical devices are Floppy, Parallel, Serial 1, Serial 2, Keyboard Controller, and Auxiliary_I/O. A separate set (bank) of control and configuration registers exists for Table 54 - Logical Device Registers LOGICAL DEVICE REGISTER ADDRESS DESCRIPTION STATE Activate (Note 1) Default = 0x00 on VCC POR, VTR POR, SOFT RESET and HARD RESET Logical Device Control Logical Device Control Memory Base Address I/O Base Address (Note 2) (see Device Base I/O Address Table) Default = 0x00 on VCC POR, VTR POR, SOFT RESET and HARD RESET (0x30) Bits[7:1] Reserved, set to zero. Bit[0] =1 Activates the logical device currently selected through the Logical Device # register. =0 Logical device currently selected is inactive Reserved - Writes are ignored, reads return 0. Vendor Defined - Reserved - Writes are ignored, reads return 0. Reserved - Writes are ignored, reads return 0. Registers 0x60 and 0x61 set the base address for the device. If more than one base address is required, the second base address is set by registers 0x62 and 0x63. Refer to Table 63 for the number of base address registers used by each device. Unused registers will ignore writes and return zero when read. C (0x31-0x37) (0x38-0x3f) (0x40-0x5F) (0x60-0x6F) 0x60,2,... = addr[15:8] 0x61,3,... = addr[7:0] C C C C 143 Table 54 - Logical Device Registers LOGICAL DEVICE REGISTER ADDRESS DESCRIPTION STATE Interrupt Select Defaults : 0x70 = 0x00 or 0X06 (Note 3) on VCC POR, VTR POR, SOFT RESET and HARD RESET 0x72 = 0x00, on VCC POR, VTR POR, SOFT RESET and HARD RESET (0x70,0x72) 0x70 is implemented for each logical device. Refer to Interrupt Configuration Register description. Only the keyboard controller uses Interrupt Select register 0x72. Unused register (0x72) will ignore writes and return zero when read. Interrupts default to edge high (ISA compatible). C (0x71,0x73) Reserved - not implemented. These register locations ignore writes and return zero when read. Only 0x74 is implemented for FDC and Parallel port. 0x75 is not implemented and ignores writes and returns zero when read. Refer to DMA Channel Configuration. C DMA Channel Select Default = 0x04 or 0X02 (Note 4) on VCC POR, VTR POR, SOFT RESET and HARD RESET 32-Bit Memory Space Configuration Logical Device (0x74,0x75) (0x76-0xA8) Reserved - not implemented. These register locations ignore writes and return zero when read. Reserved - not implemented. These register locations ignore writes and return zero when read. Reserved - Vendor Defined (see SMSC defined Logical Device Configuration Registers). Reserved C (0xA9-0xDF) Logical Device Configuration Reserved (0xE0-0xFE) C 0xFF C Note 1: A logical device will be active and powered up according to the following equation: DEVICE ON (ACTIVE) = (Activate Bit SET or Pwr/Control Bit SET). The Logical device's Activate Bit and its Pwr/Control Bit are linked such that setting or clearing one sets or clears the other. If the I/O Base Addr of the logical device is not within the Base I/O range as shown in the Logical Device I/O map, then read or write is not valid and is ignored. 144 Note 2: If the I/O Base Addr of the logical device is not within the Base I/O range as shown in the Logical Device I/O map, then read or write is not valid and is ignored. Note 3: The default value of the Primary Interrupt Select register for logical device 0 is 0x06. Note 4: The DMA (0x74) default address for logical device 0 (FDD) is 0x02 and for logical device 3 is 0x04. Table 55 - I/O Base Address Configuration Register Description LOGICAL DEVICE NUMBER 0x00 LOGICAL DEVICE FDC REGISTER INDEX 0x60,0x61 BASE I/O RANGE (NOTE 1) [0x100:0x0FF8] FIXED BASE OFFSETS +0 : SRA +1 : SRB +2 : DOR +3 : TDR +4 : MSR/DSR +5 : FIFO +7 : DIR/CCR ON 8 BYTE BOUNDARIES 0x01 0x02 0x03 Reserved Reserved Parallel Port n/a n/a 0x60,0x61 n/a n/a [0x100:0x0FFC] ON 4 BYTE BOUNDARIES (EPP Not supported) or [0x100:0x0FF8] ON 8 BYTE BOUNDARIES (all modes supported, EPP is only available when the base address is on an 8byte boundary) [0x100:0x0FF8] ON 8 BYTE BOUNDARIES n/a n/a +0 : Data|ecpAfifo +1 : Status +2 : Control +3 : EPP Address +4 : EPP Data 0 +5 : EPP Data 1 +6 : EPP Data 2 +7 : EPP Data 3 +400h : cfifo|ecpDfifo|tfifo |cnfgA +401h : cnfgB +402h : ecr +0 : RB/TB|LSB div +1 : IER|MSB div +2 : IIR/FCR +3 : LCR +4 : MSR +5 : LCR +6 : MSR +7 : SCR +0 : RB/TB|LSB div +1 : IER|MSB div +2 : IIR/FCR +3 : LCR +4 : MSR +5 : LCR +6 : MSR +7 : SCR 0x04 Serial Port 1 0x60,0x61 0x05 Serial Port 2 0x60,0x61 [0x100:0x0FF8] ON 8 BYTE BOUNDARIES 145 Table 55 - I/O Base Address Configuration Register Description LOGICAL DEVICE NUMBER 0x06 LOGICAL DEVICE Reserved REGISTER INDEX BASE I/O RANGE (NOTE 1) FIXED BASE OFFSETS 0x07 0x08 0x09 Config. Port KYBD Auxilary I/O Reserved Config. Port n/a n/a n/a 0x26,0x27 (Note 2) Not Relocatable Fixed Base Address: 60,64 n/a n/a [0x0100:0x0FFE] ON 2 BYTE BOUNDARIES +0 : Data Register +4 : Command/Status Reg. n/a n/a See Configuration Registers in Table 51. Accessed through the INDEX and DATA Ports located at the Configuration Port Address and the Configuration Port Address +1 respectively. Note 1: This chip uses ISA address bits [A11:A0] to decode the base address of each of its logical devices. Bit 6 of the OSC Global Configuration Register (CR24) must be set to ‘1’ and Address Bits [A15:A12] must be ‘0’ for 16-bit address qualification. Note 2: The Configuration Port is at either 0x03F0 or 0x0370 (for SYSOPT=0 or SYSOPT=1) at power up and can be relocated via the global configuration registers at 0x26 and 0x27. 146 NAME Table 56 - Interrupt Select Configuration Register Description REG INDEX DEFINITION STATE Interrupt Request Level Select 0 Default = 0x00 or 0X06 (Note 1) on VCC POR, VTR POR, SOFT RESET and HARD RESET 0x70 (R/W) Bits[3:0] selects which interrupt level is used for Interrupt 0. 0x00= no interrupt selected 0x01= IRQ1 0x02= IRQ2/nSMI 0x03= IRQ3 0x04= IRQ4 0x05= IRQ5 0x06= IRQ6 0x07= IRQ7 0x08= IRQ8 0x09= IRQ9 0x0A= IRQ10 0x0B= IRQ11 0x0C= IRQ12 0x0D= IRQ13 0x0E= IRQ14 0x0F= IRQ15 Note: All interrupts are edge high (except ECP/EPP) Note: nSMI is active low C An Interrupt is activated by setting the Interrupt Request Level Select 0 register to a non-zero value AND : For the FDC logical device by setting DMAEN, bit D3 of the Digital Output Register. For the PP logical device by setting IRQE, bit D4 of the Control Port and in addition For the PP logical device in ECP mode by clearing serviceIntr, bit D2 of the ecr. For the Serial Port logical device by setting any combination of bits D0-D3 in the IER and by setting the OUT2 bit in the UART's Modem Control (MCR) Register. For the RTC by (refer to the RTC section of this spec). For the KYBD logical device (refer to the KYBD controller section of this spec). Note: IRQ pins must tri-state if not used/selected by any Logical Device. Refer to Note A. Note: nSMI must be disabled to use IRQ2. Note: All IRQ’s are available in Serial IRQ mode. Only IRQ[3:7] and IRQ[10:12] are available in Parallel IRQ mode. Note 1: The default value of the Primary Interrupt Select register for logical device 0 is 0x06. Note: 147 NAME Table 57 - DMA Channel Select Configuration Register Description REG INDEX DEFINITION STATE DMA Channel Select Default = 0x04 or 0X02 (Note 1) on VCC POR, VTR POR, SOFT RESET and HARD RESET Note: 0x74 (R/W) Bits[2:0] select the DMA Channel. 0x00= Reserved 0x01= DMA1 0x02= DMA2 0x03= DMA3 0x04-0x07= No DMA active C A DMA channel is activated by setting the DMA Channel Select register to [0x01-0x03] AND : For the FDC logical device by setting DMAEN, bit D3 of the Digital Output Register. For the PP logical device in ECP mode by setting dmaEn, bit D3 of the ecr. Note: DMAREQ pins must tri-state if not used/selected by any Logical Device. Refer to Note A. Note 1: The DMA (0x74) default address for logical device 0 (FDD) is 0x02 and for logical device 3 is 0x04. 148 Note A. Logical Device IRQ and DMA Operation 1. IRQ and DMA Enable and Disable: Any time the IRQ or DACK for a logical block is disabled by a register bit in that logical block, the IRQ and/or DACK must be disabled. This is in addition to the IRQ and DACK disabled by the Configuration Registers (active bit or address not valid). a. FDC: For the following cases, the IRQ and DACK used by the FDC are disabled (high impedance). Digital Output Register (Base+2) bit D3 (DMAEN) set to "0". The FDC is in power down (disabled). Serial Port 1 and 2: Modem Control Register (MCR) Bit D2 (OUT2) - When OUT2 is a logic "0", the serial port interrupt is forced to a high impedance state - disabled. Parallel Port: I. SPP and EPP modes: Control Port (Base+2) bit D4 (IRQE) set to "0", IRQ is disabled (high impedance). ii. ECP Mode: (1) (DMA) dmaEn from ecr register. See table. (2) IRQ - See table. MODE (FROM ECR REGISTER) 000 PRINTER IRQ PIN CONTROLLED BY IRQE PDREQ PIN CONTROLLED BY dmaEn b. c. 001 010 011 100 101 110 111 d. SPP FIFO ECP EPP RES TEST CONFIG IRQE (on) (on) IRQE IRQE (on) IRQE dmaEn dmaEn dmaEn dmaEn dmaEn dmaEn dmaEn Keyboard Controller: Refer to the KBD section of this spec. 149 SMSC Defined Logical Device Configuration Registers The SMSC Specific Logical Device Configuration Registers reset to their default values only on hard resets generated by Vcc or VTR POR (as shown) or the RESET_DRV signal. These registers are not affected by soft resets. Table 58 - Floppy Disk Controller, Logical Device 0 [Logical Device Number = 0x00] NAME REG INDEX DEFINITION STATE FDD Mode Register Default = 0x0E on VCC POR, VTR POR and HARD RESET 0xF0 R/W Bit[0] Floppy Mode =0 Normal Floppy Mode (default) =1 Enhanced Floppy Mode 2 (OS2) Bit[1] FDC DMA Mode =0 Burst Mode is enabled =1 Non-Burst Mode (default) Bit[3:2] Interface Mode = 11 AT Mode (default) = 10 (Reserved) = 01 PS/2 = 00 Model 30 Bit[4] Reserved Bit[5] Reserved, set to zero Bit[6] FDC Output Type Control =0 FDC outputs are OD24 open drain (default) =1 FDC outputs are O24 push-pull Bit[7] FDC Output Control =0 FDC outputs active (default) =1 FDC outputs tri-stated Note: Bits 6 & 7 do not affect the parallel port FDC pins. Bit[0] Forced Write Protect 0 = 0 Inactive (default) = 1 FDD nWRTPRT input is forced active when the drive has been selected. Bit[1] Reserved Bits[3:2] Density Select = 00 Normal (default) = 01 Normal (reserved for users) = 10 1 (forced to logic "1") = 11 0 (forced to logic "0") Bit[7:4] Reserved. nWRTPRT (to the FDC Core) = (nDS0 AND FORCE WRTPRT) OR nWRTPRT (from the FDD Interface) Note: Boot floppy is always drive 0. Note: the Force Write Protect 0 bit also applies to the Parallel Port FDC. C FDD Option Register Default = 0x00 on VCC POR, VTR POR and HARD RESET 0xF1 R/W C 150 Table 58 - Floppy Disk Controller, Logical Device 0 [Logical Device Number = 0x00] NAME REG INDEX DEFINITION STATE FDD Type Register Default = 0xFF on VCC POR, VTR POR and HARD RESET 0xF2 R/W 0xF3 R FDD0 Default = 0x00 on VCC POR, VTR POR and HARD RESET 0xF4 R/W Bits[1:0] Floppy Drive A Type Bits[3:2] Floppy Drive B Type Bits[5:4] Reserved (could be used to store Floppy Drive C type) Bits[7:6] Reserved (could be used to store Floppy Drive D type) Note: The FDC37M81x supports two floppy drives Reserved, Read as 0 (read only) Bits[1:0] Drive Type Select: DT1, DT0 Bits[2] Read as 0 (read only) Bits[4:3] Data Rate Table Select: DRT1, DRT0 Bits[5] Read as 0 (read only) Bits[6] Precompensation Disable PTS =0 Use Precompensation =1 No Precompensation Bits[7] Read as 0 (read only) Refer to definition and default for 0xF4 C C C FDD1 0xF5 R/W C 151 Table 59 - Parallel Port, Logical Device 3 [Logical Device Number = 0x03] NAME REG INDEX DEFINITION STATE PP Mode Register Default = 0x3C on VCC POR, VTR POR and HARD RESET 0xF0 R/W Bits[2:0] Parallel Port Mode = 100 Printer Mode (default) = 000 Standard and Bi-directional (SPP) Mode = 001 EPP-1.9 and SPP Mode = 101 EPP-1.7 and SPP Mode = 010 ECP Mode = 011 ECP and EPP-1.9 Mode = 111 ECP and EPP-1.7 Mode Bit[6:3] ECP FIFO Threshold 0111b (default) Bit[7] PP Interupt Type Not valid when the parallel port is in the Printer Mode (100) or the Standard & Bi-directional Mode (000). =1 Pulsed Low, released to high-Z. =0 IRQ follows nACK when parallel port in EPP Mode or [Printer,SPP, EPP] under ECP. IRQ level type when the parallel port is in ECP, TEST, or Centronics FIFO Mode. C PP Mode Register 2 Default = 0x00 on VCC POR, VTR POR and HARD RESET 0xF1 R/W Bits[1:0] PPFDC - muxed PP/FDC control = 00 Normal Parallel Port Mode = 01 PPFD1: Drive 0 is on the FDC pins Drive 1 is on the Parallel port pins = 10 PPFD2: Drive 0 is on the Parallel port pins Drive 1 is on the Parallel port pins Bits[7:2] Reserved. Set to zero. 152 Table 60 - Serial Port 1, Logical Device 4 [Logical Device Number = 0x04] NAME REG INDEX DEFINITION STATE Serial Port 1 Mode Register Default = 0x00 on VCC POR, VTR POR and HARD RESET 0xF0 R/W Bit[0] MIDI Mode =0 MIDI support disabled (default) =1 MIDI support enabled Bit[1] High Speed =0 High Speed Disabled(default) =1 High Speed Enabled Bit[6:2] Reserved, set to zero Bit[7]: Share IRQ =0 UARTS use different IRQs =1 UARTS share a common IRQ See Note 1 below. C Note 1: To properly share and IRQ, 1. Configure UART1 (or UART2) to use the desired IRQ pin. 2. Configure UART2 (or UART1) to use No IRQ selected. 3. Set the share IRQ bit. Note: If both UARTs are configured to use different IRQ pins and the share IRQ bit is set, both of the UART IRQ pins will assert when either UART generates an interrupt. UART Interrupt Operation Table Table 61 - Serial Port 2, Logical Device 5 [Logical Device Number = 0x05] NAME REG INDEX DEFINITION then STATE Serial Port 2 Mode Register Default = 0x00 on VCC POR, VTR POR and HARD RESET 0xF0 R/W Bit[0] MIDI Mode =0 MIDI support disabled (default) =1 MIDI support enabled Bit[1] High Speed =0 High Speed disabled(default) =1 High Speed enabled Bit[7:2] Reserved, set to zero C 153 Table 61 - Serial Port 2, Logical Device 5 [Logical Device Number = 0x05] NAME REG INDEX DEFINITION STATE IR Option Register Default = 0x02 on VCC POR, VTR POR and HARD RESET 0xF1 R/W Bit[0] Receive Polarity =0 Active High (Default) =1 Active Low Bit[1] Transmit Polarity =0 Active High =1 Active Low (Default) Bit[2] Duplex Select =0 Full Duplex (Default) =1 Half Duplex Bits[5:3] IR Mode = 000 Standard COM Functionality (Default) = 001 IrDA = 010 ASK-IR = 011 Reserved = 1xx Reserved Bit[6] IR Location Mux =0 Use Serial port TX2 and RX2 (Default) =1 Use alternate IRRX (pin 61) and IRTX (pin 62) Bit[7] Reserved, write 0. Bits [7:0] These bits set the half duplex time-out for the IR port. This value is 0 to 10msec in 100usec increments. 0= blank during transmit/receive 1= blank during transmit/receive + 100usec ... C IR Half Duplex Timeout Default = 0x03 on VCC POR, VTR POR and HARD RESET 0xF2 154 Table 62 - KYBD, Logical Device 7 [Logical Device Number = 0x07] NAME REG INDEX DEFINITION STATE KRST_GA20 Default = 0x00 on VCC POR, VTR POR and HARD RESET 0xF0 R/W KRESET and GateA20 Select Bit[7] Polarity Select for P12 = 0 P12 active low (default) = 1 P12 active high Bit[6] M_ISO. Enables/disables isolation of mouse signals into 8042. Does not affect MDAT signal to mouse wakeup (PME) logic. 1=block mouse clock and data signals into 8042 0= do not block mouse clock and data signals into 8042 Bit[5] K_ISO. Enables/disables isolation of keyboard signals into 8042. Does not affect KDAT signal to keyboard wakeup (PME) logic. 1=block keyboard clock and data signals into 8042 0= do not block keyboard clock and data signals into 8042 Bit[4] MLATCH = 0 MINT is the 8042 MINT ANDed with Latched MINT (default) = 1 MINT is the latched 8042 MINT Bit[3] KLATCH = 0 KINT is the 8042 KINT ANDed with Latched KINT (default) = 1 KINT is the latched 8042 KINT Bit[2] Port 92 Select = 0 Port 92 Disabled = 1 Port 92 Enabled Bit[1] Reserved Bit[0] Reserved Reserved - read as ‘0’ 0xF1 0xFF Table 63 - Auxiliary I/O, Logical Device 8 [Logical Device Number = 0x08] 155 NAME SMI Enable Register 1 REG INDEX 0xB4 R/W Default = 0x00 on VCC POR and VTR POR SMI Enable Register 2 Default = 0x00 on VCC POR and VTR POR Bit 1 is set to ‘1’ on VCC POR, VTR POR, HARD RESET and SOFT RESET 0xB5 R/W DEFINITION This register is used to enable the different interrupt sources onto the group nSMI output. 1=Enable 0=Disable Bit[0] Reserved Bit[1] EN_PINT Bit[2] EN_U2INT Bit[3] EN_U1INT Bit[4] EN_FINT Bit[5] Reserved Bit[6] Reserved Bit[7] EN_WDT This register is used to enable the different interrupt sources onto the group nSMI output, and the group nSMI output onto the nSMI frame in the Serial IRQ stream.. STATE C C Unless otherwise noted, 1=Enable 0=Disable Bit[0] EN_MINT Bit[1] EN_KINT Bit[2] EN_IRINT Bit[3] Reserved Bit[4] EN_P12: Enable 8042 P1.2 to route internally to nSMI. 0=Do not route to nSMI, 1=Enable routing to nSMI. Bit[5] Reserved Bit[6] EN_SMI_S: Enables nSMI Interrupt onto Serial IRQ. Bit[7] Reserved This register is used to read the status of the SMI inputs. The following bits must be cleared at their source. Bit[0] Reserved Bit[1] PINT (Parallel Port Interrupt) The Parallel Port interrupt defaults to ‘1’ when the Parallel Port activate bit is cleared. When the Parallel Port is activated, PINT follows the nACK input. Bit[2] U2INT (UART 2 Interrupt) Bit[3] U1INT (UART 1 Interrupt) Bit[4] FINT (Floppy Disk Controller Interrupt) Bit[5] Reserved Bit[6] Reserved Bit[7] WDT (Watch Dog Timer) This register is used to read the status of the SMI 156 SMI Status Register 1 Default = 0x00 on VCC POR and VTR POR 0xB6 R/W C SMI Status Register 0xB7 R/W C Table 63 - Auxiliary I/O, Logical Device 8 [Logical Device Number = 0x08] REG INDEX DEFINITION 2 inputs. Bit[0] MINT: Mouse Interrupt. Cleared at source. Default = 0x00 Bit[1] KINT: Keyboard Interrupt. Cleared at source. on VCC POR and Bit[2] IRINT: This bit is set by a transition on the IR pin VTR POR (RDX2 or IRRX as selected in CR L5-F1-B6 i.e., after the MUX). Cleared by a read of this register. Bit[3] Reserved Bit[4] P12: 8042 P1.2. Cleared at source Bit[7:5] Reserved Default = 0x00 0xB8 R/W Bits[7:0] Reserved on VTR POR Pin Multiplex 0xC0 Bit[0] Reserved Controls Bit[1] DMA 3 Select Bit[2] Reserved Default = 0x02 on Bit[3] 8042 Select VCC POR, VTR Bit[4] Reserved POR and HARD Bit[5:7] Reserved RESET Force Disk Change 0xC1 Bit[0] Force Change 0 Default = 0x01 on (R/W) 0 = Inactive VCC POR 1 = Active Bit[7:1] Reserved Force Change[0] can be written to 1 but is not clearable by software. Force Change 0 is cleared on nSTEP and nDS0 NAME STATE C C,R Floppy Data Rate Select Shadow 0xC2 (R) UART1 FIFO Control Shadow 0xC3 (R) UART2 FIFO Control Shadow 0xC4 (R) DSKCHG (FDC DIR Register, Bit 7) = (nDS0 AND Force Change 0) OR nDSKCHG Bit[0] Data Rate Select 0 Bit[1] Data Rate Select 1 Bit[2] PRECOMP 0 Bit[3] PRECOMP 1 Bit[4] PRECOMP 2 Bit[5] Reserved Bit[6] Power Down Bit[7] Soft Reset Bit[0] FIFO Enable Bit[1] RCVR FIFO Reset Bit[2] XMIT FIFO Reset Bit[3] DMA Mode Select Bit[5:4] Reserved Bit[6] RCVR Trigger (LSB) Bit[7] RCVR Trigger (MSB) Bit[0] FIFO Enable Bit[1] RCVR FIFO Reset Bit[2] XMIT FIFO Reset 157 C C C Table 63 - Auxiliary I/O, Logical Device 8 [Logical Device Number = 0x08] REG INDEX DEFINITION Bit[3] DMA Mode Select Bit[5:4] Reserved Bit[6] RCVR Trigger (LSB) Bit[7] RCVR Trigger (MSB) PME Control 0xC5 Bit[0] PME_En Default = 0x00 on (R/W) = 0 nIO_PME signal assertion is disabled (default) VTR POR = 1 Enables FDC37M81x to assert nIO_PME signal Bit[7:1] Reserved PME_En is not affected by VCC POR, SOFT RESET or HARD RESET PME Status 0xC6 Bit[0] PME_Status Default = 0x00 on (R/w Clear) = 0 (default) VTR POR = 1 Set when FDC37M81x would normally assert the PCI nIO_PME signal, independent of the state of the PME_En bit. Bit[7:1] Reserved PME_Status is not affected by Vcc POR, SOFT RESET or HARD RESET. Writing a “1” to PME_Status will clear it and cause the FDC37M81x to stop asserting nIO_PME, in enabled. Writing a “0” to PME_Status has no effect. PME Wake Status 0xC7 This register indicates the state of the individual PME Default = 0x00 on (R/w Clear) wake sources, independent of the individual source VTR POR enables or the PME_En bit. If the wake source has asserted a wake event, the associated PME Wake Status bit will be a “1”. Bit[0] Reserved Bit[1] RI2 Bit[2] RI1 Bit[3] KBD Bit[4] MOUSE Bit[7:5] Reserved The PME Wake Status register is not affected by VCC POR, SOFT RESET or HARD RESET. Writing a “1” to Bit[4:0] will clear it. Writing a “0” to any bit in PME Wake Status Register has no effect. 0xC8 This register is used to enable individual FDC37M81x PME Wake Enable (R/W) PME wake sources onto the nIO_PME wake bus. Default = 0x00 on When the PME Wake Enable register bit for a wake VTR POR source is active (“1”), if the source asserts a wake event and the PME_En bit is “1”, the source will assert the PCI nIO_PME signal. When the PME Wake Enable register bit for a wake source is inactive (“0”), the PME Wake Status register will indicate the state of the wake source but will not assert the PCI nIO_PME signal. NAME STATE 158 NAME Table 63 - Auxiliary I/O, Logical Device 8 [Logical Device Number = 0x08] REG INDEX DEFINITION Bit[0] Reserved Bit[1] RI2 Bit[2] RI1 Bit[3] KBD Bit[4] MOUSE Bit[7:5] Reserved The PME Wake Enable register is not affected by Vcc POR, SOFT RESET or HARD RESET. STATE 159 PIN NAME nRTS2 Table 64 - nRTS MUXING MUX CONTROL 16 BIT ADDRESS QUAL. (CR24.6) SELECTED FUNCTION 0 nRTS2 (default) 1 SA12 Table 65 - nCTS2 MUXING MUX CONTROL 16 BIT ADDRESS QUAL. (CR24.6) SELECTED FUNCTION 0 nCTS2 (default) 1 SA13 Table 66 - nDTR2 MUXING MUX CONTROL 16 BIT ADDRESS QUAL. (CR24.6) SELECTED FUNCTION 0 nDTR2 (default) 1 SA14 Table 67 - nDSR2 MUXING MUX CONTROL 16 BIT ADDRESS QUAL. (CR24.6) SELECTED FUNCTION 0 nDSR2 (default) 1 SA15 Table 68 - nDCD2 MUXING MUX CONTROL 8042COMSEL. (LD8:CRC0.3) SELECTED FUNCTION 0 nDCD2 (default) 1 P12 Table 69 - nRI2 MUXING MUX CONTROL 8042COMSEL. (LD8:CRC0.3) SELECTED FUNCTION 0 nR12 (default) 1 P16 STATE OF UNCONNECTED INPUTS 0 PIN NAME nCTS2 STATE OF UNCONNECTED INPUTS 1 0 PIN NAME nDTR2 STATE OF UNCONNECTED INPUTS 0 PIN NAME nDSR2 STATE OF UNCONNECTED INPUTS 1 0 PIN NAME nDCD2 STATE OF UNCONNECTED INPUTS 1 - PIN NAME nRI2 STATE OF UNCONNECTED INPUTS 1 - 160 PIN NAME DRQ3 Table 70 - DRQ3 MUXING MUX CONTROL DMA3SEL (LD8:CRC0.1) SELECTED FUNCTION 1 DRQ3 (default) 0 P12 Table 71 - nDACK3 MUXING MUX CONTROL DMA3SEL (LD8:CRC0.1) SELECTED FUNCTION 1 nDACK3 (default) 0 P16 STATE OF UNCONNECTED INPUTS - PIN NAME nDACK3 STATE OF UNCONNECTED INPUTS 1 - 161 Table 72 - Auxiliary I/O, Logical Device 8 [Logical Device Number = 0x08] NAME REG INDEX DEFINITION STATE WDT_TIME_OUT Default = 0x00 on VCC POR, VTR POR and HARD RESET WDT_VAL Default = 0x00 on VCC POR, VTR POR and HARD RESET WDT_CFG Default = 0x00 on VCC POR, VTR POR and HARD RESET 0xF1 Bit[0] Reserved Bit[1] Reserved Bits[6:2] Reserved, = 00000 Bit[7] WDT Time-out Value Units Select = 0 Minutes (default) = 1 Seconds Watch-dog Timer Time-out Value Binary coded, units = minutes (default) or seconds, selectable via Bit[7] of Reg 0xF1, LD 8. 0x00 Time out disabled 0x01 Time-out = 1 minute (second) ......... 0xFF Time-out = 255 minutes (seconds) Watch-dog timer Configuration Bit[0] Joy-stick Enable =1 WDT is reset upon an I/O read or write of the Game Port =0 WDT is not affected by I/O reads or writes to the Game Port. Bit[1] Keyboard Enable =1 WDT is reset upon a Keyboard interrupt. =0 WDT is not affected by Keyboard interrupts. Bit[2] Mouse Enable =1 WDT is reset upon a Mouse interrupt. =0 WDT is not affected by Mouse interrupts. Bit[3] Reserved Bits[7:4] WDT Interrupt Mapping 1111 = IRQ15 ......... 0011 = IRQ3 0010 = Invalid 0001 = IRQ1 0000 = Disable C 0xF2 C 0xF3 C 162 Table 72 - Auxiliary I/O, Logical Device 8 [Logical Device Number = 0x08] NAME REG INDEX DEFINITION STATE WDT_CTRL Default = 0x00 on VCC POR, VTR POR and HARD RESET 0xF4 Watch-dog timer Control Bit[0] Watch-dog Status Bit, R/W =1 WD timeout occurred =0 WD timer counting Bit[1] Reserved Bit[2] Force Timeout, W =1 Forces WD timeout event; this bit is selfclearing Bit[3] P20 Force Timeout Enable, R/W =1 Allows rising edge of P20, from the Keyboard Controller, to force the WD timeout event. A WD timeout event may still be forced by setting the Force Timeout Bit, bit 2. =0 P20 activity does not generate the WD timeout event. Note: The P20 signal will remain high for a minimum of 1us and can remain high indefinitely. Therefore, when P20 forced timeouts are enabled, a self-clearing edgedetect circuit is used to generate a signal which is ORed with the signal generated by the Force Timeout Bit. Bit[7:4] Reserved. Set to 0 C 163 OPERATIONAL DESCRIPTION MAXIMUM GUARANTEED RATINGS Operating Temperature Range.....................................................................................................0oC to +70oC Storage Temperature Range ..................................................................................................... -55o to +150oC Lead Temperature Range........................................................................... Refer to JEDEC Spec. J-STD-020 Positive Voltage on any pin, with respect to Ground ...........................................................................Vcc+0.3V Negative Voltage on any pin, with respect to Ground............................................................................... -0.3V Maximum Vcc ............................................................................................................................................... +7V Note: Stresses above those listed above could cause permanent damage to the device. This is a stress rating only and functional operation of the device at any other condition above those indicated in the operation sections of this specification is not implied. Note: When powering this device from laboratory or system power supplies, it is important that the Absolute Maximum Ratings not be exceeded or device failure can result. Some power supplies exhibit voltage spikes on their outputs when the AC power is switched on or off. In addition, voltage transients on the AC power line may appear on the DC output. If this possibility exists, it is suggested that a clamp circuit be used. DC ELECTRICAL CHARACTERISTICS (TA = 0°C - 70°C, Vcc, VTR = +5 V ± 10%) PARAMETER SYMBOL I Type Input Buffer MIN TYP MAX UNITS COMMENTS Low Input Level High Input Level IS Type Input Buffer VILI VIHI 2.0 0.8 V V TTL Levels Low Input Level High Input Level Schmitt Trigger Hysteresis ICLK Input Buffer VILIS VIHIS VHYS 2.2 250 0.8 V V mV Schmitt Trigger Schmitt Trigger Low Input Level High Input Level Input Leakage (All I and IS buffers) VILCK VIHCK 2.2 0.4 V V Low Input Leakage High Input Leakage IIL IIH -10 -10 164 +10 +10 μA μA VIN = 0 VIN = VCC PARAMETER O4 Type Buffer SYMBOL MIN TYP MAX UNITS COMMENTS Low Output Level High Output Level Output Leakage IO8 Type Buffer VOL VOH IOL 2.4 -10 0.4 V V IOL = 4 mA IOH = -2 mA VIN = 0 to VCC (Note 1) +10 μA Low Output Level High Output Level Output Leakage O8SR Type Buffer VOL VOH IOL 2.4 -10 0.4 V V IOL = 8 mA IOH = -4 mA VIN = 0 to VCC (Note 1) +10 μA Low Output Level High Output Level Output Leakage Rise Time Fall Time O24 Type Buffer VOL VOH IOL TRT TFL 2.4 -10 5 5 0.4 V V IOL = 8 mA IOH = -8 mA VIN = 0 to VCC (Note 1) +10 μA ns ns Low Output Level High Output Level Output Leakage VOL VOH IOL 2.4 -10 0.4 V V IOL = 24 mA IOH = -12 mA VIN = 0 to VCC (Note 1) +10 μA IO12 Type Buffer Low Output Level High Output Level Output Leakage VOL VOH IOL 2.4 -10 0.4 V V IOL = 12 mA IOH = -6 mA VIN = 0 to VCC (Note 1) +10 μA 165 PARAMETER O12 Type Buffer SYMBOL MIN TYP MAX UNITS COMMENTS Low Output Level High Output Level Output Leakage O24PD Type Buffer VOL VOH IOL 2.4 -10 0.4 V V IOL = 12 mA IOH = -6 mA VIN = 0 to VCC (Note 1) +10 μA Low Output Level High Output Level Output Leakage O16SR Type Buffer VOL VOH IOL 2.4 -10 0.4 V V IOL = 24 mA IOH = -12 mA VIN = 0 to VCC (Note 1) +10 μA Low Output Level High Output Level Output Leakage Rise Time Fall Time OD16P Type Buffer VOL VOH IOL TRT TFL 2.4 -10 5 5 0.4 V V IOL = 16 mA IOH = -16 mA VIN = 0 to VCC (Note 1) +10 μA ns ns Low Output Level Output Leakage OD24 Type Buffer VOL IOL -10 0.4 +10 V μA IOL = 16 mA IOH = 90 μA VIN = 0 to VCC (Note 1) Low Output Level Output Leakage OD48 Type Buffer VOL IOL 0.4 +10 V μA IOL = 24 mA VIN = 0 to VCC (Note 1) Low Output Level Output Leakage VOL IOL 166 0.4 +10 V μA IOL = 48 mA VIN = 0 to VCC (Note 1) PARAMETER ChiProtect (SLCT, PE, BUSY, nACK, nERROR) OD12 Type Buffer SYMBOL MIN TYP MAX UNITS μA COMMENTS IIL ± 10 VCC = 0V VIN = 6V Max Low Output Level Output Leakage Backdrive (nSTROBE, nAUTOFD, nINIT, nSLCTIN) Backdrive (PD0-PD7) VOL IOL IIL -10 0.4 +10 ± 10 V μA μA IOL = 12 mA VIN = 0 to VCC (Note 1) VCC = 0V VIN = 6V Max VCC = 0V VIN = 6V Max All Outputs Open VCC must not be greater than .5V above VTR All outputs open IIL ICCI VTR VCC min -.5V5 6 15 ± 10 30 VCC max 10 μA VCC Supply Current Active (Note 4) Trickle Supply Voltage mA V VTR Supply Current Active (Note 4) ITRI mA Note 1: All output leakage’s are measured with the current pins in high impedance. Note 2: Output leakage is measured with the low driving output off, either for a high level output or a high impedance state. Note 3: KBCLK, KBDATA, MCLK, MDATA contain 90μA min pull-ups. Note 4: Please contact SMSC for the latest value. Note 5: The minimum value given for VTR applies when VCC is active. When VCC is 0V, the minimum VTR is 0V. 167 CAPACITANCE TA = 25°C; fc = 1MHz; VCC = 5V PARAMETER Clock Input Capacitance SYMBOL CIN MIN LIMITS TYP MAX 20 UNIT pF TEST CONDITION All pins except pin under test tied to AC ground Input Capacitance Output Capacitance CIN COUT 10 20 pF pF 168 TIMING DIAGRAMS For the Timing Diagrams shown, the following capacitive loads are used on outputs. CAPACITANCE TOTAL (pF) 50 240 50 240 240 240 50 240 50 50 50 240 240 50 240 50 50 240 240 240 240 50 NAME SD[7:0] PD[7:0] DRQx nDIR nSTEP nDS0-1 nMTR0-1 nWDATA nRTSx nDTRx nINIT nSTROBE nALF nSLCTIN IOCHRDY TXD1 TXD2 KDAT KCLK MDAT MCLK SER_IRQ 169 t3 SAx t4 SD nIOW t1 t2 t5 FIGURE 4 - IOW TIMING FOR PORT 92 IOW Timing NAME DESCRIPTION MIN TYP MAX UNITS t1 t2 t3 t4 t5 SAx Valid to nIOW Asserted SDATA Valid to nIOW Asserted nIOW Asserted to SAx Invalid nIOW Deasserted to DATA Invalid nIOW Deasserted to nIOW or nIOR Asserted 40 0 10 0 100 ns ns ns ns ns 170 t1 V cc t2 t3 A ll H o s t A ccesses FIGURE 5 - POWER-UP TIMING NAME DESCRIPTION MIN TYP MAX UNITS μs μs t1 t2 t3 Vcc Slew from 4.5V to 0V Vcc Slew from 0V to 4.5V All Host Accesses After Powerup (Note 1) 300 100 125 500 μs Note 1: Internal write-protection period after Vcc passes 4.5 volts on power-up 171 t7 AEN t3 SA[x], nCS t2 nIOW t1 t4 t6 t5 SD[x] DATA VALID FIGURE 6 - ISA WRITE NAME DESCRIPTION MIN TYP MAX UNITS t1 t2 t3 t4 t5 t6 t7 SA[x], nCS and AEN valid to nIOW asserted nIOW asserted to nIOW deasserted nIOW asserted to SA[x], nCS invalid SD[x] Valid to nIOW deasserted SD[x] Hold from nIOW deasserted nIOW deasserted to nIOW asserted nIOW deasserted to AEN invalid 10 80 10 45 0 25 10 ns ns ns ns ns ns ns 172 t9 AEN t3 SA[x], nCS t1 nIOR t7 t4 SD[x] DATA VALID t2 t5 t6 PD[x], nERROR, PE, SLCT, nACK, BUSY t8 nIOR/nIOW FIGURE 7 - ISA READ ISA READ TIMING DESCRIPTION NAME MIN TYP MAX UNITS t1 t2 t3 t4 t5 t6 t7 t8 t8 t9 SA[x], nCS and AEN valid to nIOR asserted nIOR asserted to nIOR deasserted nIOR asserted to SA[x], nCS invalid nIOR asserted to Data Valid Data Hold/float from nIOR deasserted nIOR deasserted Parallel Port setup to nIOR asserted nIOR asserted after nIOW deasserted nIOR/nIOR, nIOW/nIOW transfers from/to ECP FIFO nIOW deasserted to AEN invalid 10 50 10 50 10 25 20 80 150 10 25 ns ns ns ns ns ns ns ns ns ns 173 KCLK/ MCLK t1 CLK CLK 1 2 t3 t4 t2 t6 CLK 9 CLK 10 CLK 11 t5 KDAT/ Start Bit MDAT Bit 0 Bit 7 Parity Bit Stop Bit FIGURE 8 - KEYBOARD/MOUSE RECEIVE/SEND DATA TIMING NAME DESCRIPTION MIN TYP MAX UNITS t1 t2 t3 t4 t5 t6 Time from DATA transition to falling edge of CLOCK (Receive) Time from rising edge of CLOCK to DATA transition (Receive) Duration of CLOCK inactive (Receive/Send) Duration of CLOCK active (Receive/Send) Time to keyboard inhibit after clock 11 to ensure the keyboard does not start another transmission (Receive) Time from inactive to active CLOCK transition, used to time when the auxiliary device samples DATA (Send) 5 5 30 30 >0 5 25 T4-5 50 50 50 25 µsec µsec µsec µsec µsec µsec 174 t1 t2 CLOCKI FIGURE 9A - INPUT CLOCK TIMING NAME t1 t2 DESCRIPTION Clock Cycle Time for 14.318MHz (Note) Clock High Time/Low Time for 14.318MHz Clock Rise Time/Fall Time (not shown) Tolerance is ± 0.01% MIN TYP 69.84 35 MAX UNITS ns ns ns t2 20 5 Note: P C I_ C L K t1 t5 t3 t4 t2 FIGURE 9B – PCI CLOCK TIMING NAME t1 t2 t3 t4 t5 DESCRIPTION Period High Time Low Time Rise Time Fall Time MIN 30 12 12 TYP MAX 33.3 3 3 UNITS nsec nsec nsec nsec nsec FIGURE 9C - RESET TIMING t1 nR ESET_DRV NAME DESCRIPTION MIN TYP MAX UNITS t1 nRESET_DRV width (Note) 1.5 μs Note: The RESET width is dependent upon the processor clock. The RESET must be active while the clock is running and stable. 175 t15 AEN t16 t3 t2 FDRQ, PDRQ t1 nDACK[x] t12 t14 t11 t6 t5 nIOR or nIOW t7 SD t13 TC DATA VALID t8 t4 t10 t9 FIGURE 10A - DMA TIMING (SINGLE TRANSFER MODE) NAME DESCRIPTION t1 nDACK Delay Time from FDRQ High t2 DRQ Reset Delay from nIOR or nIOW t3 FDRQ Reset Delay from nDACK Low t4 nDACK Width t5 nIOR Delay from FDRQ High t6 nIOW Delay from FDRQ High t7 SData Access Time from nIOR Low t8 SData Set Up Time to nIOW High t9 SData to Float Delay from nIOR High t10 SData Hold Time from nIOW High t11 nDACK Set Up to nIOW/nIOR Low t12 nDACK Hold after nIOW/nIOR High t13 TC Pulse Width t14 AEN Set Up to nIOR/nIOW t15 AEN Hold from nDACK t16 TC Active to PDRQ Inactive Note: FDRQ is the DMA request for the FDC. PDRQ is the DMA request for the Parallel Port. MIN 0 TYP MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 100 100 150 0 0 100 40 10 10 5 10 60 40 10 60 100 176 t15 AEN t16 t3 t2 FDRQ, PDRQ t1 nDACK[x] t12 t14 t11 t6 nIOR or nIOW t5 t8 t4 t7 SD DATA VALID t13 TC t10 t9 DATA VALID FIGURE 10B - DMA TIMING (BURST TRANSFER MODE) NAME DESCRIPTION MIN TYP t1 nDACK Delay Time from FDRQ High 0 t2 DRQ Reset Delay from nIOR or nIOW t3 FDRQ Reset Delay from nDACK Low t4 nDACK Width 150 t5 nIOR Delay from FDRQ High 0 t6 nIOW Delay from FDRQ High 0 t7 SData Access Time from nIOR Low t8 SData Set Up Time to nIOW High 40 t9 SData to Float Delay from nIOR High 10 t10 SData Hold Time from nIOW High 10 t11 nDACK Set Up to nIOW/nIOR Low 5 t12 nDACK Hold after nIOW/nIOR High 10 t13 TC Pulse Width 60 t14 AEN Set Up to nIOR/nIOW 40 t15 AEN Hold from nDACK 10 t16 TC Active to PDRQ Inactive Note: FDRQ is the DMA request for the FDC. PDRQ is the DMA request for the Parallel Port. MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 100 100 100 60 100 177 nDIR t4 t1 nSTEP t2 t5 nDS0-3 t6 nINDEX t7 nRDATA t8 nWDATA nIOW t9 nDS0-1, nMTR0-1 t9 FIGURE 11 - DISK DRIVE TIMING (AT MODE ONLY) NAME DESCRIPTION MIN TYP MAX UNITS t1 t2 t3 t4 t5 t6 t7 t8 t9 nDIR Set Up to STEP Low nSTEP Active Time Low nDIR Hold Time after nSTEP nSTEP Cycle Time nDS0-1 Hold Time from nSTEP Low nINDEX Pulse Width nRDATA Active Time Low nWDATA Write Data Width Low nDS0-1, MTRO-1 from End of nIOW 4 24 96 132 20 2 40 .5 25 X* X* X* X* X* X* ns Y* ns *X specifies one MCLK period and Y specifies one WCLK period. MCLK = 16 x Data Rate (at 500 kb/s MCLK = 8 MHz) WCLK = 2 x Data Rate (at 500 kb/s WCLK = 1 MHz) 178 nIOW t1 nRTSx, nDTRx FIGURE 12A - SERIAL PORT TIMING NAME DESCRIPTION MIN TYP MAX UNITS t1 nRTSx, nDTRx Delay from nIOW 200 ns Data Start TXD1, 2 Data (5-8 Bits) t1 Parity Stop (1-2 Bits) FIGURE 12B – SERIAL PORT DATA NAME DESCRIPTION MIN TYP MAX UNITS t1 Serial Port Data Bit Time tBR1 nsec Note 1: tBR is 1/Baud Rate. The Baud Rate is programmed through the divisor latch registers. Baud Rates have percentage errors indicated in the “Baud Rate” table in the “Serial Port” section. PCI_CLK t1 SER_IRQ t2 FIGURE 12C – SETUP AND HOLD TIME NAME t1 t2 DESCRIPTION SER_IRQ Setup Time to PCI_CLK Rising SER_IRQ Hold Time to PCI_CLK Rising MIN 7 0 TYP MAX UNITS nsec nsec 179 PD t2 nIOW t1 nINIT, nSTROBE, nALF, SLCTIN FIGURE 13 - PARALLEL PORT TIMING NAME DESCRIPTION MIN TYP MAX UNITS t1 t2 PD0-7, nINIT, nSTROBE, nALF Delay from nIOW PD0 - PD7 Delay from IOW Active 100 100 ns ns 180 t18 SA t9 SD nIOW IOCHRDY t13 nWRITE PD t16 t3 t20 t1 t2 t5 t17 t8 t10 t11 t12 t19 nDATASTB nADDRSTB t14 t4 t6 nWAIT t15 t7 FIGURE 14 - EPP 1.9 DATA OR ADDRESS WRITE CYCLE SEE TIMING PARAMETERS ON NEXT PAGE 181 TABLE 73 - EPP 1.9 DATA OR ADDRESS WRITE CYCLE TIMING NAME DESCRIPTION MIN TYP MAX UNITS t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 nIOW Asserted to PDATA Valid nWAIT Asserted to nWRITE Change (Note 1) nWRITE to Command Asserted nWAIT Deasserted to Command Deasserted (Note 1) nWAIT Asserted to PDATA Invalid (Note 1) Time Out Command Deasserted to nWAIT Asserted SDATA Valid to nIOW Asserted nIOW Deasserted to SDATA Invalid nIOW Asserted to IOCHRDY Asserted nWAIT Deasserted to IOCHRDY Deasserted (Note 1) IOCHRDY Deasserted to nIOW Deasserted nIOW Asserted to nWRITE Asserted nWAIT Asserted to Command Asserted (Note 1) Command Asserted to nWAIT Deasserted PDATA Valid to Command Asserted Ax Valid to nIOW Asserted nIOW Asserted to Ax Invalid nIOW Deasserted to nIOW or nIOR Asserted nWAIT Asserted to nWRITE Asserted (Note 1) 0 60 5 60 0 10 0 10 0 0 60 10 0 60 0 10 40 10 40 60 50 185 35 190 ns ns ns ns ns 12 s ns ns ns 24 160 ns ns ns 70 210 10 ns ns s ns ns ns ns 185 ns Note 1: nWAIT must be filtered to compensate for ringing on the parallel bus cable. WAIT is considered to have settled after it does not transition for a minimum of 50 nsec. 182 t20 A0-A10 IOR t19 t13 SD t8 t24 t23 PDIR t9 t21 nWRITE t2 t25 PD t28 t26 t1 DATASTB ADDRSTB t15 t7 nWAIT t6 t14 t3 t5 PData bus driven by peripheral t11 t12 t18 t10 t22 IOCHRDY t27 t17 t4 t16 FIGURE 15 - EPP 1.9 DATA OR ADDRESS READ CYCLE SEE TIMING PARAMETERS ON NEXT PAGE 183 TABLE 74 - EPP 1.9 DATA OR ADDRESS READ CYCLE TIMING PARAMETERS NAME t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 t26 t27 t28 Note 1: Note 2: Note 3: DESCRIPTION PDATA Hi-Z to Command Asserted nIOR Asserted to PDATA Hi-Z nWAIT Deasserted to Command Deasserted (Note 1) Command Deasserted to PDATA Hi-Z Command Asserted to PDATA Valid PDATA Hi-Z to nWAIT Deasserted PDATA Valid to nWAIT Deasserted nIOR Asserted to IOCHRDY Asserted nWRITE Deasserted to nIOR Asserted (Note 2) nWAIT Deasserted to IOCHRDY Deasserted (Note 1) IOCHRDY Deasserted to nIOR Deasserted nIOR Deasserted to SDATA Hi-Z (Hold Time) PDATA Valid to SDATA Valid nWAIT Asserted to Command Asserted Time Out nWAIT Deasserted to PDATA Driven (Note 1) nWAIT Deasserted to nWRITE Modified (Notes 1,2) SDATA Valid to IOCHRDY Deasserted (Note 3) Ax Valid to nIOR Asserted nIOR Deasserted to Ax Invalid nWAIT Asserted to nWRITE Deasserted nIOR Deasserted to nIOW or nIOR Asserted nWAIT Asserted to PDIR Set (Note 1) PDATA Hi-Z to PDIR Set nWAIT Asserted to PDATA Hi-Z (Note 1) PDIR Set to Command nWAIT Deasserted to PDIR Low (Note 1) nWRITE Deasserted to Command MIN 0 0 60 0 0 0 0 0 0 60 0 0 0 0 10 60 60 0 40 10 0 40 60 0 60 0 60 1 180 20 180 185 10 185 40 75 195 12 190 190 85 160 24 TYP MAX 30 50 180 UNITS ns ns ns ns ns μs ns ns ns ns ns ns ns ns μs ns ns ns ns ns ns ns ns ns ns ns ns ns nWAIT is considered to have settled after it does not transition for a minimum of 50 ns. When not executing a write cycle, EPP nWRITE is inactive high. 85 is true only if t7 = 0. 184 t18 A0-A10 t9 SD t17 t8 t6 t12 t10 t20 t19 nIOW IOCHRDY t13 nWRITE t1 PD t11 t2 t5 t16 t3 nDATAST nADDRSTB t4 t21 nWAIT PDIR FIGURE 16 - EPP 1.7 DATA OR ADDRESS WRITE CYCLE SEE TIMING PARAMETERS ON NEXT PAGE 185 TABLE 75 - EPP 1.7 DATA OR ADDRESS WRITE CYCLE PARAMETERS NAME DESCRIPTION MIN TYP MAX UNITS t1 t2 t3 t4 t5 t6 t8 t9 t10 t11 t12 t13 t16 t17 t18 t19 t20 t21 nIOW Asserted to PDATA Valid Command Deasserted to nWRITE Change nWRITE to Command nIOW Deasserted to Command Deasserted (Note 2) Command Deasserted to PDATA Invalid Time Out SDATA Valid to nIOW Asserted nIOW Deasserted to DATA Invalid nIOW Asserted to IOCHRDY Asserted nWAIT Deasserted to IOCHRDY Deasserted IOCHRDY Deasserted to nIOW Deasserted nIOW Asserted to nWRITE Asserted PDATA Valid to Command Asserted Ax Valid to nIOW Asserted nIOW Deasserted to Ax Invalid nIOW Deasserted to nIOW or nIOR Asserted nWAIT Asserted to IOCHRDY Deasserted Command Deasserted to nWAIT Deasserted 0 0 5 50 10 10 0 0 10 0 10 40 10 100 50 40 35 50 12 ns ns ns ns ns μs ns ns 24 40 50 35 ns ns ns ns ns ns μs ns 45 ns ns 0 Note 1: nWRITE is controlled by clearing the PDIR bit to "0" in the control register before performing an EPP Write. Note 2: The number is only valid if nWAIT is active when IOW goes active. 186 t20 A0-A10 t15 t19 nIOR t13 SD t8 t3 IOCHRDY t10 t11 t22 t12 nWRITE t5 PD t23 nDATASTB nADDRSTB t2 t4 t21 nWAIT PDIR FIGURE 17 - EPP 1.7 DATA OR ADDRESS READ CYCLE SEE TIMING PARAMETERS ON NEXT PAGE 187 TABLE 76 - EPP 1.7 DATA OR ADDRESS READ CYCLE PARAMETERS NAME DESCRIPTION MIN TYP MAX UNITS t2 t3 t4 t5 t8 t10 t11 t12 t13 t15 t19 t20 t21 t22 t23 Note: nIOR Deasserted to Command Deasserted nWAIT Asserted to IOCHRDY Deasserted Command Deasserted to PDATA Hi-Z Command Asserted to PDATA Valid nIOR Asserted to IOCHRDY Asserted nWAIT Deasserted to IOCHRDY Deasserted IOCHRDY Deasserted to nIOR Deasserted nIOR Deasserted to SDATA High-Z (Hold Time) PDATA Valid to SDATA Valid Time Out Ax Valid to nIOR Asserted nIOR Deasserted to Ax Invalid Command Deasserted to nWAIT Deasserted nIOR Deasserted to nIOW or nIOR Asserted nIOR Asserted to Command Asserted 10 40 10 0 40 0 0 0 0 0 50 40 ns ns ns ns 24 50 40 40 12 ns ns ns ns ns μs ns ns ns ns 55 ns WRITE is controlled by setting the PDIR bit to "1" in the control register before performing an EPP Read. 188 ECP PARALLEL PORT TIMING Parallel Port FIFO (Mode 101) Reverse-Idle Phase The standard parallel port is run at or near the peak 500KBytes/sec allowed in the forward direction using DMA. The state machine does not examine nACK and begins the next transfer based on Busy. Refer to Figure 19. ECP Parallel Port Timing The peripheral has no data to send and keeps PeriphClk high. The host is idle and keeps HostAck low. Reverse Data Transfer Phase The timing is designed to allow operation at approximately 2.0 Mbytes/sec over a 15ft cable. If a shorter cable is used then the bandwidth will increase. Forward-Idle The interface transfers data and commands from the peripheral to the host using an interlocked HostAck and PeriphClk. The Reverse Data Transfer Phase may be entered from the Reverse-Idle Phase. After the previous byte has beed accepted the host sets HostAck (nALF) low. The peripheral then sets PeriphClk (nACK) low when it has data to send. The data must be stable for the specified setup time prior to the falling edge of PeriphClk. When the host is ready to accept a byte it sets HostAck (nALF) high to acknowledge the handshake. The peripheral then sets PeriphClk (nACK) high. After the host has accepted the data it sets HostAck (nALF) low, completing the transfer. This sequence is shown in Figure 20. Output Drivers When the host has no data to send it keeps HostClk (nStrobe) high and the peripheral will leave PeriphClk (Busy) low. Forward Data Transfer Phase The interface transfers data and commands from the host to the peripheral using an interlocked PeriphAck and HostClk. The peripheral may indicate its desire to send data to the host by asserting nPeriphRequest. The Forward Data Transfer Phase may be entered from the Forward-Idle Phase. While in the Forward Phase the peripheral may asynchronously assert the nPeriphRequest (nFault) to request that the channel be reversed. When the peripheral is not busy it sets PeriphAck (Busy) low. The host then sets HostClk (nStrobe) low when it is prepared to send data. The data must be stable for the specified setup time prior to the falling edge of HostClk. The peripheral then sets PeriphAck (Busy) high to acknowledge the handshake. The host then sets HostClk (nStrobe) high. The peripheral then accepts the data and sets PeriphAck (Busy) low, completing the transfer. This sequence is shown in Figure 19. The timing is designed to provide 3 cable round-trip times for data setup if Data is driven simultaneously with HostClk (nStrobe). 189 To facilitate higher performance data transfer, the use of balanced CMOS active drivers for critical signals (Data, HostAck, HostClk, PeriphAck, PeriphClk) are used ECP Mode. Because the use of active drivers can present compatibility problems in Compatible Mode (the control signals, by tradition, are specified as open-collector), the drivers are dynamically changed from open-collector to totem-pole. The timing for the dynamic driver change is specified in then IEEE 1284 Extended Capabilities Port Protocol and ISA Interface Standard, Rev. 1.14, July 14, 1993, available from Microsoft. The dynamic driver change must be implemented properly to prevent glitching the outputs. t6 t3 PD t1 t2 t5 nSTROBE t4 BUSY FIGURE 18 - PARALLEL PORT FIFO TIMING NAME DESCRIPTION MIN TYP MAX UNITS t1 t2 t3 t4 t5 t6 PDATA Valid to nSTROBE Active nSTROBE Active Pulse Width PDATA Hold from nSTROBE Inactive (Note 1) nSTROBE Active to BUSY Active BUSY Inactive to nSTROBE Active BUSY Inactive to PDATA Invalid (Note 1) 600 600 450 500 680 80 ns ns ns ns ns ns Note 1: The data is held until BUSY goes inactive or for time t3, whichever is longer. This only applies if another data transfer is pending. If no other data transfer is pending, the data is held indefinitely. 190 t3 nALF t4 PD t2 t1 t7 nSTROBE t6 BUSY t5 t6 t8 FIGURE 19 - ECP PARALLEL PORT FORWARD TIMING NAME DESCRIPTION MIN TYP MAX UNITS t1 t2 t3 t4 t5 t6 t7 t8 nALF Valid to nSTROBE Asserted PDATA Valid to nSTROBE Asserted BUSY Deasserted to nALF Changed (Notes 1,2) BUSY Deasserted to PDATA Changed (Notes 1,2) nSTROBE Deasserted to Busy Asserted nSTROBE Deasserted to Busy Deasserted BUSY Deasserted to nSTROBE Asserted (Notes 1,2) BUSY Asserted to nSTROBE Deasserted (Note 2) 0 0 80 80 0 0 80 80 60 60 180 180 ns ns ns ns ns ns 200 180 ns ns Note 1: Maximum value only applies if there is data in the FIFO waiting to be written out. Note 2: BUSY is not considered asserted or deasserted until it is stable for a minimum of 75 to 130 ns. 191 t2 PD t1 t5 nACK t4 nALF t3 t4 t6 FIGURE 20 - ECP PARALLEL PORT REVERSE TIMING NAME DESCRIPTION MIN TYP MAX UNITS t1 t2 t3 t4 t5 t6 PDATA Valid to nACK Asserted nALF Deasserted to PDATA Changed nACK Asserted to nALF Deasserted (Notes 1,2) nACK Deasserted to nALF Asserted (Note 2) nALF Asserted to nACK Asserted nALF Deasserted to nACK Deasserted 0 0 80 80 0 0 200 200 ns ns ns ns ns ns Note 1: Maximum value only applies if there is room in the FIFO and terminal count has not been received. ECP can stall by keeping nALF low. Note 2: nACK is not considered asserted or deasserted until it is stable for a minimum of 75 to 130 ns. 192 DATA 0 t2 t1 1 0 1 0 0 1 1 0 1 1 t2 t1 IRRX n IRRX Parameter t1 t1 t1 t1 t1 t1 t1 t2 t2 t2 t2 t2 t2 t2 Pulse Width at 115kbaud Pulse Width at 57.6kbaud Pulse Width at 38.4kbaud Pulse Width at 19.2kbaud Pulse Width at 9.6kbaud Pulse Width at 4.8kbaud Pulse Width at 2.4kbaud Bit Time at 115kbaud Bit Time at 57.6kbaud Bit Time at 38.4kbaud Bit Time at 19.2kbaud Bit Time at 9.6kbaud Bit Time at 4.8kbaud Bit Time at 2.4kbaud min 1.4 1.4 1.4 1.4 1.4 1.4 1.4 typ 1.6 3.22 4.8 9.7 19.5 39 78 8.68 17.4 26 52 104 208 416 max 2.71 3.69 5.53 11.07 22.13 44.27 88.55 units µs µs µs µs µs µs µs µs µs µs µs µs µs µs Notes: 1. Receive Pulse Detection Criteria: A received pulse is considered detected if the received pulse is a minimum of 1.41µs. 2. IRRX: L5, CRF1 Bit 0 = 1 nIRRX: L5, CRF1 Bit 0 = 0 (default) FIGURE 21 - IrDA RECEIVE TIMING 193 DATA 0 t2 t1 1 0 1 0 0 1 1 0 1 1 t2 t1 IRTX n IRTX Parameter t1 t1 t1 t1 t1 t1 t1 t2 t2 t2 t2 t2 t2 t2 Pulse Width at 115kbaud Pulse Width at 57.6kbaud Pulse Width at 38.4kbaud Pulse Width at 19.2kbaud Pulse Width at 9.6kbaud Pulse Width at 4.8kbaud Pulse Width at 2.4kbaud Bit Time at 115kbaud Bit Time at 57.6kbaud Bit Time at 38.4kbaud Bit Time at 19.2kbaud Bit Time at 9.6kbaud Bit Time at 4.8kbaud Bit Time at 2.4kbaud min 1.41 1.41 1.41 1.41 1.41 1.41 1.41 typ 1.6 3.22 4.8 9.7 19.5 39 78 8.68 17.4 26 52 104 208 416 max 2.71 3.69 5.53 11.07 22.13 44.27 88.55 units µs µs µs µs µs µs µs µs µs µs µs µs µs µs Notes: 1. IrDA @ 115k is HPSIR compatible. IrDA @ 2400 will allow compatibility with HP95LX and 48SX. 2. IRTX: L5, CRF1 Bit 1: 1 = XMIT active low (default) nIRTX: L5, CRF1 Bit 1: 0 = XMIT active high FIGURE 22 - IrDA TRANSMIT TIMING 194 DATA 0 t1 1 t2 0 1 0 0 1 1 0 1 1 IRRX n IRRX t3 MIRRX t4 t5 nMIRRX t6 Parameter t1 t2 t3 t4 t5 t6 Modulated Output Bit Time Off Bit Time Modulated Output "On" Modulated Output "Off" Modulated Output "On" Modulated Output "Off" min typ max units µs µs 0.8 0.8 0.8 0.8 1 1 1 1 1.2 1.2 1.2 1.2 µs µs µs µs Notes: 1. IRRX: L5, CRF1 Bit 0: 1 = RCV active low nIRRX: L5, CRF1 Bit 0: 0 = RCV active high (default) MIRRX, nMIRRX are the modulated outputs FIGURE 23 - AMPLITUDE SHIFT KEYED IR RECEIVE TIMING 195 DATA 0 t1 1 t2 0 1 0 0 1 1 0 1 1 IRTX n IRTX t3 MIRTX t5 nMIRTX t4 t6 Parameter t1 t2 t3 t4 t5 t6 Modulated Output Bit Time Off Bit Time Modulated Output "On" Modulated Output "Off" Modulated Output "On" Modulated Output "Off" min typ max units µs µs 0.8 0.8 0.8 0.8 1 1 1 1 1.2 1.2 1.2 1.2 µs µs µs µs Notes: 1. IRTX: L5, CRF1 Bit 1: 1 = XMIT active low (default) nIRTX: L5, CRF1 Bit 1: 0 = XMIT active high MIRTX, nMIRTX are the modulated outputs FIGURE 24 - AMPLITUDE SHIFT KEYED IR TRANSMIT TIMING 196 D D1 E E1 e W A H 0 .10 -CDIM A A1 A2 D D1 E E1 H L L1 e 0 W TD(1) TE(1) TD(2) TE(2) A2 TD/TE 0 A1 M IN M AX 2.80 3.15 0.1 0.45 2.57 2.87 23.4 24.15 19.9 20.1 17.4 18.15 13.9 14.1 0.1 0.2 0.65 0.95 1.8 2.6 0.65 BSC 0° 12° .2 .4 21.8 22.2 15.8 16.2 22.21 22.76 16.27 16.82 M AX M IN .124 .110 .018 .004 .113 .101 .951 .921 .791 .783 .715 .685 .555 .547 .008 .004 .037 .026 .102 .071 .0256 BSC 0° 12° .008 .016 .858 .874 .622 .638 .874 .896 .641 .662 L L1 Notes: 1) Coplanarity is 0.100m m (.004") m ax im um . 2) Toleranc e on the position of the leads is 0.200m m (.008") m axim um . 3) Package body dim ens ions D1 and E1 do not include the m old protrusion. M axim um m old protrus ion is 0.25m m (.010"). 4) Dim ensions TD and TE are im portant for testing by robotic handler. Only above com binations of (1) or (2) are acc eptable. 5) Controlling dim ens ion: m illim eter. Dim ens ions in inches for reference only and not nec ess arily acc urate. FIGURE 25 - 100 PIN QFP PACKAGE OUTLINE 197 80 Arkay Drive Hauppauge, NY 11788 (631) 435-6000 FAX (631) 273-3123 Copyright © 2006 SMSC or its subsidiaries. All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems Corporation (“SMSC”). Product names and company names are the trademarks of their respective holders. SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. FDC37M81x Rev. 11/03/06
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