FDC37N869

FDC37N869 5V and 3.3V Super I/O Controller with Infrared Support for Portable Applications FEATURES § § § § § P C 99 Compliant 5 Volt and 3.3 Volt Operation Intelligent Auto Power Management 16 Bit Address Qualification 2.88MB Super I/O Floppy Disk Controller - Licensed CMOS 765B Floppy Disk Controller - Software and Register Compatible with SMSC’s Proprietary 82077AA Compatible Core - Supports One Floppy Drive Directly - Configurable Open Drain/Push-Pull Output Drivers - Supports Vertical Recording Format - 16 Byte Data FIFO - 100% IBM Compatibility - Detects All Overrun and Underrun Conditions - Sophisticated Power Control Circuitry (PCC) Including Multiple Power-Down Modes for Reduced Power Consumption - DMA Enable Logic - Data Rate and Drive Control Registers - Swap Drives A and B - Non-Burst Mode DMA Option - 48 Base I/O Address, 15 IRQ and 4 DMA Options - Forceable Write Protect and Disk Change Controls Floppy Disk Available on Parallel Port Pins ACPI Compliant Enhanced Digital Data Separator - 2Mbps, 1 Mbps, 500 Kbps, 300 Kbps, 250 Kbps Data Rates - Programmable Precompensation Modes Serial Ports - Two High Speed NS16C550 Compatible UARTs with Send/Receive 16 Byte FIFOs - Supports 230k and 460k Baud - Programmable Baud Rate Generator - Modem Control Circuitry Infrared Communications Controller - IrDA v1.1 (4Mbps), HPSIR, ASKIR, Consumer IR Support - 2 IR Ports - 96 Base I/O Address, 15 IRQ Options and 4 DMA Options Multi-Mode Parallel Port with ChiProtect - Standard Mode - IBM PC/XT, PC/AT, and PS/2 Compatible Bidirectional Parallel Port - Enhanced Parallel Port (EPP) Compatible - EPP 1.7 and EPP 1.9 (IEEE 1284 Compliant) - Enhanced Capabilities Port (ECP) Compatible (IEEE 1284 Compliant) - Incorporates ChiProtect Circuitry for Protection Against Damage Due to Printer Power-On - 192 Base I/O Address, 15 IRQ and 4 DMA Options Game Port Select Logic - 48 Base I/O Addresses General Purpose Address Decoder - 16-Byte Block Decode § § § § § § § ORDERING INFORMATION Order Number: FDC37N869TQFP 100 Pin TQFP Package SMSC DS – FDC37N869 11/09/2000 © 2000 STANDARD MICROSYSTEMS CORPORATION (SMSC) 80 Arkay Drive Hauppauge, NY 11788 (631) 435-6000 FAX (631) 273-3123 Standard Microsystems is a registered trademark of Standard Microsystems Corporation, and SMSC, ChiProtect, SuperCell and Multi-Mode are trademarks of Standard Microsystems Corporation. Product names and company names are the trademarks of their respective holders. Circuit diagrams utilizing SMSC products are included as a means of illustrating typical applications; consequently complete information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does not convey to the purchaser of the semiconductor devices described any licenses under the patent rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com. SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. SMSC DS – FDC37N869 Page 2 Rev. 11/09/2000 GENERAL DESCRIPTION The SMSC FDC37N869 is a 5v/3.3v PC 99-compliant Super I/O Controller with Infrared support. The FDC37N869 utilizes SMSC’s proven SuperCell technology and is optimized for motherboard applications. The FDC37N869 incorporates SMSC’s true CMOS 765B floppy disk controller, advanced digital data separator, 16-byte data FIFO, two 16C550 compatible UARTs, one Multi-Mode parallel port with ChiProtect circuitry plus EPP and ECP support, game port chip select logic and one floppy direct drive support. The FDC37N869 does not require any external filter components, is easy to use and offers lower system cost and reduced board area. The FDC37N869 is software and register compatible with SMSC’s proprietary 82077AA core. The true CMOS 765B core provides 100% compatibility with IBM PC/XT and PC/AT architectures and provides data overflow and underflow protection. The SMSC advanced digital data separator incorporates SMSC’s patented data separator technology allowing for ease of testing and use. The FDC37N869 supports both 1Mbps and 2Mbps data rates and vertical recording operation at 1Mbps Data Rate. The FDC37N869 also features a full 16-bit internally decoded address bus, a Serial IRQinterface with PCI nCLKRUN support, relocatable configuration ports and four DMA channel options. Both on-chip UARTs are compatible with the NS16C550. One UART includes additional support for a Serial Infrared Interface that complies with IrDA v1.2 (Fast IR), HPSIR, and ASKIR formats (used by Sharp, Apple Newton, and other PDAs), as well as Consumer IR. The parallel port and the game port select logic are compatible with IBM PC/AT architectures. The parallel port ChiProtect circuitry prevents damage caused by an attached powered printer when the FDC37N869 is not powered. The FDC37N869 incorporates sophisticated power control circuitry (PCC). The PCC supports multiple low power down modes. The FDC37N869 also features Software Configurable Logic (SCL) for ease of use. SCL allows programmable system configuration of key functions such as the FDC, parallel port, and UARTs. SMSC DS – FDC37N869 Page 3 Rev. 11/09/2000 TABLE OF CONTENTS GENERAL DESCRIPTION ...................................................................................................................3 PIN CONFIGURATION ........................................................................................................................8 PIN DESCRIPTION .............................................................................................................................9 BUFFER TYPE PER PIN..................................................................................................................9 BUFFER TYPE SUMMARY .................................................................................................................... 15 OUTPUT DRIVERS.............................................................................................................................. 15 FUNCTIONAL DESCRIPTION............................................................................................................ 17 HOST PROCESSOR INTERFACE............................................................................................................. 17 FLOPPY DISK CONTROLLER........................................................................................................... 17 MODES OF OPERATION ...................................................................................................................... 17 Floppy Modes........................................................................................................................... 17 Interface Modes......................................................................................................................... 18 FLOPPY DISK CONTROLLER INTERNAL REGISTERS .................................................................................... 18 STATUS REGISTER A (SRA)..................................................................................................... 18 STATUS REGISTER B (SRB) ..................................................................................................... 21 DIGITAL OUTPUT REGISTER (DOR)........................................................................................... 23 TAPE DRIVE REGISTER (TDR) .................................................................................................. 24 MAIN STATUS REGISTER (MSR) .............................................................................................. 25 DATA RATE SELECT REGISTER (DSR) .................................................................................... 26 DATA REGISTER (FIFO) ............................................................................................................ 29 DIGITAL INPUT REGISTER (DIR) ................................................................................................ 29 CONFIGURATION CONTROL REGISTER (CCR) .......................................................................... 31 STATUS REGISTER ENCODING.............................................................................................................. 32 RESET ............................................................................................................................................ 33 RESET Pin (Hardware Reset) ..................................................................................................... 34 DOR Reset vs. DSR Reset (Software Reset)................................................................................. 34 DMA TRANSFERS............................................................................................................................. 34 CONTROLLER PHASES ....................................................................................................................... 34 Command Phase........................................................................................................................ 34 Execution Phase ....................................................................................................................... 34 Result Phase ............................................................................................................................. 35 COMMAND SET/DESCRIPTIONS ............................................................................................................. 36 INSTRUCTION SET.............................................................................................................................. 38 DATA TRANSFER COMMANDS .............................................................................................................. 46 Read Data ................................................................................................................................. 46 Read Deleted Data ..................................................................................................................... 48 Read A Track ............................................................................................................................ 48 Write Data ................................................................................................................................. 49 Write Deleted Data .................................................................................................................... 50 Verify......................................................................................................................................... 50 Format A Track ......................................................................................................................... 51 CONTROL COMMANDS ....................................................................................................................... 52 Read ID..................................................................................................................................... 52 Recalibrate................................................................................................................................ 52 Seek ......................................................................................................................................... 53 Sense Interrupt Status ................................................................................................................ 53 Sense Drive Status .................................................................................................................... 54 Specify ..................................................................................................................................... 54 SMSC DS – FDC37N869 Page 4 Rev. 11/09/2000 Configure.................................................................................................................................. 54 Version ..................................................................................................................................... 55 Relative Seek ............................................................................................................................. 55 Perpendicular Mode.................................................................................................................. 56 LOCK ........................................................................................................................................ 57 ENHANCED DUMPREG ............................................................................................................. 57 COMPATIBILITY ............................................................................................................................ 57 PARALLEL PORT FLOPPY DISK CONTROLLER.......................................................................................... 57 SERIAL PORT (UART) ...................................................................................................................... 59 REGISTER DESCRIPTION ...................................................................................................................... 59 RECEIVE BUFFER REGISTER (RB)............................................................................................ 59 TRANSMIT BUFFER REGISTER (TB) ......................................................................................... 59 INTERRUPT ENABLE REGISTER (IER)....................................................................................... 59 INTERRUPT IDENTIFICATION REGISTER (IIR) ............................................................................ 60 FIFO CONTROL REGISTER (FCR) .............................................................................................. 62 LINE CONTROL REGISTER (LCR) .............................................................................................. 63 MODEM CONTROL REGISTER (MCR) ....................................................................................... 64 LINE STATUS REGISTER (LSR) ................................................................................................ 65 MODEM STATUS REGISTER (MSR).......................................................................................... 66 SCRATCHPAD REGISTER (SCR) ............................................................................................... 67 PROGRAMMABLE BAUD RATE GENERATOR DIVISOR LATCHES ........................................... 67 The Affects of RESET on the UART Registers............................................................................ 68 FIFO INTERRUPT MODE OPERATION...................................................................................................... 68 FIFO POLLED MODE OPERATION ......................................................................................................... 69 NOTES ON SERIAL PORT FIFO MODE OPERATION ................................................................................... 70 GENERAL................................................................................................................................. 70 TX AND RX FIFO OPERATION ................................................................................................... 71 INFRARED INTERFACE .................................................................................................................... 71 IRDA SIR/FIR AND ASKIR ................................................................................................................ 71 CONSUMER IR.................................................................................................................................. 72 HARDWARE INTERFACE ...................................................................................................................... 72 IR HALF DUPLEX TURNAROUND DELAY TIME........................................................................................... 72 PARALLEL PORT............................................................................................................................. 74 IBM XT/AT COMPATIBLE, BI-DIRECTIONAL AND EPP MODES........................................................ 75 DATA PORT .............................................................................................................................. 75 STATUS PORT .......................................................................................................................... 75 CONTROL PORT ....................................................................................................................... 76 EPP ADDRESS PORT ................................................................................................................ 77 EPP DATA PORT 0.................................................................................................................... 77 EPP DATA PORT 1.................................................................................................................... 77 EPP DATA PORT 2.................................................................................................................... 77 EPP DATA PORT 3.................................................................................................................... 77 EPP 1.9 OPERATION .................................................................................................................... 77 Software Constraints ................................................................................................................. 78 EPP 1.9 Write ............................................................................................................................ 78 EPP 1.9 Read ............................................................................................................................ 78 EPP 1.7 OPERATION .................................................................................................................... 79 Software Constraints ................................................................................................................. 79 EPP 1.7 Write ............................................................................................................................ 79 EPP 1.7 Read ............................................................................................................................ 79 EXTENDED CAPABILITIES PARALLEL PORT.................................................................................. 81 Vocabulary ............................................................................................................................... 81 ISA IMPLEMENTATION STANDARD.......................................................................................... 82 SMSC DS – FDC37N869 Page 5 Rev. 11/09/2000 Description ............................................................................................................................... 82 Register Definitions................................................................................................................... 83 OPERATION .............................................................................................................................. 89 AUTO POWER MANAGEMENT ......................................................................................................... 93 FDC POWER MANAGEMENT ............................................................................................................... 93 DSR From Powerdown .............................................................................................................. 93 Wake Up From Auto Powerdown .............................................................................................. 93 Register Behavior...................................................................................................................... 94 Pin Behavior ............................................................................................................................. 94 UART POWER MANAGEMENT ............................................................................................................. 96 PARALLEL PORT .............................................................................................................................. 96 SERIAL IRQ .................................................................................................................................. 96 Introduction .............................................................................................................................. 96 IRQSER Cycle Modes................................................................................................................ 97 IRQSER IRQ/Data Frames .......................................................................................................... 98 Stop Cycle Control.................................................................................................................... 99 Latency ..................................................................................................................................... 99 EOI/ISR Read Latency ............................................................................................................... 99 AC/DC Specification Issue ......................................................................................................... 99 Reset and Initialization................................................................................................................ 99 ADD PCI NCLKRUN SUPPORT.................................................................................................... 100 Overview................................................................................................................................. 100 Using nCLKRUN ...................................................................................................................... 100 CONFIGURATION........................................................................................................................... 101 CONFIGURATION ACCESS PORTS........................................................................................................ 101 CONFIGURATION STATE.................................................................................................................... 102 Entering the Configuration State ............................................................................................. 102 Configuration Register Programming ...................................................................................... 102 Exiting the Configuration State ............................................................................................... 102 Programming Example ........................................................................................................... 102 Configuration Select Register (CSR) ........................................................................................ 103 CONFIGURATION REGISTERS DESCRIPTION ............................................................................................ 103 CR00 ....................................................................................................................................... 104 CR01 ....................................................................................................................................... 104 CR02 ....................................................................................................................................... 106 CR03 ....................................................................................................................................... 106 CR04 ....................................................................................................................................... 107 CR05 ....................................................................................................................................... 108 CR06 ....................................................................................................................................... 108 CR07 ....................................................................................................................................... 109 CR08 ....................................................................................................................................... 109 CR09 ....................................................................................................................................... 109 CR0A ...................................................................................................................................... 110 CR0B ...................................................................................................................................... 110 CR0C ...................................................................................................................................... 111 CR0D ...................................................................................................................................... 111 CR0E ...................................................................................................................................... 111 CR0F....................................................................................................................................... 111 CR10 ....................................................................................................................................... 112 CR11 ....................................................................................................................................... 112 CR12 - CR13 ............................................................................................................................ 112 CR14 ....................................................................................................................................... 113 CR15 ....................................................................................................................................... 113 CR16 ....................................................................................................................................... 113 SMSC DS – FDC37N869 Page 6 Rev. 11/09/2000 CR17 ....................................................................................................................................... 113 CR18 - CR1D ........................................................................................................................... 114 CR1E ...................................................................................................................................... 114 CR1F....................................................................................................................................... 114 CR20 ....................................................................................................................................... 115 CR21 ....................................................................................................................................... 115 CR23 ....................................................................................................................................... 115 CR24 ....................................................................................................................................... 116 CR25 ....................................................................................................................................... 116 CR26 ....................................................................................................................................... 116 CR27 ....................................................................................................................................... 117 CR28 ....................................................................................................................................... 117 CR29 ....................................................................................................................................... 118 CR2A ...................................................................................................................................... 118 CR2B ...................................................................................................................................... 118 CR2C ...................................................................................................................................... 118 CR2D ...................................................................................................................................... 119 CR2E ...................................................................................................................................... 119 CR2F....................................................................................................................................... 119 OPERATIONAL DESCRIPTION ....................................................................................................... 120 MAXIMUM GUARANTEED RATINGS............................................................................................. 120 DC ELECTRICAL CHARACTERISTICS........................................................................................... 120 AC TIMING..................................................................................................................................... 126 HOST TIMING.................................................................................................................................. 126 FDD TIMING .................................................................................................................................. 130 SERIAL PORT TIMING ....................................................................................................................... 131 PARALLEL PORT TIMING................................................................................................................... 136 Parallel Port EPP Timing ......................................................................................................... 137 Parallel Port ECP Timing......................................................................................................... 142 PACKAGE OUTLINES..................................................................................................................... 146 FDC37N869 REVISIONS ................................................................................................................. 147 SMSC DS – FDC37N869 Page 7 Rev. 11/09/2000 PIN CONFIGURATION nSTROBE nAUTOFD nERROR nINIT nSLCT VCC PD0 PD1 PD2 PD3 VSS PD4 PD5 PD6 PD7 nACK BUSY PE SLCT PWRGD RESET_DRV D7 D6 D5 D4 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 RXD1 TXD1 nDSR1 nRTS1 nCTS1 nDTR1 nRI1 nDCD1 nRI2 nDCD2 RXD2 TXD2 nDSR2 nRTS2 nCTS2 nDTR2 nADRX/nCLKRUN VSS nDACK_C A10 IRQIN DRQ_C IOCHRDY DRVDEN0 nMTR0 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 FDC37N869 100 PIN TQFP 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 DRQ_B D3 D2 D1 D0 VSS AEN nIOW nIOR A9 A8 A7 CLK33 SIRQ A12 A11 nDACK_B TC A6 A5 A4 A3 A2 A1 A0 SMSC DS – FDC37N869 A13 nDS0 A14 VSS nDIR nSTEP nWDATA nWGATE nHDSEL nINDEX nTRK0 nWRTPRT VCC nRDATA nDSKCHG DRVDEN1 DRQ_D CLK14 DRQ_A nDACK_A IRMODE/IRRX3 nDACK_D IRRX2 IRTX2 A15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 FIGURE 1 - FDC37N869 PIN CONFIGURATION Page 8 Rev. 11/09/2000 PIN DESCRIPTION BUFFER TYPE PER PIN Table 1 - DESCRIPTION OF PIN FUNCTIONS BUFFER SYMBOL MODE6 DESCRIPTION HOST PROCESSOR INTERFACE D0-D7 IO12 The data bus connection used by the host microprocessor to transmit data to and from the chip. These pins are in a high-impedance state when not in the output mode. nIOR IS This active low signal is issued by the host microprocessor to indicate an I/O read operation. nIOW IS This active low signal is issued by the host microprocessor to indicate an I/O write operation. AEN IS Active high Address Enable indicates DMA operations on the host data bus. Used internally to qualify appropriate address decodes. A0-A15 I These host address bits determine the I/O address to be accessed during nIOR and nIOW cycles. These bits are latched internally by the leading edge of nIOR and nIOW. All internal address decodes use the full A0 to A15 address bits. DRQ_A O12 These active high outputs are the DMA request DRQ_B for byte transfers of data between the host and DRQ_C the chip. These signals are cleared on the last DRQ_D byte of the data transfer by the nDACK signal going low (or by nIOR going low if nDACK was already low as in demand mode). nDACK_A IS These are active low inputs acknowledging the nDACK_B request for a DMA transfer of data between the nDACK_C host and the chip. These inputs enable the DMA nDACK_D read or write internally. TC IS This signal indicates that DMA data transfer is complete. TC is only accepted when nDACK_x is low. In AT and PS/2 model 30 modes, TC is active high and in PS/2 mode, TC is active low. SIRQ IO12 Serial IRQ pin used with the CLK33 pin to transfer FDC37N869 interrupts to the host. CLK33 ICLK 33MHz PCI clock input, used with the SIRQ and the nCLKRUN pins to serially transfer FDC37N869 interrupts to the host. RESET_ IS This active high signal resets the chip and must DRV be valid for 500ns minimum. The effect on the internal registers is described in the appropriate section. The configuration registers are not affected by this reset. IOCHRDY OD12 This pin is pulled low to extend the read/write command. IOCHRDY can used by the IRCC and by the Parallel Port in EPP mode. FLOPPY DISK INTERFACE nRDATA IS Raw serial bit stream from the disk drive, low active. Each falling edge represents a flux transition of the encoded data. TQFP PIN # 46-49 51-54 NAME Data Bus 07 42 nI/O Read 43 nI/O Write 44 Address Enable 26-32 Address 39-41, Bus 95,35, 36,1, 3,25 19,50, DMA 97,17 Request A, B, C, D 20,34, nDMA 94,22 Acknowledge A, B, C, D 33 Terminal Count 37 38 Serial IRQ PCI Clock 55 Reset 98 I/O Channel Ready (Note 4) nRead Disk Data 14 SMSC DS – FDC37N869 Page 9 Rev. 11/09/2000 TQFP PIN # 8 NAME nWrite Gate nWrite Data nHead Select SYMBOL nWGATE BUFFER MODE6 (O12/ OD12) (O12/ OD12) (O12/ OD12) 7 nWDATA 9 nHDSEL 5 Direction Control nDIR (O12/ OD12) 6 nStep Pulse nSTEP (O12/ OD12) IS 15 Disk Change nDSKCHG 2 100 99 12 nDrive Select 0 nMotor On 0 Drive Density 0 nWrite Protected nDS0 nMTR0 DRVDEN0 11 wTrack 00 10 nIndex 16 Drive Density 1 Receive Data 2 Transmit Data 2 (Note 5) Receive Data 1 86 87 Indicates the drive and media selected. Refer to configuration registers CR03, CR0B, CR1F. nWRTPRT This active low Schmitt Trigger input senses from the disk drive that a disk is write protected. Any write command is ignored. The nWRPRT bit also depends upon the state of the Force Write Protect bit in the Force FDD Status Change configuration register (see section CR17 on page 109). nTRK0 IS This active low Schmitt Trigger input senses from the disk drive that the head is positioned over the outermost track. nINDEX IS This active low Schmitt Trigger input senses from the disk drive that the head is positioned over the beginning of a track, as marked by an index hole. DRVDEN 1 (O12/ Indicates the drive and media selected. Refer to OD12) configuration registers CR03, CR0B, CR1F. SERIAL PORTS INTERFACE RXD2 IS Receiver serial data input for port 2. IR Receive Data TXD2 O12PD Transmit serial data output for port 2. IR transmit data. RXD1 I Receiver serial data input for port 1. (O12/ OD12) (O12/ OD12) (O12/ OD12) IS DESCRIPTION This active low high current driver allows current to flow through the write head. It becomes active just prior to writing to the diskette. This active low high current driver provides the encoded data to the disk drive. Each falling edge causes a flux transition on the media. This high current output selects the floppy disk side for reading or writing. A logic “1” on this pin means side 0 will be accessed, while a logic “0” means side 1 will be accessed. This high current low active output determines the direction of the head movement. A logic “1” on this pin means outward motion, while a logic “0” means inward motion. This active low high current driver issues a low pulse for each track-to-track movement of the head. This input senses that the drive door is open or that the diskette has possibly been changed since the last drive selection. This input is inverted and read via bit 7 of I/O address 3F7H. The nDSKCHG bit also depends upon the state of the Force Disk Change bits in the Force FDD Status Change configuration register (see section CR17 on page 109). Active low output selects drive 0. These active low output selects motor drive 0. 76 SMSC DS – FDC37N869 Page 10 Rev. 11/09/2000 TQFP PIN # 77 79,89 NAME Transmit Data 1 nRequest to Send (System Option) SYMBOL TXD1 nRTS1 nRTS2 (SYSOPT) BUFFER MODE6 O12 O6 DESCRIPTION Transmit serial data output for port 1. Active low Request to Send outputs for the Serial Port. Handshake output signal notifies modem that the UART is ready to transmit data. This signal can be programmed by writing to bit 1 of the Modem Control Register (MCR). The hardware reset will reset the nRTS signal to inactive mode (high). nRTS is forced inactive during loop mode operation. At the trailing edge of hardware reset the nRTS2 inputs is latched to determine the configuration base address: 0 = INDEX Base I/O Address 3F0 Hex; 1 = INDEX Base I/O Address 370 Hex. Active low Data Terminal Ready outputs for the serial port. Handshake output signal notifies modem that the UART is ready to establish data communication link. This signal can be programmed by writing to bit 0 of Modem Control Register (MCR). The hardware reset will reset the nDTR signal to inactive mode (high). nDTR is forced inactive during loop mode operation. Active low Clear to Send inputs for the serial port. Handshake signal which notifies the UART that the modem is ready to receive data. The CPU can monitor the status of nCTS signal by reading bit 4 of Modem Status Register (MSR). A nCTS signal state change from low to high after the last MSR read will set MSR bit 0 to a 1. If bit 3 of the Interrupt Enable Register is set, the interrupt is generated when nCTS changes state. The nCTS signal has no effect on the transmitter. Note: Bit 4 of MSR is the complement of nCTS. Active low Data Set Ready inputs for the serial port. Handshake signal which notifies the UART that the modem is ready to establish the communication link. The CPU can monitor the status of nDSR signal by reading bit 5 of Modem Status Register (MSR). A nDSR signal state change from low to high after the last MSR read will set MSR bit 1 to a 1. If bit 3 of Interrupt Enable Register is set, the interrupt is generated when nDSR changes state. Note: Bit 5 of MSR is the complement of nDSR. Active low Data Carrier Detect inputs for the serial port. Handshake signal which notifies the UART that carrier signal is detected by the modem. The CPU can monitor the status of nDCD signal by reading bit 7 of Modem Status Register (MSR). A nDCD signal state change from low to high after the last MSR read will set MSR bit 3 to a 1. If bit 3 of Interrupt Enable Register is set, the interrupt is generated when nDCD changes state. Note: Bit 7 of MSR is the complement of nDCD. 81,91 nData Terminal Ready nDTR1 nDTR2 O6 80,90 nClear to Send nCTS1 nCTS2 I 78,88 nData Set Ready nDSR1 nDSR2 I 83,85 nData Carrier Detect nDCD1 nDCD2 I SMSC DS – FDC37N869 Page 11 Rev. 11/09/2000 TQFP PIN # 82,84 NAME nRing Indicator SYMBOL nRI1 nRI2 BUFFER MODE6 I (Note 1) DESCRIPTION Active low Ring Indicator inputs for the serial port. Handshake signal which notifies the UART that the telephone ring signal is detected by the modem. The CPU can monitor the status of nRI signal by reading bit 6 of Modem Status Register (MSR). A nRI signal state change from low to high after the last MSR read will set MSR bit 2 to a 1. If bit 3 of Interrupt Enable Register is set, the interrupt is generated when nRI changes state. Note: Bit 6 of MSR is the complement of nRI. TQFP PIN # 71 NAME nPrinter Select Input/FDC nStep Pulse (Note 3) nInitiate Output/ FDC nDirection Control (Note 3) nAutofeed Output/ FDC nDensity Select (Note 3) 72 74 75 nStrobe Output/ FDC nDrive Select 0 (Note 3) Busy/ FDC nMotor On 1 59 BUFFER SYMBOL MODE6 DESCRIPTION PARALLEL PORT INTERFACE (NOTE 2) nSLCT (OD14/OP14)/OD12 This active low output selects the printer. This is the complement of bit 3 of the Printer Control Register. Refer to Parallel Port description for use of this pin in ECP and EPP mode. nSTEP See FDC Pin definition. nINIT (OD14/OP14)/OD12 This output is bit 2 of the printer control register. This is used to initiate the printer when low. Refer to Parallel Port description for use of this pin in ECP and EPP mode. nDIR See FDC Pin definition. nAUTOFD (OD14/OP14)/OD12 This output goes low to cause the printer to automatically feed one line after each line is printed. The nAUTOFD output is the complement of bit 1 of the Printer Control Register. Refer to Parallel Port description for use nDENSEL of this pin in ECP and EPP mode. See FDC Pin definition. nSTROBE (OD14/OP14)/OD12 An active low pulse on this output is used to strobe the printer data into the printer. The nSTROBE output is the complement of bit 0 of the Printer Control Register. Refer to Parallel Port description for use of this pin in ECP and EPP mode. nDS0 See FDC Pin definition. BUSY I/OD12 This is a status output from the printer, a high indicating that the printer is not ready to receive new data. Bit 7 of the Printer Status Register is the complement of the BUSY input. Refer to Parallel Port description for use of this pin in ECP and nMTR1 EPP mode. See FDC Pin definition. SMSC DS – FDC37N869 Page 12 Rev. 11/09/2000 TQFP PIN # 60 NAME nAcknowledge/FDC nDrive Select 1 SYMBOL nACK BUFFER MODE6 I/OD12 nDS1 58 Paper End/ PE FDC nWrite Data nWRDATA 57 Printer SLCT Selected Status/ FDC nWrite Gate nWGATE nError/FDC nERROR nHead Select I/OD12 I/OD12 73 I/OD12 nHDSEL 69 Port Data 0/FDC nIndex Port Data 1/FDC nTrack 0 Port Data 2/FDC nWrite Protected Port Data 3/FDC nRead Disk Data Port Data 4/FDC nDisk Change Port Data 5 Port Data 6/FDC nMotor On 0 Port Data 7 PD0 nINDEX PD1 nTRK0 PD2 nWRTPRT PD3 nRDATA PD4 nDSKCHG PD5 PD6 nMTR0 PD7 IOP14 IOP14 IOP14/ OD12 IOP14/IS IOP14/IS IOP14/IS DESCRIPTION A low active output from the printer indicating that it has received the data and is ready to accept new data. Bit 6 of the Printer Status Register reads the nACK input. Refer to Parallel Port description for use of this pin in ECP and EPP mode. See FDC Pin definition. Another status output from the printer, a high indicating that the printer is out of paper. Bit 5 of the Printer Status Register reads the PE input. Refer to Parallel Port description for use of this pin in ECP and EPP mode. See FDC Pin definition. This high active output from the printer indicates that it has power on. Bit 4 of the Printer Status Register reads the SLCT input. Refer to Parallel Port description for use of this pin in ECP and EPP mode. See FDC Pin definition. A low on this input from the printer indicates that there is a error condition at the printer. Bit 3 of the Printer Status register reads the nERR input. Refer to Parallel Port description for use of this pin in ECP and EPP mode. See FDC Pin definition. Port Data 0 See FDC Pin definition. Port Data 1 See FDC Pin definition. Port Data 2 See FDC Pin definition. Port Data 3 See FDC Pin definition. Port Data 4 See FDC Pin definition. Port Data 5 Port Data 6 See FDC Pin definition. Port Data 7 68 IOP14/IS 67 IOP14/IS 66 64 63 62 61 SMSC DS – FDC37N869 Page 13 Rev. 11/09/2000 TQFP PIN # 18 23 24 92 NAME 14.318 MHz Input Clock IR Receive 2 IR Transmit 2 (Note 5) Address X/ PCI Clock Controller SYMBOL CLK14 IRRX2 IRTX2 nADRX/ nCLKRU N BUFFER MODE6 DESCRIPTION ALTERNATE IR PINS/MISC ICLK The external connection to a single source 14.318 MHz clock. IS IR Receive input O12PD OD12/ IOD12 IR transmit output The active-low address decoder output nADRX can be asserted on 1, 8, or 16-byte address boundaries (an external pull-up is required). Refer to configuration registers CR03, CR08, and CR09 for more information. nCLKRUN is used to indicate the PCI clock status and to request that a stopped clock be started. IR mode IR Receive 3 21 IR Mode/ IR Receive 3 Power Good/ nGame Port Chip Select IRMODE/ IRRX3 PWRGD O6/IS 56 I/O4 nGAMEC S 96 External Interrupt Input Power Ground IRQIN IS This active high input indicates that the power (VCC) is valid. For device operation PWRGD must be active. When PWRGD is inactive, all inputs are disconnected and put into a low power mode; all outputs are put into high impedance. The contents of all registers are preserved as long as VCC is valid. The output driver current drain when PWRGD is inactive mode drops to ISTBY - standby current. This is the Game Port Chip Select output - active low. It will go active when the I/O address, qualified by AEN, matches that selected in Configuration register CR1E. This pin is used to steer an interrupt signal from an external device onto one of 15 IRQs. 13,70 4,45, 65,93 Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: VCC VSS POWER INTERFACE Positive Supply Voltage. (5V or 3.3V) Ground Supply. nRI and the UART interrupts are active when PWRGD is active and the UARTS are either fully powered or in AUTOPOWER DOWN mode. The FDD output pins multiplexed in the PARALLEL PORT INTERFACE are OD drivers only and are not affected by the FDD Output Driver Controls (see section CR05 on page 108). Active (push-pull) output drivers are required on these pins in the enhanced parallel port modes. An external pull-up must be provided for IOCHRDY. The pull-down on this pin is always active including when the output driver is tristated and regardless of the state of PWRGD. Buffer Modes describe the pad driver properties per function. Buffer Modes on multiplexed pins are separated by a slash “/”. For example, the Buffer Modes for a multiplexed pin with two functions where the primary function is an input and the secondary function is an 8mA bidirectional driver is “I/IO8”. Buffer Modes in parenthesis represent multiple Buffer Modes for a single pin function. SMSC DS – FDC37N869 Page 14 Rev. 11/09/2000 Buffer Type Summary Table 2 below describes the buffer types shown in Table 1. All values are specified at Vcc = +3.3v, ± 10% Table 2 - FDC37N869 Buffer Type Summary (See Note) BUFFER TYPE DESCRIPTION IO12 O12 O12PD OD12 O6 OD14 OP14 IOP14 O4 ICLK I IS IOD12 Input/Output. 12mA sink; 6mA source Output. 12mA sink; 6mA source Output. 12mA sink; 6mA source with 30µa pull-down Open Drain. 12mA sink Output. 6mA sink; 3mA source Open Drain. 14mA sink Output. 14mA sink; 14mA source. Backdrive Protected Input/Output. 14mA sink; 14mA source. Backdrive Protected Output. 4mA sink; 2mA source Input to Crystal Oscillator Circuit (TTL levels) Input TTL Compatible Input with Schmitt Trigger Input/Open Drain Output. 12mA sink Note: These are minimum ratings guaranteed at 5V and 3.3V. Output Drivers Active output drivers in the FDC37N869 will always achieve the minimum specified DC Electrical Characteristics shown in Table 120. Note: If there is a pull-up on an external node driven by an active output driver the FDC37N869 may sink current from the pull-up through the low impedance source. SMSC DS – FDC37N869 Page 15 Rev. 11/09/2000 PWRGD/nGAMECS Vcc (2) Vss (4) nSLCTIN/nSTEP,nINI T/nDIR, nAUTOFD/ nDENSEL, nSTROBE/nDS0, BUSY/nMTR1, nACK/nDS1, PE/nWRDATA,nERR OR/nHDSEL, PD0/nINDEX, PD1/nTRK0, PD2/nWRTPRT, PD3/nRDATA, PD4/nDSKCHG, PD5/ PD6/nMTR, PD7 POWER MANAGEMENT MULTI-MODE PARALLEL PORT/FDC MUX DATA BUS nCS ADDRESS BUS nIOR nIOW CONFIGURATION AEN A0-A15 CONTROL BUS D0-D7 DRQ_A-D nDACK_A-D TC HOST CPU INTERFACE SMSC WDATA WCLOCK REGISTERS 16C550 COMPATIBLE SERIAL PORT 1 TXD1, nCTS1, nRTS1, RXD1 nDSR1, nDCD1, nRI, nDTR1 IR Mode/IRR3 16C550 COMPATIBLE SERIAL PORT 2 WITH INFRARED TXD2/IRTX,nCTS2, nRTS2 RXD2/IRRX nDSR2,nDCD2, nRI2,nDTR2 PROPRIETARY 82077 COMPATIBLE VERTICAL FLOPPYDISK CONTROLLER CORE RCLOCK RDATA SIRQ CLK33 nADRX/nCLKRUN RESET IRQIN CLOCK IOCHRDY GEN DIGITAL DATA SEPARATOR WITH WRITE PRECOMPENSATION IR IRRX2, IRTX2 nINDEX nTRK0 14.318 CLOCK nDIR nSTEP nDS0 nMTR0 nHDSEL nWDATA nRDATA nDSKCHG DRVDEN0 nWRPRT DRVDEN1 nWGATE GAME PORT DECODER See Power Mgt FIGURE 2 - FDC37N869 BLOCK DIAGRAM SMSC DS – FDC37N869 Page 16 Rev. 11/09/2000 FUNCTIONAL DESCRIPTION Super I/O Registers Table 3 shows the addresses of the various device blocks of the Super I/O immediately after power up. The base addresses must be set in the configuration registers before accessing these devices. The base addresses of the FDC, Serial and Parallel Ports can be moved via the configuration registers. Host Processor Interface The host processor communicates with the FDC37N869 using the Super I/O registers. Register access is accomplished through programmed I/O or DMA transfers. All registers are 8 bits wide. All host interface output buffers are capable of sinking a minimum of 12 mA. ADDRESS 3F0, 3F1 or 370, 371 Base +[0:7] Base +[0:7] Base1 +[0:7] Base2 +[0:7] Base +[0:3] all modes Base +[4:7] for EPP Base +[400:403] for ECP Table 3 - FDC37N869 Block Addresses BLOCK NAME NOTES Configuration Floppy Disk Serial Port Com 1 Serial Port Com 2 Parallel Port Write only; Note 1 Disabled at power up; Note 2 Disabled at power up; Note 2 Disabled at power up; Note 2 Disabled at power up; Note 2 Note 1: Configuration registers can only be modified in the configuration state, refer to section CONFIGURATION on page 101 for more information. All logical blocks in the FDC37N869 can operate normally in the Configuration State. Note 2: The base addresses must be set in the configuration registers before accessing the logical device blocks. FLOPPY DISK CONTROLLER The Floppy Disk Controller (FDC) provides the interface between a host microprocessor and the floppy disk drives. The FDC integrates the functions of the Formatter/Controller, Digital Data Separator, Write Precompensation and Data Rate Selection logic for an IBM XT/AT compatible FDC. The true CMOS 765B core guarantees 100% IBM PC XT/AT compatibility in addition to providing data overflow and underflow protection. The FDC37N869 is compatible with the 82077AA using SMSC’s proprietary floppy disk controller core. For information about the floppy disk on the Parallel Port pins refer to section Parallel Port Floppy Disk Controller on page 57. Modes Of Operation The FDC37N869 Floppy Disk Controller has two Floppy modes and three Interface modes. Each of the three Interface modes are available in each of the two Floppy modes. Floppy Modes The Floppy modes are used to select alternate configurations for the Tape Drive register. The active Floppy mode is determined by the Enhanced Floppy Mode 2 bit in Configuration Register 3 (see section CR03 on page 106). When the Enhanced Floppy Mode 2 bit is 0 N ormal Floppy mode is selected, otherwise Enhanced Floppy Mode 2 (OS/2 mode) is selected. See section TAPE DRIVE REGISTER (TDR) on page 24 for the affects of the Enhanced Floppy Mode 2 bit on the Tape Drive register. SMSC DS – FDC37N869 Page 17 Rev. 11/09/2000 Interface Modes The Interface modes are determined by the MFM and I DENT configuration bits in Configuration Register 3 (see section CR03 on page 106). PC/AT Interface Mode When both IDENT and MFM are high the PC/AT register set is enabled, the DMA enable bit of the Digital Output Register becomes valid, FINTR and DRQ can be hi-Z, and TC and DENSEL become active high. PS/2 Interface Mode When IDENT is low and MFM is high PS/2 Interface mode is selected. This mode supports the PS/2 models 50/60/80 configuration and register set. The DMA bit of the Digital Output Register becomes a “don’t care,” FINTR and DRQ are always valid, TC and DENSEL become active low. Model 30 Interface Mode When both IDENT and MFM are low Model 30 Interface Mode is selected. This mode supports PS/2 Model 30 configuration and register set. The DMA enable bit of the Digital Output Register becomes valid, FINTR and DRQ can be hi-Z, TC is active high and DENSEL is active low. Floppy Disk Controller Internal Registers The Floppy Disk Controller contains eight internal registers that provide the interface between the host microprocessor and the floppy disk drives. Table 4 shows the addresses required to access these registers. Registers other than the ones shown are not supported. Table 4 - Status, Data and Control Registers BASE I/O ADDRESS +0 +1 +2 +3 +4 +4 +5 +6 +7 +7 REGISTER Status Register A Status Register B Digital Output Register Tape Drive Register Main Status Register Data Rate Select Register Data (FIFO) Reserved Digital Input Register Configuration Control Register R R R/W R/W R W R/W R W SRA SRB DOR TDR MSR DSR FIFO DIR CCR STATUS REGISTER A (SRA) Status Register A (Base Address + 0) monitors the state of the FINTR pin and several disk interface pins in PS/2 interface mode (Table 5) and Model 30 interface mode (Table 6). SRA is read-only and can be accessed at any time when in these modes. During a read in the PC/AT interface mode the data bus pins D0 - D7 are held in a high impedance state. SMSC DS – FDC37N869 Page 18 Rev. 11/09/2000 PS/2 Interface Mode 7 INT PENDING RESET CONDITION Direction, Bit 0 Active high status indicating the direction of head movement. A logic “1” indicating inward direction, a logic “0” outward. nWRITE PROTECT, Bit 1 Active low status of the WRITE PROTECT disk interface input. A logic “0” indicating that the disk is write protected. The nWRITE PROTECT bit also depends upon the state of the Force Write Protect bits in the Force FDD Status Change configuration register (see section CR17 on page 109). nINDEX, Bit 2 Active low status of the INDEX disk interface input. Head Select, Bit 3 Active high status of the HDSEL disk interface input. A logic “1” selects side 1 and a logic “0” selects side 0. nTRACK 0, Bit 4 Active low status of the TRK0 disk interface input. Step, Bit 5 Active high status of the STEP output disk interface output pin. nDRV2, Bit 6 The nDRV2 bit is always “1”. Interrupt Pending, Bit 7 Active high bit indicating the state of the Floppy Disk Interrupt output. 0 6 nDRV2 1 Table 5 - SRA PS/2 Mode 5 4 3 STEP 0 nTRK0 N/A HDSEL 0 2 nINDX N/A 1 nWP N/A 0 DIR 0 SMSC DS – FDC37N869 Page 19 Rev. 11/09/2000 PS/2 Model 30 Interface Mode Table 6 - SRA PS/2 Model 30 Mode 6 5 4 3 DRQ 0 STEP F/F 0 TRK0 N/A nHDSEL 1 7 INT PENDING RESET CONDITION nDIRECTION, Bit 0 0 2 INDX N/A 1 WP N/A 0 nDIR 1 Active low status indicating the direction of head movement. A logic “0” indicating inward direction a logic “1” outward. Write Protect, Bit 1 Active high status of the WRITE PROTECT disk interface input. A logic “1” indicating that the disk is write protected. The nWRITE PROTECT bit also depends upon the state of the Force Write Protect bits in the Force FDD Status Change configuration register (see section CR17 on page 109). Index, Bit 2 Active high status of the INDEX disk interface input. nHEAD SELECT, Bit 3 Active low status of the HDSEL disk interface input. A logic “0” selects side 1 and a logic “1” selects side 0. Track, Bit 4 Active high status of the TRK0 disk interface input. Step, Bit 5 Active high status of the latched STEP disk interface output pin. This bit is latched with the STEP output going active, and is cleared with a read from the DIR register, or with a hardware or software reset. DMA Request, Bit 6 Active high status of the DRQ output pin. Interrupt Pending, Bit 7 Active high bit indicating the state of the Floppy Disk Interrupt output. SMSC DS – FDC37N869 Page 20 Rev. 11/09/2000 STATUS REGISTER B (SRB) Status Register B (Base Address + 1) is read-only and monitors the state of several disk interface pins in PS/2 interface mode (Table 7) and Model 30 interface mode (Table 8). SRB can be accessed at any time when in these modes. During a read in PC/AT interface mode the data bus pins D0 - D7 are held in a high impedance state. PS/2 Interface Mode Table 7 - SRB PS/2 Mode 5 4 3 DRIVE SEL0 0 WDATA TOGGLE 0 RDATA TOGGLE 0 7 1 RESET CONDITION Motor Enable 0, Bit 0 1 6 1 1 2 1 0 WGATE MOT EN1 MOT EN0 0 0 0 Active high status of the MTR0 disk interface output pin. This bit is low after a hardware reset and unaffected by a software reset. Motor Enable 1, Bit 1 Active high status of the MTR1 disk interface output pin. This bit is low after a hardware reset and unaffected by a software reset. Write Gate, Bit 2 Active high status of the WGATE disk interface output. Read Data Toggle, Bit 3 Every inactive edge of the RDATA input causes this bit to change state. Write Data Toggle, Bit 4 Every inactive edge of the WDATA input causes this bit to change state. Drive Select 0, Bit 5 Reflects the status of the Drive Select 0 bit of the DOR (address 3F2 bit 0). This bit is cleared after a hardware reset, it is unaffected by a software reset. Reserved, Bits 6 - 7 Always read as a logic “1”. SMSC DS – FDC37N869 Page 21 Rev. 11/09/2000 PS/2 Model 30 Interface Mode Table 8 - SRB PS/2 Model 30 Mode 5 4 3 nDS0 1 WDATA F/F RDATA F/F 0 0 7 nDRV2 RESET CONDITION N/A 6 nDS1 1 2 WGATE F/F 0 1 nDS3 1 0 nDS2 1 nDRIVE SELECT 2, Bit 0 Active low status of the DS2 disk interface output. nDRIVE SELECT 3, Bit 1 Active low status of the DS3 disk interface output. Write Gate, Bit 2 Active high status of the latched WGATE output signal. This bit is latched by the active going edge of WGATE and is cleared by the read of the DIR register. Read Data, Bit 3 Active high status of the latched RDATA output signal. This bit is latched by the inactive going edge of RDATA and is cleared by the read of the DIR register. Write Data, Bit 4 Active high status of the latched WDATA output signal. This bit is latched by the inactive going edge of WDATA and is cleared by the read of the DIR register. This bit is not gated with WGATE. nDRIVE SELECT 0, Bit 5 Active low status of the DS0 disk interface output. nDRIVE SELECT 1, Bit 6 Active low status of the DS1 disk interface output. nDRV2, Bit 7 The nDRV2 bit is always “1”. SMSC DS – FDC37N869 Page 22 Rev. 11/09/2000 DIGITAL OUTPUT REGISTER (DOR) The Digital Output register (Base Address + 2) controls the drive select and motor enables of the disk interface outputs (Table 9 and Table 10). The DOR also contains the DMA logic enable and a software reset bit. The DOR is read/write and unaffected by a software reset. Table 9 - Digital Output Register 5 4 3 7 6 2 1 DRIVE SEL1 0 0 DRIVE SEL0 0 MOT EN3 MOT EN2 MOT EN1 MOT EN0 DMAEN nRESET RESET CONDITION DOR Bit Descriptions DRIVE SELECT, Bits 0 - 1 0 0 0 0 0 0 These two bits are binary encoded for the four drive selects DS0-DS3, there by allowing only one drive to be selected at one time. nRESET, Bit 2 A logic “0” written to this bit resets the Floppy disk controller. This reset will remain active until a logic “1” is written to this bit. This software reset does not affect the DSR and CCR registers, nor does it affect the other bits of the DOR register. The minimum reset duration required is 100ns, therefore toggling this bit by consecutive writes to this register is a valid method of issuing a software reset. DMAEN, Bit 3 PC/AT and Model 30 Interface Mode In PC/AT and Model 30 mode writing this bit to logic “1” will enable the DRQ, nDACK, TC and FINTR outputs. This bit being a logic “0” will disable the nDACK and TC inputs, and hold the DRQ and FINTR outputs in a high impedance state. In PC/AT and Model 30 mode the DMAEN bit is a logic “0” after a reset. PS/2 Interface Mode In PS/2 mode the DRQ, nDACK, TC and FINTR pins are always enabled. During a reset the DRQ, nDACK, TC, and FINTR pins will remain enabled, but the DMAEN bit will be cleared to a logic “0”. MOTOR ENABLE 0, Bit 4 This bit controls the MTR0 disk interface output. A logic “1” in this bit will cause the output pin to go active. MOTOR ENABLE 1, Bit 5 This bit controls the MTR1 disk interface output. A logic “1” in this bit will cause the output pin to go active. MOTOR ENABLE 2, Bit 6 The MOTOR ENABLE 2 bit controls the MTR2 disk interface output. A logic “1” in this bit will cause the output pin to go active. MOTOR ENABLE 3, Bit 7 The MOTOR ENABLE 3 bit controls the MTR3 disk interface output. A logic “1” in this bit causes the output to go active. SMSC DS – FDC37N869 Page 23 Rev. 11/09/2000 Table 10 - Drive Activation Values DRIVE DOR VALUE 0 1CH 1 2DH 2 4EH 3 8FH Table 11 - Internal 2 Drive Decode: Drives 0 and 1 DRIVE SELECT OUTPUTS MOTOR ON OUTPUTS DIGITAL OUTPUT REGISTER (ACTIVE LOW) (ACTIVE LOW) Bit 7 Bit 6 Bit 5 Bit 4 Bit1 Bit 0 nDS1 nDS0 nMTR1 nMTR0 X X X 1 0 X X 1 X 0 X 1 X X 0 1 X X X 0 0 0 1 1 X 0 1 0 1 X 1 0 1 1 1 0 1 1 1 1 nBIT 5 nBIT 5 nBIT 5 nBIT 5 nBIT 5 nBIT 4 nBIT 4 nBIT 4 nBIT 4 nBIT 4 TAPE DRIVE REGISTER (TDR) The Tape Drive register (Base Address + 3) is included for 82077 software compatibility and allows the user to assign tape support to a particular drive during initialization. Any future reference to that drive automatically invokes tape support. The Tape Select bits TDR.[1:0] determine the tape drive number. Table 12 illustrates the Tape Select bit encoding. Note that drive 0 is the boot device and cannot be assigned tape support. The encoding of the TDR depends on the Floppy mode (see section Floppy Modes on page 17). The TDR is unaffected by a software reset. Table 12 - Tape Select Bits TAPE SEL1 TAPE SEL0 DRIVE (TDR.1) (TDR.0) SELECTED 0 0 NONE 0 1 1 1 0 2 1 1 3 Normal Floppy Mode In N ormal mode the TDR contains only bits 0 and 1 (Table 13). During a read in Normal mode TDR bits 2 - 7 are high impedance. The Tape Select Bits are Read/Write. Table 13 - TDR Normal Floppy Mode DB5 DB4 DB3 DB2 DB7 TDR DB6 DB1 Tape Sel1 DB0 Tape Sel0 Tri-state Tri-state Tri-state Tri-state Tri-state Tri-state SMSC DS – FDC37N869 Page 24 Rev. 11/09/2000 Enhanced Floppy Mode 2 (OS2) The configuration of the TDR in the Enhanced Floppy Mode 2 (OS/2 mode) is shown in Table 14. Table 14 - TDR Enhanced Floppy Mode 2 DB5 DB4 DB3 DB2 Drive Type ID Floppy Boot Drive DB7 TDR DB6 DB1 Tape Sel1 DB0 Tape Sel0 Reserved Reserved, Bits 6 - 7 Bits 6 and 7 are RESERVED. Reserved bits cannot be written and return 0 when read. Drive Type ID, Bits 4 - 5 The Drive Type ID bits depend on the last drive selected in the Digital Output Register and the Drive Type IDs that are programmed in configuration register 6 (Table 15). Table 15 - Drive Type ID DIGITAL OUTPUT REGISTER TDR - DRIVE TYPE ID Bit 1 0 0 1 1 Floppy Boot Drive, Bits 2 - 3 The Floppy Boot Drive bits come from Configuration Register 7: TDR Bit 3 = CR7 Bit 1; TDR Bit 2 = CR7 Bit 0. Tape Drive Select, Bits 0 - 1 The Tape Drive Select bits are the same as in N ormal mode. These bits are Read/Write. Bit 0 0 1 0 1 Bit 5 CR6 - Bit 1 CR6 - Bit 3 CR6 - Bit 5 CR6 - Bit 7 Bit 4 CR6 - Bit 0 CR6 - Bit 2 CR6 - Bit 4 CR6 - Bit 6 MAIN STATUS REGISTER (MSR) The Main Status Register (Base Address + 4: Read-only) indicates the status of the disk controller (Table 16). The Main Status Register is valid in all modes and can be read at any time. The MSR indicates when the disk controller is ready to receive data via the Data Register. It should be read before transferring each byte to or from the data register, except in DMA mode. No delay is required when reading the MSR after a data transfer. Table 16 - Main Status Register 5 4 3 NON DMA CMD BUSY DRV3 BUSY 7 MSR RQM 6 DIO 2 DRV2 BUSY 1 DRV1 BUSY 0 DRV0 BUSY DRVx Busy, Bits 0 - 3 These bits are set to a “1” when a drive is in the seek portion of a command, including implied and overlapped seeks and recalibrates. SMSC DS – FDC37N869 Page 25 Rev. 11/09/2000 Command Busy, Bit 4 This bit is set to a “1” when a command is in progress. This bit will go active after the command byte has been accepted and goes inactive at the end of the results phase. If there is no result phase (Seek, Recalibrate commands), this bit is returned to a “0” after the last command byte. Non-DMA, Bit 5 This mode is selected in the SPECIFY command and will be set to a “1” during the execution phase of a command. This is for polled data transfers and helps to differentiate between the data transfer phase and the reading of result bytes. DIO, Bit 6 Indicates the direction of a data transfer once an RQM is set. A “1” indicates a read and a “0” indicates a write is required. RQM, Bit 7 Indicates that the host can transfer data if set to a “1”. No access is permitted if set to a “0”. DATA RATE SELECT REGISTER (DSR) The Data Rate Select Register (Base Address + 4: Write-only) is used to program the data rate, amount of write precompensation, power down status, and software reset (Table 17). Note: the data rate is programmed using the Configuration Control Register (CCR) not the DSR, for PC/AT and PS/2 Model 30 and Microchannel applications. Other applications can set the data rate in the DSR. The data rate of the floppy controller is the most recent write of either the DSR or CCR. The DSR is unaffected by a software reset. A hardware reset will set the DSR to 02H, which corresponds to the default precompensation setting and 250 Kbps. Table 17 - Data Rate Select Register 6 5 4 3 POWER DOWN 0 0 0 PRECOMP2 0 PRECOMP1 0 7 S/W RESET RESET CONDITION Data Rate Select, Bits 0 - 1 0 2 PRECOMP0 0 1 DRATE SEL1 1 0 DRATE SEL0 0 These bits control the data rate of the floppy controller. See Table 19 for the settings corresponding to the individual data rates. The data rate select bits are unaffected by a software reset and are set to 250 Kbps after a hardware reset. Precompensation Select, Bits 2 - 4 These three bits select the value of write precompensation that will be applied to the WDATA output signal. Table 18 shows the precompensation values for the combination of these bits settings. Track 0 is the default starting track number to start precompensation. The starting track number can be changed using the Configure command. Undefined, Bit 5 Should be written as a logic “0”. SMSC DS – FDC37N869 Page 26 Rev. 11/09/2000 Low Power, Bit 6 A logic “1” written to this bit will put the floppy controller into Manual Low Power mode. The floppy controller clock and data separator circuits will be turned off. The controller will come out of manual low power mode after a software reset or following access to the Data Register or Main Status Register. Software Reset, Bit 7 This active high bit has the same function as the DOR RESET (DOR bit 2) except that this bit is self clearing. Table 18 - Precompensation Delays PRECOMP SELECT PRECOMPENSATION DELAY 4 3 2 1 1 1 0.00 ns-DISABLED 0 0 1 41.67 ns 0 1 0 83.34 ns 0 1 1 125.00 ns 1 0 0 166.67 ns 1 0 1 208.33 ns 1 1 0 250.00 ns 0 0 0 Default (see Table 21) SMSC DS – FDC37N869 Page 27 Rev. 11/09/2000 Table 19 - Data Rates DRIVE RATE SELECT (CR0B) DRT1 DRT0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 DATA RATE SELECT (DSR) SEL1 SEL0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 DENSEL (Note 1) IDENT=1 IDENT=0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 DATA RATE MFM FM 1Meg 500 300 250 1Meg 500 500 250 1Meg 500 2Meg 250 --250 150 125 --250 250 125 --250 --125 DRATE 1 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 Note 1: This is for DENSEL in normal mode (see section CR05 on page 108). The DENSEL pin is set high after a hardware reset and is unaffected by the DOR and the DSR resets. Table 20 - Drive Rate Table (Recommended) FORMAT (see section CR0B on page 110 to program Drive Rate) 360K, 1.2M, 720K, 1.44M and 2.88M Vertical Format 3-Mode Drive 2 Meg Tape DRIVE RATE DRT1 DRT0 0 0 0 1 1 0 Table 21 - Default Precompensation Delays PRECOMPENSATION DATA RATE DELAYS 2 Mbps 125 ns 1 Mbps 41.67 ns 500 Kbps 125 ns 300 Kbps 125 ns 250 Kbps 125 ns SMSC DS – FDC37N869 Page 28 Rev. 11/09/2000 DATA REGISTER (FIFO) The Data Register (Base Address + 5) is used to transfer all command parameter information, disk data and result status between the host processor and the floppy disk controller. The Data Register is Read/Write. Data transfers are governed by the RQM and DIO bits in the Main Status Register. The Data Register defaults to FIFO disabled mode after any form of reset. This maintains PC/AT hardware compatibility. The default values can be changed through the Configure command (enable full FIFO operation with threshold control). The advantage of the FIFO is that it allows the system a larger DMA latency without causing a disk error. Table 22 gives several examples of service delays with a FIFO. The data is based upon the following formula: Threshold# × (8 ÷ Data Rate) - 1.5 µ S = DELAY At the start of a command the FIFO action is always disabled and command parameters must be sent based upon the RQM and DIO bit settings. As the command execution phase is entered, the FIFO is cleared of any data to ensure that invalid data is not transferred. An overrun or underrun will terminate the current command and the transfer of data. Disk writes will complete the current sector by generating a 00 pattern and valid CRC. Reads require the host to remove the remaining data so that the result phase may be entered. Table 22 - Example FIFO Service Delays EXAMPLE DATA RATES FIFO THRESHOLD EXAMPLES 1 byte 2 bytes 8 bytes 15 bytes 2Mbps 1 x 4 µs - 1.5 µs = 2.5 µs 2 x 4 µs - 1.5 µs = 6.5 µs 8 x 4 µs - 1.5 µs = 30.5 µs 15 x 4 µs - 1.5 µs = 58.5 µs 1Mbps 1 x 8 µs - 1.5 µs = 6.5 µs 2 x 8 µs - 1.5 µs = 14.5 µs 8 x 8 µs - 1.5 µs = 62.5 µs 15 x 8 µs - 1.5 µs = 118.5 µs 500Kbps 1 x 16µs - 1.5 µs = 14.5 µs 2 x 16µs - 1.5 µs = 30.5 µs 8 x 16µs - 1.5 µs = 126.5 µs 15 x 16µs - 1.5 µs = 238.5 µs DIGITAL INPUT REGISTER (DIR) The Digital Input Register (Bass Address + 7: Read-only) is read-only in all modes. Table 23 shows the DIR in PC/AT mode, Table 24 shows the DIR in PS/2 mode, and Table 25 shows the DIR in Model 30 mode. PC-AT Interface Mode Table 23 - DIR PC/AT Interface Mode 7 6 5 4 3 DSK CHG RESET CONDITION Undefined, Bits 0 - 6 The data bus outputs D0 - 6 will remain in a high impedance state during a read of this register. DSK CHG, Bit 7 The DSK CHG bit monitors the state of the pin of the same name and reflects the opposite value seen on the disk cable. The DSK CHG bit also depends upon the Force Disk Change bits in the Force FDD Status Change register (see section CR17 on page 109). N/A N/A N/A N/A N/A N/A N/A N/A 2 1 0 SMSC DS – FDC37N869 Page 29 Rev. 11/09/2000 PS/2 Interface Mode 7 DSK CHG RESET CONDITION nHIGH DENS, Bit 0 This bit is low whenever the 500 Kbps or 1 Mbps data rates are selected, and high when 250 Kbps and 300 Kbps are selected. Data Rate Select, Bits 1 - 2 These bits control the data rate of the floppy controller. See Table 19 for the settings corresponding to the individual data rates. The data rate select bits are unaffected by a software reset, and are set to 250 Kbps after a hardware reset. Undefined, Bits 3 - 6 Always read as a logic “1” DSK CHG, Bit 7 The DSK CHG bit monitors the pin of the same name and reflects the opposite value seen on the disk cable. The DSK CHG bit also depends upon the Force Disk Change bits in the Force FDD Status Change register (see section CR17 on page 109). N/A Table 24 - DIR PS/2 Interface Mode 6 5 4 3 2 1 N/A 1 N/A 1 N/A 1 N/A DRATE SEL1 N/A 1 DRATE SEL0 N/A 0 nHIGH DENS 1 Model 30 Interface Mode 7 DSK CHG N/A Table 25 - DIR Model 30 Interface Mode 6 5 4 3 2 0 0 0 DMAEN NOPREC 0 0 0 0 0 1 0 DRATE SEL1 DRATE SEL0 1 0 RESET CONDITION Data Rate Select, Bits 0 - 1 These bits control the data rate of the floppy controller. See Table 19 for the settings corresponding to the individual data rates. The data rate select bits are unaffected by a software reset, and are set to 250kb/s after a hardware reset Noprec, Bit 2 This bit reflects the value of the NOPREC bit set in the CCR register. DMAEN, Bit 3 This bit reflects the value of DMAEN bit set in the DOR register bit 3. Undefined, Bits 4 - 6 Always read as a logic “0” SMSC DS – FDC37N869 Page 30 Rev. 11/09/2000 DSK CHG, Bit 7 The DSK CHG bit monitors the pin of the same name and reflects the opposite value seen on the pin. The DSK CHG bit also depends upon the Force Disk Change bits in the Force FDD Status Change register (see section CR17 on page 109). CONFIGURATION CONTROL REGISTER (CCR) The Configuration Control Register (Bass Address + 7: Write-only) is write-only in all modes. Table 26 shows the CCR in PC/AT mode and PS/2 mode. Table 27 shows the CCR in Model 30 mode. PC/AT and PS/2 Interface Modes Table 26 - CCR PC/AT and PS/2 Interface Modes 7 6 5 4 3 2 1 DRATE SEL1 RESET CONDITION Data Rate Select, Bits 0 - 1 These bits determine the data rate of the floppy controller. See Table 19 for the appropriate values. Reserved, Bits 2 - 7 Bits 2 to 7 are RESERVED. Reserved bits cannot be written and return 0 when read. N/A N/A N/A N/A N/A N/A 1 0 DRATE SEL0 0 Model 30 Interface Mode Table 27 - CCR Model 30 Interface Mode 6 5 4 3 2 NOPREC RESET CONDITION Data Rate Select, Bits 0 - 1 These bits determine the data rate of the floppy controller. See Table 19 for the appropriate values. No Precompensation, Bit 2 This bit can be set by software, but it has no functionality. It can be read by bit 2 of the DSR when in Model 30 register mode. Unaffected by software reset. RESERVED, Bits 3 - 7 Bits 3 to 7 are RESERVED. Reserved bits cannot be written and return 0 when read. N/A N/A N/A N/A N/A N/A 7 1 DRATE SEL1 1 0 DRATE SEL0 0 SMSC DS – FDC37N869 Page 31 Rev. 11/09/2000 Status Register Encoding During the Result Phase of certain commands, the Data Register contains data bytes that give the status of the command just executed. Table 28 - Status Register 0 BIT NO. 7,6 SYMBOL NAME IC Interrupt Code DESCRIPTION 00 - Normal termination of command. The specified command was properly executed and completed without error. 01 - Abnormal termination of command. Command execution was started, but was not successfully completed. 10 - Invalid command. The requested command could not be executed. 11 - Abnormal termination caused by Polling. Seek End The FDC completed a Seek, Relative Seek or Recalibrate command (used during a Sense Interrupt Command). Equipment The TRK0 pin failed to become a “1” after: Check 1. 80 step pulses in the Recalibrate command. 2. The Relative Seek command caused the FDC to step outward beyond Track 0. Unused. This bit is always “0”. Head The current head address. Address Drive The current selected drive. Select 5 4 SE EC 3 2 1,0 H DS1,0 Table 29 - Status Register 1 BIT NO. 7 6 5 4 3 2 SYMBOL NAME EN End of Cylinder DE OR Data Error Overrun/ Underrun No Data DESCRIPTION The FDC tried to access a sector beyond the final sector of the track (255D). Will be set if TC is not issued after Read or Write Data command. Unused. This bit is always “0”. The FDC detected a CRC error in either the ID field or the data field of a sector. Becomes set if the FDC does not receive CPU or DMA service within the required time interval, resulting in data overrun or underrun. Unused. This bit is always “0”. Any one of the following: 1. Read Data, Read Deleted Data command - the FDC did not find the specified sector. 2. Read ID command - the FDC cannot read the ID field without an error. 3. Read A Track command - the FDC cannot find the proper sector sequence. WP pin became a “1” while the FDC is executing a Write Data, Write Deleted Data, or Format A Track command. Any one of the following: 1. The FDC did not detect an ID address mark at the specified track after encountering the index pulse from the IDX pin twice. 2. The FDC cannot detect a data address mark or a deleted data address mark on the specified track. ND 1 0 NW MA Not Writable Missing Address Mark SMSC DS – FDC37N869 Page 32 Rev. 11/09/2000 Table 30 - Status Register 2 BIT NO. SYMBOL NAME 7 6 CM Control Mark DESCRIPTION Unused. This bit is always “0”. Any one of the following: 1. Read Data command - the FDC encountered a deleted data address mark. 2. Read Deleted Data command - the FDC encountered a data address mark. The FDC detected a CRC error in the data field. 5 DD 4 3 2 1 WC Data Error in Data Field Wrong Cylinder BC Bad Cylinder 0 MD Missing Data Address Mark The track address from the sector ID field is different from the track address maintained inside the FDC. Unused. This bit is always “0”. Unused. This bit is always “0”. The track address from the sector ID field is different from the track address maintained inside the FDC and is equal to FF hex, which indicates a bad track with a hard error according to the IBM soft-sectored format. The FDC cannot detect a data address mark or a deleted data address mark. Table 31 - Status Register 3 BIT NO. SYMBOL NAME 7 6 WP Write Protected DESCRIPTION Unused. This bit is always “0”. Indicates the status of the WP pin. The Write Protected bit also depends upon the state of the Force Write Protect bits in the Force FDD Status Change configuration register (see section CR17 on page 109). Unused. This bit is always “1”. Indicates the status of the TRK0 pin. Unused. This bit is always “1”. Indicates the status of the HDSEL pin. Indicates the status of the DS1, DS0 pins. 5 4 3 2 1,0 T0 HD DS1,0 Track 0 Head Address Drive Select Reset There are three sources of system reset on the FDC: the RESET pin of the FDC37N869, a reset generated via a bit in the DOR, and a reset generated via a bit in the DSR. At power on, a Power On Reset initializes the FDC. All resets take the FDC out of the power down state. All operations are terminated upon a RESET, and the FDC enters an idle state. A reset while a disk write is in progress will corrupt the data and CRC. On exiting the reset state, various internal registers are cleared, including the Configure command information, and the FDC waits for a new command. Drive polling will start unless disabled by a new Configure command. SMSC DS – FDC37N869 Page 33 Rev. 11/09/2000 RESET Pin (Hardware Reset) The RESET pin is a global reset and clears all registers except those programmed by the Specify command. The DOR reset bit is enabled and must be cleared by the host to exit the reset state. DOR Reset vs. DSR Reset (Software Reset) These two resets are functionally the same. Both will reset the FDC core, which affects drive status information and the FIFO circuits. The DSR reset clears itself automatically while the DOR reset requires the host to manually clear it. DOR reset has precedence over the DSR reset. The DOR reset is set automatically upon a pin reset. The user must manually clear this reset bit in the DOR to exit the reset state. DMA Transfers DMA transfers are enabled with the Specify command and are initiated by the FDC by activating the FDRQ pin during a data transfer command. The FIFO is enabled directly by asserting nDACK and addresses need not be valid. Note that if the DMA controller (i.e. 8237A) is programmed to function in verify mode, a pseudo read is performed by the FDC based only on nDACK. This mode is only available when the FDC has been configured into byte mode (FIFO disabled) and is programmed to do a read. With the FIFO enabled, the FDC can perform the above operation by using the new Verify command; no DMA operation is needed. Controller Phases For simplicity, command handling in the FDC can be divided into three phases: Command, Execution, and Result. Each phase is described in the following sections. Command Phase After a reset, the FDC enters the command phase and is ready to accept a command from the host. For each of the commands, a defined set of command code bytes and parameter bytes has to be written to the FDC before the command phase is complete. (Refer to Table 33 for the command set descriptions). These bytes of data must be transferred in the order prescribed. Before writing to the FDC, the host must examine the RQM and DIO bits of the Main Status Register. RQM and DIO must be equal to “1” and “0” respectively before command bytes may be written. RQM is set false by the FDC after each write cycle until the received byte is processed. The FDC asserts RQM again to request each parameter byte of the command unless an illegal command condition is detected. After the last parameter byte is received, RQM remains “0” and the FDC automatically enters the next phase as defined by the command definition. The FIFO is disabled during the command phase to provide for the proper handling of the “Invalid Command” condition. Execution Phase All data transfers to or from the FDC occur during the execution phase, which can proceed in DMA or non-DMA mode as indicated in the Specify command. After a reset, the FIFO is disabled. Each data byte is transferred by an FINT or FDRQ depending on the DMA mode. The Configure command can enable the FIFO and set the FIFO threshold value. The following paragraphs detail the operation of the FIFO flow control. In these descriptions, is defined as the number of bytes available to the FDC when service is requested from the host and ranges from 1 to 16. The parameter FIFOTHR, which the user programs, is one less and ranges from 0 to 15. A low threshold value (i.e. 2) results in longer periods of time between service requests, but requires faster servicing of the request for both read and write cases. The host reads (writes) from (to) the FIFO until empty (full), then the transfer request goes inactive. The host must be very responsive to the service request. This is the SMSC DS – FDC37N869 Page 34 Rev. 11/09/2000 desired case for use with a “fast” system. A high value of threshold (i.e. 12) is used with a “sluggish” system by affording a long latency period after a service request, but results in more frequent service requests. Non-DMA Mode Transfers FIFO to Host The FINT pin and RQM bits in the Main Status Register are activated when the FIFO contains (16-) bytes or the last bytes of a full sector have been placed in the FIFO. The FINT pin can be used for interrupt-driven systems,and RQM can be used for polled systems. The host must respond to the request by reading data from the FIFO. This process is repeated until the last byte is transferred out of the FIFO. The FDC will deactivate the FINT pin and RQM bit when the FIFO becomes empty. Host to FIFO The FINT pin and RQM bit in the Main Status Register are activated upon entering the execution phase of data transfer commands. The host must respond to the request by writing data into the FIFO. The FINT pin and RQM bit remain true until the FIFO becomes full. They are set true again when the FIFO has bytes remaining in the FIFO. The FINT pin will also be deactivated if TC and nDACK both go inactive. The FDC enters the result phase after the last byte is taken by the FDC from the FIFO (i.e. FIFO empty condition). DMA Mode Transfers FIFO to Host The FDC activates the DDRQ pin when the FIFO contains (16 - ) bytes, or the last byte of a full sector transfer has been placed in the FIFO. The DMA controller must respond to the request by reading data from the FIFO. The FDC will deactivate the DDRQ pin when the FIFO becomes empty. FDRQ goes inactive after nDACK goes active for the last byte of a data transfer (or on the active edge of nIOR, on the last byte, if no edge is present on nDACK). A data underrun may occur if FDRQ is not removed in time to prevent an unwanted cycle. Host to FIFO The FDC activates the FDRQ pin when entering the execution phase of the data transfer commands. The DMA controller must respond by activating the nDACK and nIOW pins and placing data in the FIFO. FDRQ remains active until the FIFO becomes full. FDRQ is again set true when the FIFO has bytes remaining in the FIFO. The FDC will also deactivate the FDRQ pin when TC becomes true (qualified by nDACK), indicating that no more data is required. FDRQ goes inactive after nDACK goes active for the last byte of a data transfer (or on the active edge of nIOW of the last byte, if no edge is present on nDACK). A data overrun may occur if FDRQ is not removed in time to prevent an unwanted cycle. Data Transfer Termination The FDC supports terminal count explicitly through the TC pin and implicitly through the underrun/overrun and endof-track (EOT) functions. For full sector transfers, the EOT parameter can define the last sector to be transferred in a single or multi-sector transfer. If the last sector to be transferred is a partial sector, the host can stop transferring the data in mid-sector, and the FDC will continue to complete the sector as if a hardware TC was received. The only difference between these implicit functions and TC is that they return “abnormal termination” result status. Such status indications can be ignored if they were expected. Note that when the host is sending data to the FIFO of the FDC, the internal sector count will be complete when the FDC reads the last byte from its side of the FIFO. There may be a delay in the removal of the transfer request signal of up to the time taken for the FDC to read the last 16 bytes from the FIFO. The host must tolerate this delay. Result Phase The generation of FINT determines the beginning of the result phase. For each of the commands, a defined set of result bytes has to be read from the FDC before the result phase is complete. These bytes of data must be read out for another command to start. SMSC DS – FDC37N869 Page 35 Rev. 11/09/2000 RQM and DIO must both equal “1” before the result bytes may be read. After all the result bytes have been read, the RQM and DIO bits switch to “1” and “0” respectively, and the CB bit is cleared, indicating that the FDC is ready to accept the next command. Command Set/Descriptions Commands can be written whenever the FDC is in the command phase. Each command has a unique set of needed parameters and status results. The FDC checks to see that the first byte is a valid command and, if valid, proceeds with the command. If it is invalid, an interrupt is issued. The user sends a Sense Interrupt Status command which returns an invalid command error. Refer to Table 32 for explanations of the various symbols used. Table 33 lists the required parameters and the results associated with each command that the FDC is capable of performing. Table 32 - Description of Command Symbols DESCRIPTION The currently selected address; 0 to 255. The pattern to be written in each sector data field during formatting. Designates which drives are perpendicular drives on the Perpendicular Mode Command. A “1” indicates a perpendicular drive. If this bit is “0”, then the head will step out from the spindle during a relative seek. If set to a “1”, the head will step in toward the spindle. DS1 0 0 1 1 DTL Special Sector Size DS0 0 1 0 1 DRIVE Drive 0 Drive 1 Drive 2 Drive 3 SYMBOL C D D0, D1, D2, D3 DIR DS0, DS1 NAME Cylinder Address Data Pattern Drive Select 0-3 Direction Control Disk Drive Select By setting N to zero (00), DTL may be used to control the number of bytes transferred in disk read/write commands. The sector size (N = 0) is set to 128. If the actual sector (on the diskette) is larger than DTL, the remainder of the actual sector is read but is not passed to the host during read commands; during write commands, the remainder of the actual sector is written with all zero bytes. The CRC check code is calculated with the actual sector. When N is not zero, DTL has no meaning and should be set to FF HEX. When this bit is “1” the “DTL” parameter of the Verify command becomes SC (number of sectors per track). This active low bit when a 0, enables the FIFO. A “1” disables the FIFO (default). When set, a seek operation will be performed before executing any read or write command that requires the C parameter in the command phase. A “0” disables the implied seek. The final sector number of the current track. Alters Gap 2 length when using Perpendicular Mode. EC EFIFO EIS Enable Count Enable FIFO Enable Implied Seek End of Track EOT GAP GPL H/HDS HLT Gap Length Head Address Head Load Time The Gap 3 size. (Gap 3 is the space between sectors excluding the VCO synchronization field). Selected head: 0 or 1 (disk side 0 or 1) as encoded in the sector ID field. The time interval that FDC waits after loading the head and before initializing a read or write operation. Refer to the Specify command for actual delays. The time interval from the end of the execution phase (of a read or write command) until the head is unloaded. Refer to the Specify command HUT Head Unload SMSC DS – FDC37N869 Page 36 Rev. 11/09/2000 SYMBOL Time LOCK NAME for actual delays. DESCRIPTION Lock defines whether EFIFO, FIFOTHR, and PRETRK parameters of the CONFIGURE COMMAND can be reset to their default values by a “software Reset” (A reset caused by writing to the appropriate bits of either the DSR or DOR). MFM MT MFM/FM Mode Selector Multi-Track Selector A one selects the double density (MFM) mode. A zero selects single density (FM) mode. When set, this flag selects the multi-track operating mode. In this mode, the FDC treats a complete cylinder under head 0 and 1 as a single track. The FDC operates as this expanded track started at the first sector under head 0 and ended at the last sector under head 1. With this flag set, a multitrack read or write operation will automatically continue to the first sector under head 1 when the FDC finishes operating on the last sector under head 0. This specifies the number of bytes in a sector. If this parameter is “00”, then the sector size is 128 bytes. The number of bytes transferred is determined by the DTL parameter. Otherwise the sector size is (2 raised to the “N’th” power) times 128. All values up to “07” hex are allowable. “07”h would equal a sector size of 16k. It is the user’s responsibility to not select combinations that are not possible with the drive. N 00 01 02 ... 07 SECTOR SIZE 128bytes 256bytes 512bytes ... 16Kbytes N Sector Size Code NCN ND New Cylinder Number Non-DMA Mode Flag The desired cylinder number. When set to “1”, indicates that the FDC is to operate in the non-DMA mode. In this mode, the host is interrupted for each data transfer. When set to 0, the FDC operates in DMA mode, interfacing to a DMA controller by means of the DRQ and nDACK signals. The bits D0-D3 of the Perpendicular Mode Command can only be modified if OW is set to “1”. OW id defined in the Lock command. The current position of the head at the completion of Sense Interrupt Status command. When set, the internal polling routine is disabled. When clear, polling is enabled. Programmable from track 00 to FFH. OW PCN POLL PRETRK Overwrite Present Cylinder Number Polling Disable Precompensatio n Start Track Number Sector Address R The sector number to be read or written. In multi-sector transfers, this parameter specifies the sector number of the first sector to be read or written. Relative cylinder offset from present cylinder as used by the Relative Seek command. RCN SC Relative Cylinder Number Number of The number of sectors per track to be initialized by the Format Sectors Per Track command. The number of sectors per track to be verified during a Verify command when EC is set. SMSC DS – FDC37N869 Page 37 Rev. 11/09/2000 SYMBOL SK NAME Skip Flag DESCRIPTION When set to “1”, sectors containing a deleted data address mark will automatically be skipped during the execution of Read Data. If Read Deleted is executed, only sectors with a deleted address mark will be accessed. When set to “0”, the sector is read or written the same as the read and write commands. SRT Step Rate Interval The time interval between step pulses issued by the FDC. Programmable from 0.5 to 8 milliseconds in increments of 0.5 ms at the 1 Mbit data rate. Refer to the SPECIFY command for actual delays. Status 0 Status 1 Status 2 Status 3 Write Gate Registers within the FDC which store status information after a command has been executed. This status information is available to the host during the result phase after command execution. Alters timing of WE to allow for pre-erase loads in perpendicular drives. ST0 ST1 ST2 ST3 WGATE Instruction Set Table 33 - Instruction Set READ DATA DATA BUS D6 D5 D4 D3 D2 D1 D0 REMARKS MFM SK 0 0 1 1 0 Command Codes 0 0 0 0 HDS DS1 DS0 - - - - - - - - C- - - - - - - Sector ID information prior to Command execution. - - - - - - - - H- - - - - - - - - - - - - - - R- - - - - - - - - - - - - - - N- - - - - - - - - - - - - - EOT - - - - - - - - - - - - - GPL - - - - - - - - - - - - - DTL - - - - - - Data transfer between the FDD and system. - - - - - - - ST0 - - - - - - Status information after Com mand execution. - - - - - - - ST1 - - - - - - - - - - - - - ST2 - - - - - - - - - - - - - - C- - - - - - - Sector ID information after Com mand execution. - - - - - - - - H- - - - - - - - - - - - - - - R- - - - - - - - - - - - - - - N- - - - - - - - PHASE Command R/W W W W W W W W W W D7 MT 0 Execution Result R R R R R R R SMSC DS – FDC37N869 Page 38 Rev. 11/09/2000 PHASE Command R/W W W W W W W W W W D7 MT 0 Execution Result R R R R R R R READ DELETED DATA DATA BUS D6 D5 D4 D3 D2 D1 D0 REMARKS MFM SK 0 1 1 0 0 Command Codes 0 0 0 0 HDS DS1 DS0 - - - - - - - - C- - - - - - - Sector ID information prior to Command execution. - - - - - - - - H- - - - - - - - - - - - - - - R- - - - - - - - - - - - - - - N- - - - - - - - - - - - - - EOT - - - - - - - - - - - - - GPL - - - - - - - - - - - - - DTL - - - - - - Data transfer between the FDD and system. - - - - - - - ST0 - - - - - - Status information after Com mand execution. - - - - - - - ST1 - - - - - - - - - - - - - ST2 - - - - - - - - - - - - - - C- - - - - - - Sector ID information after Com mand execution. - - - - - - - - H- - - - - - - - - - - - - - - R- - - - - - - - - - - - - - - N- - - - - - - - PHASE Command R/W W W W W W W W W W D7 MT 0 Execution Result R R R R R R R WRITE DATA DATA BUS D6 D5 D4 D3 D2 D1 D0 REMARKS MFM 0 0 0 1 0 1 Command Codes 0 0 0 0 HDS DS1 DS0 - - - - - - - - C- - - - - - - Sector ID information prior to Command execution. - - - - - - - - H- - - - - - - - - - - - - - - R- - - - - - - - - - - - - - - N- - - - - - - - - - - - - - EOT - - - - - - - - - - - - - GPL - - - - - - - - - - - - - DTL - - - - - - Data transfer between the FDD and system. - - - - - - - ST0 - - - - - - Status information after Com mand execution. - - - - - - - ST1 - - - - - - - - - - - - - ST2 - - - - - - - - - - - - - - C- - - - - - - Sector ID information after Command execution. - - - - - - - - H- - - - - - - - - - - - - - - R- - - - - - - - - - - - - - - N- - - - - - - - SMSC DS – FDC37N869 Page 39 Rev. 11/09/2000 WRITE DELETED DATA PHASE Command R/W W W W D7 MT 0 D6 MFM 0 -DATA BUS D5 D4 D3 D2 D1 0 0 1 0 0 0 0 0 HDS DS1 - - - - - - C- - - - - - - D0 1 DS0 REMARKS Command Codes Sector ID information prior to Command execution. W W W W W W Execution Result R R R R - - - - - - - - H- - - - - - - - - - - - - - - R- - - - - - - - - - - - - - - N- - - - - - - - - - - - - - EOT - - - - - - - - - - - - - GPL - - - - - - - - - - - - - DTL - - - - - - Data transfer between the FDD and system. Status information after Com mand execution. - - - - - - - ST0 - - - - - - - - - - - - - ST1 - - - - - - - - - - - - - ST2 - - - - - - - - - - - - - - C- - - - - - - - Sector ID information after Command execution. R R R - - - - - - - - H- - - - - - - - - - - - - - - R- - - - - - - - - - - - - - - N- - - - - - - READ A TRACK DATA BUS D6 D5 D4 D3 D2 D1 MFM 0 0 0 0 1 0 0 0 0 HDS DS1 - - - - - - - - C- - - - - - - - PHASE Command R/W W W W D7 0 0 D0 0 DS0 REMARKS Command Codes Sector ID information prior to Command execution. W W W W W W Execution - - - - - - - - H- - - - - - - - - - - - - - - R- - - - - - - - - - - - - - - N- - - - - - - - - - - - - - EOT - - - - - - - - - - - - - GPL - - - - - - - - - - - - - DTL - - - - - - Data transfer between the FDD and system. FDC reads all of cylinders’ contents from index hole to EOT. Status information after Com mand execution. Result R R R R - - - - - - - ST0 - - - - - - - - - - - - - ST1 - - - - - - - - - - - - - ST2 - - - - - - - - - - - - - - C- - - - - - - - Sector ID information after Command execution. R - - - - - - - - H- - - - - - - - SMSC DS – FDC37N869 Page 40 Rev. 11/09/2000 PHASE R/W R R D7 READ A TRACK DATA BUS D6 D5 D4 D3 D2 D1 - - - - - - - - R- - - - - - - - - - - - - - - N- - - - - - - VERIFY DATA BUS D6 D5 D4 D3 D2 D1 MFM SK 1 0 1 1 0 0 0 0 HDS DS1 - - - - - - - - C- - - - - - - - D0 REMARKS PHASE Command R/W W W W D7 MT EC D0 0 DS0 REMARKS Command Codes Sector ID information prior to Command execution. W W W W W W Execution Result R R R R - - - - - - - - H- - - - - - - - - R- - - - - - - - - N- - - - - - - - EOT - - - - - - - GPL - - - - - - DTL/SC - - - - - No data transfer takes place. Status information after Com mand execution. - - - - - - - ST0 - - - - - - - - - - - - - ST1 - - - - - - - - - - - - - ST2 - - - - - - - - - - - - - - C- - - - - - - - Sector ID information after Command execution. R R R - - - - - - - - H- - - - - - - - - - - - - - - R- - - - - - - - - - - - - - - N- - - - - - - - PHASE Command Result R/W W R D7 0 1 D6 0 0 D5 0 0 VERSION DATA BUS D4 D3 D2 1 0 0 1 0 0 D1 0 0 D0 0 0 REMARKS Command Code Enhanced Controller SMSC DS – FDC37N869 Page 41 Rev. 11/09/2000 PHASE Command R/W W W W W W W D7 0 0 D6 MFM 0 FORMAT A TRACK DATA BUS D5 D4 D3 D2 0 0 1 1 0 0 0 HDS D1 0 DS1 D0 1 DS0 REMARKS Command Codes Bytes/Sector Sectors/Cylinder Gap 3 Filler Byte Input Sector Parameters - - - - - - - - N- - - - - - - - - - - - - - - SC - - - - - - - - - - - - - - GPL - - - - - - - - - - - - - - D- - - - - - - - - - - - - - - C- - - - - - - - Execution for Each Sector Repeat: W W W W - - - - - - - - H- - - - - - - - - - - - - - - R- - - - - - - - - - - - - - - N- - - - - - - FDC formats an entire cylinder Result R R R R R R R - - - - - - - ST0 - - - - - - - - - - - - - ST1 - - - - - - - - - - - - - ST2 - - - - - - - - - - - - Undefined - - - - - - - - - - - Undefined - - - - - - - - - - - Undefined - - - - - - - - - - - Undefined - - - - - - Status information after Command execution PHASE Command Execution R/W W W D7 0 0 D6 0 0 D5 0 0 RECALIBRATE DATA BUS D4 D3 D2 0 0 1 0 0 0 D1 1 DS1 D0 1 DS0 REMARKS Command Codes Head retracted to Track 0 Interrupt. SMSC DS – FDC37N869 Page 42 Rev. 11/09/2000 SENSE INTERRUPT STATUS PHASE Command Result R/W W R R D7 0 D6 0 D5 0 DATA BUS D4 D3 D2 0 1 0 D1 0 D0 0 REMARKS Command Codes Status information at the end of each seek operation. - - - - - - - ST0 - - - - - - - - - - - - - PCN - - - - - - - SPECIFY PHASE Command R/W W W W DATA BUS D7 D6 D5 D4 0 0 0 0 - - - SRT - - - - - - - - HLT - - - D3 D2 D1 0 0 1 - - - HUT - - -D0 1 ND REMARKS Command Codes SENSE DRIVE STATUS PHASE Command Result R/W W W R D7 0 0 D6 0 0 D5 0 0 DATA BUS D4 D3 D2 0 0 1 0 0 HDS D1 0 DS1 D0 0 DS0 Status information about FDD REMARKS Command Codes - - - - - - - ST3 - - - - - - - SEEK PHASE Command R/W W W W Execution D7 0 0 D6 0 0 D5 0 0 DATA BUS D4 D3 D2 0 1 1 0 0 HDS D1 1 DS1 D0 1 DS0 Head positioned over proper cylinder on diskette. REMARKS Command Codes - - - - - - - NCN - - - - - - - CONFIGURE PHASE Command R/W W W W Execution W D7 0 0 0 D6 0 0 D5 0 0 DATA BUS D4 D3 1 0 0 POLL 0 D2 0 0 D1 1 0 D0 1 0 REMARKS Configure Information EIS EFIFO - - - FIFOTHR - - - - - - - - - - - - PRETRK - - - - - - - - - SMSC DS – FDC37N869 Page 43 Rev. 11/09/2000 RELATIVE SEEK DATA BUS PHASE Command R/W W W W D7 1 0 D6 DIR 0 D5 0 0 D4 0 0 D3 1 0 D2 1 HDS D1 1 DS1 D0 1 DS0 REMARKS - - - - - - - RCN - - - - - - - DUMPREG DATA BUS PHASE Command R/W W D7 0 D6 0 D5 0 D4 0 D3 1 D2 1 D1 1 D0 0 REMARKS *Note: Registers placed in FIFO Execution Result R R R R R R R R R R LOCK 0 0 - - - - - - PCN-Drive 0 - - - - - - - - - - - - PCN-Drive 1 - - - - - - - - - - - - PCN-Drive 2 - - - - - - - - - - - - PCN-Drive 3 - - - - - - - - - - SRT - - - - - - HUT - - ND GAP WGATE - - - - - - - HLT - - - - - - - - - - - - - SC/EOT - - - - - - D3 D2 POLL D1 D0 EIS EFIFO - - FIFOTHR - - - - - - - - - - PRETRK - - - - - - - - SMSC DS – FDC37N869 Page 44 Rev. 11/09/2000 READ ID DATA BUS PHASE Command Execution R/W W W D7 0 0 D6 MFM 0 D5 0 0 D4 0 0 D3 1 0 D2 0 HDS D1 1 DS1 D0 0 DS0 The first correct ID information on the Cylinder is stored in Data Register R - - - - - - - - ST0 - - - - - - - Status information after Command execution. REMARKS Commands Result Disk status after the Command has completed R R R R R R - - - - - - - - ST1 - - - - - - - - - - - - - - - ST2 - - - - - - - - - - - - - - - C- - - - - - - - - - - - - - - H- - - - - - - - - - - - - - - R- - - - - - - - - - - - - - - N- - - - - - - - PERPENDICULAR MODE DATA BUS PHASE Command R/W W D7 0 OW D6 0 0 D5 0 D3 D4 1 D2 D3 0 D1 D2 0 D0 D1 1 GAP D0 0 WGATE REMARKS Command Codes SMSC DS – FDC37N869 Page 45 Rev. 11/09/2000 INVALID CODES DATA BUS PHASE Command R/W W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS Invalid Command Codes (NoOp - FDC37N869 goes into Standby State) ST0 = 80H - - - - - Invalid Codes - - - - - Result R - - - - - - - ST0 - - - - - - - LOCK DATA BUS PHASE Command Result R/W W R D7 LOCK 0 D6 0 0 D5 0 0 D4 1 LOCK D3 0 0 D2 1 0 D1 0 0 D0 0 0 REMARKS Command Codes SC is returned if the last command that was issued was the Format command. EOT is returned if the last command was a Read or Write. Note: These bits are used internally only. They are not reflected in the Drive Select pins. responsibility to maintain correspondence between these bits and the Drive Select pins (DOR). Data Transfer Commands All of the Read Data, Write Data and Verify type commands use the same parameter bytes and return the same results information, the only difference being the coding of bits 0-4 in the first byte. An implied seek will be executed if the feature was enabled by the Configure command. This seek is completely transparent to the user. The Drive Busy bit for the drive will go active in the Main Status Register during the seek portion of the command. If the seek portion fails, it will be reflected in the results status normally returned for a Read/Write Data command. Status Register 0 (ST0) would contain the error code and C would contain the cylinder on which the seek failed. Read Data A set of nine bytes is required to place the FDC in the Read Data Mode. After the Read Data command has been issued, the FDC loads the head (if it is in the unloaded state), waits the specified head settling time (defined in the Specify command), and begins reading ID Address Marks and ID fields. When the sector address read off the diskette matches with the sector address specified in the command, the FDC reads the sector’s data field and transfers the data to the FIFO. After completion of the read operation from the current sector, the sector address is incremented by one and the data from the next logical sector is read and output via the FIFO. This continuous read function is called “MultiSector Read Operation”. Upon receipt of TC, or an implied TC (FIFO overrun/underrun), the FDC stops sending data but will continue to read data from the current sector, check the CRC bytes, and at the end of the sector, terminate the Read Data Command. N determines the number of bytes per sector (see Table 34 below). If N is set to zero, the sector size is set to 128. The DTL value determines the number of bytes to be transferred. If DTL is less than 128, the FDC transfers the specified number of bytes to the host. For reads, it continues to read the entire 128-byte sector and checks for CRC errors. For writes, it completes the 128-byte sector by filling in zeros. If N is not set to 00 Hex, DTL should be set to FF Hex and has no impact on the number of bytes transferred. It is the user’s SMSC DS – FDC37N869 Page 46 Rev. 11/09/2000 N 00 01 02 03 .. 07 Table 34 - Sector Sizes SECTOR SIZE 128 bytes 256 bytes 512 bytes 1024 bytes ... 16 Kbytes The amount of data which can be handled with a single command to the FDC depends upon MT (multi-track) and N (number of bytes/sector). The Multi-Track function (MT) allows the FDC to read data from both sides of the diskette. For a particular cylinder, data will be transferred starting at Sector 1, Side 0 and completing the last sector of the same track at Side 1. If the host terminates a read or write operation in the FDC, the ID information in the result phase is dependent upon the state of the MT bit and EOT byte. Refer to Table 38. At the completion of the Read Data command, the head is not unloaded until after the Head Unload Time Interval (specified in the Specify command) has elapsed. If the host issues another command before the head unloads, then the head settling time may be saved between subsequent reads. If the FDC detects a pulse on the nINDEX pin twice without finding the specified sector (meaning that the diskette’s index hole passes through index detect logic in the drive twice), the FDC sets the IC code in Status Register 0 to “01” indicating abnormal termination, sets the ND bit in Status Register 1 to “1” indicating a sector not found, and terminates the Read Data Command. After reading the ID and Data Fields in each sector, the FDC checks the CRC bytes. If a CRC error occurs in the ID or data field, the FDC sets the IC code in Status Register 0 to “01” indicating abnormal termination, sets the DE bit flag in Status Register 1 to “1”, sets the DD bit in Status Register 2 to “1” if CRC is incorrect in the ID field, and terminates the Read Data Command. Table 36 describes the effect of the SK bit on the Read Data command execution and results. Except where noted in Table 36, the C or R value of the sector address is automatically incremented (see Table 38). MT 0 1 0 1 0 1 N 1 1 2 2 3 3 Table 35 - Affects of MT and N Bits MAXIMUM TRANSFER FINAL SECTOR READ FROM CAPACITY DISK 256 x 26 = 6,656 26 at side 0 or 1 256 x 52 = 13,312 26 at side 1 512 x 15 = 7,680 15 at side 0 or 1 512 x 30 = 15,360 15 at side 1 1024 x 8 = 8,192 8 at side 0 or 1 1024 x 16 = 16,384 16 at side 1 SK BIT VALUE 0 0 1 1 Table 36 - Skip Bit vs. Read Data Command DATA ADDRESS MARK TYPE ENCOUNTERED RESULTS SECTOR CM BIT OF READ? ST2 SET? DESCRIPTION OF RESULTS Normal Data Yes No Normal termination Address not incremented Deleted Data Yes Yes Next sector not searched for Normal Data Deleted Data Yes No No Yes Normal termination Normal termination. Sector not read (“skipped”) SMSC DS – FDC37N869 Page 47 Rev. 11/09/2000 Read Deleted Data This command is the same as the Read Data command, only it operates on sectors that contain a Deleted Data Address Mark at the beginning of a Data Field. Table 37 describes the effect of the SK bit on the Read Deleted Data command execution and results. Except where noted in Table 37 the C or R value of the sector address is automatically incremented (see Table 38). Table 37 - Skip Bit vs. Read Deleted Data Command DATA ADDRESS MARK TYPE RESULTS ENCOUNTERED SK BIT VALUE SECTOR CM BIT OF DESCRIPTION OF READ? ST2 SET? RESULTS 0 Normal Data Yes Yes Address not incremented. Next sector not searched for. Normal termination. Normal termination. Sector not read (“skipped”). Normal termination. 0 1 Deleted Data Normal Data Yes No No Yes 1 Deleted Data Yes No Read A Track This command is similar to the Read Data command except that the entire data field is read continuously from each of the sectors of a track. Immediately after encountering a pulse on the nINDEX pin, the FDC starts to read all data fields on the track as continuous blocks of data without regard to logical sector numbers. If the FDC finds an error in the ID or DATA CRC check bytes, it continues to read data from the track and sets the appropriate error bits at the end of the command. The FDC compares the ID information read from each sector with the specified value in the command and sets the ND flag of Status Register 1 to a “1” if there is no comparison. Multi-track or skip operations are not allowed with this command. The MT and SK bits (bits D7 and D5 of the first command byte respectively) should always be set to “0”. This command terminates when the EOT specified number of sectors has not been read. If the FDC does not find an ID Address Mark on the diskette after the second occurrence of a pulse on the IDX pin, then it sets the IC code in Status Register 0 to “01” (abnormal termination), sets the MA bit in Status Register 1 to “1”, and terminates the command. SMSC DS – FDC37N869 Page 48 Rev. 11/09/2000 MT HEAD Table 38 - Result Phase Table FINAL SECTOR TRANSFERRED TO HOST ID INFORMATION AT RESULT PHASE C H R N Less than EOT NC NC R+1 NC Equal to EOT Less than EOT C+1 NC C+1 NC NC NC C+1 NC NC NC NC LSB NC LSB 01 R+1 01 R+1 01 R+1 01 NC NC NC NC NC NC NC 0 0 1 Equal to EOT Less than EOT 1 0 Equal to EOT Less than EOT 1 Equal to EOT NC: No Change, the same value as the one at the beginning of command execution. LSB: Least Significant Bit, the LSB of H is complemented. Write Data After the Write Data command has been issued, the FDC loads the head (if it is in the unloaded state), waits the specified head load time if unloaded (defined in the Specify command), and begins reading ID fields. When the sector address read from the diskette matches the sector address specified in the command, the FDC reads the data from the host via the FIFO and writes it to the sector’s data field. After writing data into the current sector, the FDC computes the CRC value and writes it into the CRC field at the end of the sector transfer. The Sector Number stored in “R” is incremented by one, and the FDC continues writing to the next data field. The FDC continues this “Multi-Sector Write Operation”. Upon receipt of a terminal count signal or if a FIFO over/under run occurs while a data field is being written, then the remainder of the data field is filled with zeros. The FDC reads the ID field of each sector and checks the CRC bytes. If it detects a CRC error in one of the ID fields, it sets the IC code in Status Register 0 to “01” (abnormal termination), sets the DE bit of Status Register 1 to “1”, and terminates the Write Data command. The Write Data command operates in much the same manner as the Read Data command. The following items are the same. Please refer to the Read Data Command for details: • Transfer Capacity • EN (End of Cylinder) bit • ND (No Data) bit • Head Load, Unload Time Interval • ID information when the host terminates the command • Definition of DTL when N = 0 and when N does not = 0 SMSC DS – FDC37N869 Page 49 Rev. 11/09/2000 Write Deleted Data This command is almost the same as the Write Data command except that a Deleted Data Address Mark is written at the beginning of the Data Field instead of the normal Data Address Mark. This command is typically used to mark a bad sector containing an error on the floppy disk. Verify The Verify command is used to verify the data stored on a disk. This command acts exactly like a Read Data command except that no data is transferred to the host. Data is read from the disk and CRC is computed and checked against the previously-stored value. Because data is not transferred to the host, TC (pin 25) cannot be used to terminate this command. By setting the EC bit to “1”, an implicit TC will be issued to the FDC. This implicit TC will occur when the SC value has decremented to 0 (an SC value of 0 will verify 256 sectors). This command can also be terminated by setting the EC bit to “0” and the EOT value equal to the final sector to be checked. If EC is set to “0”, DTL/SC should be programmed to 0FFH. Refer to Table 38 and Table 39 for information concerning the values of MT and EC versus SC and EOT value. Definitions: # Sectors Per Side = Number of formatted sectors per each side of the disk. # Sectors Remaining = Number of formatted sectors left which can be read, including side 1 of the disk if MT is set to “1”. Table 39 - Verify Command Result Phase Table SC/EOT VALUE TERMINATION RESULT SC = DTL EOT £ # Sectors Per Side SC = DTL EOT > # Sectors Per Side SC £ # Sectors Remaining AND EOT £ # Sectors Per Side SC > # Sectors Remaining OR EOT > # Sectors Per Side SC = DTL EOT £ # Sectors Per Side SC = DTL EOT > # Sectors Per Side SC £ # Sectors Remaining AND EOT £ # Sectors Per Side SC > # Sectors Remaining OR EOT > # Sectors Per Side Success Termination Result Phase Valid Unsuccessful Termination Result Phase Invalid Successful Termination Result Phase Valid Unsuccessful Termination Result Phase Invalid Successful Termination Result Phase Valid Unsuccessful Termination Result Phase Invalid Successful Termination Result Phase Valid Unsuccessful Termination Result Phase Invalid MT 0 0 0 0 1 1 1 1 EC 0 0 1 1 0 0 1 1 Note: If MT is set to “1” and the SC value is greater than the number of remaining formatted sectors on Side 0, verifying will continue on Side 1 of the disk. SMSC DS – FDC37N869 Page 50 Rev. 11/09/2000 Format A Track The Format command allows an entire track to be formatted. After a pulse from the IDX pin is detected, the FDC starts writing data on the disk including gaps, address marks, ID fields, and data fields per the IBM System 34 or 3740 format (MFM or FM respectively). The particular values that will be written to the gap and data field are controlled by the values programmed into N, SC, GPL, and D which are specified by the host during the command phase. The data field of the sector is filled with the data byte specified by D. The ID field for each sector is supplied by the host; that is, four data bytes per sector are needed by the FDC for C, H, R, and N (cylinder, head, sector number and sector size respectively). After formatting each sector, the host must send new values for C, H, R and N to the FDC for the next sector on the track. The R value (sector number) is the only value that must be changed by the host after each sector is formatted. This allows the disk to be formatted with nonsequential sector addresses (interleaving). This incrementing and formatting continues for the whole track until the FDC encounters a pulse on the IDX pin again and it terminates the command. Table 41 contains typical values for gap fields which are dependent upon the size of the sector and the number of sectors on each track. Actual values can vary due to drive electronics. Table 40 - FORMAT FIELDS SYSTEM 34 (DOUBLE DENSITY) FORMAT DATA GAP4 SYN IAM GAP SYN IDAM C H S N C GAP SYN AM C DATA R GAP3 GAP a C 1 C YDEOR 2 C 80x 12x 50x 12x L C C 22x 12x C 4b 4E 00 4E 00 4E 00 3x FC 3x FE 3x FB C A1 A1 F8 2 SYSTEM 3740 (SINGLE DENSITY) FORMAT DATA IAM GAP SYN IDAM C H S N C GAP SYN AM C DATA R GAP3 GAP 1 C YDEOR 2 C 26x 6x L C C 11x 6x C 4b FF 00 FF 00 FC FE FB or F8 PERPENDICULAR FORMAT GAP4 SYN a C 80x 12x 4E 00 DATA IAM GAP SYN IDAM C H S N C GAP SYN AM C DATA R GAP3 GAP 1 C YDEOR 2 C 50x 12x L C C 41x 12x C 4b 4E 00 4E 00 3x FC 3x FE 3x FB C A1 A1 F8 2 GAP4 SYN a C 40x 6x FF 00 SMSC DS – FDC37N869 Page 51 Rev. 11/09/2000 FORMAT FM 5.25” Drives Table 41 - Typical Values for Formatting SECTOR SIZE N SC 128 00 12 128 00 10 512 02 08 1024 03 04 2048 04 02 4096 05 01 ... ... 256 256 512* 1024 2048 4096 ... 128 256 512 256 512** 1024 01 01 02 03 04 05 ... 0 1 2 1 2 3 12 10 09 04 02 01 0F 09 05 0F 09 05 GPL1 07 10 18 46 C8 C8 0A 20 2A 80 C8 C8 07 0F 1B 0E 1B 35 GPL2 09 19 30 87 FF FF 0C 32 50 F0 FF FF 1B 2A 3A 36 54 74 MFM 3.5” Drives FM MFM GPL1 = suggested GPL values in Read and Write commands to avoid splice point between data field and ID field of contiguous sections. GPL2 = suggested GPL value in Format A Track command. *PC/AT values (typical) **PS/2 values (typical). Applies with 1.0 MB and 2.0 MB drives. Note: All values except sector size are in hex. Control Commands Control commands differ from the other commands in that no data transfer takes place. Three commands generate an interrupt when complete: Read ID, Recalibrate, and Seek. The other control commands do not generate an interrupt. Read ID The Read ID command is used to find the present position of the recording heads. The FDC stores the values from the first ID field it is able to read into its registers. If the FDC does not find an ID address mark on the diskette after the second occurrence of a pulse on the nINDEX pin, it then sets the IC code in Status Register 0 to “01” (abnormal termination), sets the MA bit in Status Register 1 to “1”, and terminates the command. The following commands will generate an interrupt upon completion. They do not return any result bytes. It is highly recommended that control commands be followed by the Sense Interrupt Status command. Otherwise, valuable interrupt status information will be lost. Recalibrate This command causes the read/write head within the FDC to retract to the track 0 position. The FDC clears the contents of the PCN counter and checks the status of the nTR0 pin from the FDD. As long as the nTR0 pin is low, the DIR pin remains 0 and step pulses are issued. When the nTR0 pin goes high, the SE bit in Status Register 0 is set to “1” and the command is terminated. If the nTR0 pin is still low after 79 step pulses have been issued, the FDC sets the SE and the EC bits of Status Register 0 to “1” and terminates the command. Disks capable of handling more than 80 tracks per side may require more than one Recalibrate command to return the head back to physical Track 0. The Recalibrate command does not have a result phase. The Sense Interrupt Status command must be issued after the Recalibrate command to effectively terminate it and to provide verification of the SMSC DS – FDC37N869 Page 52 Rev. 11/09/2000 head position (PCN). During the command phase of the recalibrate operation, the FDC is in the BUSY state, but during the execution phase it is in a NON-BUSY state. At this time, another Recalibrate command may be issued, and in this manner parallel Recalibrate operations may be done on up to four drives at once. Upon power up, the software must issue a Recalibrate command to properly initialize all drives and the controller. Seek The read/write head within the drive is moved from track to track under the control of the Seek command. The FDC compares the PCN, which is the current head position, with the NCN and performs the following operation if there is a difference: PCN < NCN: Direction signal to drive set to “1” (step in) and issues step pulses. PCN > NCN: Direction signal to drive set to “0” (step out) and issues step pulses. The rate at which step pulses are issued is controlled by SRT (Stepping Rate Time) in the Specify command. After each step pulse is issued, NCN is compared against PCN, and when NCN = PCN the SE bit in Status Register 0 is set to “1” and the command is terminated. During the command phase of the seek or recalibrate operation, the FDC is in the BUSY state, but during the execution phase it is in the NON-BUSY state. At this time, another Seek or Recalibrate command may be issued, and in this manner, parallel seek operations may be done on up to four drives at once. Note that if implied seek is not enabled, the read and write commands should be preceded by: 1) Seek command - Step to the proper track 2) Sense Interrupt Status command - Terminate the Seek command 3) Read ID - Verify head is on proper track 4) Issue Read/Write command. The Seek command does not have a result phase. Therefore, it is highly recommended that the Sense Interrupt Status command be issued after the Seek command to terminate it and to provide verification of the head position (PCN). The H bit (Head Address) in ST0 will always return to a “0”. When exiting POWERDOWN mode, the FDC clears the PCN value and the status information to zero. Prior to issuing the POWERDOWN command, it is highly recommended that the user service all pending interrupts through the Sense Interrupt Status command. Sense Interrupt Status An interrupt signal on FINT pin is generated by the FDC for one of the following reasons: 1) Upon entering the Result Phase of: a. Read Data command b. Read A Track command c. Read ID command d. Read Deleted Data command e. Write Data command f. Format A Track command g. Write Deleted Data command h. Verify command 2) End of Seek, Relative Seek, or Recalibrate command 3) FDC requires a data transfer during the execution phase in the non-DMA mode The Sense Interrupt Status command resets the interrupt signal and, via the IC code and SE bit of Status Register 0, identifies the cause of the interrupt. SE 0 1 1 Table 42 - Interrupt Identification IC INTERRUPT DUE TO 11 Polling 00 Normal termination of Seek or Recalibrate command 01 Abnormal termination of Seek or Recalibrate command SMSC DS – FDC37N869 Page 53 Rev. 11/09/2000 The Seek, Relative Seek, and Recalibrate commands have no result phase. The Sense Interrupt Status command must be issued immediately after these commands to terminate them and to provide verification of the head position (PCN). The H (Head Address) bit in ST0 will always return a “0”. If a Sense Interrupt Status is not issued, the drive will continue to be BUSY and may affect the operation of the next command. Sense Drive Status Sense Drive Status obtains drive status information. It has not execution phase and goes directly to the result phase from the command phase. Status Register 3 contains the drive status information. Specify The Specify command sets the initial values for each of the three internal times. The HUT (Head Unload Time) defines the time from the end of the execution phase of one of the read/write commands to the head unload state. The SRT (Step Rate Time) defines the time interval between adjacent step pulses. Note that the spacing between the first and second step pulses may be shorter than the remaining step pulses. The HLT (Head Load Time) defines the time between when the Head Load signal goes high and the read/write operation starts. The values change with the data rate speed selection and are documented in Table 43. The values are the same for MFM and FM. Table 43 - Drive Control Delays (ms) HUT 2M 0 1 .. E F 64 4 .. 56 60 1M 128 8 .. 112 120 500K 256 16 .. 224 240 300K 426 26.7 .. 373 400 250K 512 32 .. 448 480 2M 4 3.75 .. 0.5 0.25 HLT 2M 00 01 02 .. 7F 7F 64 0.5 1 .. 63 63.5 1M 128 1 2 .. 126 127 500K 256 2 4 .. 252 254 300K 426 3.3 6.7 .. 420 423 250K 512 4 8 . 504 508 1M 8 7.5 .. 1 0.5 SRT 500K 16 15 .. 2 1 300K 26.7 25 .. 3.33 1.67 250K 32 30 .. 4 2 The choice of DMA or non-DMA operations is made by the ND bit. When this bit is “1”, the non-DMA mode is selected, and when ND is “0”, the DMA mode is selected. In DMA mode, data transfers are signaled by the FDRQ pin. Non-DMA mode uses the RQM bit and the FINT pin to signal data transfers. Configure The Configure command is issued to select the special features of the FDC. A Configure command need not be issued if the default values of the FDC meet the system requirements. Configure Default Values: EIS - No Implied Seeks EFIFO - FIFO Disabled POLL - Polling Enabled FIFOTHR - FIFO Threshold Set to 1 Byte PRETRK - Pre-Compensation Set to Track 0 EIS - Enable Implied Seek. When set to “1”, the FDC will perform a Seek operation before executing a read or write command. Defaults to no implied seek. EFIFO - A “1” disables the FIFO (default). This means data transfers are asked for on a byte-by-byte basis. Defaults to “1”, FIFO disabled. The threshold defaults to “1”. SMSC DS – FDC37N869 Page 54 Rev. 11/09/2000 POLL - Disable polling of the drives. Defaults to “0”, polling enabled. When enabled, a single interrupt is generated after a reset. No polling is performed while the drive head is loaded and the head unload delay has not expired. FIFOTHR - The FIFO threshold in the execution phase of read or write commands. This is programmable from 1 to 16 bytes. Defaults to one byte. A “00” selects one byte; “0F” selects 16 bytes. PRETRK - Pre-Compensation Start Track Number. Programmable from track 0 to 255. Defaults to track 0. A “00” selects track 0; “FF” selects track 255. Version The Version command checks to see if the controller is an enhanced type or the older type (765A). A value of 90 H is returned as the result byte. Relative Seek The command is coded the same as for Seek, except for the MSB of the first byte and the DIR bit. Table 44 - Head Step Direction Control DIR ACTION 0 Step Head Out 1 Step Head In RCN - Relative Cylinder Number that determines how many tracks to step the head in or out from the current track number. The Relative Seek command differs from the Seek command in that it steps the head the absolute number of tracks specified in the command instead of making a comparison against an internal register. The Seek command is good for drives that support a maximum of 256 tracks. Relative Seeks cannot be overlapped with other Relative Seeks. Only one Relative Seek can be active at a time. Relative Seeks may be overlapped with Seeks and Recalibrates. Bit 4 of Status Register 0 (EC) will be set if Relative Seek attempts to step outward beyond Track 0. As an example, assume that a floppy drive has 300 useable tracks. The host needs to read track 300 and the head is on any track (0-255). If a Seek command is issued, the head will stop at track 255. If a Relative Seek command is issued, the FDC will move the head the specified number of tracks, regardless of the internal cylinder position register (but will increment the register). If the head was on track 40 (d), the maximum track that the FDC could position the head on using Relative Seek will be 295 (D), the initial track + 255 (D). The maximum count that the head can be moved with a single Relative Seek command is 255 (D). The internal register, PCN, will overflow as the cylinder number crosses track 255 and will contain 39 (D). The resulting PCN value is thus (RCN + PCN) mod 256. Functionally, the FDC starts counting from 0 again as the track number goes above 255 (D). It is the user’s responsibility to compensate FDC functions (precompensation track number) when accessing tracks greater than 255. The FDC does not keep track that it is working in an “extended track area” (greater than 255). Any command issued will use the current PCN value except for the Recalibrate command, which only looks for the TRACK0 signal. Recalibrate will return an error if the head is farther than 79 due to its limitation of issuing a maximum of 80 step pulses. The user simply needs to issue a second Recalibrate command. The Seek command and implied seeks will function correctly within the 44 (D) track (299-255) area of the “extended track area”. It is the user’s responsibility not to issue a new track position that will exceed the maximum track that is present in the extended area. To return to the standard floppy range (0255) of tracks, a Relative Seek should be issued to cross the track 255 boundary. A Relative Seek can be used instead of the normal Seek, but the host is required to calculate the difference between the current head location and the new (target) head location. This may require the host to issue a Read ID command to ensure that the head is physically on the track that software assumes it to be. Different FDC commands will return different cylinder results which may be difficult to keep track of with software without the Read ID command. SMSC DS – FDC37N869 Page 55 Rev. 11/09/2000 Perpendicular Mode The Perpendicular Mode command should be issued prior to executing Read/Write/Format commands that access a disk drive with perpendicular recording capability. With this command, the length of the Gap2 field and VCO enable timing can be altered to accommodate the unique requirements of these drives. Table 45 describes the affects of the WGATE and GAP bits for the Perpendicular Mode command. Upon a reset, the FDC will default to the conventional mode (WGATE = 0, GAP = 0). Selection of the 500 Kbps and 1 Mbps perpendicular modes is independent of the actual data rate selected in the Data Rate Select Register. The user must ensure that these two data rates remain consistent. The Gap2 and VCO timing requirements for perpendicular recording type drives are dictated by the design of the read/write head. In the design of this head, a pre-erase head precedes the normal read/write head by a distance of 200 micrometers. This works out to about 38 bytes at a 1 Mbps recording density. Whenever the write head is enabled by the Write Gate signal, the pre-erase head is also activated at the same time. Thus, when the write head is initially turned on, flux transitions recorded on the media for the first 38 bytes will not be preconditioned with the pre-erase head since it has not yet been activated. To accommodate this head activation and deactivation time, the Gap2 field is expanded to a length of 41 bytes. The format field shown on page 61 illustrates the change in the Gap2 field size for the perpendicular format. On the read back by the FDC, the controller must begin synchronization at the beginning of the sync field. For the conventional mode, the internal PLL VCO is enabled (VCOEN) approximately 24 bytes from the start of the Gap2 field. But, when the controller operates in the 1 Mbps perpendicular mode (WGATE = 1, GAP = 1), VCOEN goes active after 43 bytes to accommodate the increased Gap2 field size. For both cases, and approximate two-byte cushion is maintained from the beginning of the sync field for the purposes of avoiding write splices in the presence of motor speed variation. For the Write Data case, the FDC activates Write Gate at the beginning of the sync field under the conventional mode. The controller then writes a new sync field, data address mark, data field, and CRC as shown in Figure 4. With the pre-erase head of the perpendicular drive, the write head must be activated in the Gap2 field to insure a proper write of the new sync field. For the 1 Mbps perpendicular mode (WGATE = 1, GAP = 1), 38 bytes will be written in the Gap2 space. Since the bit density is proportional to the data rate, 19 bytes will be written in the Gap2 field for the 500 Kbps perpendicular mode (WGATE = 1, GAP =0). It should be noted that none of the alterations in Gap2 size, VCO timing, or Write Gate timing affect normal program flow. The information provided here is just for background purposes and is not needed for normal operation. Once the Perpendicular Mode command is invoked, FDC software behavior from the user standpoint is unchanged. The perpendicular mode command is enhanced to allow specific drives to be designated Perpendicular recording drives. This enhancement allows data transfers between Conventional and Perpendicular drives without having to issue Perpendicular mode commands between the accesses of the different drive types, nor having to change write pre-compensation values. When both GAP and WGATE bits of the PERPENDICULAR MODE COMMAND are both programmed to “0” (Conventional mode), then D0, D1, D2, D3, and D4 can be programmed independently to “1” for that drive to be set automatically to Perpendicular mode. In this mode the following set of conditions also apply: 1. 2. 3. The GAP2 written to a perpendicular drive during a write operation will depend upon the programmed data rate. The write pre-compensation given to a perpendicular mode drive will be 0ns. For D0-D3 programmed to “0” for conventional mode drives any data written will be at the currently programmed write pre-compensation. Note: Bits D0-D3 can only be overwritten when OW is programmed as a “1”. If either GAP or WGATE is a “1” then D0-D3 are ignored. SMSC DS – FDC37N869 Page 56 Rev. 11/09/2000 Software and hardware resets have the following effect on the PERPENDICULAR MODE COMMAND: 1. “Software” resets (via the DOR or DSR registers) will only clear GAP and WGATE bits to “0”. D0-D3 are unaffected and retain their previous value. 2. “Hardware” resets will clear all bits (GAP, WGATE and D0-D3) to “0”, i.e. all conventional mode. Table 45 - Affects of WGATE and GAP Bits LENGTH OF GAP2 PORTION OF GAP 2 WRITTEN BY MODE FORMAT FIELD WRITE DATA OPERATION Conventional Perpendicular (500 Kbps) Reserved (Conventional) Perpendicular (1 Mbps) 22 Bytes 22 Bytes 22 Bytes 41 Bytes 0 Bytes 19 Bytes 0 Bytes 38 Bytes WGATE 0 0 1 1 GAP 0 1 0 1 LOCK In order to protect systems with long DMA latencies against older application software that can disable the FIFO the LOCK Command has been added. This command should only be used by the FDC routines, and application software should refrain from using it. If an application calls for the FIFO to be disabled then the CONFIGURE command should be used. The LOCK command defines whether the EFIFO, FIFOTHR, and PRETRK parameters of the CONFIGURE command can be RESET by the DOR and DSR registers. When the LOCK bit is set to logic “1” all subsequent “software RESETS by the DOR and DSR registers will not change the previously set parameters to their default values. All “hardware” RESET from the RESET pin will set the LOCK bit to logic “0” and return the EFIFO, FIFOTHR, and PRETRK to their default values. A status byte is returned immediately after issuing a LOCK command. This byte reflects the value of the LOCK bit set by the command byte. ENHANCED DUMPREG The DUMPREG command is designed to support system run-time diagnostics and application software development and debug. To accommodate the LOCK command and the enhanced PERPENDICULAR MODE command the eighth byte of the DUMPREG command has been modified to contain the additional data from these two commands. COMPATIBILITY The FDC37N869 was designed with software compatibility in mind. It is a fully backwards-compatible solution with the older generation 765A/B disk controllers. The FDC also implements on-board registers for compatibility with the PS/2, as well as PC/AT and PC/XT, floppy disk controller subsystems. After a hardware reset of the FDC, all registers, functions and enhancements default to a PC/AT, PS/2 or PS/2 Model 30 compatible operating mode, depending on how the IDENT and MFM bits are configured by the system BIOS. Parallel Port Floppy Disk Controller In this mode, the Floppy Disk Control signals are available on the parallel port pins. When this mode is selected, the parallel port is not available. There are two modes of operation, PPFD1 and PPFD2. These modes can be selected in Configuration Register 4. PPFD1 has only drive 1 on the parallel port pins; PPFD2 has drive 0 and 1 on the parallel port pins. PPFD1: Drive 0 is on the FDC pins Drive 1 is on the Parallel port pins PPFD2: Drive 0 is on the Parallel port pins Drive 1 is on the Parallel port pins When the PPFDC is selected the following pins are set as follows: 1. nDACK: Assigned to the parallel port device during configuration. 2. PDRQ (assigned to the parallel port): not ECP = high-Z, ECP & dmaEn = 0, ECP & not dmaEn = high-Z SMSC DS – FDC37N869 Page 57 Rev. 11/09/2000 3. IRQ assigned to the parallel port: not active, this is hi-Z or Low depending on settings. The following parallel port pins are read as follows by a read of the parallel port register: 1. Data Register (read) = last Data Register (write) 2. Control Register are read as “cable not connected” STROBE, AUTOFD and SLC = 0 and nINIT = 1; 3. Status Register reads: nBUSY = 0, PE = 0, SLCT = 0, nACK = 1, nERR = 1. The following FDC pins are all in the high impedance state when the PPFDC is actually selected by the drive select register: 1. nWDATA, DENSEL, nHDSEL, nWGATE, nDIR, nSTEP, nDS1, nDS0, nMTRO, nMTR1. 2. If PPFDx is selected, then the parallel port can not be used as a parallel port until “Normal” mode is selected. The FDC signals are muxed onto the Parallel Port pins as shown in Table 46 . Table 46 - FDC Parallel Port Pins CONNECTOR PIN # CHIP PIN # SPP MODE PIN DIRECTION FDC MODE 1 75 nSTB I/O (nDS0) 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Note1: 69 68 67 66 64 63 62 61 60 59 58 57 74 73 72 71 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 nACK BUSY PE SLCT nAFD nERR nINIT nSLIN I/O I/O I/O I/O I/O I/O I/O I/O I I I I I/O I I/O I/O nDS1 nMTR1 nWDATA nWGATE nDENSEL nHDSEL nDIR nSTEP 0 0 0 0 0 0 0 0 (nMTR0) I/(0) 1 nINDEX nTRK0 nWP nRDATA nDSKCHG PIN DIRECTION I/(0)1 I I I I I These pins are outputs in mode PPFD2. Inputs in mode PPFD1 For ACPI compliance the FDD pins that are multiplexed onto the Parallel Port must function independently of the state of the Parallel Port controller. For example, if the FDC is enabled onto the Parallel Port the multiplexed FDD Interface should function normally regardless of the Parallel Port Power control CR01.2. Table 47 illustrates this functionality. PARALLEL PORT POWER CR01.2 1 0 X Table 47 - Parallel Port FDD Control PARALLEL PORT FDC PARALLEL PORT CONTROL FDC STATE CR04.3 CR04.2 0 0 OFF 0 0 OFF 1 X ON X 1 PARALLEL PORT STATE ON OFF OFF1 SMSC DS – FDC37N869 Page 58 Rev. 11/09/2000 Note1: The Parallel Port Control register reads as “Cable Not Connected” when the PP FDC is enabled; i.e., STROBE = AUTOFD = SLC = 0 and nINIT = 1 SERIAL PORT (UART) The FDC37N869 incorporates two full function UARTs. They are compatible with the NS16450, the 16450 ACE registers and the NS16550A. The UARTs perform serial-to-parallel conversion on received characters and parallel-to-serial conversion on transmit characters. The data rates are independently programmable from 115.2K baud down to 50 baud. The character options are programmable for 1 start; 1, 1.5 or 2 stop bits; even, odd, sticky or no parity; and prioritized interrupts. The UARTs each contain a programmable baud rate generator that is capable of dividing the input clock or crystal by a number from 1 to 65535. The UARTs are also capable of supporting the MIDI data rate. Refer to the FDC37N869 Configuration Registers for information on disabling, powering down and changing the base address of the UARTs. The interrupt from a UART is enabled by programming OUT2 of that UART to a logic “1”. When OUT2 is a logic “0” the UART Interrupt is disabled. Register Description Addressing of the accessible registers of the Serial Port is shown below (Table 48). The base addresses of the serial ports are defined by the configuration registers (see section CONFIGURATION on page 101. The Serial Port registers are located at sequentially increasing addresses above these base addresses. The FDC37N869 contains two serial ports, each of which contain a register set as described below. Table 48 - Addressing the Serial Port DLAB1 A2 A1 A0 REGISTER NAME 0 0 0 0 Receive Buffer (read) 0 0 0 0 Transmit Buffer (write) 0 0 0 1 Interrupt Enable (read/write) X 0 1 0 Interrupt Identification (read) X 0 1 0 FIFO Control (write) X 0 1 1 Line Control (read/write) X 1 0 0 Modem Control (read/write) X 1 0 1 Line Status (read/write) X 1 1 0 Modem Status (read/write) X 1 1 1 Scratchpad (read/write) 1 0 0 0 Divisor LSB (read/write) 1 0 0 1 Divisor MSB (read/write) Note1: DLAB is Bit 7 of the Line Control Register RECEIVE BUFFER REGISTER (RB) The Receive Buffer register (Address Offset = 0H, DLAB = 0, READ ONLY) holds the received incoming data byte. Bit 0 is the least significant bit, which is transmitted and received first. Received data is double buffered; this uses an additional shift register to receive the serial data stream and convert it to a parallel 8 bit character which is transferred to the Receive Buffer register. The shift register is not accessible. TRANSMIT BUFFER REGISTER (TB) The Transmit Buffer register (Address Offset = 0H, DLAB = 0, WRITE ONLY) contains the data byte to be transmitted. The transmit buffer is double buffered, utilizing an additional shift register (not accessible) to convert the 8 bit data character to a serial format. This shift register is loaded from the Transmit Buffer when the transmission of the previous byte is complete. INTERRUPT ENABLE REGISTER (IER) The lower four bits of the Interrupt Enable register (Address Offset = 1H, DLAB = 0, READ/WRITE) control the enables of the five interrupt sources of the Serial Port interrupt. It is possible to totally disable the interrupt system by resetting bits 0 through 3 of this register. Similarly, by setting the appropriate bits of this register to a high selected interrupts can be enabled. Disabling the interrupt system inhibits the Interrupt Identification Register and SMSC DS – FDC37N869 Page 59 Rev. 11/09/2000 disables any Serial Port interrupt out of the FDC37N869. All other system functions operate in their normal manner, including the Line Status and MODEM Status Registers. The contents of the Interrupt Enable Register are described below. ERDAI, Bit 0 The ERDAI bit enables the Received Data Available Interrupt (and time-out interrupts in the FIFO mode) when set to logic “1”. ETHREI, Bit 1 The ETHREI bit enables the Transmitter Holding Register Empty Interrupt when set to logic “1”. ELSI, Bit 2 The ELSI bit enables the Received Line Status Interrupt when set to logic “1”. The error sources causing the interrupt are Overrun, Parity, Framing and Break. The Line Status Register must be read to determine the source. EMSI, Bit 3 The EMSI bit enables the MODEM Status Interrupt when set to logic “1”. An MSI is caused when one of the Modem Status Register bits changes state. Reserved, Bits 4 - 7 Bits 4 to 7 are RESERVED. Reserved bits cannot be written and return 0 when read. INTERRUPT IDENTIFICATION REGISTER (IIR) By accessing the Interrupt Identification register (Address Offset = 2H, DLAB = X, READ), the host CPU can determine the highest priority interrupt and its source. Four levels of interrupt priority exist. They are in descending order of priority: 1. Receiver Line Status (highest priority) 2. Received Data Ready 3. Transmitter Holding Register Empty 4. MODEM Status (lowest priority) Information indicating that a prioritized interrupt is pending and the source of that interrupt is stored in the Interrupt Identification Register (refer to the Interrupt Control Table, Table 49). When the CPU accesses the IIR, the Serial Port freezes all interrupts and indicates the highest priority pending interrupt to the CPU. During this CPU access, even if the Serial Port records new interrupts, the current indication does not change until access is completed. Interrupt Pending, Bit 0 The Interrupt Pending bit can be used in either a hardwired prioritized or polled environment to indicate whether an interrupt is pending. When bit 0 is a logic “0”, an interrupt is pending and the contents of the IIR may be used as a pointer to the appropriate internal service routine. When bit 0 is a logic “1”, no interrupt is pending. Interrupt ID, Bits 1 - 2 The Interrupt ID bits of the IIR are used to identify the highest priority interrupt pending as indicated by the Interrupt Control Table ( Table 49). Time-Out, Bit 3 In non-FIFO mode, the Time-Out bit is a logic “0”. In FIFO mode the Time-Out bit is set along with bit 2 when a time-out interrupt is pending. SMSC DS – FDC37N869 Page 60 Rev. 11/09/2000 Reserved, Bits 4 - 5 Bits 4 to 5 are RESERVED. Reserved bits cannot be written and return 0 when read. FIFOs Enabled, Bits 6 - 7 The FIFOs Enabled bits are set when the FIFO CONTROL Register bit 0 equals 1. Table 49 - Interrupt Control FIFO MODE ONLY BIT 3 0 0 INTERRUPT IDENTIFICATION REGISTER BIT 2 BIT 1 BIT 0 0 0 1 1 1 0 INTERRUPT SET AND RESET FUNCTIONS PRIORITY LEVEL Highest INTERRUPT TYPE None Receiver Line Status INTERRUPT SOURCE None Overrun Error, Parity Error, Framing Error or Break Interrupt Receiver Data Available INTERRUPT RESET CONTROL Reading the Line Status Register 0 1 0 0 Second Received Data Available Character Time-out Indication 1 1 0 0 Second 0 0 1 0 Third Transmitter Holding Register Empty 0 0 0 0 Fourth MODEM Status Read Receiver Buffer or the FIFO drops below the trigger level. No Characters Reading the Have Been Receiver Buffer Removed Register From or Input to the RCVR FIFO during the last 4 Character times and there is at least 1 character in it during this time Transmitter Reading the IIR Holding Register (if Source Register of Interrupt) or Empty Writing the Transmitter Holding Register Clear to Send Reading the or Data Set MODEM Status Ready or Ring Register Indicator or Data Carrier Detect SMSC DS – FDC37N869 Page 61 Rev. 11/09/2000 FIFO CONTROL REGISTER (FCR) The FIFO Control register (Address Offset = 2H, DLAB = X, WRITE) appears at the same location as the IIR. This register is used to enable and clear the FIFOs and set the RCVR FIFO trigger level. Note: DMA is not supported. FIFO Enable, Bit 0 Setting the FIFO Enable bit to a logic “1” enables both the XMIT and RCVR FIFOs. Clearing this bit to a logic “0” disables both the XMIT and RCVR FIFOs and clears all bytes from both FIFOs. When changing from FIFO Mode to non-FIFO (16450) mode, data is automatically cleared from the FIFOs. This bit must be a 1 when other bits in this register are written to or they will not be properly programmed. RCVR FIFO Reset, Bit 1 Setting the RCVR FIFO Reset bit to a logic “1” clears all bytes in the RCVR FIFO and resets its counter logic to 0. The shift register is not cleared. This bit is self-clearing. XMIT FIFO Reset, Bit 2 Setting the XMIT FIFO Reset bit to a logic “1” clears all bytes in the XMIT FIFO and resets its counter logic to 0. The shift register is not cleared. This bit is self-clearing. DMA Mode Select, Bit 3 Writing to the DMA Mode Select bit has no effect on the operation of the UART. The RXRDY and TXRDY pins are not available on this chip. Reserved, Bits 4 - 5 Bits 4 to 5 are RESERVED. Reserved bits cannot be written and return 0 when read. RCVR Trigger, Bits 6 - 7 The RCVR Trigger bits are used to set the trigger level for the RCVR FIFO interrupt (Table 50). Table 50 - RCVR Trigger Encoding RCVR RCVR FIFO Trigger Level TRIGGER (BYTES) Bit 7 Bit 6 0 0 1 0 1 4 1 0 8 1 1 14 SMSC DS – FDC37N869 Page 62 Rev. 11/09/2000 LINE CONTROL REGISTER (LCR) The Line Control register (Address Offset = 3H, DLAB = 0, READ/WRITE) contains the formatting information for the serial line. Word Length Select, Bits 0 - 1 The Word Length Select bits specify the number of bits in each transmitted or received serial character. Note: the Start, Stop and Parity bits are not included in the word length. The encoding of the Word Length bits is shown in Table 51. Table 51 - Word Length Encoding WORD LENGTH SELECT WORD LENGTH (Bits) Bit 1 Bit 0 0 0 5 0 1 6 1 0 7 1 1 8 Stop Bits, Bit 2 The Stop Bits bit specifies the number of stop bits in each transmitted or received serial character. Table 52 describes the Stop Bits encoding. Table 52 - STOP Bit Encoding STOP BITS WORD NUMBER OF (Bit 2) LENGTH STOP BITS 0 1 0 5 Bits 1.5 1 6 Bits 2 1 7 Bits 2 1 8 Bits 2 Note: The receiver ignores stop bits beyond the first, regardless of the number of stop bits used in transmitting. Parity Enable, Bit 3 When the Parity Enable bit is a logic “1” a parity bit is generated (transmit data) or checked (receive data) between the last data word bit and the first stop bit of the serial data. The parity bit is used to generate an even or odd number of 1s when the data word bits and the parity bit are summed. Even Parity Select, Bit 4 When the Even Parity Select (EPS) bit is a logic “0” and the Parity Enable is a logic “1”, an odd number of logic “1”’s is transmitted or checked in the data word and the parity bit. When the Parity Enable is a logic “1” and the EPS bit is a logic “1” an even number of bits is transmitted and checked. Stick Parity, Bit 5 When the Stick Parity bit is a logic “1” and the Parity Enable is a logic “1”, the parity bit is transmitted and then detected by the receiver in the opposite state indicated by the EPS bit. Set Break, Bit 6 When the Set Break Control bit is a logic “1”, the transmit data output (TXD) is forced to the Spacing or logic “0” state and remains there until reset by a low level bit 6, regardless of other transmitter activity. This feature enables the Serial Port to alert a terminal in a communications system. SMSC DS – FDC37N869 Page 63 Rev. 11/09/2000 DLAB, Bit 7 The Divisor Latch Access Bit must be set high (logic “1”) to access the Divisor Latches of the Baud Rate Generator during read or write operations. It must be set low (logic “0”) to access the Receiver Buffer Register, the Transmitter Holding Register, or the Interrupt Enable Register. MODEM CONTROL REGISTER (MCR) The Modem Control register (Address Offset = 4H, DLAB = X, READ/WRITE) manages the interface for the MODEM, data set, or device emulating a MODEM. Data Terminal Ready, Bit 0 The Data Terminal Ready bit controls the Data Terminal Ready (nDTR) output. When bit 0 is set to a logic “1”, the nDTR output is forced to a logic “0”. When bit 0 is a logic “0”, the nDTR output is forced to a logic “1”. Request To Send, Bit 1 The Request To Send bit controls the Request To Send (nRTS) output. . When bit 1 is set to a logic “1”, the nRTS output is forced to a logic “0”. When bit 1 is a logic “0”, the nRTS output is forced to a logic “1”. OUT1, Bit 2 The OUT1 bit controls the Output 1 (OUT1) bit. This bit does not have an output pin and can only be read or written by the CPU. OUT2, Bit 3 The OUT2 bit is used to enable the UART interrupt. When OUT2 is a logic “0”, the serial port interrupt output is forced to a high impedance state; i.e, disabled. When OUT2 is a logic “1”, the serial port interrupt outputs are enabled. Loop, Bit 4 The Loop bit provides the loopback feature for diagnostic testing of the Serial Port. When bit 4 is set to logic “1”, the following occurs: 1. The TXD is set to the Marking State (logic “1”). 2. The receiver Serial Input (RXD) is disconnected. 3. The output of the Transmitter Shift Register is “looped back” into the Receiver Shift Register input. 4. All MODEM Control inputs (nCTS, nDSR, nRI and nDCD) are disconnected. 5. The four MODEM Control outputs (nDTR, nRTS, OUT1 and OUT2) are internally connected to the four MODEM Control inputs (nDSR, nCTS, RI and DCD) respectively. 6. The Modem Control output pins are forced inactive. 7. Data that is transmitted is immediately received. The Loopback feature allows the processor to verify the transmit and receive data paths of the Serial Port. The receiver and the transmitter interrupts are fully operational in loopback mode. The MODEM Control Interrupts are also operational but the interrupts’ sources are now the lower four bits of the MODEM Control Register instead of the MODEM Control inputs. The interrupts are still controlled by the Interrupt Enable Register. Reserved, Bits 5 - 7 Bits 5 to 7 are RESERVED. Reserved bits cannot be written and return 0 when read. SMSC DS – FDC37N869 Page 64 Rev. 11/09/2000 LINE STATUS REGISTER (LSR) Address Offset = 5H, DLAB = X, READ/WRITE Data Ready, Bit 0 Data Ready (DR) is set to a logic “1” whenever a complete received data character has been transferred into the Receiver Buffer Register or the FIFO. DR is reset to a logic “0” by reading all of the data in the Receive Buffer Register or the FIFO. Overrun Error, Bit 1 The Overrun Error (OE) bit indicates that data in the Receiver Buffer Register was not read before the next character was transferred into the register, thereby destroying the previous character. In FIFO mode, an overrun error will occur only when the FIFO is full and the next character has been completely received in the shift register: the character in the shift register is overwritten but not transferred to the FIFO. The OE indicator is set to a logic “1” immediately upon detection of an overrun condition and reset whenever the Line Status Register is read. Parity Error, Bit 2 The Parity Error (PE) bit indicates that the received data character does not have the correct even or odd parity, as selected by the even parity select bit. The PE is set to a logic “1” upon detection of a parity error and is reset to a logic “0” whenever the Line Status Register is read. In the FIFO mode this error is associated with the particular character in the FIFO it applies to. This error is indicated when the associated character is at the top of the FIFO. Framing Error, Bit 3 The Framing Error (FE) bit indicates that the received character did not have a valid stop bit. Bit 3 is set to a logic “1” whenever the stop bit following the last data bit or parity bit is detected as a zero bit (Spacing level). The FE is reset to a logic “0” whenever the Line Status Register is read. In the FIFO mode this error is associated with the particular character in the FIFO it applies to. This error is indicated when the associated character is at the top of the FIFO. The Serial Port will try to resynchronize after a framing error. To do this, it assumes that the framing error was due to the next start bit, so it samples this ‘start’ bit twice and then takes in the ‘data’. Break Interrupt, Bit 4 The Break Interrupt (BI) bit is set to a logic “1” whenever the received data input is held in the Spacing state (logic “0”) for longer than a full word transmission time (that is, the total time of the start bit + data bits + parity bits + stop bits). The BI is reset after the CPU reads the contents of the Line Status Register. In the FIFO mode this error is associated with the particular character in the FIFO it applies to. This error is indicated when the associated character is at the top of the FIFO. When break occurs only one zero character is loaded into the FIFO. Restarting after a break is received requires the serial data (RXD) to be logic “1” for at least ½ bit time. Note: LSR Bits 1 through 4 produce a Receiver Line Status Interrupt whenever any of the corresponding conditions are detected and the interrupt is enabled. Transmitter Holding Register Empty, Bit 5 The Transmitter Holding Register Empty (THRE) bit indicates that the Serial Port is ready to accept a new character for transmission. In addition, this bit causes the Serial Port to issue an interrupt when the Transmitter Holding Register interrupt enable is set high. The THRE bit is set to a logic “1” when a character is transferred from the Transmitter Holding Register into the Transmitter Shift Register. The bit is reset to logic “0” whenever the CPU loads the Transmitter Holding Register. In the FIFO mode this bit is set when the XMIT FIFO is empty, it is cleared when at least 1 byte is written to the XMIT FIFO. Bit 5 is read-only. SMSC DS – FDC37N869 Page 65 Rev. 11/09/2000 Transmitter Empty, Bit 6 The Transmitter Empty (TEMT) bit is set to a logic “1” whenever the Transmitter Holding Register (THR) and Transmitter Shift Register (TSR) are both empty. It is reset to logic “0” whenever either the THR or TSR contains a data character. Bit 6 is read-only. In the FIFO mode this bit is set whenever the THR and TSR are both empty. RCVR FIFO Error, Bit 7 The RCVR FIFO Error bit is permanently set to logic “0” in the 450 mode. In the FIFO mode this bit is set to a logic “1” when there is at least one parity error, framing error or break indication in the FIFO. This bit is cleared when the LSR is read if there are no subsequent errors in the FIFO. MODEM STATUS REGISTER (MSR) The Modem Status register (Address Offset = 6H, DLAB = X, READ/WRITE) provides the current state of the control lines from the MODEM or peripheral device. In addition to this current state information, four bits of the MODEM Status Register provide state change information. These four bits are set to logic “1” whenever a control input from the MODEM changes state. They are reset to logic “0” whenever the MODEM Status Register is read. Delta Clear To Send, Bit 0 The Delta Clear To Send (DCTS) bit indicates that the nCTS input to the chip has changed state since the last time the MSR was read. Delta Data Set Ready, Bit 1 The Delta Data Set Ready (DDSR) bit indicates that the nDSR input has changed state since the last time the MSR was read. Trailing Edge Of Ring Indicator, Bit 2 The Trailing Edge of Ring Indicator (TERI) bit indicates that the nRI input has changed from logic “0” to logic “1”. Delta Data Carrier Detect, Bit 3 The Delta Data Carrier Detect (DDCD) bit indicates that the nDCD input to the chip has changed state. Note: Whenever bits 0, 1, 2, or 3 are set to a logic “1”, a MODEM Status Interrupt is generated. Clear To Send, Bit 4 The Clear To Send bit is the complement of the Clear To Send input (nCTS). If the Loop bit of the MCR is set to logic “1”, this bit is equivalent to nRTS in the MCR. Data Set Ready, Bit 5 The Data Set Ready bit is the complement of the Data Set Ready input (nDSR). If the Loop bit of the MCR is set to logic “1”, this bit is equivalent to DTR in the MCR. Ring Indicator, Bit 6 The Ring Indicator bit is the complement of the Ring Indicator input (nRI). If the Loop bit of the MCR is set to logic “1”, this bit is equivalent to OUT1 in the MCR. Data Carrier Detect, Bit 7 The Data Carrier Detect bit is the complement of the Data Carrier Detect input (nDCD). If the Loop bit of the MCR is set to logic “1”, this bit is equivalent to OUT2 in the MCR. SMSC DS – FDC37N869 Page 66 Rev. 11/09/2000 SCRATCHPAD REGISTER (SCR) The Scratchpad register (Address Offset =7H, DLAB =X, READ/WRITE) has no effect on the operation of the Serial Port. It is intended as a scratchpad register to be used by the programmer to hold data temporarily. PROGRAMMABLE BAUD RATE GENERATOR DIVISOR LATCHES The internal Baud Rate Generator (BRG) using the Programmable Baud Rate Generator Divisor Latches DDL and DDM (Address Offset = 0 and 1, DLAB = 1, READ/WRITE) is capable of taking any clock input (DC to 3 MHz) and dividing it by any divisor from 1 to 65535. The Baud Rate Generator output is 16x the baud rate. Two 8-bit latches store the divisor in 16-bit binary format. These Divisor Latches must be loaded during initialization in order to insure desired operation of the Baud Rate Generator. Upon loading either of the Divisor Latches, a 16 bit Baud counter is immediately loaded. This prevents long counts on initial load. If a 0 is loaded into the DDL and DDM registers the BRG clock is divided by 3. If a 1 is loaded the output is the inverse of the input oscillator. If a two is loaded the clock is divided by 2 with a 50% duty cycle. If a 3 or greater is loaded the output is low for 2 bits and high for the remainder of the count. The input clock to the BRG is a 1.8462 MHz clock. Table 53 shows the baud rates possible with a 1.8462 MHz clock. Table 53 - Baud Rates Using 1.8462 MHz Clock DIVISOR USED TO GENERATE 16X PERCENT ERROR DIFFERENCE CLOCK BETWEEN DESIRED AND ACTUAL* 2307 0.03 1538 1049 858 769 384 192 96 64 58 48 32 24 16 12 6 3 2 1 32770 32769 0.03 0.005 0.01 0.03 0.16 0.16 0.16 0.16 0.5 0.16 0.16 0.16 0.16 0.16 0.16 0.16 1.6 0.16 0.16 0.16 DESIRED BAUD RATE 50 75 110 134.5 150 300 600 1200 1800 2000 2400 3600 4800 7200 9600 19200 38400 57600 115200 230400 460800 CROC: BIT 7 OR 6 X X X X X X X X X X X X X X X X X X X 1 1 SMSC DS – FDC37N869 Page 67 Rev. 11/09/2000 The Affects of RESET on the UART Registers The RESET Function (Table 54) details the affects of RESET on each of the Serial Port registers. Table 54 - RESET Function RESET CONTROL RESET RESET RESET RESET RESET RESET RESET RESET RESET/Read LSR RESET/Read RBR RESET/ReadIIR/Write THR RESET RESET RESET RESET RESET/FCR1*FCR0/_FCR0 RESET/FCR1*FCR0/_FCR0 REGISTER/SIGNAL Interrupt Enable Register Interrupt Identification Reg. FIFO Control Line Control Reg. MODEM Control Reg. Line Status Reg. MODEM Status Reg. TXD1, TXD2 INTRPT (RCVR errs) INTRPT (RCVR Data Ready) INTRPT (THRE) OUT2B RTSB DTRB OUT1B RCVR FIFO XMIT FIFO FIFO Interrupt Mode Operation RESET STATE All bits low Bit 0 is high; Bits 1 - 7 low All bits low All bits low All bits low All bits low except 5 - 6 high Bits 0 - 3 low; Bits 4 - 7 input High Low Low Low High High High High All bits low All bits low When the RCVR FIFO and receiver interrupts are enabled (FCR bit 0 = “1”, IER bit 0 = “1”), RCVR interrupts occur as follows: 1. The receive data available interrupt will be issued when the FIFO has reached its programmed trigger level; it is cleared as soon as the FIFO drops below its programmed trigger level. 2. The IIR receive data available indication also occurs when the FIFO trigger level is reached. It is cleared when the FIFO drops below the trigger level. 3. The receiver line status interrupt (IIR=06H), has higher priority than the received data available (IIR=04H) interrupt. 4. The data ready bit (LSR bit 0)is set as soon as a character is transferred from the shift register to the RCVR FIFO. It is reset when the FIFO is empty. When RCVR FIFO and receiver interrupts are enabled, RCVR FIFO time-out interrupts occur as follows: 1. A FIFO time-out interrupt occurs if all the following conditions exist: • at least one character is in the FIFO • The most recent serial character received was longer than 4 continuous character times ago. (If 2 stop bits are programmed, the second one is included in this time delay.) • The most recent CPU read of the FIFO was longer than 4 continuous character times ago. 2. 3. 4. 5. This will cause a maximum character received to interrupt issued delay of 160 msec at 300 BAUD with a 12 bit character. Character times are calculated by using the RCLK input for a clock signal (this makes the delay proportional to the baud rate). When a time-out interrupt has occurred it is cleared and the timer reset when the CPU reads one character from the RCVR FIFO. When a time-out interrupt has not occurred the time-out timer is reset after a new character is received or after the CPU reads the RCVR FIFO. SMSC DS – FDC37N869 Page 68 Rev. 11/09/2000 When the XMIT FIFO and transmitter interrupts are enabled (FCR bit 0 = “1”, IER bit 1 = “1”), XMIT interrupts occur as follows: 1. The transmitter holding register interrupt (02H) occurs when the XMIT FIFO is empty; it is cleared as soon as the transmitter holding register is written to (1 of 16 characters may be written to the XMIT FIFO while servicing this interrupt) or the IIR is read. 2. The transmitter FIFO empty indications will be delayed 1 character time minus the last stop bit time whenever the following occurs: THRE=1 and there have not been at least two bytes at the same time in the transmit FIFO since the last THRE=1. The transmitter interrupt after changing FCR0 will be immediate, if it is enabled. Character time-out and RCVR FIFO trigger level interrupts have the same priority as the current received data available interrupt; XMIT FIFO empty has the same priority as the current transmitter holding register empty interrupt. FIFO Polled Mode Operation With FCR bit 0 = “1” resetting IER bits 0, 1, 2 or 3 or all to zero puts the UART in the FIFO Polled Mode of operation. Since the RCVR and XMITTER are controlled separately, either one or both can be in the polled mode of operation. In this mode, the user’s program will check RCVR and XMITTER status via the LSR. LSR definitions for the FIFO Polled Mode are as follows: 1. Bit 0=1 as long as there is one byte in the RCVR FIFO. 2. Bits 1 to 4 specify which error(s) have occurred. Character error status is handled the same way as when in the interrupt mode, the IIR is not affected since EIR bit 2=0. 3. Bit 5 indicates when the XMIT FIFO is empty. 4. Bit 6 indicates that both the XMIT FIFO and shift register are empty. 5. Bit 7 indicates whether there are any errors in the RCVR FIFO. There is no trigger level reached or time-out condition indicated in the FIFO Polled Mode, however, the RCVR and XMIT FIFOs are still fully capable of holding characters. Table 55 - Individual UART Channel Register Summary REGISTER REGISTER NAME SYMBOL BIT 0 BIT 1 Receive Buffer Register RBR Data Bit 0 (Note 1) Data Bit 1 (Read Only) Transmitter Holding Register (Write Only) Interrupt Enable Register THR IER Data Bit 0 Enable Received Data Available Interrupt (ERDAI) ”0” if Interrupt Pending FIFO Enable Data Bit 1 Enable Transmitter Holding Register Empty Interrupt (ETHREI) Interrupt ID Bit RCVR FIFO Reset REGISTER ADDRESS* ADDR = 0 DLAB = 0 ADDR = 0 DLAB = 0 ADDR = 1 DLAB = 0 ADDR = 2 ADDR = 2 ADDR = 3 ADDR = 4 ADDR = 5 ADDR = 6 ADDR = 7 ADDR = 0 DLAB = 1 Interrupt Ident. Register (Read Only) FIFO Control Register (Write Only) Line Control Register MODEM Control Register Line Status Register MODEM Status Register Scratch Register (Note 4) Divisor Latch (LS) IIR FCR LCR MCR LSR MSR SCR DDL Word Length Select Bit 0 Word Length Select Bit 1 (WLS0) (WLS1) Data Terminal Ready (DTR) Data Ready (DR) Delta Clear to Send (DCTS) Bit 0 Bit 0 Request to Send (RTS) Overrun Error (OE) Delta Data Set Ready (DDSR) Bit 1 Bit 1 SMSC DS – FDC37N869 Page 69 Rev. 11/09/2000 REGISTER ADDRESS* ADDR = 1 DLAB = 1 REGISTER NAME Divisor Latch (MS) REGISTER SYMBOL DLM BIT 0 Bit 8 Bit 9 BIT 1 *DLAB is Bit 7 of the Line Control Register (ADDR = 3). Note 1: Bit 0 is the least significant bit. It is the first bit serially transmitted or received. Note 2: When operating in the XT mode, this bit will be set any time that the transmitter shift register is empty. Table 56 - Individual UART Channel Register Summary Continued BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 Data Bit 3 Data Bit 3 Enable MODEM Status Interrupt (EMSI) Data Bit 4 Data Bit 4 0 Data Bit 5 Data Bit 5 0 Data Bit 6 Data Bit 6 0 Data Bit 7 Data Bit 7 0 BIT 2 Data Bit 2 Data Bit 2 Enable Receiver Line Status Interrupt (ELSI) Interrupt ID Bit Interrupt ID Bit 0 (Note 5) XMIT FIFO Reset Number of Stop Bits (STB) OUT1 (Note 3) Parity Error (PE) DMA Mode Select (Note 6) Parity Enable (PEN) OUT2 (Note 3) Reserved 0 FIFOs Enabled (Note 5) RCVR Trigger LSB Set Break FIFOs Enabled (Note 5) RCVR Trigger MSB Divisor Latch Access Bit (DLAB) 0 Error in RCVR FIFO (Note 5) Data Carrier Detect (DCD) Bit 7 Bit 7 Bit 15 Reserved Even Parity Select (EPS) Loop Stick Parity 0 0 Transmitter Empty (TEMT) (Note 2) Ring Indicator (RI) Bit 6 Bit 6 Bit 14 Framing Error Break Transmitte (FE) Interrupt (BI) r Holding Register (THRE) Data Set Ready (DSR) Bit 5 Bit 5 Bit 13 Trailing Edge Delta Data Clear to Ring Indicator Carrier Detect Send (CTS) (TERI) (DDCD) Bit 2 Bit 2 Bit 10 Note 3: Note 4: Note 5: Note 6: Bit 3 Bit 3 Bit 11 Bit 4 Bit 4 Bit 12 This bit no longer has a pin associated with it. When operating in the XT mode, this register is not available. These bits are always zero in the non-FIFO mode. Writing a one to this bit has no effect. DMA modes are not supported in this chip. Notes On Serial Port FIFO Mode Operation GENERAL The RCVR FIFO will hold up to 16 bytes regardless of which trigger level is selected. SMSC DS – FDC37N869 Page 70 Rev. 11/09/2000 TX AND RX FIFO OPERATION The Tx portion of the UART transmits data through TXD as soon as the CPU loads a byte into the Tx FIFO. The UART will prevent loads to the Tx FIFO if it currently holds 16 characters. Loading to the Tx FIFO will again be enabled as soon as the next character is transferred to the Tx shift register. These capabilities account for the largely autonomous operation of the Tx. The UART starts the above operations typically with a Tx interrupt. The chip issues a Tx interrupt whenever the Tx FIFO is empty and the Tx interrupt is enabled, except in the following instance. Assume that the Tx FIFO is empty and the CPU starts to load it. When the first byte enters the FIFO the Tx FIFO empty interrupt will transition from active to inactive. Depending on the execution speed of the service routine software, the UART may be able to transfer this byte from the FIFO to the shift register before the CPU loads another byte. If this happens, the Tx FIFO will be empty again and typically the UART’s interrupt line would transition to the active state. This could cause a system with an interrupt control unit to record a Tx FIFO empty condition, even though the CPU is currently servicing that interrupt. Therefore, after the first byte has been loaded into the FIFO the UART will wait one serial character transmission time before issuing a new Tx FIFO empty interrupt. This one character Tx interrupt delay will remain active until at least two bytes have been loaded into the FIFO, concurrently. When the Tx FIFO empties after this condition, the Tx interrupt will be activated without a one character delay. Rx support functions and operation are quite different from those described for the transmitter. The Rx FIFO receives data until the number of bytes in the FIFO equals the selected interrupt trigger level. At that time if Rx interrupts are enabled, the UART will issue an interrupt to the CPU. The Rx FIFO will continue to store bytes until it holds 16 of them. It will not accept any more data when it is full. Any more data entering the Rx shift register will set the Overrun Error flag. Normally, the FIFO depth and the programmable trigger levels will give the CPU ample time to empty the Rx FIFO before an overrun occurs. One side-effect of having a Rx FIFO is that the selected interrupt trigger level may be above the data level in the FIFO. This could occur when data at the end of the block contains fewer bytes than the trigger level. No interrupt would be issued to the CPU and the data would remain in the UART. To prevent the software from having to check for this situation the chip incorporates a time-out interrupt. The time-out interrupt is activated when there is a least one byte in the Rx FIFO, and neither the CPU nor the Rx shift register has accessed the Rx FIFO within 4 character times of the last byte. The time-out interrupt is cleared or reset when the CPU reads the Rx FIFO or another character enters it. These FIFO related features allow optimization of CPU/UART transactions and are especially useful given the higher baud rate capability (256K baud). INFRARED INTERFACE The FDC37N869 infrared interface provides a two-way wireless communications port using infrared as the transmission medium. Several infrared protocols have been provided in this implementation including IrDA v1.1 (SIR/FIR), ASKIR, and Consumer IR (Figure 3). For more information consult the SMSC Infrared Communication Controller (IRCC) specification. The IrDA v1.0 (SIR) and ASKIR formats are driven by the ACE registers found in UART2. The UART2 registers are described in section SERIAL PORT (UART) starting on page 59. The base address for UART2 is programmed in CR25, the UART2 Base Address Register (see section CR25 on page 116). The IrDA V1.2 (FIR) and Consumer IR formats are driven by the SCE registers. Descriptions of these registers can be found in the SMSC Infrared Communications Controller Specification. The Base Address for the SCE registers is programmed in CR2B, the SCE Base Address Register (see section CR28 on page 117). IrDA SIR/FIR and ASKIR IrDA SIR (v1.0) specifies asynchronous serial communication at baud rates up to 115.2Kbps. Each byte is sent serially LSB first beginning with a zero value start bit. A zero is signaled by sending a single infrared pulse at the SMSC DS – FDC37N869 Page 71 Rev. 11/09/2000 beginning of the serial bit time. A one is signaled by the absence of an infrared pulse during the bit time. Please refer to section AC TIMING for the parameters of these pulses and the IrDA waveforms. IrDA FIR (v1.2) includes IrDA v1.0 SIR and additionally specifies synchronous serial communications at data rates up to 4Mbps. Data is transferred LSB first in packets that can be up to 2048 bits in length. IrDA v1.2 includes .576Mbps and 1.152Mbps data rates using an encoding scheme that is similar to SIR. The 4Mbps data rate uses a pulse position modulation (PPM) technique. The ASKIR infrared allows asynchronous serial communication at baud rates up to 19.2Kbps. Each byte is sent serially LSB first beginning with a zero value start bit. A zero is signaled by sending a 500KHz carrier waveform for the duration of the serial bit time. A one is signaled by the absence of carrier during the bit time. Please refer to section AC TIMING for the parameters of the ASKIR waveforms. Consumer IR The FDC37N869 Consumer IR interface is a general-purpose Amplitude Shift Keyed encoder/decoder with programmable carrier and bit-cell rates that can emulate many popular TV Remote encoding formats; including, 38KHz PPM, PWM and RC-5. The carrier frequency is programmable from 1.6MHz to 6.25KHz. The bit-cell rate range is 100KHz to 390Hz. Hardware Interface The FDC37N869 IR hardware interface is shown in Figure 3. This interface supports two types of external FIR transceiver modules. One uses a mode pin (IR Mode) to program the data rate, while the other has a second Rx data pin (IRR3). The FDC37N869 uses Pin 21 for these functions. Pin 21 has IR Mode and IRR3 as its first and second alternate function, respectively. These functions are selected through CR29 as shown in Table 57. Table 57 - FIR Transceiver Module-Type Select HP MODE1 FUNCTION 0 IR Mode 1 IRR3 Note1: HPMODE is CR29, BIT 4 (see section CR29 on page 118). Refer to the Infrared Interface Block Diagram on the following page for HPMODE implementation. The FAST bit is used to select between the SIR mode and FIR mode receiver, regardless of the transceiver type. If FAST = 1, the FIR mode receiver is selected; if FAST = 0, the SIR mode receiver is selected (Table 58). Table 58 - IR Rx Data Pin Selection CONTROL SIGNALS INPUTS FAST HPMODE RX1 RX2 0 X RX1=RXD2 RX2=IRRX2 X 0 RX1=RXD2 RX2=IRRX2 1 1 RX1=IR Mode/IRR3 RX2=IR Mode/IRR3 IR Half Duplex Turnaround Delay Time If the Half Duplex option is chosen there is an IR Half Duplex Time-out that constrains IRCC direction mode changes. This time-out starts as each bit is transferred and prevents direction mode changes until the time-out expires. The timer is restarted whenever new data arrives in the current direction mode. For example, if data is loaded into the transmit buffer while a character is being received, the transmission will not start until the last bit has been received and the time-out expires. If the start bit of another character is received during this time-out, the timer is restarted after the new character is received. The Half Duplex Time-out is programmable from 0 to 25.5ms in 100µs increments (see section CR2D on page 115). SMSC DS – FDC37N869 Page 72 Rev. 11/09/2000 IrCC Block TXD2 0 RAW COM TV TX1 RX1 1 RXD2 1 ASK TX2 OUT MUX 1 IRTX2 IR RX2 2 IrDA TX3 AUX COM IR MODE RX3 0 IRRX2 FIR G.P. Data IR Mode /IRR3 Fast Bit FAST FIGURE 3 - INFRARED INTERFACE BLOCK DIAGRAM SMSC DS – FDC37N869 Page 73 Rev. 11/09/2000 PARALLEL PORT The FDC37N869 incorporates an IBM XT/AT compatible parallel port. The FDC37N869 supports the optional PS/2 type bi-directional parallel port (SPP), the Enhanced Parallel Port (EPP) and the Extended Capabilities Port (ECP) parallel port modes. Refer to the FDC37N869 Configuration Registers and the following hardware configuration description for information on disabling, powering down, changing the base address, and selecting the mode of operation of the parallel port. The FDC37N869 also incorporates SMSC’s ChiProtect™ circuitry, which prevents possible damage to the parallel port due to printer power-up. The functionality of the Parallel Port is achieved through the use of eight addressable ports, with their associated registers and control gating. The control and data port are read/write by the CPU, the status port is read/write in the EPP mode. The address map and bit encoding of the Parallel Port registers is shown in Table 59; the Parallel Port Connector is shown in Table 63. Table 59 - Parallel Port Registers BASE ADDRESS OFFSET 00H 01H 02H 03H 04H 05H 06H 07H DATA PORT1 STATUS PORT1 CONTROL PORT1 EPP ADDR PORT2,3 EPP DATA PORT 02,3 EPP DATA PORT 12,3 EPP DATA PORT 22,3 EPP DATA PORT 32,3 Note1: Note2: Note3: D0 PD0 TMOUT STROBE PD0 PD0 PD0 PD0 PD0 D1 PD1 0 AUTOFD PD1 PD1 PD1 PD1 PD1 D2 PD2 0 nINIT PD2 PD2 PD2 PD2 PD2 D3 PD3 nERR SLC PD3 PD3 PD3 PD3 PD3 D4 PD4 SLCT IRQE PD4 PD4 PD4 PD4 PD4 D5 PD5 PE PCD PD5 PD5 PD5 PD5 PD5 D6 PD6 nACK 0 PD6 PD6 PD6 PD6 PD6 D7 PD7 nBUSY 0 AD7 PD7 PD7 PD7 PD7 These registers are available in all modes. These registers are only available in EPP mode. For EPP mode, IOCHRDY must be connected to the ISA bus. SMSC DS – FDC37N869 Page 74 Rev. 11/09/2000 Table 60 - Parallel Port Connector HOST CONNECTOR 1 2-9 10 11 12 13 14 15 16 17 (1) = Compatible Mode (3) = High Speed Mode Note: For the cable interconnection required for ECP support and the Slave Connector pin numbers, refer to the IEEE 1284 Extended Capabilities Port Protocol and ISA Standard, Rev. 1.09, Jan. 7, 1993. This document is available from Microsoft. PIN NUMBER 75 69-66, 64-61 60 59 58 57 74 73 72 71 STANDARD nStrobe PData nAck Busy PE Select nAutofd nError nInit nSelectin EPP nWrite PData Intr nWait (NU) (NU) nDatastb (NU) (NU) nAddrstrb ECP nStrobe PData nAck Busy, PeriphAck(3) PError, nAckReverse(3) Select nAutoFd, HostAck(3) nFault(1) nPeriphRequest(3) nInit(1) nReverseRqst(3) nSelectIn(1,3) IBM XT/AT COMPATIBLE, BI-DIRECTIONAL AND EPP MODES DATA PORT ADDRESS OFFSET = 00H The Data Port is located at an offset of ‘00H’ from the base address. The data register is cleared at initialization by RESET. During a WRITE operation, the Data Register latches the contents of the data bus with the rising edge of the nIOW input. The contents of this register are buffered (non inverting) and output onto the PD0 - PD7 ports. During a READ operation in SPP mode, PD0 - PD7 ports are buffered (not latched) and output to the host CPU. STATUS PORT ADDRESS OFFSET = 01H The Status Port is located at an offset of ‘01H’ from the base address. The contents of this register are latched for the duration of an nIOR read cycle. The bits of the Status Port are defined as follows: BIT 0 TMOUT - TIME OUT This bit is valid in EPP mode only and indicates that a 10 usec time out has occurred on the EPP bus. A logic “0” means that no time out error has occurred; a logic “1” means that a time out error has been detected. This bit is cleared by a RESET. Writing a one to this bit clears the time out status bit. On a write, this bit is self clearing and does not require a write of a zero. Writing a zero to this bit has no effect. BITS 1, 2 - are not implemented as register bits, during a read of the Printer Status Register these bits are a low level. BIT 3 nERR - nERROR The level on the nERROR input is read by the CPU as bit 3 of the Printer Status Register. A logic “0” means an error has been detected; a logic “1” means no error has been detected. SMSC DS – FDC37N869 Page 75 Rev. 11/09/2000 BIT 4 SLCT - PRINTER SELECTED STATUS The level on the SLCT input is read by the CPU as bit 4 of the Printer Status Register. A logic “1” means the printer is on line; a logic “0” means it is not selected. BIT 5 PE - PAPER END The level on the PE input is read by the CPU as bit 5 of the Printer Status Register. A logic “1” indicates a paper end; a logic “0” indicates the presence of paper. BIT 6 nACK - nACKNOWLEDGE The level on the nACK input is read by the CPU as bit 6 of the Printer Status Register. A logic 0 means that the printer has received a character and can now accept another. A logic “1” means that it is still processing the last character or has not received the data. BIT 7 nBUSY - nBUSY The complement of the level on the nBUSY input is read by the CPU as bit 7 of the Printer Status Register. A logic 0 in this bit means that the printer is busy and cannot accept a new character. A logic “1” means that it is ready to accept the next character. CONTROL PORT ADDRESS OFFSET = 02H The Control Port is located at an offset of ‘02H’ from the base address. The Control Register is initialized by the RESET input, bits 0 to 5 only being affected; bits 6 and 7 are hard wired low. BIT 0 STROBE - STROBE This bit is inverted and output onto the nSTROBE output. BIT 1 AUTOFD – AUTOFEED This bit is inverted and output onto the nAUTOFD output. A logic “1” causes the printer to generate a line feed after each line is printed. A logic 0 means no autofeed. BIT 2 nINIT - nINITIATE OUTPUT This bit is output onto the nINIT output without inversion. BIT 3 SLCTIN - PRINTER SELECT INPUT This bit is inverted and output onto the nSLCTIN output. A logic “1” on this bit selects the printer; a logic “0” means the printer is not selected. BIT 4 IRQE - INTERRUPT REQUEST ENABLE The interrupt request enable bit when set to a high level may be used to enable interrupt requests from the Parallel Port to the CPU. An interrupt request is generated on the IRQ port by a positive going nACK input. When the IRQE bit is programmed low the IRQ is disabled. BIT 5 PCD - PARALLEL CONTROL DIRECTION Parallel Control Direction is valid in extended mode only (CR#1=0). In printer mode, the direction is always out regardless of the state of this bit. In bi-directional mode, a logic “0” means that the printer port is in output mode (write); a logic “1” means that the printer port is in input mode (read). SMSC DS – FDC37N869 Page 76 Rev. 11/09/2000 Bits 6 and 7 during a read are a low level, and cannot be written. EPP ADDRESS PORT ADDRESS OFFSET = 03H The EPP Address Port is located at an offset of ‘03H’ from the base address. The address register is cleared at initialization by RESET. During a WRITE operation, the contents of DB0-DB7 are buffered (non inverting) and output onto the PD0 - PD7 ports, the leading edge of nIOW causes an EPP ADDRESS WRITE cycle to be performed, the trailing edge of IOW latches the data for the duration of the EPP write cycle. During a READ operation, PD0 - PD7 ports are read, the leading edge of IOR causes an EPP ADDRESS READ cycle to be performed and the data output to the host CPU, the deassertion of ADDRSTB latches the PData for the duration of the IOR cycle. This register is only available in EPP mode. EPP DATA PORT 0 ADDRESS OFFSET = 04H The EPP Data Port 0 is located at an offset of ‘04H’ from the base address. The data register is cleared at initialization by RESET. During a WRITE operation, the contents of DB0-DB7 are buffered (non inverting) and output onto the PD0 - PD7 ports, the leading edge of nIOW causes an EPP DATA WRITE cycle to be performed, the trailing edge of IOW latches the data for the duration of the EPP write cycle. During a READ operation, PD0 - PD7 ports are read, the leading edge of IOR causes an EPP READ cycle to be performed and the data output to the host CPU, the deassertion of DATASTB latches the PData for the duration of the IOR cycle. This register is only available in EPP mode. EPP DATA PORT 1 ADDRESS OFFSET = 05H The EPP Data Port 1 is located at an offset of ‘05H’ from the base address. Refer to EPP DATA PORT 0 for a description of operation. This register is only available in EPP mode. EPP DATA PORT 2 ADDRESS OFFSET = 06H The EPP Data Port 2 is located at an offset of ‘06H’ from the base address. Refer to EPP DATA PORT 0 for a description of operation. This register is only available in EPP mode. EPP DATA PORT 3 ADDRESS OFFSET = 07H The EPP Data Port 3 is located at an offset of ‘07H’ from the base address. Refer to EPP DATA PORT 0 for a description of operation. This register is only available in EPP mode. EPP 1.9 OPERATION When the EPP mode is selected in the configuration register, the standard and bi-directional modes are also available. If no EPP Read, Write or Address cycle is currently executing, then the PDx bus is in the standard or bidirectional mode, and all output signals (STROBE, AUTOFD, INIT) are as set by the SPP Control Port and direction is controlled by PCD of the Control port. In EPP mode, the system timing is closely coupled to the EPP timing. For this reason, a watchdog timer is required to prevent system lockup. The timer indicates if more than 10µsec have elapsed from the start of the EPP cycle (nIOR or nIOW asserted) to nWAIT being deasserted (after command). If a time-out occurs, the current EPP cycle is aborted and the time-out condition is indicated in Status bit 0. During an EPP cycle, if STROBE is active, it overrides the EPP write signal forcing the PDx bus to always be in a write mode and the nWRITE signal to always be asserted. SMSC DS – FDC37N869 Page 77 Rev. 11/09/2000 Software Constraints Before an EPP cycle is executed, the software must ensure that the control register bit PCD is a logic “0” (i.e. a 04H or 05H should be written to the Control port). If the user leaves PCD as a logic “1”, and attempts to perform an EPP write, the chip is unable to perform the write (because PCD is a logic “1”) and will appear to perform an EPP read on the parallel bus, no error is indicated. EPP 1.9 Write The timing for a write operation (address or data) is shown in timing diagram EPP 1.9 Write Data or Address cycle. IOCHRDY is driven active low at the start of each EPP write and is released when it has been determined that the write cycle can complete. The write cycle can complete under the following circumstances: 1. If the EPP bus is not ready (nWAIT is active low) when nDATASTB or nADDRSTB goes active then the write can complete when nWAIT goes inactive high. 2. If the EPP bus is ready (nWAIT is inactive high) then the chip must wait for it to go active low before changing the state of nDATASTB, nWRITE or nADDRSTB. The write can complete once nWAIT is determined inactive. Write Sequence of Operation 1. 2. 3. 4. 5. 6. 7. The host selects an EPP register, places data on the SData bus and drives nIOW active. The chip drives IOCHRDY inactive (low). If WAIT is not asserted, the chip must wait until WAIT is asserted. The chip places address or data on PData bus, clears PDIR, and asserts nWRITE. Chip asserts nDATASTB or nADDRSTRB indicating that PData bus contains valid information, and the WRITE signal is valid. Peripheral deasserts nWAIT, indicating that any setup requirements have been satisfied and the chip may begin the termination phase of the cycle. A) The chip deasserts nDATASTB or nADDRSTRB, this marks the beginning of the termination phase. If it has not already done so, the peripheral should latch the information byte now. B) The chip latches the data from the SData bus for the PData bus and asserts (releases) IOCHRDY allowing the host to complete the write cycle. Peripheral asserts nWAIT, indicating to the host that any hold time requirements have been satisfied and acknowledging the termination of the cycle. Chip may modify nWRITE and nPDATA in preparation for the next cycle. 8. 9. EPP 1.9 Read The timing for a read operation (data) is shown in timing diagram EPP Read Data cycle. IOCHRDY is driven active low at the start of each EPP read and is released when it has been determined that the read cycle can complete. The read cycle can complete under the following circumstances: 1. 2. If the EPP bus is not ready (nWAIT is active low) when nDATASTB goes active then the read can complete when nWAIT goes inactive high. If the EPP bus is ready (nWAIT is inactive high) then the chip must wait for it to go active low before changing the state of WRITE or before nDATASTB goes active. The read can complete once nWAIT is determined inactive. Read Sequence of Operation 1. 2. 3. 4. 5. 6. 7. The host selects an EPP register and drives nIOR active. The chip drives IOCHRDY inactive (low). If WAIT is not asserted, the chip must wait until WAIT is asserted. The chip tri-states the PData bus and deasserts nWRITE. Chip asserts nDATASTB or nADDRSTRB indicating that PData bus is tri-stated, PDIR is set and the nWRITE signal is valid. Peripheral drives PData bus valid. Peripheral deasserts nWAIT, indicating that PData is valid and the chip may begin the termination phase of the cycle. SMSC DS – FDC37N869 Page 78 Rev. 11/09/2000 8. A) The chip latches the data from the PData bus for the SData bus, deasserts DATASTB or nADDRSTRB, this marks the beginning of the termination phase. The chip drives the valid data onto the SData bus and asserts (releases) IOCHRDY allowing the host to complete the read cycle. 9. Peripheral tri-states the PData bus and asserts nWAIT, indicating to the host that the PData bus is tri-stated. 10. Chip may modify nWRITE, PDIR and nPDATA in preparation for the next cycle. B) EPP 1.7 OPERATION When the EPP 1.7 mode is selected in the configuration register, the standard and bi-directional modes are also available. If no EPP Read, Write or Address cycle is currently executing, then the PDx bus is in the standard or bidirectional mode, and all output signals (STROBE, AUTOFD, INIT) are as set by the SPP Control Port and direction is controlled by PCD of the Control port. In EPP mode, the system timing is closely coupled to the EPP timing. For this reason, a watchdog timer is required to prevent system lockup. The timer indicates if more than10usec have elapsed from the start of the EPP cycle (nIOR or nIOW asserted) to the end of the cycle nIOR or nIOW deasserted). If a time-out occurs, the current EPP cycle is aborted and the time-out condition is indicated in Status bit 0. Software Constraints Before an EPP cycle is executed, the software must ensure that the control register bits D0, D1 and D3 are set to zero. Also, bit D5 (PCD) is a logic “0” for an EPP write or a logic “1” for and EPP read. EPP 1.7 Write The timing for a write operation (address or data) is shown in timing diagram EPP 1.7 Write Data or Address cycle. IOCHRDY is driven active low when nWAIT is active low during the EPP cycle. This can be used to extend the cycle time. The write cycle can complete when nWAIT is inactive high. Write Sequence of Operation 1. The host sets PDIR bit in the control register to a logic “0”. This asserts nWRITE. 2. The host selects an EPP register, places data on the SData bus and drives nIOW active. 3. The chip places address or data on PData bus. 4. Chip asserts nDATASTB or nADDRSTRB indicating that PData bus contains valid information, and the WRITE signal is valid. 5. If nWAIT is asserted, IOCHRDY is deasserted until the peripheral deasserts nWAIT or a time-out occurs. 6. When the host deasserts nI0W the chip deasserts nDATASTB or nADDRSTRB and latches the data from the SData bus for the PData bus. 7. Chip may modify nWRITE, PDIR and nPDATA in preparation of the next cycle. EPP 1.7 Read The timing for a read operation (data) is shown in timing diagram EPP 1.7 Read Data cycle. IOCHRDY is driven active low when nWAIT is active low during the EPP cycle. This can be used to extend the cycle time. The read cycle can complete when nWAIT is inactive high. Read Sequence of Operation 1. The host sets PDIR bit in the control register to a logic “1”. This deasserts nWRITE and tri-states the PData bus. 2. The host selects an EPP register and drives nIOR active. 3. Chip asserts nDATASTB or nADDRSTRB indicating that PData bus is tri-stated, PDIR is set and the nWRITE signal is valid. 4. If nWAIT is asserted, IOCHRDY is deasserted until the peripheral deasserts nWAIT or a time-out occurs. 5. The Peripheral drives PData bus valid. 6. The Peripheral deasserts nWAIT, indicating that PData is valid and the chip may begin the termination phase of the cycle. SMSC DS – FDC37N869 Page 79 Rev. 11/09/2000 7. 8. 9. When the host deasserts nI0R the chip deasserts nDATASTB or nADDRSTRB. Peripheral tri-states the PData bus. Chip may modify nWRITE, PDIR and nPDATA in preparation of the next cycle. Table 61 - EPP Pin Descriptions EPP SIGNAL nWRITE PD INTR WAIT EPP NAME nWrite Address/Data Interrupt nWait TYPE DESCRIPTION O This signal is active low. It denotes a write operation. I/O I I Bi-directional EPP byte wide address and data bus. This signal is active high and positive edge triggered. (Pass through with no inversion, Same as SPP). This signal is active low. It is driven inactive as a positive acknowledgment from the device that the transfer of data is completed. It is driven active as an indication that the device is ready for the next transfer. This signal is active low. write operation. It is used to denote data read or DATASTB RESET nData Strobe nReset O O O I I This signal is active low. When driven active, the EPP device is reset to its initial operational mode. This signal is active low. or write operation. Same as SPP mode. Same as SPP mode. It is used to denote address read ADDRSTB nAddress Strobe PE SLCT Paper End Printer Selected Status Error Parallel Port Direction NERR PDIR I O Same as SPP mode. This output shows the direction of the data transfer on the parallel port bus. A low means an output/write condition and a high means an input/read condition. This signal is normally a low (output/write) unless PCD of the control register is set or if an EPP read cycle is in progress. Note 1: SPP and EPP can use 1 common register. Note 2: nWrite is the only EPP output that can be over-ridden by SPP control port during an EPP cycle. For correct EPP read cycles, PCD is required to be a low. SMSC DS – FDC37N869 Page 80 Rev. 11/09/2000 EXTENDED CAPABILITIES PARALLEL PORT ECP provides a number of advantages, some of which are listed below. The individual features are explained in greater detail in the remainder of this section. • High performance half-duplex forward and reverse channel • Interlocked handshake, for fast reliable transfer • Optional single byte RLE compression for improved throughput (64:1) • Channel addressing for low-cost peripherals • Maintains link and data layer separation • Permits the use of active output drivers • Permits the use of adaptive signal timing • Peer-to-peer capability Vocabulary The following terms are used in this document: assert When a signal asserts it transitions to a “true” state, when a signal deasserts it transitions to a “false” state. forward Host to Peripheral communication. reverse Peripheral to Host communication. Pword A port word; equal in size to the width of the ISA interface. For this implementation, PWord is always 8 bits. 1 A high level 0 A low level These terms may be considered synonymous: • PeriphClk, nAck • HostAck, nAutoFd • PeriphAck, Busy • nPeriphRequest, nFault • nReverseRequest, nInit • nAckReverse, PError • Xflag, Select • ECPMode, nSelectln • HostClk, nStrobe Reference Document: IEEE 1284 Extended Capabilities Port Protocol and ISA Interface Standard, Rev 1.09, Jan 7, 1993. This document is available from Microsoft. The bit map of the Extended Parallel Port registers is shown in Table 65. Table 62 - ECP Registers D5 D4 PD5 PD4 D7 data ecpAFifo dsr dcr 1 1 2 2 D6 PD6 D3 PD3 D2 PD2 D1 PD1 D0 PD0 PD7 Addr/RLE nBusy 0 Address or RLE field nAck 0 PError Direction Select ackIntEn nFault SelectIn 0 nInit 0 0 autofd strobe cFifo Parallel Port Data FIFO ECP Data FIFO Test FIFO 0 compress 0 intrValue MODE 0 1 IRQ Software Select nErrIntrEn dmaEn 0 0 0 0 ecpDFifo 2 tFifo 2 cnfgA cnfgB ecr Note1: Note2: DMA Software Select serviceIntr full empty These registers are available in all modes. All FIFOs use one common 16 byte FIFO. SMSC DS – FDC37N869 Page 81 Rev. 11/09/2000 ISA IMPLEMENTATION STANDARD This specification describes the standard ISA interface to the Extended Capabilities Port (ECP). All ISA devices supporting ECP must meet the requirements contained in this section or the port will not be supported by Microsoft. For a description of the ECP Protocol, please refer to the IEEE 1284 Extended Capabilities Port Protocol and ISA Interface Standard, Rev. 1.09, Jan.7, 1993. This document is available from Microsoft. Description The port is software and hardware compatible with existing parallel ports so that it may be used as a standard LPT port if ECP is not required. The port is designed to be simple and requires a small number of gates to implement. It does not do any “protocol” negotiation, rather it provides an automatic high burst-bandwidth channel that supports DMA for ECP in both the forward and reverse directions. Small FIFOs are employed in both forward and reverse directions to smooth data flow and improve the maximum bandwidth requirement. The size of the FIFO is 16 bytes deep. The port supports an automatic handshake for the standard parallel port to improve compatibility mode transfer speed. The port also supports run length encoded (RLE) decompression (required) in hardware. Compression is accomplished by counting identical bytes and transmitting an RLE byte that indicates how many times the next byte is to be repeated. Decompression simply intercepts the RLE byte and repeats the following byte the specified number of times. Hardware support for compression is optional. Table 63 - ECP Pin Descriptions DESCRIPTION During write operations nSTROBE registers data or address into the slave on the asserting edge (handshakes with Busy). Contains address or data or RLE data. Indicates valid data driven by the peripheral when asserted. This signal handshakes with nAUTOFD in reverse. This signal deasserts to indicate that the peripheral can accept data. This signal handshakes with nStrobe in the forward direction. In the reverse direction this signal indicates whether the data lines contain ECP command information or data. The peripheral uses this signal to flow control in the forward direction. It is an “interlocked” handshake with nStrobe. PeriphAck also provides command information in the reverse direction. Used to acknowledge a change in the direction the transfer (asserted = forward). The peripheral drives this signal low to acknowledge nReverseRequest. It is an “interlocked” handshake with nReverseRequest. The host relies upon nAckReverse to determine when it is permitted to drive the data bus. Indicates printer on line. Requests a byte of data from the peripheral when asserted, handshaking with nACK in the reverse direction. In the forward direction this signal indicates whether the data lines contain ECP address or data. The host drives this signal to flow control in the reverse direction. It is an “interlocked” handshake with nACK. HostAck also provides command information in the forward phase. Generates an error interrupt when asserted. This signal provides a mechanism for peer-to-peer communication. This signal is valid only in the forward direction. During ECP Mode the peripheral is permitted (but not required) to drive this pin low to request a reverse transfer. The request is merely a “hint” to the host; the host has ultimate control over the transfer direction. This signal would be typically used to generate an interrupt to the host CPU. NAME nSTROBE Pdata 7:0 nACK PeriphAck (Busy) TYPE O I/O I I Perror (nAckReverse) I Select nAUTOFD (HostAck) I O nFAULT (nPeriphRequest) I SMSC DS – FDC37N869 Page 82 Rev. 11/09/2000 NAME nINIT TYPE O DESCRIPTION Sets the transfer direction (asserted = reverse, deasserted = forward). This pin is driven low to place the channel in the reverse direction. The peripheral is only allowed to drive the bi-directional data bus while in ECP Mode and HostAck is low and nSelectIn is high. Always deasserted in ECP mode. nSELECTIN Register Definitions O The register definitions are based on the standard IBM addresses for LPT. All of the standard printer ports are supported. The additional registers attach to an upper bit decode of the standard LPT port definition to avoid conflict with standard ISA devices. The port is equivalent to a generic parallel port interface and may be operated in that mode. The port registers vary depending on the mode field in the ecr ( Table 68). Table 67 lists these dependencies. Operation of the devices in modes other that those specified is undefined. Table 64 - ECP Register Definitions ADDRESS (Note 1) ECP MODES +000h R/W +000h R/W +001h R/W +002h R/W +400h R/W +400h R/W +400h R/W +400h R +401h R/W +402h R/W 000-001 011 All All 010 011 110 111 111 All NAME data ecpAFifo dsr dcr cFifo ecpDFifo tFifo cnfgA cnfgB ecr FUNCTION Data Register ECP FIFO (Address) Status Register Control Register Parallel Port Data FIFO ECP FIFO (DATA) Test FIFO Configuration Register A Configuration Register B Extended Control Register Note 1: These addresses are added to the parallel port base address as selected by configuration register or jumpers. Note 2: All addresses are qualified with AEN. Refer to the AEN pin definition. Table 65 - Mode Descriptions DESCRIPTION (Refer to ECR Register Description) SPP mode PS/2 Parallel Port mode Parallel Port Data FIFO mode ECP Parallel Port mode EPP mode (If this option is enabled in the configuration registers) (Reserved) Test mode Configuration mode MODE 000 001 010 011 100 101 110 111 SMSC DS – FDC37N869 Page 83 Rev. 11/09/2000 DATA and ecpAFifo PORT ADDRESS OFFSET = 00H Modes 000 and 001 (Data Port) The Data Port is located at an offset of ‘00H’ from the base address. The data register is cleared at initialization by RESET. During a WRITE operation, the Data Register latches the contents of the data bus on the rising edge of the nIOW input. The contents of this register are buffered (non inverting) and output onto the PD0 - PD7 ports. During a READ operation, PD0 - PD7 ports are read and output to the host CPU. Mode 011 (ECP FIFO - Address/RLE) A data byte written to this address is placed in the FIFO and tagged as an ECP Address/RLE. The hardware at the ECP port transmits this byte to the peripheral automatically. The operation of this register is only defined for the forward direction (direction is 0). Refer to the ECP Parallel Port Forward Timing Diagram, located in the Timing Diagrams section of this data sheet. DEVICE STATUS REGISTER (dsr) ADDRESS OFFSET = 01H The Status Port is located at an offset of ‘01H’ from the base address. Bits 0 - 2 are not implemented as register bits, during a read of the Printer Status Register these bits are a low level. The bits of the Status Port are defined as follows: BIT 3 nFault The level on the nFault input is read by the CPU as bit 3 of the Device Status Register. BIT 4 Select The level on the Select input is read by the CPU as bit 4 of the Device Status Register. BIT 5 PError The level on the PError input is read by the CPU as bit 5 of the Device Status Register. Printer Status Register. BIT 6 nAck The level on the nAck input is read by the CPU as bit 6 of the Device Status Register. BIT 7 nBusy The complement of the level on the BUSY input is read by the CPU as bit 7 of the Device Status Register. DEVICE CONTROL REGISTER (dcr) ADDRESS OFFSET = 02H The Control Register is located at an offset of ‘02H’ from the base address. The Control Register is initialized to zero by the RESET input, bits 0 to 5 only being affected; bits 6 and 7 are hard wired low. BIT 0 STROBE - STROBE This bit is inverted and output onto the nSTROBE output. SMSC DS – FDC37N869 Page 84 Rev. 11/09/2000 BIT 1 AUTOFD - AUTOFEED This bit is inverted and output onto the nAUTOFD output. A logic 1 causes the printer to generate a line feed after each line is printed. A logic 0 means no autofeed. BIT 2 nINIT - nINITIATE OUTPUT This bit is output onto the nINIT output without inversion. BIT 3 SELECTIN This bit is inverted and output onto the nSLCTIN output. A logic 1 on this bit selects the printer; a logic 0 means the printer is not selected. BIT 4 ackIntEn - INTERRUPT REQUEST ENABLE The interrupt request enable bit when set to a high level may be used to enable interrupt requests from the Parallel Port to the CPU due to a low to high transition on the nACK input. Refer to the description of the interrupt under Operation, Interrupts. BIT 5 DIRECTION If mode=000 or mode=010, this bit has no effect and the direction is always out regardless of the state of this bit. In all other modes, Direction is valid and a logic 0 means that the printer port is in output mode (write); a logic 1 means that the printer port is in input mode (read). Bits 6 and 7 during a read are a low level, and cannot be written. cFifo (Parallel Port Data FIFO) ADDRESS OFFSET = 400h Mode = 010 Bytes written or DMAed from the system to this FIFO are transmitted by a hardware handshake to the peripheral using the standard parallel port protocol. Transfers to the FIFO are byte aligned. This mode is only defined for the forward direction. ecpDFifo (ECP Data FIFO) ADDRESS OFFSET = 400H Mode = 011 Bytes written or DMAed from the system to this FIFO, when the direction bit is 0, are transmitted by a hardware handshake to the peripheral using the ECP parallel port protocol. Transfers to the FIFO are byte aligned. Data bytes from the peripheral are read under automatic hardware handshake from ECP into this FIFO when the direction bit is 1. Reads or DMAs from the FIFO will return bytes of ECP data to the system. tFifo (Test FIFO Mode) ADDRESS OFFSET = 400H Mode = 110 Data bytes may be read, written or DMAed to or from the system to this FIFO in any direction. SMSC DS – FDC37N869 Page 85 Rev. 11/09/2000 Data in the tFIFO will not be transmitted to the to the parallel port lines using a hardware protocol handshake. However, data in the tFIFO may be displayed on the parallel port data lines. The tFIFO will not stall when overwritten or underrun. If an attempt is made to write data to a full tFIFO, the new data is not accepted into the tFIFO. If an attempt is made to read data from an empty tFIFO, the last data byte is reread again. The full and empty bits must always keep track of the correct FIFO state. The tFIFO will transfer data at the maximum ISA rate so that software may generate performance metrics. The FIFO size and interrupt threshold can be determined by writing bytes to the FIFO and checking the full and serviceIntr bits. The writeIntrThreshold can be determined by starting with a full tFIFO, setting the direction bit to 0 and emptying it a byte at a time until serviceIntr is set. This may generate a spurious interrupt, but will indicate that the threshold has been reached. The readIntrThreshold can be determined by setting the direction bit to 1 and filling the empty tFIFO a byte at a time until serviceIntr is set. This may generate a spurious interrupt, but will indicate that the threshold has been reached. Data bytes are always read from the head of tFIFO regardless of the value of the direction bit. For example if 44h, 33h, 22h is written to the FIFO, then reading the tFIFO will return 44h, 33h, 22h in the same order as was written. cnfgA (Configuration Register A) ADDRESS OFFSET = 400H Mode = 111 This register is a read only register. When read, 10H is returned. This indicates to the system that this is an 8-bit implementation. (PWord = 1 byte) cnfgB (Configuration Register B) ADDRESS OFFSET = 401H Mode = 111 BIT 7 compress This bit is read only. During a read it is a low level. This means that this chip does not support hardware RLE compression. It does support hardware de-compression! BIT 6 intrValue Returns the value on the ISA iRq line to determine possible conflicts. BITS 2:0 DMA Software Select The DMA Software Select bits indicate the DMA channel number that has been allocated to the Parallel Port. The channel encoding is shown in Table 66. The DMA Software select bits shadow the ECP DMA Select bits in the ECP Software Select register CR22. SMSC DS – FDC37N869 Page 86 Rev. 11/09/2000 Table 66 - DMA SOFTWARE SELECT ENCODING DMA Software Select DMA (cnfgB) SELECTED D2 D1 D0 3 0 1 1 2 0 1 0 1 0 0 1 Other 0 0 0 BITS 5:3 IRQ Software Select The IRQ Software Select bits indicate the IRQ channel number that has been allocated to the Parallel Port. The IRQ encoding is shown in Table 67. The IRQ Software select bits shadow the ECP IRQ Select bits in the ECP Software Select register CR22. Table 67 - IRQ SOFTWARE SELECT ENCODING IRQ Software IRQ SELECTED Select (cnfgB) D5 D4 D3 15 1 1 0 14 1 0 1 11 1 0 0 10 0 1 1 9 0 1 0 7 0 0 1 5 1 1 1 Other 0 0 0 ecr (Extended Control Register) ADDRESS OFFSET = 402H Mode = all This register controls the extended ECP parallel port functions (Table 69). BITS 7,6,5 These bits are Read/Write and select the Mode. BIT 4 nErrIntrEn Read/Write (Valid only in ECP Mode) 1: Disables the interrupt generated on the asserting edge of nFault. 0: Enables an interrupt pulse on the high to low edge of nFault. Note that an interrupt will be generated if nFault is asserted (interrupting) and this bit is written from a “1” to a “0”. This prevents interrupts from being lost in the time between the read of the ecr and the write of the ecr. BIT 3 dmaEn Read/Write 1: Enables DMA (DMA starts when serviceIntr is “0”). 0: Disables DMA unconditionally. SMSC DS – FDC37N869 Page 87 Rev. 11/09/2000 BIT 2 serviceIntr Read/Write 1: Disables DMA and all of the service interrupts. 0: Enables one of the following 3 cases of interrupts. Once one of the 3 service interrupts has occurred serviceIntr bit shall be set to a “1” by hardware, it must be reset to “0” to re-enable the interrupts. Writing this bit to a “1” will not cause an interrupt. case dmaEn=1: During DMA (this bit is set to a “1” when terminal count is reached). case dmaEn=0 direction=0: This bit shall be set to “1” whenever there are writeIntrThreshold or more bytes free in the FIFO. case dmaEn=0 direction=1: This bit shall be set to “1” whenever there are readIntrThreshold or more valid bytes to be read from the FIFO. BIT 1 full Read only 1: The FIFO cannot accept another byte or the FIFO is completely full. 0: The FIFO has at least 1 free byte. BIT 0 empty Read only 1: The FIFO is completely empty. 0: The FIFO contains at least 1 byte of data. R/W 000: Table 68 - Extended Control Register MODE Standard Parallel Port mode. In this mode the FIFO is reset and common collector drivers are used on the control lines (nStrobe, nAutoFd, nInit and nSelectIn). Setting the direction bit will not tri-state the output drivers in this mode. PS/2 Parallel Port mode. Same as above except that direction may be used to tri-state the data lines and reading the data register returns the value on the data lines and not the value in the data register. All drivers have active pull-ups (push-pull). Parallel Port FIFO mode. This is the same as 000 except that bytes are written or DMAed to the FIFO. FIFO data is automatically transmitted using the standard parallel port protocol. Note that this mode is only useful when direction is 0. All drivers have active pull-ups (push-pull). ECP Parallel Port Mode. In the forward direction (direction is 0) bytes placed into the ecpDFifo and bytes written to the ecpAFifo are placed in a single FIFO and transmitted automatically to the peripheral using ECP Protocol. In the reverse direction (direction is 1) bytes are moved from the ECP parallel port and packed into bytes in the ecpDFifo. All drivers have active pull-ups (push-pull). Selects EPP Mode: In this mode, EPP is selected if the EPP supported option is selected in configuration register CR4. All drivers have active pull-ups (push-pull). Reserved Test Mode. In this mode the FIFO may be written and read, but the data will not be transmitted on the parallel port. All drivers have active pull-ups (push-pull). Configuration Mode. In this mode the confgA, confgB registers are accessible at 0x400 and 0x401. All drivers have active pull-ups (push-pull). 001: 010: 011: 100: 101: 110: 111: SMSC DS – FDC37N869 Page 88 Rev. 11/09/2000 OPERATION Mode Switching/Software Control Software will execute P1284 negotiation and all operation prior to a data transfer phase under programmed I/O control (mode 000 or 001). Hardware provides an automatic control line handshake, moving data between the FIFO and the ECP port only in the data transfer phase (modes 011 or 010). Setting the mode to 011 or 010 will cause the hardware to initiate data transfer. If the port is in mode 000 or 001 it may switch to any other mode. If the port is not in mode 000 or 001 it can only be switched into mode 000 or 001. The direction can only be changed in mode 001. Once in an extended forward mode the software should wait for the FIFO to be empty before switching back to mode 000 or 001. In this case all control signals will be deasserted before the mode switch. In an ECP reverse mode the software waits for all the data to be read from the FIFO before changing back to mode 000 or 001. Since the automatic hardware ECP reverse handshake only cares about the state of the FIFO it may have acquired extra data which will be discarded. It may in fact be in the middle of a transfer when the mode is changed back to 000 or 001. In this case the port will deassert nAutoFd independent of the state of the transfer. The design shall not cause glitches on the handshake signals if the software meets the constraints above. ECP Operation Prior to ECP operation the Host must negotiate on the parallel port to determine if the peripheral supports the ECP protocol. This is a somewhat complex negotiation carried out under program control in mode 000. After negotiation, it is necessary to initialize some of the port bits. The following are required: • Set Direction = 0, enabling the drivers. • Set strobe = 0, causing the nStrobe signal to default to the deasserted state. • Set autoFd = 0, causing the nAutoFd signal to default to the deasserted state. • Set mode = 011 (ECP Mode) ECP address/RLE bytes or data bytes may be sent automatically by writing the ecpAFifo or ecpDFifo respectively. Note that all FIFO data transfers are byte wide and byte aligned. Address/RLE transfers are byte-wide and only allowed in the forward direction. The host may switch directions by first switching to mode = 001, negotiating for the forward or reverse channel, setting direction to 1 or 0, then setting mode = 011. When direction is 1 the hardware shall handshake for each ECP read data byte and attempt to fill the FIFO. Bytes may then be read from the ecpDFifo as long as it is not empty . ECP transfers may also be accomplished (albeit slowly) by handshaking individual bytes under program control in mode = 001, or 000. Termination from ECP Mode Termination from ECP Mode is similar to the termination from Nibble/Byte Modes. The host is permitted to terminate from ECP Mode only in specific well-defined states. The termination can only be executed while the bus is in the forward direction. To terminate while the channel is in the reverse direction, it must first be transitioned into the forward direction. Command/Data ECP Mode supports two advanced features to improve the effectiveness of the protocol for some applications. The features are implemented by allowing the transfer of normal 8 bit data or 8 -bit commands (Table 70). When in the forward direction, normal data is transferred when HostAck is high and an 8 bit command is transferred when HostAck is low. SMSC DS – FDC37N869 Page 89 Rev. 11/09/2000 The most significant bit of the command indicates whether it is a run-length count (for compression) or a channel address. When in the reverse direction, normal data is transferred when PeriphAck is high and an 8 bit command is transferred when PeriphAck is low. The most significant bit of the command is always zero. Reverse channel addresses are seldom used and may not be supported in hardware. Table 69 - Forward Channel Commands (HostAck Low) Reverse Channel Commands (PeripAck Low) Data Compression D7 D[6:0] 0 Run-Length Count (0-127) (mode 0011 0X00 only) 1 Channel Address (0-127) The FDC37N869 supports run length encoded (RLE) decompression in hardware and can transfer compressed data to a peripheral. Run length encoded (RLE) compression in hardware is not supported. To transfer compressed data in ECP mode, the compression count is written to the ecpAFifo and the data byte is written to the ecpDFifo. Compression is accomplished by counting identical bytes and transmitting an RLE byte that indicates how many times the next byte is to be repeated. Decompression simply intercepts the RLE byte and repeats the following byte the specified number of times. When a run-length count is received from a peripheral, the subsequent data byte is replicated the specified number of times. A run-length count of zero specifies that only one byte of data is represented by the next data byte, whereas a run-length count of 127 indicates that the next byte should be expanded to 128 bytes. To prevent data expansion, however, run-length counts of zero should be avoided. Pin Definition The drivers for nStrobe, nAutoFd, nInit and nSelectIn are open-collector in mode 000 and are push-pull in all other modes. ISA Connections The interface can never stall causing the host to hang. The width of data transfers is strictly controlled on an I/O address basis per this specification. All FIFO-DMA transfers are byte wide, byte aligned and end on a byte boundary. (The PWord value can be obtained by reading Configuration Register A, cnfgA, described in the next section). Single byte wide transfers are always possible with standard or PS/2 mode using program control of the control signals. Interrupts The interrupts are enabled by serviceIntr in the ecr register. serviceIntr = 1 Disables the DMA and all of the service interrupts. serviceIntr = 0Enables the selected interrupt condition. If the interrupting condition is valid, then the interrupt is generated immediately when this bit is changed from a 1 to a 0. This can occur during Programmed I/O if the number of bytes removed or added from/to the FIFO does not cross the threshold. The interrupt generated is ISA friendly in that it must pulse the interrupt line low, allowing for interrupt sharing. After a brief pulse low following the interrupt event, the interrupt line is tri-stated so that other interrupts may assert. An interrupt is generated when: 1. For DMA transfers: When serviceIntr is 0, dmaEn is 1 and the DMA TC is received. 2. For Programmed I/O: a. When serviceIntr is “0”, dmaEn is “0”, direction is “0” and there are writeIntrThreshold or more free bytes in the FIFO. Also, an interrupt is generated when serviceIntr is cleared to “0” whenever there are writeIntrThreshold or more free bytes in the FIFO. SMSC DS – FDC37N869 Page 90 Rev. 11/09/2000 3. 4. b(1) When serviceIntr is 0, dmaEn is 0, direction is “1” and there are readIntrThreshold or more bytes in the FIFO. Also, an interrupt is generated when serviceIntr is cleared to “0” whenever there are readIntr Threshold or more bytes in the FIFO. When nErrIntrEn is “0” and nFault transitions from high to low or when nErrIntrEn is set from “1” to “0” and nFault is asserted. When ackIntEn is “1” and the nAck signal transitions from a low to a high. FIFO Operation The FIFO threshold is set in the chip configuration registers. All data transfers to or from the parallel port can proceed in DMA or Programmed I/O (non-DMA) mode as indicated by the selected mode. The FIFO is used by selecting the Parallel Port FIFO mode or ECP Parallel Port Mode. (FIFO test mode will be addressed separately.) After a reset, the FIFO is disabled. Each data byte is transferred by a Programmed I/O cycle or PDRQ depending on the selection of DMA or Programmed I/O mode. The following paragraphs detail the operation of the FIFO flow control. In these descriptions, ranges from 1 to 16. The parameter FIFOTHR, which the user programs, is one less and ranges from 0 to 15. A low threshold value (i.e. 2) results in longer periods of time between service requests, but requires faster servicing of the request for both read and write cases. The host must be very responsive to the service request. This is the desired case for use with a “fast” system. A high value of threshold (i.e. 12) is used with a “sluggish” system by affording a long latency period after a service request, but results in more frequent service requests. DMA TRANSFERS Note: PDRQ - Currently selected Parallel Port DRQ channel nPDACK - Currently selected Parallel Port DACK channel PINTR - Currently selected Parallel Port IRQ channel Typical DMA Mode Transfers DMA transfers are always to or from the ecpDFifo, tFifo or CFifo. DMA utilizes the standard PC DMA services. To use the DMA transfers, the host first sets up the direction and state as in the programmed I/O case. Then it programs the DMA controller in the host with the desired count and memory address. Lastly it sets dmaEn to “1” and serviceIntr to “0”. The ECP requests DMA transfers from the host by activating the PDRQ pin. The DMA will empty or fill the FIFO using the appropriate direction and mode. When the terminal count in the DMA controller is reached, an interrupt is generated and serviceIntr is asserted, disabling DMA. In order to prevent possible blocking of refresh requests dReq shall not be asserted for more than 32 DMA cycles in a row. The FIFO is enabled directly by asserting nPDACK and addresses need not be valid. PINTR is generated when a TC is received. PDRQ must not be asserted for more than 32 DMA cycles in a row. After the 32nd cycle, PDRQ must be kept unasserted until nPDACK is deasserted for a minimum of 350nsec. (Note: The only way to properly terminate DMA transfers is with a TC). DMA may be disabled in the middle of a transfer by first disabling the host DMA controller. Then setting serviceIntr to 1, followed by setting dmaEn to 0, and waiting for the FIFO to become empty or full. Restarting the DMA is accomplished by enabling DMA in the host, setting dmaEn to 1, followed by setting serviceIntr to 0. DMA Mode - Transfers from the FIFO to the Host (Note: In the reverse mode, the peripheral may not continue to fill the FIFO if it runs out of data to transfer, even if the chip continues to request more data from the peripheral). The ECP activates the PDRQ pin whenever there is data in the FIFO. The DMA controller must respond to the request by reading data from the FIFO. The ECP will deactivate the PDRQ pin when the FIFO becomes empty or when the TC becomes true (qualified by nPDACK), indicating that no more data is required. PDRQ goes SMSC DS – FDC37N869 Page 91 Rev. 11/09/2000 inactive after nPDACK goes active for the last byte of a data transfer (or on the active edge of nIOR, on the last byte, if no edge is present on nPDACK). If PDRQ goes inactive due to the FIFO going empty, then PDRQ is active again as soon as there is one byte in the FIFO. If PDRQ goes inactive due to the TC, then PDRQ is active again when there is one byte in the FIFO, and serviceIntr has been re-enabled. (Note: A data underrun may occur if PDRQ is not removed in time to prevent an unwanted cycle). Programmed I/O Mode or Non-DMA Mode The ECP or parallel port FIFOs may also be operated using interrupt driven programmed I/O. Software can determine the writeIntrThreshold, readIntrThreshold, and FIFO depth by accessing the FIFO in Test Mode. Programmed I/O transfers are to the ecpDFifo at 400H and ecpAFifo at 000H or from the ecpDFifo located at 400H, or to/from the tFifo at 400H. To use the programmed I/O transfers, the host first sets up the direction and state, sets dmaEn to 0 and serviceIntr to 0. The ECP requests programmed I/O transfers from the host by activating the PINTR pin. The programmed I/O will empty or fill the FIFO using the appropriate direction and mode. Note: A threshold of 16 is equivalent to a threshold of 15. These two cases are treated the same. Programmed I/O - Transfers from the FIFO to the Host In the reverse direction an interrupt occurs when serviceIntr is 0 and readIntrThreshold bytes are available in the FIFO. If at this time the FIFO is full it can be emptied completely in a single burst, otherwise readIntrThreshold bytes may be read from the FIFO in a single burst. readIntrThreshold =(16-) data bytes in FIFO An interrupt is generated when serviceIntr is 0 and the number of bytes in the FIFO is greater than or equal to (16). (If the threshold = 12, then the interrupt is set whenever there are 4-16 bytes in the FIFO.) The PINT pin can be used for interrupt-driven systems. The host must respond to the request by reading data from the FIFO. This process is repeated until the last byte is transferred out of the FIFO. If at this time the FIFO is full, it can be completely emptied in a single burst, otherwise a minimum of (16-) bytes may be read from the FIFO in a single burst. Programmed I/O - Transfers from the Host to the FIFO In the forward direction an interrupt occurs when serviceIntr is 0 and there are writeIntrThreshold or more bytes free in the FIFO. At this time if the FIFO is empty it can be filled with a single burst before the empty bit needs to be re-read. Otherwise it may be filled with writeIntrThreshold bytes. writeIntrThreshold = (16-) free bytes in FIFO An interrupt is generated when serviceIntr is 0 and the number of bytes in the FIFO is less than or equal to . (If the threshold = 12, then the interrupt is set whenever there are 12 or less bytes of data in the FIFO.) The PINT pin can be used for interrupt-driven systems. The host must respond to the request by writing data to the FIFO. If at this time the FIFO is empty, it can be completely filled in a single burst, otherwise a minimum of (16-) bytes may be written to the FIFO in a single burst. This process is repeated until the last byte is transferred into the FIFO. SMSC DS – FDC37N869 Page 92 Rev. 11/09/2000 AUTO POWER MANAGEMENT Power management is provided for the following FDC37N869 logical devices: Floppy Disk, UART1, UART2 and the Parallel Port. For each logical device two types of power management are provided; direct powerdown and auto powerdown. Direct powerdown is controlled by the powerdown bits in the configuration registers. One bit is provided for each logical device. Auto powerdown can be enabled for each logical device by setting the Auto Powerdown Enable bits in the configuration registers. In addition, a chip-level hardware powerdown function has been provided through the PWRGD pin. Refer to Table 1 and to other descriptions of the PWRGD function, for example section CONFIGURATION, for more information. FDC Power Management Direct FDC power management is controlled by FDC Power (bit 3) of Configuration Register 0 (see section CR00 on page 104). FDC auto power management is enabled by Floppy Disk Enable (bit 7) in CR7 (see section CR07 on page 109). An internal timer is activated as soon as auto power management is enabled. During the timer countdown any operation involving the MSR or the Data Register (FIFO) will re-initialize the timer. In auto powerdown mode the FDC enters the powerdown state when all of the following conditions have been met: 1. 2. 3. 4. The motor enable pins of the DOR register are inactive (zero). The FDC is idle; MSR=80H and INT = 0 (INT may be high even if MSR = 80H due to polling interrupts). The internal head unload timer has expired. The 10msec auto powerdown timer has lapsed. Disabling the FDC auto power management cancels the internal timer and prevents any of the above conditions from re-enabling the powerdown state. Note: At least 8us delay should be added when exiting FDC Auto Powerdown mode. If the operating environment is such that this delay cannot be guaranteed, the auto powerdown mode should not be used and Direct powerdown mode should be used instead. The Direct powerdown mode requires at least 8us delay at 250K bits/sec configuration and 4us delay at 500K bits/sec. The delay should be added so that the internal microcontroller can prepare itself to accept commands. DSR From Powerdown If DSR powerdown is used when the part is in auto powerdown, the DSR powerdown will override the auto powerdown. However, when the part is awakened from DSR powerdown, the auto powerdown will once again become effective. Wake Up From Auto Powerdown If the FDC enters the powerdown state through the auto powerdown mode, wake up will occur after a reset or by access to the specific registers shown below. If a hardware or software reset is used the part will follow the normal reset sequence. If wake up occurs as a result of access through selected registers the FDC37N869 will resume normal operation as if the FDC had never powered-down. The following register accesses will wake up the FDC: 1. 2. 3. Enabling any one of the motor enable bits in the DOR register (reading the DOR does not awaken the part). A read from the MSR register. A read or write to the Data register. Once awake, the FDC37N869 will reinitiate the auto powerdown timer for 10ms. The FDC will powerdown again when all of the powerdown conditions are met. SMSC DS – FDC37N869 Page 93 Rev. 11/09/2000 Register Behavior Table 71 reiterates the available FDC PC/AT and PS/2, including Model 30 mode, registers. In order to maintain software transparency, access to all the registers must be maintained regardless of the power state. As Table 70 shows, two kinds of registers are identified based on whether access results in the FDC remaining in the powerdown state or not. Registers that will not awaken the FDC can be accessed during powerdown without changing the powerdown state but will reflect the true register status as shown in the FDC register description. For example, a write to one of these registers will result in the FDC retaining the data and subsequently using it appropriately when the block reawakens. During powerdown accessing FDC registers that do not affect the power state may increase device power consumption, but only until the register access has been completed. Table 70 - Available FDC PC/AT and PS/2 Registers AVAILABLE REGISTERS BASE + ADDRESS PC-AT PS/2 (Model 30) ACCESS PERMITTED Access to these registers DOES NOT wake up the FDC 00H 01H 02H 03H 04H 06H 07H 07H ------DOR --DSR --DIR CCR 1 1 SRA SRB DOR --DSR --DIR CCR 1 1 R R R/W --W --R W Access to these registers wakes up the FDC 04H 05H Note1: MSR DATA MSR DATA R R/W Writing to any of the motor enable bits in the DOR or doing a software reset via the DOR or DSR reset bits will wake up the FDC. Writing to any other DOR or DSR bits will not wake up the FDC. Pin Behavior The FDC37N869 is specifically designed for portable PC systems where power conservation is a primary concern. Consequently, the behavior of the device pins during powerdown very important. The pins of the FDC37N869 FDC can be divided into two major categories: system interface and floppy disk drive interface. When the FDC is powered down, the floppy disk drive pins are disabled so that no power will be drawn through the part as a result of any voltage applied to the pin within the part’s power supply range. Most of the system interface pins are left active to monitor system accesses that are intended to wake up the floppy controller. System Interface Pins Table 72 gives the state of the system interface pins in the powerdown state. Pins unaffected by the powerdown are labeled “Unchanged”. Input pins are “Disabled” to prevent them from causing currents internal to the FDC37N869 when they have indeterminate input values. SMSC DS – FDC37N869 Page 94 Rev. 11/09/2000 Table 71 - State of System Pins in Auto Powerdown SYSTEM PINS STATE IN AUTO POWERDOWN Input Pins IOR IOW A[0:9] D[0:7] RESET IDENT DACK TC Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Output Pins FINTR DB[0:7] FDRQ FDD Interface Pins All pins in the FDD interface that can be connected directly to the floppy disk drive itself are either DISABLED or TRISTATED. Pins used for local logic control or part programming are unaffected. Table 73 depicts the state of the floppy disk drive interface pins in the powerdown state. Table 72 - State of FDC Interface Pins in Powerdown FDD PINS STATE IN AUTO POWERDOWN Input Pins RDATA WP TRK0 INDX DRV2 DSKCHG Output Pins MOTEN[0:3] DS[0:3} DIR STEP WRDATA WE HDSEL DENSEL DRATE[0:1] Tristated Tristated Active Active Tristated Tristated Active Active Active Input Input Input Input Input Input Unchanged (low) Unchanged Unchanged (low) SMSC DS – FDC37N869 Page 95 Rev. 11/09/2000 UART Power Management Direct UART power management is controlled by the UART1 and UART2 Power Down bits in Configuration Register 2. Refer to section CR02 on page 106 for more information. UART Auto Power Management is enabled by the UART 1 and UART 2 Enable bits in Configuration Register 7 (see section CR07 on page 109). When set, these bits enable the following auto power management features: 1. The transmitter enters auto powerdown when the transmit buffer and transmit shift register are empty. 2. The receiver enters powerdown when the following conditions are all met: • Receive FIFO is empty • The receiver is waiting for a start bit. Note: While in the powerdown state, the Ring Indicator interrupts are still valid and are activated when the RI inputs change. The UART transmitters exit the powerdown state on a write to the XMIT buffer. The UART receivers exit the auto powerdown state when RXDx changes state. Parallel Port Direct parallel port power management is controlled by the Parallel Port Power bit in Configuration Register 1. Refer to section CR01 on page 104 for more information. Parallel port Auto Power Management is enabled by the Parallel Port Enable bit in Configuration Register 7 (see section CR07 on page 109). When set, this bit allows the ECP or EPP logical parallel port blocks to be placed into the powerdown state as follows: The EPP logic is in powerdown under any of the following conditions: 1. EPP is not enabled in the configuration registers. 2. EPP is not selected through ecr while in ECP mode. The ECP logic is in powerdown under any of the following conditions: 1. ECP is not enabled in the configuration registers. 2. SPP, PS/2 Parallel port or EPP mode is selected through ecr while in ECP mode. The parallel port logic can change powerdown modes when the ECP mode is changed through the ecr register or when the parallel port mode is changed through the configuration registers. SERIAL IRQ Introduction The FDC37N869 provides a serial interrupt interface to the host. This scheme adheres to the Serial IRQ Specification for PCI Systems, Version 6.0. The CLK33, SIRQ, and nCLKRUN pins are required for this interface. The Serial IRQ Enable bit D7 in CR29 activates the serial interrupt interface. The IRQ/Data serializer is a Wired-OR structure that simply passes the state of one or more device IRQs and/or Data to the Host Controller. The transfer can be initiated by either a device or the Host. Both high and low transitions are reported in this protocol. A transfer, called an IRQSER Cycle, consists of three frame types: 1. One START F rame 2. One or more IRQ/DATA Frames 3. One STOP F rame The Serial IRQ protocol uses the PCI Clock as its clock source. The PCI clock conforms to the PCI bus electrical specification. SMSC DS – FDC37N869 Page 96 Rev. 11/09/2000 IRQSER Cycle Modes There are two modes of operation for IRQSER cycles: Quiet (Active) Mode and Continuous (Idle) Mode. In Quiet Mode any device may initiate an IRQSER cycle. In Continuous Mode only the host controller can initiate an IRQSER cycle (FIGURE 4). Following a system reset the SIRQ bus defaults to Continuous Mode. IRQSER cycle mode transitions can only occur during the Stop Frame (FIGURE 5). Slaves must continuously sample the pulse width of the Stop Frame to determine the mode of the next IRQSER cycle (see the Stop Cycle Control section on page 99). SL or START FRAME H R T IRQ0 FRAME IRQ1 FRAME IRQ2 FRAME S R T S R T S R T H PCICLK IRQSER Drive Source IRQ1 START1 Host Controller None IRQ1 None FIGURE 4 - START FRAME TIMING W/SOURCE SAMPLED LOW PULSE ON IRQ1 Notes: H=Host Control SL=Slave Control R=Recovery 1. Start Frame pulse can be 4-8 clocks wide 2. PCICLK = CLK33 pin (33MHz PCI Clock input) 3. IRQSER = SIRQ pin T=Turn-around S=Sample IRQ14 FRAME SRT PCICLK IRQSER Driver None IRQ15 FRAME SRT IOCHCK# FRAME SRT STOP FRAME NEXT CYCLE T I 2 H R STOP 1 IRQ15 None Host Controller START3 FIGURE 5 - STOP FRAME TIMING W/HOST USING 17 IRQSER SAMPLING PERIOD Notes: H=Host Control R=Recovery T=Turn-around S=Sample I= Idle 1. STOP pulse is 2 clocks wide for Quiet mode, 3 clocks wide for Continuous mode. 2. There may be none, one or more Idle states during the Stop Frame. 3. The next IRQSER cycle’s Start Frame pulse may or may not start immediately after the turn-around clock of the Stop Frame. 4. PCICLK = CLK33 pin (33MHz PCI Clock input) 5. IRQSER = SIRQ pin Quiet (Active) Mode In Quiet Mode any device may initiate a Start Frame by driving the IRQSER low for one clock while the IRQSER is Idle (FIGURE 4). After driving low for one clock, slaves must immediately tristate IRQSER without at any time driving high. SMSC DS – FDC37N869 Page 97 Rev. 11/09/2000 A Start Frame may not be initiated while the IRQSER is Active. The IRQSER is Idle between Stop and Start Frames. The IRQSER is Active between Start and Stop Frames. Quiet Mode operation allows the IRQSER to be idle when there are no IRQ/Data transitions. Once a Start Frame has been initiated, the host controller will take over driving the IRQSER low in the next clock and will continue driving the IRQSER low for a programmable period of three to seven clocks. This makes a total low pulse width of four to eight clocks. Finally, the host controller will drive the IRQSER back high for one clock, then tri-state. Any IRQSER device (e.g., The FDC37N869) which detects any transition on an IRQ/Data line for which it is responsible must initiate a Start Frame in order to update the host controller unless the IRQSER is already in an IRQSER Cycle and the IRQ/Data transition can be delivered in that IRQSER Cycle. Continuous (Idle) Mode In Continuous Mode only the host controller can initiate a Start Frame to update IRQ/Data line information. All other IRQSER agents become passive and may not initiate a Start Frame. IRQSER Start Frame will be driven low for four to eight clocks by the Host Controller. Continuous Mode has serves two purposes: it can be used to stop or idle the IRQSER, or the host controller can operate IRQSER continuously by initiating a Start Frame at the end of every Stop Frame. IRQSER IRQ/Data Frames Once a Start Frame has been initiated, the FDC37N869 will watch for the rising edge of the Start Pulse and start counting IRQ/Data Frames. Each IRQ/Data Frame has three phases. Each phase takes one PCI clock: Sample phase, Recovery phase, and Turn-around phase. During the Sample phase the FDC37N869 must drive the IRQSER (SIRQ pin) low if and only if the last detected IRQ/Data value was low. If the last detected IRQ/Data value was high IRQSER must be left tristated. During the Recovery phase the FDC37N869 must drive the SIRQ high if and only if it had driven the IRQSER low during the previous Sample Phase. During the Turn-around Phase the FDC37N869 must tri-state SIRQ. The FDC37N869 will drive the IRQSER line low at the appropriate sample point if its associated IRQ/Data line is low, regardless of which device initiated the Start Frame. The Sample Phase for each IRQ/Data Frame follows the low to high transition of the Start Frame pulse by a number of clocks equal to the IRQ/Data Frame times three, minus one. For example, the IRQ5 S ample P hase occurs on 17th clock after the rising edge of the Start Pulse because IRQ5 is the sixth IRQ/Data Frame ((6 x 3) - 1 = 17). Table 73 - IRQSER Sampling Periods # OF CLOCKS PAST IRQSER PERIOD SIGNAL SAMPLED START 1 Not Used 2 2 IRQ1 5 3 IRQ2 8 4 IRQ3 11 5 IRQ4 14 6 IRQ5 17 7 IRQ6 20 8 IRQ7 23 9 IRQ8 26 10 IRQ9 29 11 IRQ10 32 12 IRQ11 35 13 IRQ12 38 SMSC DS – FDC37N869 Page 98 Rev. 11/09/2000 IRQSER PERIOD 14 15 16 SIGNAL SAMPLED IRQ13 IRQ14 IRQ15 # OF CLOCKS PAST START 41 44 47 The IRQSER IRQ/Data Frame will supports IRQ2 from a logical device. Previously, IRQSER Period 3 was reserved for use by the System Management Interrupt (nSMI). When using Period 3 for IRQ2 the user should mask off the SMI via the SMI Enable Register. Likewise, when using Period 3 for nSMI the user should not configure any logical devices as using IRQ2. Note: There is no SMI support in the FDC37N869. Stop Cycle Control Once all IRQ/Data Frames have completed, the host controller will terminate IRQSER activity by initiating a Stop Frame. Only the host controller can initiate the Stop Frame. A Stop Frame is indicated when the IRQSER is low for two or three clocks. If the Stop Frame is low for two clocks the next IRQSER Cycle operates in the Quiet mode and any IRQSER device may initiate a Start Frame in the second clock or more after the rising edge of the Stop Frame pulse. If the Stop Frame is low for three clocks the next IRQSER Cycle operates in Continuous mode and only the host controller may initiate a Start Frame in the second clock or more after the rising edge of the Stop Frame pulse. Latency Latency for IRQ/Data updates over the IRQSER bus in bridge-less systems with the minimum IRQ/Data Frames of seventeen will range up to 96 clocks (3.84uS with a 25MHz PCI Bus or 2.88uS with a 33MHz PCI Bus). If one or more PCI to PCI Bridges are added to a system, the latency for IRQ/Data updates from the secondary or tertiary buses will be a few clocks longer for synchronous buses, and approximately double for asynchronous buses. EOI/ISR Read Latency Any serialized IRQ scheme has a potential implementation issue related to IRQ latency. IRQ latency could cause an EOI or ISR Read to precede an IRQ transition that it should have followed. This could cause a system fault. The host controller is responsible for ensuring that these latency issues are mitigated. The recommended solution is to delay EOIs and ISR Reads to the interrupt controller by the same amount as the IRQSER Cycle latency in order to ensure that these events do not occur out of order. AC/DC Specification Issue All IRQSER agents must drive/sample IRQSER synchronously relative to the rising edge of the PCI bus clock. The IRQSER (SIRQ) pin uses the electrical specification of PCI bus. Reset and Initialization The IRQSER bus uses RESET_DRV as its reset signal. The IRQSER pin is tri-stated by all agents while RESET_DRV is active. Following reset, IRQSER Slaves are put into Continuous (IDLE) mode. The host controller is responsible for starting the initial IRQSER cycle to collect the system’s IRQ/Data default values. The system then follows with the Continuous/Quiet mode protocol as determined by the Stop Frame pulse width for subsequent IRQSER Cycles. It is the responsibility of the host controller to provide the default values to 8259’s and other system logic before the first IRQSER Cycle is performed. For IRQSER system suspend, insertion, or removal application, the host controller should be programmed in Continuous (IDLE) mode first. This is to guarantee that the IRQSER bus is in the IDLE state before the system configuration changes. SMSC DS – FDC37N869 Page 99 Rev. 11/09/2000 ADD PCI nCLKRUN SUPPORT Overview The FDC37N869 supports the PCI nCLKRUN signal. nCLKRUN is used to indicate the PCI clock status as well as to request that a stopped clock be started. See Figure 6 for an example of a typical system implementation using nCLKRUN. nCLKRUN support is required because the FDC37N869 interrupt interface relies entirely on Serial IRQs. If an SIO interrupt occurs while the PCI clock is stopped, nCLKRUN must be asserted before the interrupt can be serviced. If the FDC37N869 SIRQ_EN signal is inactive, nCLKRUN support is also disabled. The FDC37N869 nCLKRUN signal is multiplexed with nADRx on TQFP pin number 92. See Configuration Register CR03 for a description of the TQFP pin 92 multiplex controls. nCLKRUN is an open drain output and an input. Refer to the PCI Mobile Design Guide Rev 1.0 for a description of the nCLKRUN function. Using nCLKRUN If nCLKRUN is sampled “high”, the PCI clock is stopped or stopping. If nCLKRUN is sampled “low”, the PCI clock is starting or started (running). If a device in the FDC37N869 asserts or de-asserts an interrupt and nCLKRUN is sample “high”, the FDC37N869 can request the restoration of the clock by asserting the nCLKRUN signal asynchronously Table 74). The FDC37N869 holds nCLKRUN low until it detects two rising edges of the clock. After the second clock edge, the FDC37N869 must disable the open drain driver (Figure 7). The FDC37N869 will not assert nCLKRUN under any conditions if SIRQ_EN is inactive (“0”). The SIRQ_EN bit is D7 in CR29. The FDC37N869 must not assert nCLKRUN if it is already driven low by the central resource; i.e., the PCI CLOCK GENERATOR in Figure 6. The FDC37N869 must not assert nCLKRUN unless the line has been deasserted for two successive clocks; i.e., before the clock was stopped (Figure 7). Table 74 - FDC37N869 nCLKRUN Function INTERNAL (PARALLEL) INTERRUPTS nCLKRUN X NO CHANGE CHANGE1 X X 0 1 SIRQ_EN 1 0 ACTION None None None Assert nCLKRUN Note1: “Change” means either-edge change on any or all parallel IRQs routed to the SIRQ block. The “change” detection logic must run asynchronously to the PCI Clock and regardless of the SIRQ mode; i.e., “continuous” or “quiet”. SMSC DS – FDC37N869 Page 100 Rev. 11/09/2000 MASTER TARGET FDC37N869 PCICLK nCLKRUN PCI CLOCK GENERATOR (Central Resource) FIGURE 6 - nCLKRUN SYSTEM IMPLEMENTATION EXAMPLE SIRQ_EN nCLKRUN DRIVEN BY 869 1,2 ANY IRQ CHANGE nCLKRUN CLK33 2 CLKS MIN. 869 STOPS DRIVING nCLKRUN FIGURE 7 - CLOCK START ILLUSTRATION Note 1: Note 2: The signal “ANY IRQ CHANGE” is the same as “CHANGE” in Table 72. The FDC37N869 must continually monitor the state of nCLKRUN to maintain the PCI Clock until an active “ANY IRQ CHANGE” condition has been transferred to the host in a Serial IRQ cycle. For example, if “ANY IRQ CHANGE” is asserted before nCLKRUN is de-asserted (not shown in Figure 7), the FDC37N869 must assert nCLKRUN as needed until the Serial IRQ cycle has completed. CONFIGURATION The configuration of the FDC37N869 is programmed through hardware selectable Configuration Access Ports that appear when the chip is placed into the configuration state. The FDC37N869 logical device blocks, if enabled, will operate normally in the configuration state. Configuration Access Ports The Configuration Access Ports are the CONFIG PORT, the INDEX PORT, and the DATA PORT (Table 75). The base address of these registers is controlled by the nRTS2/SYSOPT pin (see Table 1) and by the Configuration Port Base Address registers CR12 and CR13. To determine the configuration base address at power-up, the state of the nRTS2/SYSOPT pin is latched by the falling edge of a hardware reset. If the latched state is a 0, the base address of the Configuration Access Ports is located at address 3F0H; if the latched state is a 1, the base address is located at address 370H. SMSC DS – FDC37N869 Page 101 Rev. 11/09/2000 PORT NAME CONFIG PORT INDEX PORT DATA PORT Note1: Note2: Table 75 - Configuration Access Ports SYSOPT = 0 SYSOPT = 1 0x3F0 0x370 0x3F0 0x370 INDEX PORT + 1 TYPE WRITE READ/WRITE1,2 READ/WRITE1 The INDEX and DATA ports are active only when the FDC37N869 is in the configuration state. The INDEX PORT is only readable in the configuration state. Configuration State The configuration registers are used to select programmable chip options. The FDC37N869 operates in two possible states: the run state and the configuration state. After power up by default the chip is in the run state. To program the configuration registers, the configuration state must be explicitly enabled. Programming the configuration registers typically follows this sequence: 1. Enter the Configuration State, 2. Program the Configuration Register(s), 3. Exit the Configuration State. Entering the Configuration State To enter the configuration state write the Configuration Access Key to the CONFIG PORT. The Configuration Access Key is one byte of 55H data. The FDC37N869 will automatically activate the Configuration Access Ports following this procedure. Configuration Register Programming The FDC37N869 contains configuration registers CR00-CR2F. After the FDC37N869 enters the configuration state, configuration registers can be programmed by first writing the register index number (00 - 2FH) to the Configuration Select Register (CSR) through the INDEX PORT and then writing or reading the configuration register contents through the DATA PORT. Configuration register access remains enabled until the configuration state is explicitly exited. Exiting the Configuration State To exit the configuration state, write one byte of AAH data to the CONFIG PORT. The FDC37N869 will automatically deactivate the Configuration Access Ports following this procedure, at which point configuration register access cannot occur until the configuration state is explicitly re-enabled. Programming Example The following is a configuration register programming example written in Intel 8086 assembly language. ;-----------------------------. ; ENTER CONFIGURATION STATE | ;-----------------------------‘ MOV DX,3F0H ;SYSOPT = 0 MOV AX,055H OUT DX,AL ;-----------------------------. ; CONFIGURE REGISTERS CR0-CRx | ;-----------------------------‘ MOV DX,3F0H MOV AL,00H OUT DX,AL ;Point to CR0 MOV DX,3F1H MOV AL,3FH OUT DX,AL ;Update CR0 ; MOV DX,3F0H SMSC DS – FDC37N869 Page 102 Rev. 11/09/2000 MOV AL,01H OUT DX,AL ;Point to CR1 MOV DX,3F1H MOV AL,9FH OUT DX,AL ;Update CR1 ; ; Repeat for all CRx registers ; ;-----------------------------. ; EXIT CONFIGURATION STATE | ;-----------------------------‘ MOV DX,3F0H MOV AX,AAH OUT DX,AL Configuration Select Register (CSR) The Configuration Select Register can only be accessed when the FDC37N869 is in the configuration state. The CSR is located at the INDEX PORT address and must be initialized with configuration register index before the register can be accessed using the DATA PORT. Configuration Registers Description The configuration registers are set to their default values at power up (Table 76) and are not affected by RESET, except where noted in the register descriptions that follow. Table 76 - Configuration Registers DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Valid Reserved FDC PWR Reserved Reserved Lock Reserved PP MODE PP PWR Reserved CRx CR02 UART2 Reserved UART1 Reserved PWR PWR CR03 ADRX/ IDENT MFM DRV Reserved ADRX/ Enhanced PWRGD/ nCLKR DEN 1 nCLKRUN FDC Mode GAMECS UN 2 CR04 Reserve EPP MIDI 2 MIDI 1 Parallel Port FDC PP Ext. Modes d Type CR05 Reserved DEN SEL FDC DMA FDC Output Type Mode Control CR06 FDD3 - ID FDD2 - ID FDD1 - ID FDD0 - ID CR07 Auto Power Management Reserved Floppy Boot Drive CR08 ADRA7 ARDA6 ADRA5 ADRA4 0 0 0 0 CR09 ADRx Config Cntrl Reserved ADRA11 ADRA10 ADRA9 ADRA8 CR0A IR Output MUX Reserved ECP FIFO Threshold CR0B FDD3-DRTx FDD2-DRTx FDD1-DRTx FDD0-DRTx CR0C UART 2 UART 1 UART 2 Mode UART 2 UART 2 UART 2 Speed Speed Duplex XMIT RCV Polarity Polarity CR0D Device ID CR0E Device Revision CR0F Test 7 Test 6 Test 5 Test 4 Test 3 Test 2 Test 1 Test 0 CR10 Test 15 Test 14 Test 13 Test 12 Test 11 Test 10 Test 9 Test 8 CR11 Test 23 Test 22 Test 21 Test 20 Test 19 Test 18 Test 17 Test 16 CR12 Configuration Ports Base Address [7:1] 0 CR13 Configuration Ports Base Address [10:8] CR14 Floppy Data Rate Select Shadow INDEX CR00 CR01 DEFAULT 28H 9CH 88H 70H 00H 00H FFH 00H 00H 00H 00H 00H 02H 29H Revision 00H 00H 80H Note1 Note1 - SMSC DS – FDC37N869 Page 103 Rev. 11/09/2000 DEFAULT INDEX DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 CR15 UART1 FIFO Control Shadow CR16 UART2 FIFO Control Shadow 03H CR17 Force FDD Status Change 00H CR18 Reserved CR1D 80H CR1E GAMECS - ADR[9:4] GAMECS CONFIG 00H CR1F FDD3-DTx FDD2-DTx FDD1-DTx FDD0-DTx 3CH CR20 FDC - ADR[9:4] 0 0 00H CR21 Reserved 00H CR22 Reserved Parallel Port ECP IRQ Select Parallel Port ECP DMA Select 00H CR23 Parallel Port - ADR[9:2] 00H CR24 Serial Port 1 - ADR[9:3] 0 00H CR25 Serial Port 2 - ADR[9:3] 0 00H CR26 FDC DMA Select Parallel Port DMA Select 00H CR27 FDC IRQ Select Parallel Port IRQ Select 00H CR28 Serial Port 1 IRQ Select Serial Port 2 IRQ Select 00H CR29 SIRQ_EN Reserved HPMODE IRQIN IRQ Select 00H CR2A Reserved 00H CR2B FIR Base I/O ADDR[10:3] 0FH CR2C Reserved Serial Port 2 DMA Select 03H CR2D IR Half Duplex Time-Out 00H CR2E Software Select A 00H CR2F Software Select B Note1: CR00 CR00 can only be accessed in the configuration state and after the CSR has been initialized to 00H. The default value of this register after power up is 28H (Table 77). Table 77 - CR00 BIT NO. 0:2 3 4,5,6 7 BIT NAME Reserved FDC Power Reserved Valid 1 Refer to sections CR12 - CR13 on page 112. DESCRIPTION Read Only. A read returns 0 A high level on this bit, supplies power to the FDC (default). A low level on this bit puts the FDC in low power mode. Read only. A read returns bit 5 as a 1 and bits 4 and 6 as a 0. A high level on this software controlled bit can be used to indicate that a valid configuration cycle has occurred. The control software must take care to set this bit at the appropriate times. Set to zero after power up. This bit has no effect on any other hardware in the chip. Note1: Power Down bits disable the respective logical device and associated pins, however the power down bit does not disable the selected address range for the logical device. To disable the host address registers the logical device’s base address must be set below 100h. Devices that are powered down but still reside at a valid I/O base address will participate in Plug-and-Play range checking. CR01 CR01 can only be accessed in the configuration state and after the CSR has been initialized to 01H. The default value of this register after power up is 9CH (Table 78). SMSC DS – FDC37N869 Page 104 Rev. 11/09/2000 Table 78 - CR01 BIT NO. 0,1 2 BIT NAME Reserved Parallel Port Power1 Parallel Port Mode Reserved Reserved Lock CRx DESCRIPTION Read Only. A read returns “0”. A high level on this bit, supplies power to the Parallel Port (Default). A low level on this bit puts the Parallel Port in low power mode. Parallel Port Mode. A high level on this bit, sets the Parallel Port for Printer Mode (Default). A low level on this bit enables the Extended Parallel port modes. Refer to Bits 0 and 1 of CR4 Read Only. A read returns “1”. Read Only. A read returns “0”. A high level on this bit enables the reading and writing of CR00 CR2F (Default). A low level on this bit disables the reading and writing of CR00 - CR2F. Note: once the Lock Crx bit is set to “0”, this bit can only be set to “1” by a hard reset or power-up reset. 3 4 5,6 7 Note1: Power Down bits d isable the respective logical device and associated pins, however the power down bit does not disable the selected address range for the logical device. To disable the host address registers the logical device’s base address must be set below 100h. Devices that are powered down but still reside at a valid I/O base address will participate in Plug-and-Play range checking. SMSC DS – FDC37N869 Page 105 Rev. 11/09/2000 CR02 CR02 can only be accessed in the configuration state and after the CSR has been initialized to 02H. The default value of this register after power up is 88H (Table 79). Table 79 - CR02 BIT NO. 0:2 3 BIT NAME Reserved UART1 Power Down 1 DESCRIPTION Read Only. A read returns “0”. A high level on this bit, allows normal operation of the Primary Serial Port (Default). A low level on this bit places the Primary Serial Port into Power Down Mode. Read Only. A read returns “0”. 1 4:6 7 Reserved UART2 Power Down A high level on this bit, allows normal operation of the Secondary Serial Port, including the SCE/FIR block (Default). A low level on this bit places the Secondary Serial Port including the SCE/FIR block into Power Down Mode. Note1: Power Down bits disable the respective logical device and associated pins, however the power down bit does not disable the selected address range for the logical device. To disable the host address registers the logical device’s base address must be set below 100h. Devices that are powered down but still reside at a valid I/O base address will participate in Plug-and-Play range checking. CR03 CR03 can only be accessed in the configuration state and after the CSR has been initialized to 03H. The default value after power up is 70H (Table 80). Table 80 - CR03 BIT NO. 0 BIT NAME PWRGD/ GAMECS Enhanced Floppy Mode 2 DESCRIPTION Pin function PWRGD (default) GAMECS Floppy Mode - Refer to the description of the Bit 1 TAPE DRIVE REGISTER (TDR) for more information on these modes. 0 NORMAL Floppy Mode (Default) 1 Enhanced Floppy Mode 2 (OS2) Reserved - Read as zero Bit 4 Pin DRVDEN1 Output1 0 Output Programmed DRVDEN1 Value 1 Force DRVDEN1 Output High (default) IDENT is used in conjunction with MFM to define the FDC interface mode. IDENT MFM MODE 1 1 AT Mode (Default) 1 0 Reserved 0 1 PS/2 0 0 Model 30 Bit - 7 Bit - 2 Pin 92 (TQFP) 0 x Reserved2 1 0 nADRX 1 1 nCLKRUN Bit 0 0 1 1 3 4 Reserved DRVDEN1 5 6 MFM IDENT 7,2 nADRx/nCLKRUN Note1: Note2: See NOTE2 in section CR05 on page 108. Pin 92 (TQFP) is tri-stated at power-up. SMSC DS – FDC37N869 Page 106 Rev. 11/09/2000 CR04 CR04 can only be accessed in the configuration state and after the CSR has been initialized to 04H. The default value after power up is 00H (Table 81). Table 81 - CR04: Parallel and Serial Extended Setup Register BIT NO. 1,0 BIT NAME Parallel Port Extended Modes Bit 1 0 0 1 1 2,3 Parallel Port FDC Bit 0 0 1 0 1 DESCRIPTION If CR1 bit 3 is a low level then: Standard and Bi-directional Modes (SPP) (default) EPP Mode and SPP ECP Mode2 ECP Mode & EPP Mode1,2 Refer to Parallel Port Floppy Disk Controller description. Bit 3 0 0 1 1 Bit 2 0 1 0 1 Normal PPFD1 PPFD2 Reserved 4 MIDI 1 3 Serial Clock Select Port 1: A low level on this bit, disables MIDI support, clock = divide by 13 (default). A high level on this bit enables MIDI support, clock = divide by 12. Serial Clock Select Port 2: A low level on this bit, disables MIDI support, clock = divide by 13 (default). A high level on this bit enables MIDI support, clock = divide by 12. 0 = EPP 1.9 (default) 1 = EPP 1.7 Reserved - Read as 0. 5 MIDI 2 3 6 7 EPP Type Reserved4 Note1: In this mode, EPP can be selected through the ecr register of ECP as mode 100. Note2: In these modes, 2 drives can be supported directly, 3 or 4 drives must use external 4 drive support. SPP can be selected through the ecr register of ECP as mode 000. Note3: MIDI Support: The Musical Instrumental Digital Interface (MIDI) operates at 31.25Kbaud (+/-1%) which can be derived from 125KHz. (24 MHz/12=2 MHz, 2 MHz/16=125 kHz). Note4: The function of this bit has been modifi ed from the FDC37C669. This bit’s former function, the selection of the pins for IR receive and transmit, has been moved to CR0A. SMSC DS – FDC37N869 Page 107 Rev. 11/09/2000 CR05 CR05 can only be accessed in the configuration state and after the CSR has been initialized to 05H. The default value after power up is 00H (Table 82). Table 82 - CR05: Floppy Disk Setup Register BIT NO. 01 BIT NAME FDC Output Type Control (R/W) FDC Output Control (R/W) FDC DMA Mode DenSel DESCRIPTION 0 = FDC Outputs are open drain (default). 1 = FDC Outputs are push-pull. 11,2 0 = FDC Outputs Active (default). 1 = FDC Outputs Tri-State. 2 4,3 5-7 Reserve d 0 = Burst mode is enabled for the FDC FIFO execution phase data transfers (default). 1 = Non-Burst mode enabled. The FDRQ and FIRQ pins are strobed once for each byte transferred while the FIFO is enabled. BIT 4 BIT 3 DENSEL OUTPUT 0 0 Normal (default) 0 1 Reserved 1 0 1 1 1 0 Read Only. A read returns 0. Note1: Note2: Bits CR05[1:0] do not affect the Parallel Port FDC. In the FDC37N869, the behavior of the DRVDEN1 Control CR03.4 depends upon the FDC Output Control CR05.1 (Table 82). If the FDC Output Control is active DRVDEN1 will behave as described in the 669FR; i.e., if CR03.4 is 0 the DRVDEN1 output pin assumes the value of the DRVDEN1 function, if CR03.4 is 1 the DRVDEN1 output pin stays high. If the FDC Output Control is inactive the DRVDEN1 Control will have no affect on the DRVDEN1 output pin. Table 83 - DRVDEN1 Control FDC OUTPUT CONTROL (CR05.1) 0 0 1 DRVDEN1 CONTROL (CR03.4) 0 1 X DRVDEN1 (PIN 18) 1/0 1 TRISTATE DESCRIPTION NORMAL DRVDEN1 FUNCTION DRVDEN1 FORCED HIGH ALL FDD OUTPUT PINS ARE TRISTATED CR06 CR06 can only be accessed in the configuration state and after the CSR has been initialized to 06H. The default value of this register after power up is FFH (Table 84). CR06 holds the floppy disk drive type IDs for up to four floppy disk drives (see section Drive Type ID, Bits 4 - 5 on page 25). Table 84 - DR06: Drive Type ID Register FDD2 FDD1 D6 ID30 D5 ID21 D4 ID20 D3 ID11 D2 ID10 D1 ID01 FDD3 D7 ID31 FDD0 D0 ID00 SMSC DS – FDC37N869 Page 108 Rev. 11/09/2000 CR07 CR07 can only be accessed in the configuration state and after the CSR has been initialized to 07H. The default value of this register after power up is 00H (Table 85). CR07 controls auto power management and the floppy boot drive. Table 85 - CR07: Auto Power Management and Boot Drive Select BIT NAME DESCRIPTION Floppy Boot This bit is used to define the boot floppy. 0 = Drive A (default) 1 = Drive B Read as 0. Read as 0. This bit controls the AUTOPOWER DOWN feature of the Parallel Port. The function is: 0 = Auto powerdown disabled (default) 1 = Auto powerdown enabled This bit is reset to the default state by POR or a hardware reset. This bit controls the AUTOPOWER DOWN feature of the UART2. The function is: 0 = Auto powerdown disabled (default) 1 = Auto powerdown enabled This bit is reset to the default state by POR or a hardware reset. This bit controls the AUTOPOWER DOWN feature of the UART1. The function is: 0 = Auto powerdown disabled (default) 1 = Auto powerdown enabled This bit is reset to the default state by POR or a hardware reset. This bit controls the AUTOPOWER DOWN feature of the Floppy Disk. The function is: 0 = Auto powerdown disabled (default) 1 = Auto powerdown enabled (See Note in the “FDC Power Management” section) This bit is reset to the default state by POR or a hardware reset. BIT NO. 0,1 2 3 4 Reserved Reserved Parallel Port Enable 5 UART 2 Enable 6 UART 1 Enable 7 Floppy Disk Enable CR08 CR08 can only be accessed in the configuration state and after the CSR has been initialized to 08H. The default value of this register after power up is 00H (Table 86). CR08 contains the lower 4 bits (ADRA7:4) for the ADRx address decoder. Bits D0 - D3 are Reserved. Reserved bits cannot be written and return 0 when read. Table 86 - CR08: ADRx Lower Address Decode D5 D4 D3 D2 ADRA5 ADRA4 Reserved D7 ADRA7 D6 ADRA6 D1 D0 CR09 CR09 can only be accessed in the configuration state and after the CSR has been initialized to 09H. The default value of this register after power up is 00H (Table 87). CR09 contains the upper 4 bits (ADRA11:8) of the ADRx address decoder and the ADRx Configuration Control Bits D[7:6]. The ADRx Configuration Control Bits configure the ADRx Address Decoder (Table 88). To activate the FDC37N869 nADRx output, the system address bus bits A11 to A4 must match the values programmed in CR08 and CR09 and address bits A12 to A15 must be ‘0000b’. SMSC DS – FDC37N869 Page 109 Rev. 11/09/2000 D7 Table 87 - CR09: ADRx Upper Address Decoder and Configuration D6 D5 D4 D3 D2 D1 Reserved ADRA11 ADRA10 ADRA9 D0 ADRA8 ADRx CONFIGURATION CONTROL Table 88 - ADRx Configuration Bits ADRx CONFIGURATION CONTROL DESCRIPTION D7 D6 0 0 ADRx disabled 0 1 1 Byte decode A[3:0]=0000b 1 0 8 Byte block decode A[3:0]=0XXXb 1 1 16 byte block decode A[3:0]=XXXXb CR0A CR0A can only be accessed in the configuration state and after the CSR has been initialized to 0AH. The default value of this register after power up is 00H (Table 88). CR0A defines the FIFO threshold for the ECP mode parallel port. Bits D[5:4] are Reserved. Reserved Bits cannot be written and return 0 when read. Bits D[7:6] are the IR OUTPUT MUX bits (Table 89) and are reset to the default state by a POR or a hardware reset. Table 89 - CR0A D4 D3 D7 D6 D5 D2 D1 D0 IR OUTPUT MUX (see Table 90) RESERVED THR3 ECP FIFO THRESHOLD THR2 THR1 THR0 D7 0 0 1 1 D6 0 1 0 1 Table 90 - CR0A: IR OUTPUT MUX Bits Mux Mode Active device to COM port (Default). That is, use pins IRRX and IRTX (pins 88 and 89). Active device to IR port. That is, use IRRX2, IRTX2 (pins 23, 24). Reserved. Outputs Inactive: IRTX and IRTX2 are High-Z. Note: The function of the IR OUTPUT MUX bits and how they are reset has been modified from the FDC37C669. The first two options were previously selected through CR04. CR0B CR0B can only be accessed in the configuration state and after the CSR has been initialized to 0BH. The default value of this register after power up is 00H (Table 91). CR0B indicates the Drive Rate table used for each drive (see Table 20). Refer to section CR1F on page 114 for the Drive Type register. Table 91 - CR0B FDD3 D7 DRT1 D6 DRT0 D5 DRT1 FDD2 D4 DRT0 D3 DRT1 FDD1 D2 DRT0 D1 DRT1 FDD0 D0 DRT0 SMSC DS – FDC37N869 Page 110 Rev. 11/09/2000 CR0C CR0C can only be accessed in the configuration state and after the CSR has been initialized to 0CH. The default value of this register after power up is 02H (Table 92). CR0C controls the operating mode of the UART. This register is reset to the default state by a POR or a hardware reset. Table 92 - CR0C BIT NO. 0 1 2 BIT NAME UART 2 RCV Polarity UART 2 XMIT Polarity DESCRIPTION 0 = RX input active high (default). 1 = RX input active low. 0 = TX output active high. 1 = TX output active low (default). UART 2 Duplex This bit is used to define the FULL/HALF DUPLEX operation of UART 2. 1 = Half duplex 0 = Full duplex (default) UART 2 MODE UART 2 Mode 543 0 0 0 Standard (default) 0 0 1 IrDA (HPSIR) 0 1 0 Amplitude Shift Keyed IR @ 500kHz 0 1 1 Reserved 1xx Reserved UART 1 Speed This bit enables the high speed mode of UART 1. 1 = High speed enabled 0 = Standard (default) UART Speed This bit enables the high speed mode of UART 2. 1 = High speed enabled 0 = Standard (default) 3, 4, 5 6 7 CR0D CR0D can only be accessed in the configuration state and after the CSR has been initialized to 0DH. This register is read only. CR0D contains the FDC37N869 Device ID. The default value of this register after power up is 29H. CR0E CR0E can only be accessed in the configuration state and after the CSR has been initialized to 0EH. This register is read only. CR0E contains the current FDC37N869 Chip Revision Level starting at 00H. CR0F CR0F can only be accessed in the configuration state and after the CSR has been initialized to 0FH. The default value of this register after power up is 00H (Table 93). CR0F is a test control register and all bits must be treated as Reserved. Note: all test modes are reserved for SMSC use. Activating test mode registers may produce undesired results. Table 93 - CR0F BIT NAME DESCRIPTION Test 0 Test 1 Test 2 Test 3 RESERVED FOR SMSC USE Test 4 Test 5 Test 6 Test 7 BIT NO. 0 1 2 3 4 5 6 7 SMSC DS – FDC37N869 Page 111 Rev. 11/09/2000 CR10 CR10 can only be accessed in the configuration state and after the CSR has been initialized to 10H. The default value of this register after power up is 00H (Table 94). CR10 is a test control register and all bits must be treated as Reserved. NOTE: All test modes are reserved for SMSC use. Activating test mode registers may produce undesired results. Table 94 - CR10 BIT NAME DESCRIPTION Test 8 Test 9 Test 10 Test 11 RESERVED FOR SMSC USE Test 12 Test 13 Test 14 Test 15 BIT NO. 0 1 2 3 4 5 6 7 CR11 CR11 can only be accessed in the configuration state and after the CSR has been initialized to 11H. The default value of this register after power up is 80H (Table 95). CR11 is a test control register and all bits must be treated as Reserved. NOTE: all test modes are reserved for SMSC use. Activating test mode registers may produce undesired results. Table 95 - CR11 BIT NAME DESCRIPTION Test 16 Test 17 Test 18 Test 19 RESERVED FOR SMSC USE Test 20 Test 21 Test 22 Test 23 BIT NO. 0 1 2 3 4 5 6 7 CR12 - CR13 CR12 and CR13 are the FDC37N869 Configuration Ports base address registers (Table 96). These registers are used to relocate the Configuration Ports base address beyond the power-up defaults determined by the SYSOP pin programming. CR12 contains the Configuration Ports base address bits A[7:0]. CR13 contains the Configuration Ports base address bits A[10:8]. The Configuration Ports base address is relocatable on even-byte boundaries; i.e., A0 = ‘0’. At power-up the Configuration Ports base address is determined by the SYSOP pin programming. To relocate the Configuration Ports base address after power-up, first write the lower address bits of the new base address to CR12 and then write the upper address bits to CR13. Note: Writing CR13 changes the Configuration Ports base address. SMSC DS – FDC37N869 Page 112 Rev. 11/09/2000 INDEX 0x122 0x131 R/W R/W R/W Table 96 - Configuration Ports Base Address Registers CONFIGURATION PORTS BASE ADDRESS HARD RESET VCC POR REGISTERS D7 D6 D5 D4 D3 D2 D1 D0 SYSOP=0: 0xF0 SYSOP=0: 0xF0 A7 A6 A5 A4 A3 A2 A1 “0” SYSOP=1: 0x70 SYSOP=1: 0x70 SYSOP=0: 0 X03 SYSOP=0: 0x03 “0” “0” “0” “0” “0” A10 A9 A8 SYSOP=1: 0x03 SYSOP=1: 0x03 Note1: Note2: CR14 Writing CR13 changes the Configuration Ports base address. The Configuration Ports Base Address is relocatable on even-byte boundaries; i.e., A0 = “0”. CR14 can only be accessed in the configuration state and after the CSR has been initialized to 14H. CR14 shadows the bits in the write-only FDC run-time DSR register (Table 97). Table 97 - CR14: DSR Shadow Register D5 D4 D3 D2 D1 Res. PREPREPREDATA COMP COMP COMP RATE 2 1 0 SELECT 1 CR 14 R D7 SOFT RESET D6 PWR DOWN D0 DATA RATE SELEC T0 Default N/A CR15 CR15 can only be accessed in the configuration state and after the CSR has been initialized to 15H. CR15 shadows the bits in the write-only UART1 run-time FCR register (Table 98). Table 98 - CR15: UART1 FCR Shadow Register D6 D5 D4 D3 D2 D1 RCVR TRIGGER LSB Reserved DMA MODE SELECT XMIT FIFO RESET RCVR FIFO RESET D7 CR 15 R RCVR TRIGGER MSB D0 FIFO ENABLE Default N/A CR16 CR161 can only be accessed in the configuration state and after the CSR has been initialized to 16H. CR16 shadows the bits in the write-only UART2 run-time FCR register (Table 99). Table 99 - CR16: UART2 FCR Shadow Register D6 D5 D4 D3 D2 D1 RCVR TRIGGER LSB Reserved DMA MODE SELECT XMIT FIFO RESET RCVR FIFO RESET D7 CR16 R RCVR TRIGGER MSB D0 FIFO ENABLE Default N/A CR17 CR17 can only be accessed in the configuration state and after the CSR has been initialized to 17H. The default value of this register after power up is 003H (Table 100). CR17 is the Force FDD Status Change register. Table 100 - CR17: Force FDD Status Change Register D5 D4 D3 D2 D1 RESERVED FORCE WRTPRT FORCE DSKCHG1 D7 CR1 7 R/W D6 D0 FORCE DSKCHG0 Default 0x03 RESERVED Note: The controls in the Force FDD Status Change register (CR17) apply to the FDD Interface pins as well as to the Parallel Port FDC. SMSC DS – FDC37N869 Page 113 Rev. 11/09/2000 Force Disk Change, Bits 0 - 1 Setting either of the Force Disk Change bits active (1) forces the FDD nDSKCHG input active when the appropriate drive has been selected. FORCE DSKCHG1 and FORCE DSKCHG0 can be written to a 1 but are not clearable by software. FORCE DSKCHG1 is cleared on (nSTEP AND nDS1), FORCE DSKCHG0 is cleared on (nSTEP AND nDS0). Note: The DSK CHG bit in the Floppy DIR register, Bit 7 = (nDS0 AND FORCE DSKCHG0) OR (nDS1 AND FORCE DSKCHG1) OR nDSKCHG. Force Write Protect, Bit 2 FORCE WRTPRT asserts the internal nWRTPRT input to the controller when the FORCE WRTPRT bit is active (“1”) and a drive has been selected. The FORCE WRTPRT function applies to the nWRTPRT pin in the FDD Interface as well as the nWRTPRT pin in the Parallel Port FDC. CR18 - CR1D CR18 - CR1D registers are Reserved. Reserved registers cannot be written and return 0 when read. The default value of these registers after power up is 00H. CR1E CR1E register can only be accessed in the configuration state and after the CSR has been initialized to 1EH. The default value of this register after power up is 80H (Table 101). CR1E is used to select the base address of the Game Chip Select decoder (GAMECS). The GAMECS can be set to 48 locations on 16 byte boundaries from 100H-3F0H. To disable the GAMECS, set DB1 and DB0 to zero (Table 102). Table 101 - CR1E DB4 DB3 ADR6 ADR5 DB7 ADR9 DB6 ADR8 DB5 ADR7 DB2 ADR4 DB1 DB0 GAMECS CONFIG (see Table 100) Table 102 - GAMECS Configuration Bits GAMECS CONFIGURATION DESCRIPTION DB1 0 0 1 1 DB0 0 1 0 1 GAMECS disabled 1 Byte decode, ADR[3:0] = 0001b 8 Byte block decode, ADR[3:0] = 0XXXb 16 byte block decode, ADR[3:0] = XXXXb Upper Address Decode requirements: nCS=’0’ and A10=’0’ are required to qualify the GAMECS output. CR03.0, the PWRGD/GAMECS control bit, overrides the selection made by the GAMECS Configuration Bits. CR1F CR1F can only be accessed in the configuration state and after the CSR has been initialized to 1FH. The default value of this register after power up is 00H (Table 103). CR1F indicates the floppy disk Drive Type for each of four floppy disk drives. The floppy disk Drive Type is used to map the three FDC DENSEL, DRATE1 and DRATE0 outputs onto two Super I/O output pins DRVDEN1 and DRVDEN0 (Table 104). SMSC DS – FDC37N869 Page 114 Rev. 11/09/2000 Table 103 - CR1F FDD3 D7 DT0 D6 DT1 D5 DT0 FDD2 D4 DT1 D3 DT0 FDD1 D2 DT1 D1 DT0 FDD0 D0 DT1 DRIVE TYPE DT0 DT1 0 0 DRVDEN0 DENSEL Table 104 - Drive Type Encoding DRVDEN1 DRIVE TYPE DESCRIPTION DRATE0 4/2/1 MB 3.5” 2/1 MB 5.25” FDDS 2/1.6/1 MB 3.5” (3-MODE) DRATE0 DRATE0 DRATE1 PS/2 0 1 1 CR20 1 0 1 DRATE1 nDENSEL DRATE0 CR20 can only be accessed in the configuration state and after the CSR has been initialized to 20H. The default value of this register after power up is 3CH (Table 105). CR20 is used to select the base address of the floppy disk controller (FDC). The FDC base address can be set to 48 locations on 16 byte boundaries from 100H - 3F0H. To disable the FDC set ADR9 and ADR8 to zero. Set CR20.[1:0] to 00b when writing the FDC Base Address. FDC Address Decoding: nCS = ’0’ and A10 = ’0’ are required to access the FDC registers. A[3:0] are decoded as 0XXXb. Table 105 - CR20: FDC Base Address Register DB5 DB4 DB3 DB2 ADR7 ADR6 ADR5 ADR4 DB7 ADR9 CR21 DB6 ADR8 DB1 0 DB0 0 Register CR21 is Reserved. Reserved bits cannot be written and return 0 when read. CR22 The ECP Software Select register CR22 contains the ECP IRQ Select bits and the ECP DMA Select bits (Table 106). CR22 is part of the ECP DMA/IRQ Software Indicators described in the ECP cnfgB register. CR22 is read/write. Note: all of the ECP DMA/IRQ Software Indicators, including CR22, are software-only. Writing these bits does not affect the ECP hardware DMA or IRQ channels that are configured in CR26 and CR27. Table 106 - ECP Software Select Register (CR22) VCC POR DESCRIPTION D7 D6 D5 D4 D3 0x00 Reserved ECP IRQ Select INDEX 0x22 CR23 R/W R/W HARD RESET 0x00 D2 D1 D0 ECP DMA Select CR23 can only be accessed in the configuration state and after the CSR has been initialized to 23H. The default value of this register after power up is 00H (Table 107). CR23 is used to select the base address of the parallel port. If EPP is not enabled, the parallel port can be set to 192 locations on 4-byte boundaries from 100H - 3FCH; if EPP is enabled, the parallel port can be set to 96 locations on 8-byte boundaries from 100H - 3F8H (Table 108). To disable the parallel port, set ADR9 and ADR8 to zero. Parallel Port Address Decoding: nCS = ’0’ and A10 = ’0’ are required to access the Parallel Port when in Compatible, Bi-directional, or EPP modes. A10 is active when in ECP mode. SMSC DS – FDC37N869 Page 115 Rev. 11/09/2000 DB7 ADR9 DB6 ADR8 Table 107 - CR23: Parallel Port Base Address Register DB5 DB4 DB3 DB2 DB1 ADR7 ADR6 ADR5 ADR4 ADR3 Table 108 - Parallel Port Addressing Options EPP ENABLED ADDRESSING (LOW BITS) DECODE No A[1:0] = XXb Yes A[2:0] = XXXb DB0 ADR2 CR24 CR24 can only be accessed in the configuration state and after the CSR has been initialized to 24H. The default value of this register after power up is 00H (Table 109). CR24 is used to select the base address of Serial Port 1 (UART1). The serial port can be set to 96 locations on 8-byte boundaries from 100H - 3F8H. To disable Serial Port 1, set ADR9 and ADR8 to zero. Set CR24.0 to 0 when writing the UART1 Base Address. Serial Port 1 Address Decoding: nCS = ’0’ and A10 = ’0’ are required to access UART1 registers. A[ 2:0] are decoded as XXXb. Table 109 - CR24: UART1 Base Address Register DB5 DB4 DB3 DB2 ADR7 ADR6 ADR5 ADR4 DB7 ADR9 CR25 DB6 ADR8 DB1 ADR3 DB0 0 CR25 can only be accessed in the configuration state and after the CSR has been initialized to 25H. The default value of this register after power up is 00H (Table 110). CR25 is used to select the base address of Serial Port 2 (UART2). Serial Port 2 can be set to 96 locations on 8-byte boundaries from 100H - 3F8H. To disable Serial Port 2, set ADR9 and ADR8 to zero. Set CR25.0 to 0 when writing the UART2 Base Address. Serial Port 2 Address Decoding: nCS = ’0’ and A10 = ’0’ are required to access UART2 registers. A[ 2:0] are decoded as XXXb. Table 110 - CR25: UART2 Base Address Register DB5 DB4 DB3 DB2 ADR7 ADR6 ADR5 ADR4 DB7 ADR9 CR26 DB6 ADR8 DB1 ADR3 DB0 0 CR26 can only be accessed in the configuration state and after the CSR has been initialized to 26H. The default value of this register after power up is 00H (Table 111). CR26 is used to select the DMA for the FDC (Bits 4 - 7) and the Parallel Port (bits 0 - 3). Any unselected DMA Request output (DRQ) is in tristate. Table 111 - CR26: FDC and PP DMA Selection Register D3-D0 OR D7-D4 DMA SELECTED 0000 DMA_A 0001 DMA_B 0010 DMA_C 0011 DMA_D 0100 RESERVED 1111 NONE SMSC DS – FDC37N869 Page 116 Rev. 11/09/2000 CR27 CR27 can only be accessed in the configuration state and after the CSR has been initialized to 27H. The default value of this register after power up is 00H (Table 112). CR27 is used to select the IRQ for the FDC (Bits 4 - 7) and the Parallel Port (bits 3 - 0). Any unselected IRQ output (registers CR27 - CR29) is in tri-state. Table 112 - CR27: FDC and PP IRQ Selection Register D3-D0 OR D7-D4 IRQ SELECTED 0000 NONE 0001 IRQ_1 0010 IRQ_2 0011 IRQ_3 0100 IRQ_4 0101 IRQ_5 0110 IRQ_6 0111 IRQ_7 1000 IRQ_8 1001 IRQ_9 1010 IRQ_10 1011 IRQ_11 1100 IRQ_12 1101 IRQ_13 1110 IRQ_14 1111 IRQ_15 CR28 CR28 can only be accessed in the configuration state and after the CSR has been initialized to 28H. The default value of this register after power up is 00H. CR28 is used to select the IRQ for Serial Port 1 (bits 7 - 4) and for Serial Port 2 (bits 3 - 0). Refer to the IRQ encoding for CR27 (Table 113). Any unselected IRQ output (registers CR27 - CR29) is in tristate. Shared IRQs are not supported in the FDC37N869. Table 113 - UART Interrupt Operation UART1 UART2 IRQ PINS UART1 UART1 IRQ UART2 UART2 IRQ UART1 UART2 OUT2 bit Output State OUT2 bit Output State Pin State Pin State 0 Z 0 Z Z Z 1 asserted 0 Z 1 Z 1 de-asserted 0 Z 0 Z 0 Z 1 asserted Z 1 0 Z 1 de-asserted Z 0 1 asserted 1 asserted 1 1 1 asserted 1 de-asserted 1 0 1 de-asserted 1 asserted 0 1 1 de-asserted 1 de-asserted 0 0 It is the responsibility of the software to ensure that two IRQ’s are not set to the same IRQ number. Potential damage to chip may result. Note: Z = Don’t Care. SMSC DS – FDC37N869 Page 117 Rev. 11/09/2000 CR29 CR29 can only be accessed in the configuration state and after the CSR has been initialized to 29H. The default value of this register after power up is 00H (Table 114). CR29 controls the HPMODE bit and is used to select the IRQ mapping (bits 0 - 3) for the IRQIN pin. Refer to IRQ encoding for CR27 (Table 109). Any unselected IRQ output (registers CR27 - CR29) is in tristate. Table 114 - CR29 DESCRIPTION Selects the IRQ for IRQIN See FIGURE 3 – INFRARED INTERFACE BLOCK DIAGRAM 0 Select IRMODE (default) 1 Select IRR3 Not Writeable, Reads Return “0” Serial IRQ enable bit. 0 = Enable (default) 1 = Disable BIT NO. 0-3 4 NAME IRQIN HPMODE 5 7 CR2A RESERVED SIRQ_EN Register CR2A is reserved. The default value of this register after power up is 00H. CR2B CR2B can only be accessed in the configuration state and after the CSR has been initialized to 2BH. The default value of this register after power up is 00H (Table 115). CR2B is used to set the SCE (FIR) base address ADR[10:3]. The SCE base address can be set to 224 locations on 8-byte boundaries from 100H - 7F8H. To disable the SCE, set ADR10, ADR9 and ADR8 to zero. SCE Address Decoding: nCS = ’0’ required to access SCE registers. A[ 2:0] are decoded as XXXb. Table 115 - CR2B: SCE (FIR) Base Address Register DB5 DB4 DB3 DB2 ADR8 ADR7 ADR6 ADR5 DB7 ADR10 CR2C DB6 ADR9 DB1 ADR4 DB0 ADR3 CR2C can only be accessed in the configuration state and after the CSR has been initialized to 2CH. The default value of this register after power up is 00H (Table 116). Bits D[3:0] of this register are used to select the DMA for the SCE (FIR). Bits D[7:4] are Reserved. Reserved bits cannot be written and return 0 when read. Any unselected DMA Request output (DRQ) is in tristate. Table 116 - CR2C: SCE (FIR) DMA Select Register D3-D0 OR D7-D4 DMA SELECTED 0000 DMA_A 0001 DMA_B 0010 DMA_C 0011 DMA_D 0100 RESERVED 1111 NONE SMSC DS – FDC37N869 Page 118 Rev. 11/09/2000 CR2D CR2D can only be accessed in the configuration state and after the CSR has been initialized to 2DH. The default value of this register after power up is 03H (Table 117). CR2D is used to set the IR Half Duplex Turnaround Delay Time for the IR port. This value is 0 to 10msec in 100µsec increments. The IRCC v2.0 block includes an 8 bit IR Half Duplex Time-out register in SCE Register Block 5, Address 1 that interacts with configuration register CR2D. These two registers behave like the other IRCC Legacy controls where either source uniformly updates the value of both registers when either register is explicitly written using IOW or following a device-level POR. IRCC software resets do not affect these registers. The IR Half Duplex Time-out is programmable from 0 to 25.5mS in 100µS increments, as follows: IR HALF DUPLEX TIME-OUT = (CR2D) x 100µS Table 117 - CR2D D5 D4 D3 D2 IR HALF DUPLEX TIME-OUT D7 CR2D CR2E R/W D6 D1 D0 DEFAULT 0x03 CR2E can only be accessed in the configuration state and after the CSR has been initialized to 2EH. The default value of this register after power up is 00H (Table 118). CR2E is directly connected to SCE Register Block Three, Address 0x05 in the IRCC v2.0 block. Table 118 - CR2E D4 D3 Software Select A D7 CR2E CR2F R/W D6 D5 D2 D1 D0 DEFAULT 0x00 CR2F can only be accessed in the configuration state and after the CSR has been initialized to 2FH. The default value of this register after power up is 00H (Table 119). CR2F is directly connected to SCE Register Block Three, Address 0x06 in the IRCC v2.0 block. Table 119 - CR2F D4 D3 Software Select B D7 CR2F R/W D6 D5 D2 D1 D0 DEFAULT 0x00 SMSC DS – FDC37N869 Page 119 Rev. 11/09/2000 OPERATIONAL DESCRIPTION MAXIMUM GUARANTEED RATINGS Operating Temperature Range................................................................................................................................ 0oC to +70oC Storage Temperature Range ................................................................................................................................ -55o to +150oC Lead Temperature Range (soldering, 10 seconds)......................................................................................................+325oC Positive Voltage on any pin, with respect to Ground......................................................................................................... +5.5V Negative Voltage on any pin, with respect to Ground ........................................................................................................ -0.3V Maximum VCC................................................................................................................................................................................+5V *Stresses above those listed above could cause permanent damage to the device. This is a stress rating only and functional operation of the device at any other condition above those indicated in the operation sections of this specification is not implied. Note: When powering this device from laboratory or system power supplies, it is important that the Absolute Maximum Ratings not be exceeded or device failure can result. Some power supplies exhibit voltage spikes on their outputs when the AC power is switched on or off. In addition, voltage transients on the AC power line may appear on the DC output. If this possibility exists, it is suggested that a clamp circuit be used. DC ELECTRICAL CHARACTERISTICS (TA = 0°C - 70°C, Vcc = +3.3 V ± 10%) Refer to Table 120 on the following page. SMSC DS – FDC37N869 Page 120 Rev. 11/09/2000 Table 120 – DC Electrical Characteristics (TA = 0°C - 70°C, Vcc = +3 V ± 10%) PARAMETER I Type Input Buffer Low Input Level High Input Level IS Type Input Buffer Low Input Level High Input Level Schmitt Trigger Hysteresis ICLK Input Buffer Low Input Level High Input Level Input Leakage (All I and IS buffers except PWRGD) Low Input Leakage High Input Leakage Input Current PWRGD IO12 Type Buffer Low Output Level High Output Level Output Leakage O12 Type Buffer Low Output Level High Output Level Output Leakage O12PD Type Buffer Low Output Level High Output Level Output Leakage O6 Type Buffer Low Output Level High Output Level Output Leakage VOL VOH IOL 2.4 -10 +10 0.4 V V µA IOL = 6 mA IOH = - 3mA VIN = 0 to Vcc (Note 1) VOL VOH IOL 2.4 -10 +10 0.4 V V µA IOL = 1 2mA IOH = - 6mA VIN = 0 to Vcc (Note 1) VOL VOH IOL 2.4 -10 +10 0.4 V V µA IOL = 1 2mA IOH = - 6mA VIN = 0 to Vcc (Note 1) VOL VOH IOL 2.4 -10 +10 0.4 V V µA IOL = 1 2mA IOH = - 6mA VIN = 0 to Vcc (Note 1) IIL IIH IOH 75 150 µA VIN = 0 -10 -10 +10 +10 µA µA VIN = 0 VIN = Vcc VILCK VIHCK 2.2 0.4 V V VILIS VIHIS VHYS 2.2 250 0.8 V V mV Schmitt Trigger Schmitt Trigger VILI VIHI 2.0 0.8 V V TTL Levels SYMBOL MIN TYP MAX UNITS COMMENTS SMSC DS – FDC37N869 Page 121 Rev. 11/09/2000 Table 120 – DC Electrical Characteristics (TA = 0°C - 70°C, Vcc = +3 V ± 10%) PARAMETER OD14 Type Buffer Low Output Level Output Leakage VOL IOL -10 0.4 +10 V µA IOL = 1 4mA VIN = 0 to Vcc (Note 1) OP14 Type Buffer Low Output Level High Output Level Output Leakage VOL VOH IOL 2.4 -10 +10 0.4 V V µA IOL = 1 4mA IOH = - 14mA VIN = 0 to Vcc (Note 1) IOP14 Type Buffer Low Output Level High Output Level Output Leakage VOL VOH IOL 2.4 -10 +10 0.4 V V µA IOL = 1 4mA IOH = - 14mA VIN = 0 to Vcc (Note 1) O4 Type Buffer Low Output Level High Output Level Output Leakage VOL VOH IOL 2.4 -10 +10 0.4 V V µA IOL = 4 mA IOH = - 2mA VIN = 0 to Vcc (Note 1) OD12 Type Buffer Low Output Level Output Leakage VOL IOL -10 0.4 +10 V µA IOL = 1 2 mA VIN = 0 to Vcc (Note 1) Supply Current Active Supply Current Standby ChiProtect (SLCT, PE, BUSY, nACK, nERROR) SYMBOL MIN TYP MAX UNITS COMMENTS ICC ICSBY IIL 15 20 100 ±10 mA µA µA All outputs open. Note 3 Chip in circuit: VCC = 0V VIN = 5.5V Max. Chip in circuit: VCC = 0V VIN = 5.5V Max. Backdrive Protect (nSLCTIN, nINIT, nAUTOFD, nSTROBE, PD[7:0]) IIL ±10 µA Note 1: Output leakage is measured with the current pins in high impedance as defined by the PWRGD pin. Note 2: Output leakage is measured with the low driving output off, either for a high level output or a high impedance state defined by PWRGD. Note 3: Defined by the device configuration with the PWRGD input low. SMSC DS – FDC37N869 Page 122 Rev. 11/09/2000 Table 121 - DC Electrical Characteristics (TA = 0°C - 70°C, Vcc = +5 V ± 10%) PARAMETER I Type Input Buffer Low Input Level High Input Level IS Type Input Buffer Low Input Level High Input Level Schmitt Trigger Hysteresis ICLK Input Buffer Low Input Level High Input Level Input Leakage (All I and IS buffers except PWRGD) Low Input Leakage High Input Leakage Input Current PWRGD IO12 Type Buffer Low Output Level High Output Level Output Leakage O12 Type Buffer Low Output Level High Output Level Output Leakage O12PD Type Buffer Low Output Level High Output Level Output Leakage VOL VOH IOL 2.4 -10 +10 0.4 V V µA IOL = 1 2mA IOH = - 6mA VIN = 0 to Vcc (Note 1) VOL VOH IOL 2.4 -10 +10 0.4 V V µA IOL = 1 2mA IOH = - 6mA VIN = 0 to Vcc (Note 1) VOL VOH IOL 2.4 -10 +10 0.4 V V µA IOL = 1 2mA IOH = - 6mA VIN = 0 to Vcc (Note 1) IIL IIH IOH 75 150 µA VIN = 0 -10 -10 +10 +10 µA µA VIN = 0 VIN = Vcc VILCK VIHCK 2.2 0.4 V V VILIS VIHIS VHYS 2.2 250 0.8 V V mV Schmitt Trigger Schmitt Trigger VILI VIHI 2.0 0.8 V V TTL Levels SYMBOL MIN TYP MAX UNITS COMMENTS SMSC DS – FDC37N869 Page 123 Rev. 11/09/2000 Table 121 - DC Electrical Characteristics (TA = 0°C - 70°C, Vcc = +5 V ± 10%) PARAMETER O6 Type Buffer Low Output Level High Output Level Output Leakage OD14 Type Buffer Low Output Level Output Leakage OP14 Type Buffer Low Output Level High Output Level Output Leakage IOP14 Type Buffer Low Output Level High Output Level Output Leakage O4 Type Buffer Low Output Level High Output Level Output Leakage OD12 Type Buffer Low Output Level Output Leakage Supply Current Active VOL IOL ICC -10 15 0.4 +10 20 V µA mA IOL = 1 2 mA VIN = 0 to Vcc (Note 1) All outputs open. VOL VOH IOL 2.4 -10 +10 0.4 V V µA IOL = 4 mA IOH = - 2mA VIN = 0 to Vcc (Note 1) VOL VOH IOL 2.4 -10 +10 0.4 V V µA IOL = 1 4mA IOH = - 14mA VIN = 0 to Vcc (Note 1) VOL VOH IOL 2.4 -10 +10 0.4 V V µA IOL = 1 4mA IOH = - 14mA VIN = 0 to Vcc (Note 1) VOL IOL -10 0.4 +10 V µA IOL = 1 4mA VIN = 0 to Vcc (Note 1) VOL VOH IOL 2.4 -10 +10 0.4 V V µA IOL = 6 mA IOH = - 3mA VIN = 0 to Vcc (Note 1) SYMBOL MIN TYP MAX UNITS COMMENTS Supply Current Standby ChiProtect (nSLCTIN, nINIT, nAUTOFD, nSTROBE, PD[7:0]) ICSBY IIL 100 ±10 µA µA Note 3 Chip in circuit: VCC = 0V VIN = 5.5V Max. SMSC DS – FDC37N869 Page 124 Rev. 11/09/2000 Note 1: Output leakage is measured with the current pins in high impedance as defined by the PWRGD pin. Note 2: Output leakage is measured with the low driving output off, either for a high level output or a high impedance state defined by PWRGD. Note 3: Defined by the device configuration with the PWRGD input low. CAPACITANCE TA = 25°C; fc = 1MHz; VCC = 3.3V Table 122 - Clock Pin Loading LIMITS SYMBOL MIN TYP MAX CIN 20 CIN COUT 10 20 PARAMETER Clock Input Capacitance Input Capacitance Output Capacitance UNIT pF pF pF TEST CONDITION All pins except pin under test tied to AC ground Table 123 - Capacitive Loading per Output Pin SIGNAL NAME TOTAL CAPACITANCE (pF) SD[0:7] 240 IOCHRDY 240 IRQs 120 DRQs 120 nWGATE 240 nWDATA 240 nHDSEL 240 nDIR 240 nSTEP 240 nDS[1:0] 240 nMTR[1:0] 240 DRVDEN[1:0] 240 TXD 100 nRTS 100 nDTR 100 PD[7:0] 240 nSLCTIN 240 nINIT 240 nALF 240 nSTB 240 SMSC DS – FDC37N869 Page 125 Rev. 11/09/2000 AC TIMING Host Timing AX, AEN, nIOCS16 nIOR t3 t1 t6 t2 t4 DATA (D0-D7) PD0-PD7, nERR, PE, SLCT, nACK, BUSY FINTR t5 DATA VALID t7 nIOR/nIOW t8 t9 PINTR PINTR is the interrupt assigned to the Parallel Port FINTR is the interrupt assigned to the Floppy Disk Parameter t1 t2 t3 t4 t5 t6 t7 t8 t9 A0-A9, AEN, nIOCS16 Set Up to nIOR Low nIOR Width A0-A9, AEN, nIOCS16 Hold from nIOR High Data Access Time from nIOR Low Data to Float Delay from nIOR High Parallel Port Setup Read Strobe to Clear FINTR nIOR or nIOW Inactive for Transfers to and from ECP FIFO nIOR Active to PINTR Inactive min 40 150 10 typ max units ns ns ns 10 20 40 150 100 60 55 ns ns ns ns ns ns 260 FIGURE 8 - MICROPROCESSOR READ TIMING SMSC DS – FDC37N869 Page 126 Rev. 11/09/2000 t3 AX, AEN, nIOCS16 t2 t1 nIOW t5 DATA (D0-D7) FINTR t4 DATA VALID t6 t7 PINTR PINTR is the interrupt assigned to the Parallel Port FINTR is the interrupt assigned to the Floppy Disk Parameter t1 t2 t3 t4 t5 t6 t7 A0-A9, AEN, nIOCS16 Set Up to nIOW Low nIOW Width A0-A9, AEN, nIOCS16 Hold from nIOW High Data Set Up Time to nIOW High Data Hold Time from nIOW High Write Strobe to Clear FINTR nIOW Inactive to PINTR Inactive min 40 150 10 40 10 typ max units ns ns ns ns 40 55 260 ns ns ns FIGURE 9 - MICROPROCESSOR WRITE TIMING SMSC DS – FDC37N869 Page 127 Rev. 11/09/2000 t15 AEN t16 t3 t2 FDRQ, PDRQ FDACKX PDACKX t14 t11 nIOR or nIOW t6 t5 t8 t1 t4 t12 t7 DATA (DO-D7) t13 TC FDRQ refers to the DRQ assigned to the Floppy Disk PDRQ refers to the DRQ assigned to the Parallel Port FDACKX refers to the nDACK assigned to the to the Floppy Disk PDACKX refers to the nDACK assigned to the Parallel Port DATA VALID t10 t9 Parameter t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 nDACK Delay Time from FDRQ High DRQ Reset Delay from nIOR or nIOW FDRQ Reset Delay from nDACK Low nDACK Width nIOR Delay from FDRQ High nIOW Delay from FDRQ High Data Access Time from nIOR Low Data Set Up Time to nIOW High Data to Float Delay from nIOR High Data Hold Time from nIOW High nDACK Set Up to nIOW/nIOR Low nDACK Hold After nIOW/nIOR High TC Pulse Width AEN Set Up to nIOR/nIOW AEN Hold from nDACK TC Active to PDRQ Inactive min 0 typ max 100 100 units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 150 0 0 40 10 10 5 10 60 40 10 100 60 100 FIGURE 10 - DMA TIMING SMSC DS – FDC37N869 Page 128 Rev. 11/09/2000 t1 t2 X1K t4 t2 nRESET Parameter t1 t2 t1 t2 t4 Clock CycleTime for 14.318MHz Clock High Time/Low Time for 14.318MHz Clock Cycle Time for 32kHz Clock High Time/Low Time for 32kHz Clock Rise Time/Fall Time (not shown) nRESET Low Time min typ 70 35 31.25 16.53 max 65 units ns ns us us 5 1.5 ns us The nRESET low time is dependent upon the processor clock. The nRESET must be active for a minimum of 1.5us. FIGURE 11 - CLOCK TIMING SMSC DS – FDC37N869 Page 129 Rev. 11/09/2000 FDD Timing t3 nDIR t4 t1 nSTEP t5 nDS0-3 t6 nINDEX t7 nRDATA t8 nWDATA nIOW t9 nDS0-1, nMTR0-1 t9 t2 (AT Mode timing only) Parameter t1 t2 t3 t4 t5 t6 t7 t8 t9 nDIR Set Up to nSTEP Low nSTEP Active Time Low nDIR Hold Time After nSTEP nSTEP Cycle Time nDS0-1 Hold Time from nSTEP Low nINDEX Pulse Width nRDATA Active Time Low nWDATA Write Data Width Low nDS0-1, MTR0-1 from End of nIOW min typ 4 24 96 132 20 2 40 .5 25 max units X* X* X* X* X* X* ns Y* ns *X specifies one MCLK period and Y specifies one WCLK period. MCLK = 16x Data Rate (at 500 Kbp/s MCLK = 8 MHz) WCLK = 2x Data Rate (at 500 Kbp/s WCLK = 1 MHz) FIGURE 12 - DISK DRIVE TIMING SMSC DS – FDC37N869 Page 130 Rev. 11/09/2000 Serial Port Timing nIOW t1 nRTSx, nDTRx t5 IRQx nCTSx, nDSRx, nDCDx t6 t2 IRQx nIOW t4 t3 IRQx nIOR nRIx Parameter t1 t2 t3 t4 t5 t6 nRTSx, nDTRx Delay from nIOW IRQx Active Delay from nCTSx, nDSRx, nDCDx IRQx Inactive Delay from nIOR (Leading Edge) IRQx Inactive Delay from nIOW (Trailing Edge) IRQx Inactive Delay from nIOW IRQx Active Delay from nRIx min typ max 200 100 120 125 units ns ns ns ns ns ns 10 100 100 FIGURE 13 - SERIAL PORT TIMING SMSC DS – FDC37N869 Page 131 Rev. 11/09/2000 DATA 0 t2 t1 1 0 1 0 0 1 1 0 1 1 t2 t1 IRRX nIRRX Parameter t1 t1 t1 t1 t1 t1 t1 t2 t2 t2 t2 t2 t2 t2 Pulse Width at 115kbaud Pulse Width at 57.6kbaud Pulse Width at 38.4kbaud Pulse Width at 19.2kbaud Pulse Width at 9.6kbaud Pulse Width at 4.8kbaud Pulse Width at 2.4kbaud Bit Time at 115kbaud Bit Time at 57.6kbaud Bit Time at 38.4kbaud Bit Time at 19.2kbaud Bit Time at 9.6kbaud Bit Time at 4.8kbaud Bit Time at 2.4kbaud min 1.4 1.4 1.4 1.4 1.4 1.4 1.4 typ 1.6 3.22 4.8 9.7 19.5 39 78 8.68 17.4 26 52 104 208 416 max 2.71 3.69 5.53 11.07 22.13 44.27 88.55 units µs µs µs µs µs µs µs µs µs µs µs µs µs µs Notes: 1. Receive Pulse Detection Criteria: A received pulse is considered detected if the received pulse is a minimum of 1.41µs. 2. IRRX: CRC Bit 0: 1 = RCV active low nIRRX: CRC Bit 0: 0 = RCV active high (default) FIGURE 14 - IRDA SIR RECEIVE TIMING SMSC DS – FDC37N869 Page 132 Rev. 11/09/2000 DATA 0 t2 t1 1 0 1 0 0 1 1 0 1 1 t2 t1 IRTX nIRTX Parameter t1 t1 t1 t1 t1 t1 t1 t2 t2 t2 t2 t2 t2 t2 Pulse Width at 115kbaud Pulse Width at 57.6kbaud Pulse Width at 38.4kbaud Pulse Width at 19.2kbaud Pulse Width at 9.6kbaud Pulse Width at 4.8kbaud Pulse Width at 2.4kbaud Bit Time at 115kbaud Bit Time at 57.6kbaud Bit Time at 38.4kbaud Bit Time at 19.2kbaud Bit Time at 9.6kbaud Bit Time at 4.8kbaud Bit Time at 2.4kbaud min 1.41 1.41 1.41 1.41 1.41 1.41 1.41 typ 1.6 3.22 4.8 9.7 19.5 39 78 8.68 17.4 26 52 104 208 416 max 2.71 3.69 5.53 11.07 22.13 44.27 88.55 units µs µs µs µs µs µs µs µs µs µs µs µs µs µs Notes: 1. IrDA @ 115k is HPSIR compatible. IrDA @ 2400 will allow compatibility with HP95LX and 48SX. 2. IRTX: CRC Bit 1: 1 = XMIT active low (default) nIRTX: CRC Bit 1: 0 = XMIT active high FIGURE 15 - IRDA SIR TRANSMIT TIMING SMSC DS – FDC37N869 Page 133 Rev. 11/09/2000 DATA 0 t1 1 t2 0 1 0 0 1 1 0 1 1 IRRX nIRRX t3 MIRRX t5 nMIRRX t6 t4 Parameter t1 t2 t3 t4 t5 t6 Modulated Output Bit Time Off Bit Time Modulated Output "On" Modulated Output "Off" Modulated Output "On" Modulated Output "On" min typ max units µs µs µs µs µs µs 0.8 0.8 0.8 0.8 1 1 1 1 1.2 1.2 1.2 1.2 Notes: 1. IRRX: CRC Bit 0: 1 = RCV active low nIRRX: CRC Bit 0: 0 = RCV active high (default) MIRRX, nMIRRX are the modulated outputs FIGURE 16 - AMPLITUDE SHIFT KEYED IR RECEIVE TIMING SMSC DS – FDC37N869 Page 134 Rev. 11/09/2000 DATA 0 t1 1 t2 0 1 0 0 1 1 0 1 1 IRTX nIRTX t3 MIRTX t5 nMIRTX t4 t6 Parameter t1 t2 t3 t4 t5 t6 Modulated Output Bit Time Off Bit Time Modulated Output "On" Modulated Output "Off" Modulated Output "On" Modulated Output "On" min typ max units µs µs µs µs µs µs 0.8 0.8 0.8 0.8 1 1 1 1 1.2 1.2 1.2 1.2 Notes: 1. IRTX: CRC Bit 1: 1 = XMIT active low (default) nIRTX: CRC Bit 1: 0 = XMIT active high MIRTX, nMIRTX are the modulated outputs FIGURE 17 - AMPLITUDE SHIFT KEYED IR TRANSMIT TIMING SMSC DS – FDC37N869 Page 135 Rev. 11/09/2000 Parallel Port Timing PD0- PD7 t6 nIOW t1 nINIT, nSTROBE. nAUTOFD, SLCTIN PINTR (SPP) nACK t2 PINTR (ECP or EPP Enabled) nFAULT (ECP) nERROR (ECP) t5 t2 PINTR t3 t4 t3 Parameter t1 t2 t3 t4 t5 t6 nINIT, nSTROBE, nAUTOFD Delay from nIOW Inactive PINTR Delay from nACK, nFAULT PINTR Active Low in ECP and EPP Modes PINTR Delay from nACK nERROR Active to PINTR Active PD0-PD7 Delay from nIOW Active min typ max 100 60 300 105 105 100 units ns ns ns ns ns ns 200 PINTR is the interrupt assigned to the Parallel Port FIGURE 18 - PARALLEL PORT TIMING SMSC DS – FDC37N869 Page 136 Rev. 11/09/2000 Parallel Port EPP Timing t18 AX t9 SD nIOW IOCHRDY t13 nWRITE PD t16 nDATAST nADDRSTB t15 nWAIT t6 t7 t3 t14 t4 t20 t2 t1 t5 t17 t8 t12 t10 t11 t19 Parameter t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 NOTE: min max 50 185 35 190 units Notes nIOW Asserted to PDATA Valid 0 nWAIT Asserted to nWRITE Change 60 nWRITE to Command Asserted 5 nWAIT Deasserted to Command Deasserted 60 nWAIT Asserted to PDATA Invalid 0 Time Out 10 Command Deasserted to nWAIT Asserted 0 SDATA Valid to IOW Asserted 10 nIOW Deasserted to DATA Invalid 0 nIOW Asserted to IOCHRDY Deasserted 0 WAIT Deasserted to nIOCHRDY Asserted 60 IOCHRDY Deasserted to nIOW Asserted 10 nIOW Asserted to nWRITE Asserted 0 nWAIT Asserted to Command Asserted 60 Command Asserted to nWAIT Deasserted 0 PDATA Valid to Command Asserted 10 Ax Valid to nIOW Asserted 40 nIOW Deasserted to Ax Invalid 10 nIOW Deasserted to nIOW or nIOR Asserted 40 nWAIT Asserted to nWRITE Asserted 60 WAIT must be filtered to compensate for ringing on the parallel bus cable. after it does not transition for a minimum of 50 nsec. ns ns 1 ns ns 1 ns 1 12 µs ns ns ns 24 ns 160 ns 1 ns 70 ns 210 ns 1 10 µs ns ns ns ns 185 ns 1 WAIT is considered to have settled FIGURE 19 - EPP 1.9 DATA OR ADDRESS WRITE CYCLE SMSC DS – FDC37N869 Page 137 Rev. 11/09/2000 t20 AX t19 IOR t13 SD t8 t18 t10 t12 t11 t22 IOCHRDY t9 t21 nWRITE t2 t25 PD t28 t1 t14 DATASTB ADDRSTB t15 t7 nWAIT t6 t3 t5 PData bus driven by peripheral t17 t4 t16 Timing parameter table for the EPP Data or Address Read Cycle is found on next page. FIGURE 20 - EPP 1.9 DATA OR ADDRESS READ CYCLE SMSC DS – FDC37N869 Page 138 Rev. 11/09/2000 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t25 t28 Parameter PDATA Hi-Z to Command Asserted nIOR Asserted to PDATA Hi-Z nWAIT Deasserted to Command Deasserted Command Deasserted to PDATA Hi-Z Command Asserted to PDATA Valid PDATA Hi-Z to nWAIT Deasserted PDATA Valid to nWAIT Deasserted nIOR Assertd to IOCHRDY Deasserted nWRITE Deasserted to nIOR Asserted nWAIT Deasserted to IOCHRDY Asserted IOCHRDY Deasserted to nIOR Asserted nIOR Deasserted to SDATA Hi-Z (Hold Time) PDATA Valid to SDATA Valid nWAIT Asserted to Command Asserted Time Out nWAIT Deasserted to PDATA Driven nWAIT Deasserted to nWRITE Modified SDATA Valid to IOCHRDY Asserted Ax Valid to nIOR Asserted nIOR Deasserted to Ax Invalid nWAIT Asserted to nWRITE Deasserted nIOR Deasserted to nIOW or nIOR Asserted nWAIT Asserted to PDATA Hi-Z WRITE Deasserted to Command min 0 0 60 0 0 0 0 0 0 60 0 0 0 0 10 60 60 0 40 10 0 40 60 1 max 30 50 180 units ns ns ns ns ns µs ns ns ns ns ns Notes 1 24 160 2 1 40 75 195 12 190 190 85 ns ns ns µs ns ns ns ns ns ns ns ns ns 1 1,2 3 185 180 1 NOTES: 1. nWAIT is considered to have settled after it does not transition for a minimum of 50 ns. 2. When not executing a write cycle, EPP nWRITE is inactive high. 3. 85 is true only if t7 = 0. FIGURE 21 - EPP 1.9 DATA OR ADDRESS READ CYCLE TIMING PARAMETERS SMSC DS – FDC37N869 Page 139 Rev. 11/09/2000 t18 AX t9 SD t17 t8 nIOW t10 t20 IOCHRDY t13 nWRITE t5 PD t1 t16 t3 nDATAST nADDRSTB t21 nWAIT t4 t2 t11 t6 t12 t19 Parameter t1 t2 t3 t4 t5 t6 t8 t9 t10 t11 t12 t13 t16 t17 t18 t19 t20 t21 nIOW Asserted to PDATA Valid Command Dessserted to nWRITE Change nWRITE to Command nIOW Deasserted to Command Deasserted Command Deasserted to PDATA Invalid Time Out SDATA Valid to nIOW Asserted nIOW Deasserted to DATA Invalid nIOW Asserted to IOCHRDY Deasserted nWAIT Deasserted to IOCHRDY Asserted IOCHRDY Deasserted to nIOW Deasserted nIOW Asserted to nWRITE Asserted PDATA Valid to Command Asserted Ax Valid to nIOW Asserted nIOW Deasserted to Ax Invalid nIOW Deasserted to nIOW or nIOR Asserted nWAIT Asserted to IOCHRDY Deasserted Command Deasserted to nWAIT Deasserted min 0 0 5 50 10 10 0 0 10 0 10 40 10 100 0 max 50 40 35 50 12 units ns ns ns ns ns µs ns ns ns ns ns ns ns ns µs ns ns ns Notes 2 24 40 50 35 45 NOTES: 1. WRITE is controlled by clearing the PDIR bit to "0" in the control register before performing an EPP Write. 2. This number is only valid if WAIT is active when nIOW goes active. FIGURE 22 - EPP 1.7 DATA OR ADDRESS WRITE CYCLE SMSC DS – FDC37N869 Page 140 Rev. 11/09/2000 t20 AX t15 t19 nIOR t13 SD t8 IOCHRDY t3 t10 t11 t22 t12 nWRITE t5 PD t23 nDATASTB nADDRSTB t21 nWAIT t2 t4 Parameter t2 t3 t4 t5 t8 t10 t11 t12 t13 t15 t19 t20 t21 t22 t23 nIOR Deasserted to Command Deasserted nWAIT Asserted to IOCHRDY Deasserted Command Deasserted to PDATA Hi-Z Command Asserted to PDATA Valid nIOR Asserted to IOCHRDY Deasserted nWAIT Deasserted to IOCHRDY Asserted nIOCHRDY Deasserted to nIOR Asserted nIOR Deasserted to SDATA High-Z (Hold Time) PData Valid to SDATA Valid Time Out Ax Valid to nIOR Asserted nIOR Deasserted to Ax Invalid Command Deasserted to nWAIT Deasserted nIOR Deasserted to nIOW or nIOR Asserted nIOR Asserted to Command Asserted min 0 0 0 max 50 40 units ns ns ns ns ns ns ns ns ns µs ns ns ns ns ns Notes 24 50 0 0 10 40 10 0 40 40 40 12 55 NOTE: 1. nWRITE is controlled by setting the PDIR bit to "1" in the control register before performing an EPP Read. FIGURE 23 - EPP 1.7 DATA OR ADDRESS READ CYCLE SMSC DS – FDC37N869 Page 141 Rev. 11/09/2000 Parallel Port ECP Timing Parallel Port FIFO (Mode 101) The standard parallel port is run at or near the peak 500 Kbps allowed in the forward direction using DMA. The state machine does not examine nAck and begins the next transfer based on Busy. Refer to FIGURE 23. ECP Parallel Port Timing The timing is designed to allow operation at approximately 2.0Mbytes/sec over a 15ft cable. If a shorter cable is used then the bandwidth will increase. Forward-Idle When the host has no data to send it keeps HostClk (nStrobe) high and the peripheral will leave PeriphClk (Busy) low. Forward Data Transfer Phase The interface transfers data and commands from the host to the peripheral using an interlocked PeriphAck and HostClk. The peripheral may indicate its desire to send data to the host by asserting nPeriph Request. The Forward Data Transfer Phase may be entered from the Forward-Idle Phase. While in the Forward Phase the peripheral may asynchronously assert the nPeriph Request (nFault) to request that the channel be reversed. When the peripheral is not busy it sets PeriphAck (Busy) low. The host then sets HostClk (nStrobe) low when it is prepared to send data. The data must be stable for the specified setup time prior to the falling edge of HostClk. The peripheral then sets PeriphAck (Busy) high to acknowledge the handshake. The host then sets HostClk (nStrobe) high. The peripheral then accepts the data and sets PeriphAck (Busy) low, completing the transfer. This sequence is shown in FIGURE 24. The timing is designed to provide 3 cable round-trip times for data setup if Data is driven simultaneously with HostClk (nStrobe). Reverse-Idle Phase The peripheral has no data to send and keeps PeriphClk high. The host is idle and keeps HostAck low. Reverse Data Transfer Phase The interface transfers data and commands from the peripheral to the host using an interlocked HostAck and PeriphClk. The Reverse Data Transfer Phase may be entered from the Reverse-Idle Phase. After the previous byte has beed accepted the host sets HostAck (nAutoFd) low. The peripheral then sets PeriphClk (nAck) low when it has data to send. The data must be stable for the specified setup time prior to the falling edge of PeriphClk. When the host is ready it to accept a byte it sets. HostAck (nAutoFd) high to acknowledge the handshake. The peripheral then sets PeriphClk (nAck) high. After the host has accepted the data it sets HostAck (nAutoFd) low, completing the transfer. This sequence is shown in FIGURE 25. Output Drivers To facilitate higher performance data transfer, the use of balanced CMOS active drivers for critical signals (Data, HostAck, HostClk, PeriphAck, PeriphClk) are used ECP Mode. Because the use of active drivers can present compatibility problems in Compatible Mode (the control signals, by tradition, are specified as open-collector), the drivers are dynamically changed from open-collector to totem-pole. The timing for the dynamic driverchange is specified in the IEEE 1284 Extended Capabilities Port Protocol and ISA Interface Standard, Rev. 1.14, July. 14, 1993, available from Microsoft. The dynamic driver change must be implemented properly to prevent glitching the outputs. SMSC DS – FDC37N869 Page 142 Rev. 11/09/2000 t6 t3 PDATA t1 nSTROBE t4 BUSY t2 t5 Parameter t1 t2 t3 t4 t5 t6 DATA Valid to nSTROBE Active nSTROBE Active Pulse Width DATA Hold from nSTROBE Inactive nSTROBE Active to BUSY Active BUSY Inactive to nSTROBE Active BUSY Inactive to PDATE Invalid min 600 600 450 max units ns ns ns ns ns ns Notes 1 500 680 80 1 NOTE: 1. The data is held until BUSY goes inactive or for time t3, whichever is longer. This only applies if another data transfer is pending. If no other data transfer is pending, the data is held indefinitely. FIGURE 24 - PARALLEL PORT FIFO TIMING SMSC DS – FDC37N869 Page 143 Rev. 11/09/2000 t3 nAUTOFD t4 PDATA t2 t1 t7 nSTROBE t6 BUSY t5 t6 t8 Parameter t1 t2 t3 t4 t5 t6 t7 t8 nAUTOFD Valid to nSTROBE Asserted PDATA Valid to nSTROBE Asserted BUSY Deasserted to nAUTOFD Changed nBUSY Deasserted to PDATA Changed nSTROBE Asserted to BUSY Asserted nSTROBE Deasserted to Busy Deasserted nBUSY Deasserted to nSTROBE Asserted nBUSY Asserted to nSTROBE Deasserted min 0 0 80 80 0 0 80 80 max 60 60 180 180 units ns ns ns ns ns ns ns ns Notes 1,2 1,2 200 180 1,2 2 NOTES: 1. Maximum value only applies if there is data in the FIFO waiting to be written out. 2. BUSY is not considered asserted or deasserted until it is stable for a minimum of 75 to 130 ns. FIGURE 25 - ECP PARALLEL PORT FORWARD TIMING SMSC DS – FDC37N869 Page 144 Rev. 11/09/2000 t2 PDATA t1 t5 nACK t4 nAUTOFD t3 t4 t6 Parameter t1 t2 t3 t4 t5 t6 PDATA Valid to nACK Asserted nAUTOFD Asserted to PDATA Changed nACK Asserted to nAUTOFD Deasserted nACK Deasserted to nAUTOFD Asserted nAUTOFD Asserted to nACK Asserted nAUTOFD Deasserted to nACK Deasserted min 0 0 80 80 0 0 max units ns ns Notes 200 200 ns ns ns ns 1,2 2 NOTES: 1. Maximum value only applies if there is room in the FIFO and a terminal count has not been received. ECP can stall by keeping nAUTOFD low. 2. nACK is not considered asserted or deasserted until it is stable for a minimum of 75 to 130 ns. FIGURE 26 - ECP PARALLEL PORT REVERSE TIMING SMSC DS – FDC37N869 Page 145 Rev. 11/09/2000 Package Outlines D 3 3 D1 e E E1 5 D1/4 E1/4 2 W DETAIL "A" R1 R2 0 A H A2 SEE DETAIL "A" 4 L L1 1 0.10 -C- A1 DIM A A1 A2 D D1 E E1 H L L1 e 0 W R1 R2 MIN 0.05 1.35 15.75 13.90 15.75 13.90 0.45 NOM MAX 1.6 1.45 16.25 14.10 16.25 14.10 0.20 0.75 1.40 16.00 14.00 16.00 14.00 0.60 1.00 0.50 BSC 0.25 0.20 0.20 0° 8° Notes: 1 Coplanarity is 0.100mm maximum. 2 Tolerance on the position of the leads is 0.13mm maximum. 3 Package body dimensions D1 and E1 do not include the mold protrusion. Maximum mold protrusion is 0.25mm per side. 4 Dimension for foot length L are measured at the gauge plane 0.25mm above the seating plane. 5 Details of pin 1 identifier are optional but must be located within the zone indicated. 6. Controlling dimension: millimeter FIGURE 27 - 100 PIN TQFP PACKAGE OUTLINE SMSC DS – FDC37N869 Page 146 Rev. 11/09/2000 FDC37N869 REVISIONS PAGE(S) 93 SECTION/FIGURE/ENTRY FDC Power Management CORRECTION Note added under this section – see italicized text. DATE REVISED 11/09/00 SMSC DS – FDC37N869 Page 147 Rev. 11/09/2000